From d296faad23190cef0a9adca732beb7f1c4cf9627 Mon Sep 17 00:00:00 2001 From: Tristan Ross Date: Sun, 19 Apr 2026 18:34:47 -0700 Subject: [PATCH] refactor: use harbor --- .gitignore | 5 + LICENSE | 705 +-- analysis_options.yaml | 10 + devices.nix | 198 + docs/core/design.md | 155 +- flake.lock | 83 +- flake.nix | 350 +- nix/common-dart.nix | 7 + packages/bintools/analysis_options.yaml | 32 +- packages/bintools/lib/bintools.dart | 4 +- packages/bintools/lib/src/bintools_base.dart | 6 - packages/bintools/lib/src/elf.dart | 7 - packages/bintools/lib/src/elf_writer.dart | 231 + packages/bintools/lib/src/linker.dart | 224 + packages/bintools/lib/src/section.dart | 116 + packages/bintools/pubspec.yaml | 2 +- packages/bintools/test/bintools_test.dart | 250 +- packages/riscv/.gitignore | 9 - packages/riscv/CHANGELOG.md | 3 - packages/riscv/README.md | 3 - packages/riscv/analysis_options.yaml | 30 - packages/riscv/dartdoc_options.yaml | 9 - packages/riscv/doc/extensions.md | 12 - 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create mode 100644 packages/river_maskrom/test/maskrom_copy_jump_test.dart create mode 100644 packages/river_maskrom/test/maskrom_hdl_test.dart create mode 100644 packages/river_maskrom/test/maskrom_test.dart create mode 100644 packages/river_maskrom/test/min_tracker_test.dart create mode 100644 packages/river_maskrom/test/trap_wfi_test_sim.dart create mode 100644 pkgs/river-fpga/default.nix create mode 100644 pkgs/river-hdl/default.nix create mode 100644 pkgs/river-ip/default.nix diff --git a/.gitignore b/.gitignore index dae0624..a4288d4 100644 --- a/.gitignore +++ b/.gitignore @@ -20,3 +20,8 @@ doc/api *.out *.elf *.bin + +# Heimdall runtime SQLite databases, created when the daemon/tests run with a +# working directory inside a package (not part of the source tree) +*.db +objects diff --git a/LICENSE b/LICENSE index 8000a6f..261eeb9 100644 --- a/LICENSE +++ b/LICENSE @@ -1,504 +1,201 @@ - GNU LESSER GENERAL PUBLIC LICENSE - Version 2.1, February 1999 - - Copyright (C) 1991, 1999 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/analysis_options.yaml b/analysis_options.yaml new file mode 100644 index 0000000..0174ae3 --- /dev/null +++ b/analysis_options.yaml @@ -0,0 +1,10 @@ +# Workspace-wide production analysis baseline. +# Individual packages include this file. + +include: package:lints/recommended.yaml + +analyzer: + language: + strict-casts: true + strict-inference: true + strict-raw-types: true diff --git a/devices.nix b/devices.nix new file mode 100644 index 0000000..9a01f93 --- /dev/null +++ b/devices.nix @@ -0,0 +1,198 @@ +# Declarative SoC definitions. +# Each device has a base config and a set of targets (FPGA or ASIC). +{ + river-hdl, + sky130-pdk ? null, + gf180mcu-pdk ? null, +}: +let + creek-v1-base = { + socName = "creek_v1"; + cores = [ "rc1-s" ]; + interconnect = "wishbone"; + clockFreq = 48000000; + memories = [ + "0x20000000:16M:flash" + "0x80000000:128M:dram" + ]; + devices = [ + "clint:0x02000000" + "plic:0x04000000" + "uart:0x10000000:ns16550a" + ]; + }; + + stream-v1-base = { + socName = "stream_v1"; + cores = [ "rc1-n" ]; + interconnect = "wishbone"; + clockFreq = 12000000; + memories = [ + "0x20000000:16M:flash" + "0x80000000:1M:sram" + ]; + devices = [ + "clint:0x02000000" + "plic:0x04000000" + "uart:0x10000000:ns16550a" + ]; + }; +in +{ + creek-v1-orangecrab = { + ip = river-hdl.mkSoC ( + creek-v1-base + // { + target = "ecp5:lfe5u-25f:CSFBGA285"; + clockFreq = 48000000; + oscFreq = 48000000; + memories = [ + "0x20000000:16M:flash:orangecrab" + "0x80000000:64K:sram" + "0x90000000:128M:dram:orangecrab" + ]; + bootProgram = "monitor"; + pins = [ + "clk=A9" + "uart_tx=uart@tx:N17" + "uart_rx=uart@rx:M18" + ]; + } + ); + }; + + # Digilent Arty S7-50 (xc7s50, csga324, 100MHz osc), Xilinx via the openXC7 + # flow. DDR3 runs as x8 on the low byte-lane (arty-s7-x8, 128MB): the + # hardware-verified read and write path at cmdslot=2,wrshift=-1. The x16 high + # lane (per-lane write-leveling) is still under debug. Boot monitor runs from + # the 64K EBR SRAM and DDR is promoted separately. Pins from the working + # bring-up (clk=R2, UART R12/V12). + creek-v1-arty = { + ip = river-hdl.mkSoC ( + creek-v1-base + // { + target = "spartan7:xc7s50:csga324"; + clockFreq = 25000000; + oscFreq = 100000000; + memories = [ + "0x20000000:16M:flash:arty-s7" + "0x80000000:64K:sram" + "0x90000000:128M:dram:arty-s7-x8:ddr3fast=true,clockfreq=400000000,cmdslot=2,wrshift=-1,trainable=true" + ]; + bootProgram = "monitor"; + pins = [ + "clk=R2" + "uart_tx=uart@tx:R12" + "uart_rx=uart@rx:V12" + ]; + } + ); + }; + + creek-v1-sky130 = { + ip = river-hdl.mkSoC ( + creek-v1-base + // { + target = "sky130:hd"; + pdkRoot = "${sky130-pdk}/${sky130-pdk.pdkPath}"; + } + ); + # asix.mkTapeout metadata: topCell matches the genip SoC name, and the + # clock period is derived from the device's target frequency. + topCell = creek-v1-base.socName; + clockPeriodNs = 1.0e9 / creek-v1-base.clockFreq; + pdk = sky130-pdk; + }; + + creek-v1-gf180mcu = { + ip = river-hdl.mkSoC ( + creek-v1-base + // { + target = "gf180mcu:3v3"; + pdkRoot = "${gf180mcu-pdk}/${gf180mcu-pdk.pdkPath}"; + } + ); + topCell = creek-v1-base.socName; + clockPeriodNs = 1.0e9 / creek-v1-base.clockFreq; + pdk = gf180mcu-pdk; + }; + + # iCESugar v1.5 (iCE40UP5K-SG48, 12MHz). The up5k holds only ~128KB on-chip, + # so the shared 16M-flash/1M-sram base map does not fit. Override it with a + # single 64KB on-chip data SRAM and drop the external regions. + stream-v1-ice40 = { + ip = river-hdl.mkSoC ( + stream-v1-base + // { + target = "ice40:up5k:sg48"; + memories = [ + "0x20000000:16M:flash" + "0x80000000:128K:sram" + ]; + # No PLIC: this board has no routed interrupt sources and the unused + # 32-source arbiter costs ~900 cells of the up5k. The CLINT covers the + # timer. External IRQs can return with a slimmer controller if needed. + devices = [ + "clint:0x02000000" + "uart:0x10000000:ns16550a" + ]; + # Serial boot monitor in the boot ROM (no cache-as-RAM): prints a banner + # then loads checksummed payloads into the SRAM over the UART. + bootProgram = "monitor"; + # Board UART (iCELink USB-CDC bridge): FPGA tx=6, rx=4 per the official + # iCESugar pcf. Pins 14/15 are SPI-flash lines, not the UART. + pins = [ + "clk=35" + "uart_tx=uart@tx:6" + "uart_rx=uart@rx:4" + ]; + } + ); + }; + + # OrangeCrab r0.2 (LFE5U-25F, csfbga285, 48MHz osc). Pins proven on this + # board by the NixVegas SoC (clk=A9, uart on feather N17/M18 via an + # external USB-TTL adapter; the USB-C port is raw, no onboard bridge). + # Same monitor profile as the iCESugar: rc1-n + 64KB byte-masked EBR SRAM. + stream-v1-orangecrab = { + ip = river-hdl.mkSoC ( + stream-v1-base + // { + target = "ecp5:lfe5u-25f:CSFBGA285"; + clockFreq = 48000000; + # The OrangeCrab oscillator is 48MHz (not the 12MHz default): with + # the default the system PLL multiplies x4 and the whole SoC would + # run at 192MHz on hardware. + oscFreq = 48000000; + # DDR3 (MT41K64M16, 128MB, hardware-verified) sits beside the SRAM + # boot path; promoting it to main RAM at 0x80000000 is a follow-up. + # The dram region pulls the board's full sdram_* pad constraint set + # with it. + memories = [ + "0x20000000:16M:flash:orangecrab" + "0x80000000:64K:sram" + "0x90000000:128M:dram:orangecrab" + ]; + bootProgram = "monitor"; + pins = [ + "clk=A9" + "uart_tx=uart@tx:N17" + "uart_rx=uart@rx:M18" + ]; + } + ); + }; + + stream-v1-gf180mcu = { + ip = river-hdl.mkSoC ( + stream-v1-base + // { + target = "gf180mcu:3v3"; + pdkRoot = "${gf180mcu-pdk}/${gf180mcu-pdk.pdkPath}"; + } + ); + topCell = stream-v1-base.socName; + clockPeriodNs = 1.0e9 / stream-v1-base.clockFreq; + pdk = gf180mcu-pdk; + }; +} diff --git a/docs/core/design.md b/docs/core/design.md index c2fc841..75a04f4 100644 --- a/docs/core/design.md +++ b/docs/core/design.md @@ -36,6 +36,22 @@ This allows for a wide variety of applications and a modular design. - Intended to run Linux - Superscalar +## Execution Modes + +A River core is built in one of two execution modes, picked per profile by the +`ExecutionMode` config (`inOrder` or `outOfOrder`). + +In `inOrder` mode (the nano, micro, small, and full profiles) the core runs the +microcode execution unit described below: one instruction is fetched, decoded, +and executed at a time. This is the compact configuration intended for small +FPGAs and tight area budgets. + +In `outOfOrder` mode (the macro profile) the same front-end feeds an out-of-order +dual-issue backend with register renaming, an issue queue, multiple functional +units, and a reorder buffer for in-order commit. The two modes share the fetch +and decode logic and the microcode definitions, they differ in how execution and +retirement are scheduled. + ## Components River's core is split into 3 central components which matches the primary stages of the pipeline. @@ -44,7 +60,8 @@ River's core is split into 3 central components which matches the primary stages 2. Decode Unit - Decodes instructions 3. Execution Unit - Executes instructions -There are more components based on whether the In-Core Scaler is enabled, however those are the three base modules which River utilizes. +These are the base modules every River core shares. The out-of-order backend adds +the rename, issue, functional-unit, and reorder-buffer blocks described later. ### Fetch Unit @@ -56,6 +73,21 @@ If the instruction is compressed, the fetch unit emits that into the IR (instruc If the instruction is not compressed, the fetch unit will then read the other half-word of memory and combine the two. The full instruction will then be loaded into IR. +A 32-bit instruction can straddle a word boundary when compressed code shifts +alignment, so the fetch path can issue a second read and join the high half-word +of one word with the low half-word of the next before presenting the full +instruction. + +Two optional fetch engines trade area for instruction throughput. A pipelined +prefetch fetcher issues the next instruction read while the current instruction +is still being consumed downstream, holding results in a small instruction FIFO so +fetch latency overlaps decode and execution instead of serialising with them. It +keeps exactly one bus read outstanding at a time and drains any in-flight stale +response on a redirect, so a response is never mis-attributed to the wrong +address. The fetch port is interconnect-neutral: it only assumes a single read in +flight and one in-order response pulse per request, so the in-tree MMU/Wishbone +port works and an AXI or TileLink adapter presenting the same contract would too. + ### Decode Unit River has 2 decode unit types; static & dynamic. The static decode unit reads the microcode at build time. @@ -127,3 +159,124 @@ will hold the same values & have the same latching behavior. - `sp` - Stack pointer - `rd` - Register desination - `pc` - Program counter + +### Out-of-Order Pipeline + +In `outOfOrder` mode the in-order front-end (fetch, decode, rename) feeds an +issue queue that dispatches to out-of-order functional units, with a reorder +buffer restoring in-order commit. The functional units are two ALUs, one memory +unit, one branch unit, and one CSR unit. + +Renaming uses a Register Alias Table that maps the 32 architectural registers to +a larger physical register file. It renames two instructions per cycle and keeps +a committed snapshot of the table so a flush can roll the speculative mapping +back. Each issue-queue entry carries its reorder-buffer tag, physical source and +destination indices, per-source ready bits and captured values, and the operand +and control metadata the target functional unit needs. An entry issues once both +its sources are ready. + +The reorder buffer entry records the program counter, the new and previous +physical destinations, completion and exception state, the result, and any +control-flow redirect target. Commit happens in program order: it frees the +previous physical destination, applies branch and jump redirects, and handles +privileged returns by restoring the program counter and privilege mode from the +saved exception program counter and status. + +Stores use a store queue so they do not stall commit waiting on memory. A store +pushes an entry when it executes (address and data known), and three pointers +split the queue into a committed-and-draining region and a speculative region. A +committed store drains to memory in program order in the background, so several +writes can be in flight at once. A load waits until the queue is empty so it sees +all older stores, and a flush drops only the speculative tail while committed +entries keep draining. + +### Register File + +The register file is a configurable multiport block. The backend is chosen for +the target: a banked or arbitered multiport built from simpler memories for +simulation and ASIC, or an ECP5 block-RAM (EBR) backend on FPGA. Its read latency +is accounted for by the pipeline rather than assumed to be zero. In out-of-order +mode the physical register file is larger than the 32 architectural registers to +back renaming. When floating point is enabled a second register file holds the FP +registers and is routed into the execution datapath alongside the integer file. + +### Floating-Point and Vector + +Floating point and vector execution live in the microcode execution unit. When a +micro-op reads or writes a floating-point register, a dedicated floating-point +register file is instantiated and wired into the execution datapath. The F and D +extensions cover arithmetic, the comparison operations, and conversions, plus a +multi-cycle iterative divide that runs one operation at a time under a small state +machine. The floating-point datapath is built on the ROHD-HCL floating-point +library. + +The vector engine adds a vector register file of 32 registers each VLEN bits +wide, present when the ISA includes the V extension. The vector configuration +instructions write the element width and grouping into vtype and the active +element count into vl, and vector operations read them back. Integer element +operations are generic across the supported element widths and run over the full +vector length with proper handling of the active length and the tail, and LMUL +register grouping walks the registers of a destination group in turn. + +### Memory and Address Translation + +The MMU sits between the core and a downstream Wishbone master. It has two +upstream ports, one for instruction fetch and one data port for loads, stores, +and page-table walks, with a priority arbiter that favors the data port. When +translation is active it performs a hardware page-table walk supporting Sv39 and +Sv48 for both loads and stores and raises page faults on bad entries. With the +hypervisor extension it performs two-stage translation, where every guest-stage +pointer and the final leaf of the first-stage walk are themselves translated +through the guest-stage walk, and it reports guest faults separately. + +### Privilege and Control Registers + +The core tracks machine, supervisor, and user privilege in a mode register. With +the hypervisor extension a virtualization bit is also tracked and is saved and +restored through the status register on traps and privileged returns. Control and +status registers are described by a typed field configuration, and only declared +field bits are reconstructed on a read, so a readable register needs an explicit +field. A combinational frontdoor read port serves the pipeline and is borrowed by +the debugger while the hart is halted. Trap delivery computes the handler address +from the trap-vector register in either direct or vectored form, and delegation +routes selected traps and interrupts to supervisor mode. Alongside the standard +registers, River defines custom control registers including a pipeline and +speculation control register and the registers used to patch microcode at run +time. + +### Debug Support + +River cores may be built with external RISC-V Debug (spec 0.13.2) support. When +enabled, the core gains a halt finite state machine that freezes the pipeline at +an instruction boundary when the debugger asserts a halt request. On halt the +program counter is latched into `dpc`, and on resume the counter is restored from +`dpc` so the debugger can redirect execution by writing it. The `dcsr` control +register (CSR 0x7b0) holds the debug version, the halt cause, the privilege at +halt, and the `ebreak` enable bits. With those bits set an executed `ebreak` +re-enters debug mode instead of taking a breakpoint trap. + +While the pipeline is frozen its register file ports and combinational CSR read +port are idle, so the debugger borrows them. An abstract access-register command +reads or writes any GPR and reads any architectural CSR through these idle ports +without a dedicated debug datapath. The non-debug-maskable reset bit from the +debug module is OR-ed into the hart reset at the SoC level, so a debugger reset +drops the hart while leaving the debug logic itself alive. + +### Debug Transport + +The TAP, the Debug Transport Module, and the Debug Module are fused into one +system-clock-domain module. It samples the JTAG clock with rising-edge detection, +so a single bit-bang pulse advances the TAP by one step and there is no JTAG to +core clock-domain crossing to reason about. The DMI register is 41 bits. The +Debug Module also exposes a System Bus Access port, a small bus master that reads +and writes memory independently of the hart, so memory inspection works whether +the hart is halted or running. A System Bus to Wishbone adapter presents that +port as a second fabric master. + +On an ECP5 the debugger reaches the Debug Module over the FPGA's own +configuration JTAG (the same port a flashing tool such as dirtyJtag drives) +through the `JTAGG` ER1 user register and a SiFive nested-tap BSCAN tunnel. This +needs no extra package pins. The tunnel module reconstructs the inner TAP's +`tck`, `tms`, and `tdi` from a framed scan of the ER1 data register and returns +its `tdo`, so the full Debug Module is reachable from a stock RISC-V OpenOCD with +`riscv use_bscan_tunnel`. diff --git a/flake.lock b/flake.lock index caffbb2..8f2ec06 100644 --- a/flake.lock +++ b/flake.lock @@ -1,5 +1,26 @@ { "nodes": { + "asix": { + "inputs": { + "nixpkgs": [ + "nixpkgs" + ], + "treefmt-nix": "treefmt-nix" + }, + "locked": { + "lastModified": 1777243449, + "narHash": "sha256-NtXLD5EqWrTqf0k15BT6IkC3y6T7LLoG9005Y1gfP5E=", + "owner": "MidstallSoftware", + "repo": "asix", + "rev": "31303a2eb9ee8b4504baa3fa5ae0bf08bc1268cc", + "type": "github" + }, + "original": { + "owner": "MidstallSoftware", + "repo": "asix", + "type": "github" + } + }, "flake-parts": { "inputs": { "nixpkgs-lib": [ @@ -7,11 +28,11 @@ ] }, "locked": { - "lastModified": 1765835352, - "narHash": "sha256-XswHlK/Qtjasvhd1nOa1e8MgZ8GS//jBoTqWtrS1Giw=", + "lastModified": 1775087534, + "narHash": "sha256-91qqW8lhL7TLwgQWijoGBbiD4t7/q75KTi8NxjVmSmA=", "owner": "hercules-ci", "repo": "flake-parts", - "rev": "a34fae9c08a15ad73f295041fec82323541400a9", + "rev": "3107b77cd68437b9a76194f0f7f9c55f2329ca5b", "type": "github" }, "original": { @@ -20,13 +41,28 @@ "type": "github" } }, + "flakever": { + "locked": { + "lastModified": 1763450705, + "narHash": "sha256-TUSrRfT76OAXty9A4fXlOOfVfJGDglFQs06b8b+f5NY=", + "owner": "numinit", + "repo": "flakever", + "rev": "a69629e4133fbcdf3c7aae477bd6687bb19e0778", + "type": "github" + }, + "original": { + "owner": "numinit", + "repo": "flakever", + "type": "github" + } + }, "nixpkgs": { "locked": { - "lastModified": 1766635106, - "narHash": "sha256-XqmvlUkYpaQzV2CksGR8MzjeqTBKkB3gSf26pYoNqWw=", + "lastModified": 1776555070, + "narHash": "sha256-DXxyq8jsmkgW2ZgoIWVcCmFiXjwcCtz/2yvVyoOMayw=", "owner": "NixOS", "repo": "nixpkgs", - "rev": "6a81c8cfb009e8dbd462d8c75f49a121efcb6e17", + "rev": "9868368dc9b60a5e0f725a759701438c6acbb606", "type": "github" }, "original": { @@ -37,39 +73,46 @@ }, "root": { "inputs": { + "asix": "asix", "flake-parts": "flake-parts", + "flakever": "flakever", "nixpkgs": "nixpkgs", - "systems": "systems", - "treefmt-nix": "treefmt-nix" + "treefmt-nix": "treefmt-nix_2" } }, - "systems": { + "treefmt-nix": { + "inputs": { + "nixpkgs": [ + "asix", + "nixpkgs" + ] + }, "locked": { - "lastModified": 1681028828, - "narHash": "sha256-Vy1rq5AaRuLzOxct8nz4T6wlgyUR7zLU309k9mBC768=", - "owner": "nix-systems", - "repo": "default", - "rev": "da67096a3b9bf56a91d16901293e51ba5b49a27e", + "lastModified": 1775636079, + "narHash": "sha256-pc20NRoMdiar8oPQceQT47UUZMBTiMdUuWrYu2obUP0=", + "owner": "numtide", + "repo": "treefmt-nix", + "rev": "790751ff7fd3801feeaf96d7dc416a8d581265ba", "type": "github" }, "original": { - "owner": "nix-systems", - "repo": "default", + "owner": "numtide", + "repo": "treefmt-nix", "type": "github" } }, - "treefmt-nix": { + "treefmt-nix_2": { "inputs": { "nixpkgs": [ "nixpkgs" ] }, "locked": { - "lastModified": 1766000401, - "narHash": "sha256-+cqN4PJz9y0JQXfAK5J1drd0U05D5fcAGhzhfVrDlsI=", + "lastModified": 1775636079, + "narHash": "sha256-pc20NRoMdiar8oPQceQT47UUZMBTiMdUuWrYu2obUP0=", "owner": "numtide", "repo": "treefmt-nix", - "rev": "42d96e75aa56a3f70cab7e7dc4a32868db28e8fd", + "rev": "790751ff7fd3801feeaf96d7dc416a8d581265ba", "type": "github" }, "original": { diff --git a/flake.nix b/flake.nix index a17d4db..321ca7f 100644 --- a/flake.nix +++ b/flake.nix @@ -5,11 +5,16 @@ url = "github:hercules-ci/flake-parts"; inputs.nixpkgs-lib.follows = "nixpkgs"; }; - systems.url = "github:nix-systems/default"; + flakever.url = "github:numinit/flakever"; treefmt-nix = { url = "github:numtide/treefmt-nix"; inputs.nixpkgs.follows = "nixpkgs"; }; + # PDKs (sky130, gf180mcu) + the silicon backend (mkTapeout/mkVerify). + asix = { + url = "github:MidstallSoftware/asix"; + inputs.nixpkgs.follows = "nixpkgs"; + }; }; outputs = @@ -17,121 +22,189 @@ self, nixpkgs, flake-parts, - systems, + flakever, treefmt-nix, ... }@inputs: - flake-parts.lib.mkFlake { inherit inputs; } ( - { inputs, ... }: - { - systems = import inputs.systems; - - perSystem = - { - lib, - system, - pkgs, - ... - }: - let - treefmtEval = inputs.treefmt-nix.lib.evalModule pkgs ./treefmt.nix; - version = "0.1.0-git+${self.shortRev or "dirty"}"; - pubspecLock = lib.importJSON ./pubspec.lock.json; - - inherit (pkgs) buildDartApplication; - - gitHashes = { - rohd_hcl = "sha256-YobXIH2PTUXxp6MfcAIJG8aXhkc1MZOLthOEaQUJxOM="; - }; - - buildDartTest = - args: - (buildDartApplication ( - args - // { - pname = "${args.pname}-tests"; - - nativeBuildInputs = (args.nativeBuildInputs or [ ]) ++ [ - pkgs.lcov - ]; - - buildPhase = '' - runHook preBuild - mkdir -p $out $out/coverage - - dart --old_gen_heap_size=40960 --packages=.dart_tool/package_config.json --pause-isolates-on-exit --disable-service-auth-codes --enable-vm-service=8181 $(packagePath test)/bin/test.dart $packageRoot --file-reporter=json:$out/report.json -r expanded & - - packageRun coverage -e collect_coverage --wait-paused --uri=http://127.0.0.1:8181/ -o $out/coverage/report.json --resume-isolates --scope-output=${args.pname} - packageRun coverage -e format_coverage --packages=.dart_tool/package_config.json --lcov -i $out/coverage/report.json -o $out/coverage/lcov.info - - if [[ -s $out/coverage/lcov.info ]]; then - genhtml -o $out/coverage/html $out/coverage/lcov.info - fi - - runHook postBuild - ''; - - dontInstall = true; - } - )).overrideAttrs - { outputs = [ "out" ]; }; - in - { - _module.args.pkgs = import inputs.nixpkgs { - inherit system; - overlays = [ ]; - }; - - formatter = treefmtEval.config.build.wrapper; - - checks = { - formatting = treefmtEval.config.build.check self; - } - // lib.mapAttrs' (name: lib.nameValuePair "${name}-tests") ( - lib.genAttrs - [ - "bintools" - "riscv" - "river" - "river_adl" - "river_emulator" - "river_hdl" - ] - ( - pname: - buildDartTest { - inherit - pname - version - pubspecLock - gitHashes - ; - - src = ./.; - packageRoot = "packages/${pname}"; - } - ) - ); + let + flakeverConfig = flakever.lib.mkFlakever { + inherit inputs; - packages = { - default = buildDartApplication { - pname = "river"; - inherit version pubspecLock gitHashes; + digits = [ + 0 + 1 + 0 + ]; + }; + in + flake-parts.lib.mkFlake { inherit inputs; } { + imports = [ + inputs.flake-parts.flakeModules.easyOverlay + inputs.treefmt-nix.flakeModule + ]; - src = ./.; + flake.versionTemplate = "1.1pre--"; - dartEntryPoints = { - "bin/river-emulator" = "packages/river_emulator/bin/river_emulator.dart"; - "bin/river-hdlgen" = "packages/river_hdl/bin/river_hdlgen.dart"; - }; + systems = [ + "aarch64-linux" + "aarch64-darwin" + ]; - preBuild = '' - mkdir -p bin + perSystem = + { + system, + pkgs, + ... + }: + let + inherit (pkgs) lib; + + inherit (pkgs) buildDartApplication; + + inherit (import ./nix/common-dart.nix lib) + pubspecLock + gitHashes + ; + + buildDartTest = + args: + (buildDartApplication ( + args + // { + pname = "${args.pname}-tests"; + + nativeBuildInputs = (args.nativeBuildInputs or [ ]) ++ [ + pkgs.lcov + ]; + + buildPhase = '' + runHook preBuild + mkdir -p $out $out/coverage + + dart --old_gen_heap_size=40960 --packages=.dart_tool/package_config.json --pause-isolates-on-exit --disable-service-auth-codes --enable-vm-service=8181 $(packagePath test)/bin/test.dart $packageRoot --file-reporter=json:$out/report.json -r expanded & + + packageRun coverage -e collect_coverage --wait-paused --uri=http://127.0.0.1:8181/ -o $out/coverage/report.json --resume-isolates --scope-output=${args.pname} + packageRun coverage -e format_coverage --packages=.dart_tool/package_config.json --lcov -i $out/coverage/report.json -o $out/coverage/lcov.info + + if [[ -s $out/coverage/lcov.info ]]; then + genhtml -o $out/coverage/html $out/coverage/lcov.info + fi + + runHook postBuild ''; + + dontInstall = true; + } + )).overrideAttrs + { outputs = [ "out" ]; }; + in + { + _module.args.pkgs = import inputs.nixpkgs { + inherit system; + overlays = [ + inputs.asix.overlays.default + self.overlays.default + ]; + }; + + treefmt.programs = { + dart-format.enable = true; + nixfmt.enable = true; + }; + + # PDKs (sky130-pdk, gf180mcu-pdk) come from asix's overlay, applied + # above in _module.args.pkgs. + overlayAttrs = { + flakever = flakeverConfig; + river-hdl = pkgs.callPackage ./pkgs/river-hdl { }; + }; + + checks = { + formatting = (inputs.treefmt-nix.lib.evalModule pkgs ./treefmt.nix).config.build.check self; + } + // lib.mapAttrs' (name: lib.nameValuePair "${name}-tests") ( + lib.genAttrs + [ + "bintools" + "river" + "river_adl" + "river_emulator" + "river_hdl" + ] + ( + pname: + buildDartTest { + inherit + pname + pubspecLock + gitHashes + ; + inherit (pkgs.flakever) version; + + src = ./.; + packageRoot = "packages/${pname}"; + } + ) + ); + + packages = + let + devices = import ./devices.nix { + inherit (pkgs) river-hdl; + sky130-pdk = pkgs.sky130-pdk or null; + gf180mcu-pdk = pkgs.gf180mcu-pdk or null; }; + + fpgaVendors = [ + "ecp5" + "ice40" + ]; + asicVendors = [ + "sky130" + "gf180mcu" + ]; + + targetVendor = + ip: + let + parts = lib.splitString ":" (ip.target or ""); + in + if parts != [ ] then builtins.head parts else null; + + isFpga = ip: builtins.elem (targetVendor ip) fpgaVendors; + isAsic = ip: builtins.elem (targetVendor ip) asicVendors; + + mkDevicePackages = + name: cfg: + let + inherit (cfg) ip; + tapeout = pkgs.asix.mkTapeout { + name = "${name}-tapeout"; + inherit ip; + inherit (cfg) topCell pdk clockPeriodNs; + }; + in + { + "${name}" = ip; + } + // lib.optionalAttrs (isFpga ip) { + "${name}-bitstream" = pkgs.river-hdl.mkFpga { inherit ip; }; + } + // lib.optionalAttrs (isAsic ip) { + "${name}-tapeout" = tapeout; + "${name}-verify" = pkgs.asix.mkVerify { + name = "${name}-verify"; + inherit tapeout; + }; + }; + in + { + default = pkgs.river-hdl; + hdl = pkgs.river-hdl; emulator = buildDartApplication { pname = "river-emulator"; - inherit version pubspecLock gitHashes; + inherit pubspecLock gitHashes; + inherit (pkgs.flakever) version; src = ./.; packageRoot = "packages/river_emulator"; @@ -142,45 +215,50 @@ mkdir -p bin ''; }; - hdl = buildDartApplication { - pname = "river-hdl"; - inherit version pubspecLock gitHashes; + + # The HDL simulator, exposing the core over an OpenOCD + # remote_bitbang JTAG server (`--remote-bitbang`) so Heimdall can + # drive the real RTL the same way it drives silicon. `jtag-probe` + # is a lightweight bitbang client for smoke-testing the server. + sim = buildDartApplication { + pname = "river-sim"; + inherit pubspecLock gitHashes; + inherit (pkgs.flakever) version; src = ./.; packageRoot = "packages/river_hdl"; - dartEntryPoints."bin/river-hdlgen" = "packages/river_hdl/bin/river_hdlgen.dart"; + dartEntryPoints = { + "bin/river-sim" = "packages/river_hdl/bin/river_sim.dart"; + }; preBuild = '' mkdir -p bin ''; }; - }; - - devShells.default = pkgs.mkShell { - packages = - with pkgs; - ( - [ - yq - dart - yosys - icestorm - nextpnr - gtkwave - surfer - pkgsCross.riscv32-embedded.stdenv.cc - pkgsCross.riscv64-embedded.stdenv.cc - ] - ++ lib.optionals (!stdenv.hostPlatform.isDarwin) [ - icesprog - (openroad.overrideAttrs { - doCheck = !pkgs.stdenv.hostPlatform.isAarch64; - }) - ] - ); - }; + } + // lib.foldl' (acc: name: acc // mkDevicePackages name devices.${name}) { } ( + builtins.attrNames devices + ); + + devShells.default = pkgs.mkShell { + packages = with pkgs; [ + yq + dart + yosys + nextpnr + surfer + # Logic-analyzer capture for the DSLogic U3Pro32 (tier-3 DDR LA). + # sigrok-cli = headless/scriptable on aarch64; pulseview = GUI. + # DSLogic uses libsigrok's dreamsourcelab-dslogic driver. + sigrok-cli + pulseview + pkgsCross.riscv32-embedded.stdenv.cc + pkgsCross.riscv64-embedded.stdenv.cc + ]; }; - } - ); + + legacyPackages = pkgs; + }; + }; } diff --git a/nix/common-dart.nix b/nix/common-dart.nix new file mode 100644 index 0000000..fa8747d --- /dev/null +++ b/nix/common-dart.nix @@ -0,0 +1,7 @@ +lib: { + pubspecLock = lib.importJSON ../pubspec.lock.json; + + gitHashes = { + harbor = "sha256-Mnfls8OTiyFbRe7E3u/SvNDqQocxLpnMQpIDRSkq4uM="; + }; +} diff --git a/packages/bintools/analysis_options.yaml b/packages/bintools/analysis_options.yaml index dee8927..f5d48c9 100644 --- a/packages/bintools/analysis_options.yaml +++ b/packages/bintools/analysis_options.yaml @@ -1,30 +1,2 @@ -# This file configures the static analysis results for your project (errors, -# warnings, and lints). -# -# This enables the 'recommended' set of lints from `package:lints`. -# This set helps identify many issues that may lead to problems when running -# or consuming Dart code, and enforces writing Dart using a single, idiomatic -# style and format. -# -# If you want a smaller set of lints you can change this to specify -# 'package:lints/core.yaml'. These are just the most critical lints -# (the recommended set includes the core lints). -# The core lints are also what is used by pub.dev for scoring packages. - -include: package:lints/recommended.yaml - -# Uncomment the following section to specify additional rules. - -# linter: -# rules: -# - camel_case_types - -# analyzer: -# exclude: -# - path/to/excluded/files/** - -# For more information about the core and recommended set of lints, see -# https://dart.dev/go/core-lints - -# For additional information about configuring this file, see -# https://dart.dev/guides/language/analysis-options +# Inherits the workspace production analysis baseline. +include: ../../analysis_options.yaml diff --git a/packages/bintools/lib/bintools.dart b/packages/bintools/lib/bintools.dart index f80ffa9..f7e8cab 100644 --- a/packages/bintools/lib/bintools.dart +++ b/packages/bintools/lib/bintools.dart @@ -1,4 +1,6 @@ library; -export 'src/bintools_base.dart'; export 'src/elf.dart'; +export 'src/elf_writer.dart'; +export 'src/linker.dart'; +export 'src/section.dart'; diff --git a/packages/bintools/lib/src/bintools_base.dart b/packages/bintools/lib/src/bintools_base.dart deleted file mode 100644 index e8a6f15..0000000 --- a/packages/bintools/lib/src/bintools_base.dart +++ /dev/null @@ -1,6 +0,0 @@ -// TODO: Put public facing types in this file. - -/// Checks if you are awesome. Spoiler: you are. -class Awesome { - bool get isAwesome => true; -} diff --git a/packages/bintools/lib/src/elf.dart b/packages/bintools/lib/src/elf.dart index 52dae93..bbe2177 100644 --- a/packages/bintools/lib/src/elf.dart +++ b/packages/bintools/lib/src/elf.dart @@ -37,7 +37,6 @@ class Elf { case ElfClass.elf64: return reader.load64(endian, enc); case ElfClass.none: - default: throw UnsupportedError('Unsupported ELF class: $klass'); } } @@ -377,9 +376,6 @@ class Elf64ProgramHeader extends ElfProgramHeader { } class Elf32SectionHeader extends ElfSectionHeader { - @override - String? name; - @override final int nameIndex; @@ -425,9 +421,6 @@ class Elf32SectionHeader extends ElfSectionHeader { } class Elf64SectionHeader extends ElfSectionHeader { - @override - String? name; - @override final int nameIndex; diff --git a/packages/bintools/lib/src/elf_writer.dart b/packages/bintools/lib/src/elf_writer.dart new file mode 100644 index 0000000..4cf64b1 --- /dev/null +++ b/packages/bintools/lib/src/elf_writer.dart @@ -0,0 +1,231 @@ +import 'dart:typed_data'; +import 'section.dart'; + +enum ElfWriterClass { elf32, elf64 } + +class ElfWriter { + final ElfWriterClass elfClass; + final int machine; + final int entryPoint; + final Endian endian; + + final List<_ElfWriterSection> _sections = []; + + static const int emRiscV = 0xF3; + + ElfWriter({ + this.elfClass = ElfWriterClass.elf32, + this.machine = emRiscV, + this.entryPoint = 0, + this.endian = Endian.little, + }); + + void addSection(Section section, {int address = 0}) { + _sections.add(_ElfWriterSection(section, address)); + } + + Uint8List write() { + return elfClass == ElfWriterClass.elf32 ? _write32() : _write64(); + } + + Uint8List _write32() { + final ehdrSize = 52; + final shdrSize = 40; + final phdrSize = 32; + + final allSections = <_ElfWriterSection>[ + _ElfWriterSection._null(), + ..._sections, + _ElfWriterSection._shstrtab(_sections), + ]; + + final shstrtabIdx = allSections.length - 1; + final numLoadable = _sections + .where((s) => s.section.type != SectionType.bss) + .length; + + var offset = ehdrSize + phdrSize * numLoadable; + + for (final s in allSections) { + if (s.isNull) continue; + s.fileOffset = offset; + offset += s.data.length; + } + + final totalSize = offset + shdrSize * allSections.length; + final shoff = offset; + + final buf = ByteData(totalSize); + var pos = 0; + + // ELF header + buf.setUint8(pos++, 0x7F); + buf.setUint8(pos++, 0x45); // E + buf.setUint8(pos++, 0x4C); // L + buf.setUint8(pos++, 0x46); // F + buf.setUint8(pos++, 1); // 32-bit + buf.setUint8(pos++, endian == Endian.little ? 1 : 2); + buf.setUint8(pos++, 1); // version + buf.setUint8(pos++, 0); // OS/ABI + for (var i = 0; i < 8; i++) { + buf.setUint8(pos++, 0); // padding + } + buf.setUint16(pos, 2, endian); + pos += 2; // ET_EXEC + buf.setUint16(pos, machine, endian); + pos += 2; + buf.setUint32(pos, 1, endian); + pos += 4; // version + buf.setUint32(pos, entryPoint, endian); + pos += 4; // entry + buf.setUint32(pos, ehdrSize, endian); + pos += 4; // phoff + buf.setUint32(pos, shoff, endian); + pos += 4; // shoff + buf.setUint32(pos, 0, endian); + pos += 4; // flags + buf.setUint16(pos, ehdrSize, endian); + pos += 2; // ehsize + buf.setUint16(pos, phdrSize, endian); + pos += 2; // phentsize + buf.setUint16(pos, numLoadable, endian); + pos += 2; // phnum + buf.setUint16(pos, shdrSize, endian); + pos += 2; // shentsize + buf.setUint16(pos, allSections.length, endian); + pos += 2; // shnum + buf.setUint16(pos, shstrtabIdx, endian); + pos += 2; // shstrndx + + // Program headers (one per loadable section) + for (final s in _sections) { + if (s.section.type == SectionType.bss) continue; + buf.setUint32(pos, 1, endian); + pos += 4; // PT_LOAD + buf.setUint32(pos, s.fileOffset!, endian); + pos += 4; // offset + buf.setUint32(pos, s.address, endian); + pos += 4; // vaddr + buf.setUint32(pos, s.address, endian); + pos += 4; // paddr + buf.setUint32(pos, s.data.length, endian); + pos += 4; // filesz + buf.setUint32(pos, s.data.length, endian); + pos += 4; // memsz + var flags = 4; // PF_R + if (s.section.flags.contains(SectionFlags.write)) flags |= 2; + if (s.section.flags.contains(SectionFlags.execInstr)) flags |= 1; + buf.setUint32(pos, flags, endian); + pos += 4; // flags + buf.setUint32(pos, s.section.alignment, endian); + pos += 4; // align + } + + // Section data + for (final s in allSections) { + if (s.isNull) continue; + final data = s.data; + for (var i = 0; i < data.length; i++) { + buf.setUint8(s.fileOffset! + i, data[i]); + } + } + + // Section headers + pos = shoff; + final shstrtab = allSections[shstrtabIdx]; + + for (final s in allSections) { + final nameOffset = s.isNull + ? 0 + : shstrtab.nameOffsets[s.section.name] ?? 0; + buf.setUint32(pos, nameOffset, endian); + pos += 4; // name + buf.setUint32(pos, s.shType, endian); + pos += 4; // type + buf.setUint32(pos, s.shFlags, endian); + pos += 4; // flags + buf.setUint32(pos, s.isNull ? 0 : s.address, endian); + pos += 4; // addr + buf.setUint32(pos, s.isNull ? 0 : s.fileOffset!, endian); + pos += 4; // offset + buf.setUint32(pos, s.data.length, endian); + pos += 4; // size + buf.setUint32(pos, 0, endian); + pos += 4; // link + buf.setUint32(pos, 0, endian); + pos += 4; // info + buf.setUint32(pos, s.isNull ? 0 : s.section.alignment, endian); + pos += 4; // addralign + buf.setUint32(pos, 0, endian); + pos += 4; // entsize + } + + return buf.buffer.asUint8List(0, totalSize); + } + + Uint8List _write64() { + // Simplified: same structure but with 64-bit fields + // For now, delegate to 32-bit with wider fields + throw UnimplementedError('ELF64 writer not yet implemented'); + } +} + +class _ElfWriterSection { + final Section section; + final int address; + int? fileOffset; + final bool isNull; + final Map nameOffsets; + + _ElfWriterSection(this.section, this.address) + : isNull = false, + nameOffsets = {}; + + _ElfWriterSection._null() + : section = Section(''), + address = 0, + isNull = true, + nameOffsets = {}; + + factory _ElfWriterSection._shstrtab(List<_ElfWriterSection> sections) { + final strtab = Section('.shstrtab', type: SectionType.rodata); + final offsets = {}; + + strtab.emitByte(0); // null string at offset 0 + offsets[''] = 0; + + for (final s in sections) { + offsets[s.section.name] = strtab.size; + strtab.emitString(s.section.name); + } + + offsets['.shstrtab'] = strtab.size; + strtab.emitString('.shstrtab'); + + final result = _ElfWriterSection(strtab, 0); + result.nameOffsets.addAll(offsets); + return result; + } + + Uint8List get data => isNull ? Uint8List(0) : section.bytes; + + int get shType { + if (isNull) return 0; // SHT_NULL + if (section.name == '.shstrtab') return 3; // SHT_STRTAB + return switch (section.type) { + SectionType.text => 1, // SHT_PROGBITS + SectionType.data => 1, + SectionType.rodata => 1, + SectionType.bss => 8, // SHT_NOBITS + }; + } + + int get shFlags { + if (isNull) return 0; + var f = 0; + if (section.flags.contains(SectionFlags.alloc)) f |= 2; // SHF_ALLOC + if (section.flags.contains(SectionFlags.write)) f |= 1; // SHF_WRITE + if (section.flags.contains(SectionFlags.execInstr)) f |= 4; // SHF_EXECINSTR + return f; + } +} diff --git a/packages/bintools/lib/src/linker.dart b/packages/bintools/lib/src/linker.dart new file mode 100644 index 0000000..0ad0288 --- /dev/null +++ b/packages/bintools/lib/src/linker.dart @@ -0,0 +1,224 @@ +import 'dart:typed_data'; +import 'section.dart'; + +class LinkerError implements Exception { + final String message; + const LinkerError(this.message); + @override + String toString() => 'LinkerError: $message'; +} + +class MemoryRegion { + final String name; + final int origin; + final int length; + + const MemoryRegion({ + required this.name, + required this.origin, + required this.length, + }); + + int get end => origin + length; +} + +class LinkerScript { + final int entryPoint; + final List memory; + final Map sectionPlacement; + + const LinkerScript({ + this.entryPoint = 0, + this.memory = const [], + this.sectionPlacement = const {}, + }); +} + +class LinkedBinary { + final Uint8List bytes; + final int entryPoint; + final Map symbolTable; + final int baseAddress; + + const LinkedBinary({ + required this.bytes, + required this.entryPoint, + required this.symbolTable, + required this.baseAddress, + }); +} + +class Linker { + final List
sections = []; + final Map globalSymbols = {}; + + void addSection(Section section) { + sections.add(section); + for (final entry in section.symbols.entries) { + globalSymbols[entry.key] = Symbol( + name: entry.key, + section: section.name, + offset: entry.value, + ); + } + } + + void addGlobalSymbol(Symbol symbol) { + globalSymbols[symbol.name] = symbol; + } + + int resolveSymbol(String name, Map sectionBases) { + final sym = globalSymbols[name]; + if (sym == null) throw LinkerError('Undefined symbol: $name'); + + if (sym.section != null) { + final base = sectionBases[sym.section]; + if (base == null) { + throw LinkerError('Section "${sym.section}" not placed'); + } + return base + sym.offset; + } + + return sym.offset; + } + + LinkedBinary link({LinkerScript script = const LinkerScript()}) { + final sectionBases = {}; + var cursor = script.entryPoint; + + final orderedSections =
[]; + + for (final region in script.memory) { + cursor = region.origin; + for (final section in sections) { + final placement = script.sectionPlacement[section.name]; + if (placement != null && placement != region.name) continue; + if (sectionBases.containsKey(section.name)) continue; + + final rem = cursor % section.alignment; + if (rem != 0) cursor += section.alignment - rem; + + sectionBases[section.name] = cursor; + orderedSections.add(section); + cursor += section.size; + + if (cursor > region.end) { + throw LinkerError( + 'Section "${section.name}" overflows memory region "${region.name}" ' + '(${cursor - region.origin} > ${region.length})', + ); + } + } + } + + for (final section in sections) { + if (sectionBases.containsKey(section.name)) continue; + final rem = cursor % section.alignment; + if (rem != 0) cursor += section.alignment - rem; + sectionBases[section.name] = cursor; + orderedSections.add(section); + cursor += section.size; + } + + final totalSize = cursor - script.entryPoint; + final output = Uint8List(totalSize); + + for (final section in orderedSections) { + if (section.type == SectionType.bss) continue; + + final base = sectionBases[section.name]!; + final offset = base - script.entryPoint; + final data = section.bytes; + output.setRange(offset, offset + data.length, data); + } + + for (final section in orderedSections) { + final sectionBase = sectionBases[section.name]!; + + for (final reloc in section.relocations) { + final target = resolveSymbol(reloc.symbol, sectionBases) + reloc.addend; + final patchOffset = sectionBase - script.entryPoint + reloc.offset; + + switch (reloc.type) { + case RelocationType.abs32: + _patch32(output, patchOffset, target); + + case RelocationType.hi20: + final hi = ((target + 0x800) >> 12) & 0xFFFFF; + final existing = _read32(output, patchOffset); + _patch32(output, patchOffset, (existing & 0xFFF) | (hi << 12)); + + case RelocationType.lo12: + final lo = target & 0xFFF; + final existing = _read32(output, patchOffset); + _patch32(output, patchOffset, (existing & 0xFFFFF) | (lo << 20)); + + case RelocationType.branch: + final pc = sectionBase + reloc.offset; + final offset = target - pc; + final existing = _read32(output, patchOffset); + final b12 = (offset >> 12) & 1; + final b11 = (offset >> 11) & 1; + final b10_5 = (offset >> 5) & 0x3F; + final b4_1 = (offset >> 1) & 0xF; + _patch32( + output, + patchOffset, + (existing & 0x1FFF07F) | + (b12 << 31) | + (b10_5 << 25) | + (b4_1 << 8) | + (b11 << 7), + ); + + case RelocationType.jal: + final pc = sectionBase + reloc.offset; + final offset = target - pc; + final existing = _read32(output, patchOffset); + final b20 = (offset >> 20) & 1; + final b19_12 = (offset >> 12) & 0xFF; + final b11 = (offset >> 11) & 1; + final b10_1 = (offset >> 1) & 0x3FF; + _patch32( + output, + patchOffset, + (existing & 0xFFF) | + (b20 << 31) | + (b10_1 << 21) | + (b11 << 20) | + (b19_12 << 12), + ); + + case RelocationType.pcrel: + final pc = sectionBase + reloc.offset; + _patch32(output, patchOffset, target - pc); + } + } + } + + final resolvedSymbols = {}; + for (final entry in globalSymbols.entries) { + resolvedSymbols[entry.key] = resolveSymbol(entry.key, sectionBases); + } + + return LinkedBinary( + bytes: output, + entryPoint: script.entryPoint, + symbolTable: resolvedSymbols, + baseAddress: script.entryPoint, + ); + } + + static void _patch32(Uint8List data, int offset, int value) { + data[offset] = value & 0xFF; + data[offset + 1] = (value >> 8) & 0xFF; + data[offset + 2] = (value >> 16) & 0xFF; + data[offset + 3] = (value >> 24) & 0xFF; + } + + static int _read32(Uint8List data, int offset) => + data[offset] | + (data[offset + 1] << 8) | + (data[offset + 2] << 16) | + (data[offset + 3] << 24); +} diff --git a/packages/bintools/lib/src/section.dart b/packages/bintools/lib/src/section.dart new file mode 100644 index 0000000..290b46d --- /dev/null +++ b/packages/bintools/lib/src/section.dart @@ -0,0 +1,116 @@ +import 'dart:typed_data'; + +enum SectionType { text, data, rodata, bss } + +enum SectionFlags { alloc, write, execInstr } + +class Section { + final String name; + final SectionType type; + final Set flags; + final int alignment; + final BytesBuilder _data = BytesBuilder(); + final List relocations = []; + final Map symbols = {}; + + int get size => _data.length; + Uint8List get bytes => _data.toBytes(); + + Section( + this.name, { + this.type = SectionType.text, + Set? flags, + this.alignment = 4, + }) : flags = flags ?? _defaultFlags(type); + + static Set _defaultFlags(SectionType type) => switch (type) { + SectionType.text => {SectionFlags.alloc, SectionFlags.execInstr}, + SectionType.data => {SectionFlags.alloc, SectionFlags.write}, + SectionType.rodata => {SectionFlags.alloc}, + SectionType.bss => {SectionFlags.alloc, SectionFlags.write}, + }; + + void emitByte(int value) { + _data.addByte(value & 0xFF); + } + + void emitHalf(int value) { + _data.addByte(value & 0xFF); + _data.addByte((value >> 8) & 0xFF); + } + + void emitWord(int value) { + _data.addByte(value & 0xFF); + _data.addByte((value >> 8) & 0xFF); + _data.addByte((value >> 16) & 0xFF); + _data.addByte((value >> 24) & 0xFF); + } + + void emitDword(int value) { + emitWord(value & 0xFFFFFFFF); + emitWord((value >> 32) & 0xFFFFFFFF); + } + + void emitBytes(List data) { + _data.add(data); + } + + void emitString(String s, {bool nullTerminate = true}) { + _data.add(s.codeUnits); + if (nullTerminate) _data.addByte(0); + } + + void align(int boundary) { + final rem = size % boundary; + if (rem != 0) { + final pad = boundary - rem; + for (var i = 0; i < pad; i++) { + _data.addByte(0); + } + } + } + + void space(int count, {int fill = 0}) { + for (var i = 0; i < count; i++) { + _data.addByte(fill); + } + } + + void addSymbol(String name) { + symbols[name] = size; + } + + void addRelocation(Relocation reloc) { + relocations.add(reloc); + } +} + +enum RelocationType { abs32, branch, jal, hi20, lo12, pcrel } + +class Relocation { + final int offset; + final String symbol; + final RelocationType type; + final int addend; + + const Relocation({ + required this.offset, + required this.symbol, + required this.type, + this.addend = 0, + }); +} + +class Symbol { + final String name; + final String? section; + final int offset; + final bool global; + + const Symbol({ + required this.name, + this.section, + required this.offset, + this.global = false, + }); +} diff --git a/packages/bintools/pubspec.yaml b/packages/bintools/pubspec.yaml index 9288ed5..ebb636c 100644 --- a/packages/bintools/pubspec.yaml +++ b/packages/bintools/pubspec.yaml @@ -5,7 +5,7 @@ resolution: workspace # repository: https://github.com/my_org/my_repo environment: - sdk: ^3.9.4 + sdk: ^3.11.2 # Add regular dependencies here. dependencies: diff --git a/packages/bintools/test/bintools_test.dart b/packages/bintools/test/bintools_test.dart index f35d185..46e8019 100644 --- a/packages/bintools/test/bintools_test.dart +++ b/packages/bintools/test/bintools_test.dart @@ -2,15 +2,253 @@ import 'package:bintools/bintools.dart'; import 'package:test/test.dart'; void main() { - group('A group of tests', () { - final awesome = Awesome(); + group('Section', () { + test('emitByte adds single byte', () { + final s = Section('.data', type: SectionType.data); + s.emitByte(0x42); + expect(s.size, 1); + expect(s.bytes[0], 0x42); + }); + + test('emitWord adds 4 bytes little-endian', () { + final s = Section('.data', type: SectionType.data); + s.emitWord(0xDEADBEEF); + expect(s.size, 4); + expect(s.bytes[0], 0xEF); + expect(s.bytes[1], 0xBE); + expect(s.bytes[2], 0xAD); + expect(s.bytes[3], 0xDE); + }); + + test('emitHalf adds 2 bytes little-endian', () { + final s = Section('.data', type: SectionType.data); + s.emitHalf(0x1234); + expect(s.size, 2); + expect(s.bytes[0], 0x34); + expect(s.bytes[1], 0x12); + }); + + test('emitString adds null-terminated ASCII', () { + final s = Section('.rodata', type: SectionType.rodata); + s.emitString('hello'); + expect(s.size, 6); + expect(s.bytes[5], 0); + }); + + test('align pads to boundary', () { + final s = Section('.text'); + s.emitByte(0x01); + s.align(4); + expect(s.size, 4); + }); + + test('space fills with zeros', () { + final s = Section('.bss', type: SectionType.bss); + s.space(16); + expect(s.size, 16); + }); + + test('symbols track offset', () { + final s = Section('.text'); + s.emitWord(0); + s.addSymbol('func'); + s.emitWord(0); + expect(s.symbols['func'], 4); + }); + + test('default flags by type', () { + expect(Section('.text').flags, { + SectionFlags.alloc, + SectionFlags.execInstr, + }); + expect(Section('.data', type: SectionType.data).flags, { + SectionFlags.alloc, + SectionFlags.write, + }); + expect(Section('.rodata', type: SectionType.rodata).flags, { + SectionFlags.alloc, + }); + }); + }); + + group('Linker', () { + test('resolves symbols across sections', () { + final text = Section('.text'); + text.addSymbol('_start'); + text.emitWord(0); + text.emitWord(0); + + final data = Section('.data', type: SectionType.data); + data.addSymbol('my_var'); + data.emitWord(42); + + final linker = Linker(); + linker.addSection(text); + linker.addSection(data); + + final binary = linker.link( + script: LinkerScript( + entryPoint: 0x1000, + memory: [MemoryRegion(name: 'rom', origin: 0x1000, length: 0x1000)], + ), + ); + + expect(binary.symbolTable['_start'], 0x1000); + expect(binary.symbolTable['my_var'], 0x1008); + expect(binary.bytes.length, 12); + }); + + test('throws on undefined symbol', () { + final text = Section('.text'); + text.addRelocation( + Relocation( + offset: 0, + symbol: 'nonexistent', + type: RelocationType.abs32, + ), + ); + text.emitWord(0); + + final linker = Linker(); + linker.addSection(text); + + expect(() => linker.link(), throwsA(isA())); + }); + + test('abs32 relocation patches correctly', () { + final text = Section('.text'); + text.addRelocation( + Relocation(offset: 0, symbol: 'target', type: RelocationType.abs32), + ); + text.emitWord(0); + + final data = Section('.data', type: SectionType.data); + data.addSymbol('target'); + data.emitWord(0xCAFE); + + final linker = Linker(); + linker.addSection(text); + linker.addSection(data); + + final binary = linker.link(script: LinkerScript(entryPoint: 0x100)); - setUp(() { - // Additional setup goes here. + final patched = + binary.bytes[0] | + (binary.bytes[1] << 8) | + (binary.bytes[2] << 16) | + (binary.bytes[3] << 24); + expect(patched, 0x104); }); - test('First Test', () { - expect(awesome.isAwesome, isTrue); + test('section alignment respected', () { + final text = Section('.text', alignment: 16); + text.emitByte(0x90); + + final data = Section('.data', type: SectionType.data, alignment: 16); + data.emitWord(42); + + final linker = Linker(); + linker.addSection(text); + linker.addSection(data); + + final binary = linker.link(script: LinkerScript(entryPoint: 0)); + expect(binary.symbolTable.isEmpty, true); + expect(binary.bytes.length, 16 + 4); + }); + + test('overflow detection', () { + final text = Section('.text'); + text.space(256); + + final linker = Linker(); + linker.addSection(text); + + expect( + () => linker.link( + script: LinkerScript( + entryPoint: 0, + memory: [MemoryRegion(name: 'rom', origin: 0, length: 128)], + ), + ), + throwsA(isA()), + ); + }); + }); + + group('ElfWriter', () { + test('produces valid ELF32 header', () { + final writer = ElfWriter(entryPoint: 0x80000000); + + final text = Section('.text'); + text.emitWord(0x00000013); // nop (addi x0, x0, 0) + text.emitWord(0x00000013); + writer.addSection(text, address: 0x80000000); + + final elf = writer.write(); + + // Check magic + expect(elf[0], 0x7F); + expect(elf[1], 0x45); // E + expect(elf[2], 0x4C); // L + expect(elf[3], 0x46); // F + + // Check class (32-bit) + expect(elf[4], 1); + + // Check data (little-endian) + expect(elf[5], 1); + + // Verify it can be parsed back + final parsed = Elf.load(elf); + expect(parsed.header.entry, 0x80000000); + expect(parsed.header.machine, ElfWriter.emRiscV); + }); + + test('multiple sections', () { + final writer = ElfWriter(entryPoint: 0x1000); + + final text = Section('.text'); + text.emitWord(0x00000013); + writer.addSection(text, address: 0x1000); + + final data = Section('.data', type: SectionType.data); + data.emitWord(0xDEADBEEF); + writer.addSection(data, address: 0x2000); + + final elf = writer.write(); + final parsed = Elf.load(elf); + + expect( + parsed.sectionHeaders.length, + greaterThanOrEqualTo(3), + ); // null + text + data + shstrtab + }); + + test('section names in shstrtab', () { + final writer = ElfWriter(); + + final text = Section('.text'); + text.emitWord(0); + writer.addSection(text); + + final elf = writer.write(); + final parsed = Elf.load(elf); + + // shstrtab should be the last section + final shstrtab = parsed.sectionHeaders.last; + expect(shstrtab.type, 3); // SHT_STRTAB + }); + + test('round-trip: write then read preserves entry', () { + final writer = ElfWriter(entryPoint: 0x42); + final text = Section('.text'); + text.emitWord(0xCAFEBABE); + writer.addSection(text, address: 0x42); + + final elf = writer.write(); + final parsed = Elf.load(elf); + expect(parsed.header.entry, 0x42); + expect(parsed.header.type, 2); // ET_EXEC }); }); } diff --git a/packages/riscv/.gitignore b/packages/riscv/.gitignore deleted file mode 100644 index b4ce6a4..0000000 --- a/packages/riscv/.gitignore +++ /dev/null @@ -1,9 +0,0 @@ -# https://dart.dev/guides/libraries/private-files -# Created by `dart pub` -.dart_tool/ - -# Avoid committing pubspec.lock for library packages; see -# https://dart.dev/guides/libraries/private-files#pubspeclock. -pubspec.lock - -doc/api diff --git a/packages/riscv/CHANGELOG.md b/packages/riscv/CHANGELOG.md deleted file mode 100644 index effe43c..0000000 --- a/packages/riscv/CHANGELOG.md +++ /dev/null @@ -1,3 +0,0 @@ -## 1.0.0 - -- Initial version. diff --git a/packages/riscv/README.md b/packages/riscv/README.md deleted file mode 100644 index 9ce2dad..0000000 --- a/packages/riscv/README.md +++ /dev/null @@ -1,3 +0,0 @@ -# RISC-V - -A Dart package for the RISC-V ISA. diff --git a/packages/riscv/analysis_options.yaml b/packages/riscv/analysis_options.yaml deleted file mode 100644 index dee8927..0000000 --- a/packages/riscv/analysis_options.yaml +++ /dev/null @@ -1,30 +0,0 @@ -# This file configures the static analysis results for your project (errors, -# warnings, and lints). -# -# This enables the 'recommended' set of lints from `package:lints`. -# This set helps identify many issues that may lead to problems when running -# or consuming Dart code, and enforces writing Dart using a single, idiomatic -# style and format. -# -# If you want a smaller set of lints you can change this to specify -# 'package:lints/core.yaml'. These are just the most critical lints -# (the recommended set includes the core lints). -# The core lints are also what is used by pub.dev for scoring packages. - -include: package:lints/recommended.yaml - -# Uncomment the following section to specify additional rules. - -# linter: -# rules: -# - camel_case_types - -# analyzer: -# exclude: -# - path/to/excluded/files/** - -# For more information about the core and recommended set of lints, see -# https://dart.dev/go/core-lints - -# For additional information about configuring this file, see -# https://dart.dev/guides/language/analysis-options diff --git a/packages/riscv/dartdoc_options.yaml b/packages/riscv/dartdoc_options.yaml deleted file mode 100644 index 43abd2f..0000000 --- a/packages/riscv/dartdoc_options.yaml +++ /dev/null @@ -1,9 +0,0 @@ -dartdoc: - categories: - extensions: - displayName: Extensions - markdown: doc/extensions.md - microcode: - displayName: Microcode - markdown: doc/microcode.md - showUndocumentedCategories: true diff --git a/packages/riscv/doc/extensions.md b/packages/riscv/doc/extensions.md deleted file mode 100644 index ce26096..0000000 --- a/packages/riscv/doc/extensions.md +++ /dev/null @@ -1,12 +0,0 @@ -RISC-V extensions define optional architectural features that can be added to a base ISA to expand functionality, performance, or data-type support. -Each extension listed below is provided as a `RiscVExtension` constant that can be enabled when configuring a decoder, emulator, or microarchitecture implementation. - -These constants encapsulate everything needed for an extension: -- Supported instructions -- Decoding rules -- Microcode sequences -- Privilege requirements -- Structural metadata - -Use these extensions to compose the exact ISA profile your core supports-for example, `rvc + rv32M + rv32i`, or `rv32Atomics + rv64Atomics + rv64i + rv32i`. -Remember that each extension only implements the instructions for the bit size it references. To gain full support, add all variants which apply. diff --git a/packages/riscv/doc/microcode.md b/packages/riscv/doc/microcode.md deleted file mode 100644 index 3031100..0000000 --- a/packages/riscv/doc/microcode.md +++ /dev/null @@ -1 +0,0 @@ -# Microcode diff --git a/packages/riscv/lib/riscv.dart b/packages/riscv/lib/riscv.dart deleted file mode 100644 index bfac457..0000000 --- a/packages/riscv/lib/riscv.dart +++ /dev/null @@ -1,11 +0,0 @@ -library; - -export 'src/extensions.dart'; -export 'src/helpers.dart'; -export 'src/ops.dart'; -export 'src/privilege.dart'; -export 'src/riscv_isa_base.dart'; -export 'src/riscv_isa_decode.dart'; -export 'src/riscv_isa_encode.dart'; -export 'src/rv32i.dart'; -export 'src/rv64i.dart'; diff --git a/packages/riscv/lib/src/extensions.dart b/packages/riscv/lib/src/extensions.dart deleted file mode 100644 index 8c62353..0000000 --- a/packages/riscv/lib/src/extensions.dart +++ /dev/null @@ -1,4 +0,0 @@ -export 'extensions/a.dart'; -export 'extensions/c.dart'; -export 'extensions/m.dart'; -export 'extensions/zicsr.dart'; diff --git a/packages/riscv/lib/src/extensions/a.dart b/packages/riscv/lib/src/extensions/a.dart deleted file mode 100644 index 275a187..0000000 --- a/packages/riscv/lib/src/extensions/a.dart +++ /dev/null @@ -1 +0,0 @@ -export 'a/ops.dart'; diff --git a/packages/riscv/lib/src/extensions/a/ops.dart b/packages/riscv/lib/src/extensions/a/ops.dart deleted file mode 100644 index 2f03d93..0000000 --- a/packages/riscv/lib/src/extensions/a/ops.dart +++ /dev/null @@ -1,457 +0,0 @@ -import '../../ops.dart'; -import '../../riscv_isa_base.dart'; -import '../../riscv_isa_decode.dart'; - -/// RV32A extension -/// -/// {@category extensions} -const rv32Atomics = RiscVExtension( - [ - Operation( - mnemonic: 'lr.w', - opcode: 0x2F, - funct3: 0x2, - funct7: 0x8, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - LoadReservedMicroOp( - MicroOpField.rs1, - MicroOpField.rd, - MicroOpMemSize.word, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'sc.w', - opcode: 0x2F, - funct3: 0x2, - funct7: 0xC, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - StoreConditionalMicroOp( - base: MicroOpField.rs1, - src: MicroOpField.rs2, - dest: MicroOpField.rd, - size: MicroOpMemSize.word, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'amoadd.w', - opcode: 0x2F, - funct3: 0x2, - funct7: 0x0, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AtomicMemoryMicroOp( - funct: MicroOpAtomicFunct.add, - base: MicroOpField.rs1, - src: MicroOpField.rs2, - dest: MicroOpField.rd, - size: MicroOpMemSize.word, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'amoswap.w', - opcode: 0x2F, - funct3: 0x2, - funct7: 0x4, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AtomicMemoryMicroOp( - funct: MicroOpAtomicFunct.swap, - base: MicroOpField.rs1, - src: MicroOpField.rs2, - dest: MicroOpField.rd, - size: MicroOpMemSize.word, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'amoxor.w', - opcode: 0x2F, - funct3: 0x2, - funct7: 0x10, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AtomicMemoryMicroOp( - funct: MicroOpAtomicFunct.xor, - base: MicroOpField.rs1, - src: MicroOpField.rs2, - dest: MicroOpField.rd, - size: MicroOpMemSize.word, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'amoand.w', - opcode: 0x2F, - funct3: 0x2, - funct7: 0x20, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AtomicMemoryMicroOp( - funct: MicroOpAtomicFunct.and, - base: MicroOpField.rs1, - src: MicroOpField.rs2, - dest: MicroOpField.rd, - size: MicroOpMemSize.word, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'amoor.w', - opcode: 0x2F, - funct3: 0x2, - funct7: 0x30, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AtomicMemoryMicroOp( - funct: MicroOpAtomicFunct.or, - base: MicroOpField.rs1, - src: MicroOpField.rs2, - dest: MicroOpField.rd, - size: MicroOpMemSize.word, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'amomin.w', - opcode: 0x2F, - funct3: 0x2, - funct7: 0x40, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AtomicMemoryMicroOp( - funct: MicroOpAtomicFunct.min, - base: MicroOpField.rs1, - src: MicroOpField.rs2, - dest: MicroOpField.rd, - size: MicroOpMemSize.word, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'amomax.w', - opcode: 0x2F, - funct3: 0x2, - funct7: 0x50, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AtomicMemoryMicroOp( - funct: MicroOpAtomicFunct.max, - base: MicroOpField.rs1, - src: MicroOpField.rs2, - dest: MicroOpField.rd, - size: MicroOpMemSize.word, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'amominu.w', - opcode: 0x2F, - funct3: 0x2, - funct7: 0x60, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AtomicMemoryMicroOp( - funct: MicroOpAtomicFunct.minu, - base: MicroOpField.rs1, - src: MicroOpField.rs2, - dest: MicroOpField.rd, - size: MicroOpMemSize.word, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'amomaxu.w', - opcode: 0x2F, - funct3: 0x2, - funct7: 0x70, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AtomicMemoryMicroOp( - funct: MicroOpAtomicFunct.maxu, - base: MicroOpField.rs1, - src: MicroOpField.rs2, - dest: MicroOpField.rd, - size: MicroOpMemSize.word, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - ], - name: 'A', - key: 'A', - mask: 1 << 0, -); - -/// RV64A extension -/// -/// {@category extensions} -const rv64Atomics = RiscVExtension( - [ - Operation( - mnemonic: 'lr.d', - opcode: 0x2F, - funct3: 0x3, - funct7: 0x8, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - LoadReservedMicroOp( - MicroOpField.rs1, - MicroOpField.rd, - MicroOpMemSize.dword, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'sc.d', - opcode: 0x2F, - funct3: 0x3, - funct7: 0xC, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - StoreConditionalMicroOp( - base: MicroOpField.rs1, - src: MicroOpField.rs2, - dest: MicroOpField.rd, - size: MicroOpMemSize.dword, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'amoadd.d', - opcode: 0x2F, - funct3: 0x3, - funct7: 0x0, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AtomicMemoryMicroOp( - funct: MicroOpAtomicFunct.add, - base: MicroOpField.rs1, - src: MicroOpField.rs2, - dest: MicroOpField.rd, - size: MicroOpMemSize.dword, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'amoswap.d', - opcode: 0x2F, - funct3: 0x3, - funct7: 0x4, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AtomicMemoryMicroOp( - funct: MicroOpAtomicFunct.swap, - base: MicroOpField.rs1, - src: MicroOpField.rs2, - dest: MicroOpField.rd, - size: MicroOpMemSize.dword, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'amoxor.d', - opcode: 0x2F, - funct3: 0x3, - funct7: 0x10, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AtomicMemoryMicroOp( - funct: MicroOpAtomicFunct.xor, - base: MicroOpField.rs1, - src: MicroOpField.rs2, - dest: MicroOpField.rd, - size: MicroOpMemSize.dword, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'amoand.d', - opcode: 0x2F, - funct3: 0x3, - funct7: 0x30, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AtomicMemoryMicroOp( - funct: MicroOpAtomicFunct.and, - base: MicroOpField.rs1, - src: MicroOpField.rs2, - dest: MicroOpField.rd, - size: MicroOpMemSize.dword, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'amoor.d', - opcode: 0x2F, - funct3: 0x3, - funct7: 0x20, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AtomicMemoryMicroOp( - funct: MicroOpAtomicFunct.or, - base: MicroOpField.rs1, - src: MicroOpField.rs2, - dest: MicroOpField.rd, - size: MicroOpMemSize.dword, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'amomin.d', - opcode: 0x2F, - funct3: 0x3, - funct7: 0x40, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AtomicMemoryMicroOp( - funct: MicroOpAtomicFunct.min, - base: MicroOpField.rs1, - src: MicroOpField.rs2, - dest: MicroOpField.rd, - size: MicroOpMemSize.dword, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'amomax.d', - opcode: 0x2F, - funct3: 0x3, - funct7: 0x50, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AtomicMemoryMicroOp( - funct: MicroOpAtomicFunct.max, - base: MicroOpField.rs1, - src: MicroOpField.rs2, - dest: MicroOpField.rd, - size: MicroOpMemSize.dword, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'amominu.d', - opcode: 0x2F, - funct3: 0x3, - funct7: 0x60, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AtomicMemoryMicroOp( - funct: MicroOpAtomicFunct.minu, - base: MicroOpField.rs1, - src: MicroOpField.rs2, - dest: MicroOpField.rd, - size: MicroOpMemSize.dword, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'amomaxu.d', - opcode: 0x2F, - funct3: 0x3, - funct7: 0x70, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AtomicMemoryMicroOp( - funct: MicroOpAtomicFunct.maxu, - base: MicroOpField.rs1, - src: MicroOpField.rs2, - dest: MicroOpField.rd, - size: MicroOpMemSize.dword, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - ], - name: 'A', - key: 'A', - mask: 1 << 0, -); diff --git a/packages/riscv/lib/src/extensions/c.dart b/packages/riscv/lib/src/extensions/c.dart deleted file mode 100644 index 2a49524..0000000 --- a/packages/riscv/lib/src/extensions/c.dart +++ /dev/null @@ -1,4 +0,0 @@ -export 'c/decode.dart'; -export 'c/encode.dart'; -export 'c/isa.dart'; -export 'c/ops.dart'; diff --git a/packages/riscv/lib/src/extensions/c/decode.dart b/packages/riscv/lib/src/extensions/c/decode.dart deleted file mode 100644 index 23b9504..0000000 --- a/packages/riscv/lib/src/extensions/c/decode.dart +++ /dev/null @@ -1,134 +0,0 @@ -import '../../helpers.dart'; -import '../../riscv_isa_decode.dart'; -import 'isa.dart'; - -extension CompressedRTypeDecode on CompressedRType { - static CompressedRType decode(int instr) => - CompressedRType.map(CompressedRType.STRUCT.decode(instr)); -} - -extension CompressedITypeDecode on CompressedIType { - static CompressedIType decode(int instr) => - CompressedIType.map(CompressedIType.STRUCT.decode(instr)); -} - -extension CompressedSSTypeDecode on CompressedSSType { - static CompressedSSType decode(int instr) => - CompressedSSType.map(CompressedSSType.STRUCT.decode(instr)); -} - -extension CompressedWITypeDecode on CompressedWIType { - static CompressedWIType decode(int instr) => - CompressedWIType.map(CompressedWIType.STRUCT.decode(instr)); -} - -extension CompressedLTypeDecode on CompressedLType { - static CompressedLType decode(int instr) => - CompressedLType.map(CompressedLType.STRUCT.decode(instr)); -} - -extension CompressedSTypeDecode on CompressedSType { - static CompressedSType decode(int instr) => - CompressedSType.map(CompressedSType.STRUCT.decode(instr)); -} - -extension CompressedATypeDecode on CompressedAType { - static CompressedAType decode(int instr) => - CompressedAType.map(CompressedAType.STRUCT.decode(instr)); -} - -extension CompressedBTypeDecode on CompressedBType { - static CompressedBType decode(int instr) => - CompressedBType.map(CompressedBType.STRUCT.decode(instr)); -} - -extension CompressedJTypeDecode on CompressedJType { - static CompressedJType decode(int instr) => - CompressedJType.map(CompressedJType.STRUCT.decode(instr)); -} - -extension CompressedLwspTypeDecode on CompressedLwspType { - static CompressedLwspType decode(int instr) => - CompressedLwspType.map(CompressedLwspType.STRUCT.decode(instr)); -} - -extension CompressedSwspTypeDecode on CompressedSwspType { - static CompressedSwspType decode(int instr) => - CompressedSwspType.map(CompressedSwspType.STRUCT.decode(instr)); -} - -extension CompressedCbTypeDecode on CompressedCbType { - static CompressedCbType decode(int instr) => - CompressedCbType.map(CompressedCbType.STRUCT.decode(instr)); -} - -extension CompressedInstructionDecode on CompressedInstruction { - static CompressedInstruction decode(int instr) { - final quadrant = BitRange(0, 1).decode(instr); - final funct3 = BitRange(13, 15).decode(instr); - - switch (quadrant) { - case 0: - return _decodeQuadrant0(instr, funct3); - case 1: - return _decodeQuadrant1(instr, funct3); - case 2: - return _decodeQuadrant2(instr, funct3); - default: - throw DecodeException(quadrant, funct3); - } - } - - static CompressedInstruction _decodeQuadrant0(int instr, int funct3) { - switch (funct3) { - case 0: - return CompressedInstruction.wi(CompressedWITypeDecode.decode(instr)); - case 2: - return CompressedInstruction.l(CompressedLTypeDecode.decode(instr)); - case 6: - return CompressedInstruction.s(CompressedSTypeDecode.decode(instr)); - default: - throw DecodeException(0, funct3); - } - } - - static CompressedInstruction _decodeQuadrant1(int instr, int funct3) { - switch (funct3) { - case 0: - case 1: - case 2: - case 3: - return CompressedInstruction.i(CompressedITypeDecode.decode(instr)); - case 4: - final top2 = BitRange(10, 11).decode(instr); - if (top2 == 3) { - return CompressedInstruction.a(CompressedATypeDecode.decode(instr)); - } - return CompressedInstruction.i(CompressedITypeDecode.decode(instr)); - case 5: - return CompressedInstruction.j(CompressedJTypeDecode.decode(instr)); - case 6: - case 7: - return CompressedInstruction.a(CompressedATypeDecode.decode(instr)); - default: - throw DecodeException(1, funct3); - } - } - - static CompressedInstruction _decodeQuadrant2(int instr, int funct3) { - switch (funct3) { - case 0: - return CompressedInstruction.i(CompressedITypeDecode.decode(instr)); - case 2: - return CompressedInstruction.lwsp( - CompressedLwspTypeDecode.decode(instr), - ); - case 4: - return CompressedInstruction.i(CompressedITypeDecode.decode(instr)); - case 6: - return CompressedInstruction.ss(CompressedSSTypeDecode.decode(instr)); - default: - throw DecodeException(2, funct3); - } - } -} diff --git a/packages/riscv/lib/src/extensions/c/encode.dart b/packages/riscv/lib/src/extensions/c/encode.dart deleted file mode 100644 index 25f6746..0000000 --- a/packages/riscv/lib/src/extensions/c/encode.dart +++ /dev/null @@ -1,53 +0,0 @@ -import 'isa.dart'; - -extension CompressedRTypeEncode on CompressedRType { - int encode() => CompressedRType.STRUCT.encode(toMap()); -} - -extension CompressedITypeEncode on CompressedIType { - int encode() => CompressedIType.STRUCT.encode(toMap()); -} - -extension CompressedSSTypeEncode on CompressedSSType { - int encode() => CompressedSSType.STRUCT.encode(toMap()); -} - -extension CompressedWITypeEncode on CompressedWIType { - int encode() => CompressedWIType.STRUCT.encode(toMap()); -} - -extension CompressedLTypeEncode on CompressedLType { - int encode() => CompressedLType.STRUCT.encode(toMap()); -} - -extension CompressedSTypeEncode on CompressedSType { - int encode() => CompressedSType.STRUCT.encode(toMap()); -} - -extension CompressedATypeEncode on CompressedAType { - int encode() => CompressedAType.STRUCT.encode(toMap()); -} - -extension CompressedBTypeEncode on CompressedBType { - int encode() => CompressedBType.STRUCT.encode(toMap()); -} - -extension CompressedJTypeEncode on CompressedJType { - int encode() => CompressedJType.STRUCT.encode(toMap()); -} - -extension CompressedLwspTypeEncode on CompressedLwspType { - int encode() => CompressedLwspType.STRUCT.encode(toMap()); -} - -extension CompressedSwspTypeEncode on CompressedSwspType { - int encode() => CompressedSwspType.STRUCT.encode(toMap()); -} - -extension CompressedCbTypeEncode on CompressedCbType { - int encode() => CompressedCbType.STRUCT.encode(toMap()); -} - -extension CompressedInstructionEncode on CompressedInstruction { - int encode() => struct.encode(toMap()); -} diff --git a/packages/riscv/lib/src/extensions/c/isa.dart b/packages/riscv/lib/src/extensions/c/isa.dart deleted file mode 100644 index f91b371..0000000 --- a/packages/riscv/lib/src/extensions/c/isa.dart +++ /dev/null @@ -1,586 +0,0 @@ -import '../../riscv_isa_base.dart'; -import '../../helpers.dart'; - -const kCompressedRegisterMap = { - CompressedRegister.x8: Register.x8, - CompressedRegister.x9: Register.x9, - CompressedRegister.x10: Register.x10, - CompressedRegister.x11: Register.x11, - CompressedRegister.x12: Register.x12, - CompressedRegister.x13: Register.x13, - CompressedRegister.x14: Register.x14, - CompressedRegister.x15: Register.x15, -}; - -/// Compressed registers -enum CompressedRegister { - x8(8, 's0'), - x9(9, 's1'), - x10(10, 'a0'), - x11(11, 'a1'), - x12(12, 'a2'), - x13(13, 'a3'), - x14(14, 'a4'), - x15(15, 'a5'); - - const CompressedRegister(this.value, this.abi); - - final int value; - final String abi; - - /// Gets the full register - Register get full => kCompressedRegisterMap[this]!; - - /// Gets from the full register - static CompressedRegister? fromFull(Register r) => - kCompressedRegisterMap.map((k, v) => MapEntry(v, k))[r]; -} - -/// Compressed R-Type RISC-V instruction -class CompressedRType extends InstructionType { - final int rs2; - final int rs1; - - const CompressedRType({ - required super.opcode, - required this.rs2, - required this.rs1, - required super.funct4, - }); - - const CompressedRType.map(Map map) - : rs2 = map['rs2']!, - rs1 = map['rs1']!, - super.map(map); - - @override - Map toMap() => { - 'opcode': opcode, - 'rs2': rs2, - 'rs1': rs1, - 'funct4': funct4!, - }; - - static const BitStruct STRUCT = const BitStruct({ - 'opcode': CompressedInstruction.opcodeRange, - 'rs2': const BitRange(2, 6), - 'rs1': const BitRange(7, 11), - 'funct4': const BitRange(12, 15), - }); -} - -/// Compressed I-Type RISC-V instruction -class CompressedIType extends InstructionType { - final int imm4_0; - final int rs1; - final int imm5; - final int funct3; - - const CompressedIType({ - required super.opcode, - required this.imm4_0, - required this.rs1, - required this.imm5, - required this.funct3, - }); - - const CompressedIType.map(Map map) - : imm4_0 = map['imm[4:0]']!, - rs1 = map['rs1']!, - imm5 = map['imm[5]']!, - funct3 = map['funct3']!, - super.map(map); - - @override - int get imm => signExtend(imm5 << 5 | imm4_0, 6); - - @override - Map toMap() => { - 'opcode': opcode, - 'imm[4:0]': imm4_0, - 'rs1': rs1, - 'imm[5]': imm5, - 'funct3': funct3, - }; - - static const BitStruct STRUCT = const BitStruct({ - 'opcode': CompressedInstruction.opcodeRange, - 'imm[4:0]': const BitRange(2, 6), - 'rs1': const BitRange(7, 11), - 'imm[5]': const BitRange.single(12), - 'funct3': const BitRange(13, 15), - }); -} - -/// Compressed SS-Type RISC-V instruction -class CompressedSSType extends InstructionType { - final int rs2; - final int imm; - final int funct3; - - const CompressedSSType({ - required super.opcode, - required this.rs2, - required this.imm, - required this.funct3, - }); - - const CompressedSSType.map(Map map) - : rs2 = map['rs2']!, - imm = map['imm']!, - funct3 = map['funct3']!, - super.map(map); - - @override - Map toMap() => { - 'opcode': opcode, - 'rs2': rs2, - 'imm': imm, - 'funct3': funct3, - }; - - static const BitStruct STRUCT = const BitStruct({ - 'opcode': CompressedInstruction.opcodeRange, - 'rs2': const BitRange(2, 6), - 'imm': const BitRange(7, 12), - 'funct3': const BitRange(13, 15), - }); -} - -/// Compressed WI-Type RISC-V instruction -class CompressedWIType extends InstructionType { - final int _imm; - - final int rd; - final int funct3; - - const CompressedWIType({ - required super.opcode, - required this.rd, - required int imm, - required this.funct3, - }) : _imm = imm; - - const CompressedWIType.map(Map map) - : rd = map['rd']!, - _imm = map['imm']!, - funct3 = map['funct3']!, - super.map(map); - - @override - int get imm => _imm; - - @override - Map toMap() => { - 'opcode': opcode, - 'rd': rd, - 'imm': imm, - 'funct3': funct3, - }; - - static const BitStruct STRUCT = const BitStruct({ - 'opcode': CompressedInstruction.opcodeRange, - 'rd': const BitRange(2, 4), - 'imm': const BitRange(5, 12), - 'funct3': const BitRange(13, 15), - }); -} - -/// Compressed L-Type RISC-V instruction -class CompressedLType extends InstructionType { - final int rd; - final int imm2_6; - final int rs1; - final int imm5_3; - final int funct3; - - const CompressedLType({ - required super.opcode, - required this.rd, - required this.imm2_6, - required this.rs1, - required this.imm5_3, - required this.funct3, - }); - - const CompressedLType.map(Map map) - : rd = map['rd']!, - imm2_6 = map['imm[2:6]']!, - rs1 = map['rs1']!, - imm5_3 = map['imm[5:3]']!, - funct3 = map['funct3']!, - super.map(map); - - @override - int get imm { - final uimm2 = (imm2_6 & 0x1); - final uimm3 = (imm5_3 & 0x1); - final uimm4 = (imm5_3 >> 1) & 0x1; - final uimm5 = (imm5_3 >> 2) & 0x1; - return (uimm5 << 5) | (uimm4 << 4) | (uimm3 << 3) | (uimm2 << 2); - } - - @override - Map toMap() => { - 'opcode': opcode, - 'rd': rd, - 'imm[2:6]': imm2_6, - 'rs1': rs1, - 'imm[5:3]': imm5_3, - 'funct3': funct3, - }; - - static const BitStruct STRUCT = const BitStruct({ - 'opcode': CompressedInstruction.opcodeRange, - 'rd': const BitRange(2, 4), - 'imm[2:6]': const BitRange(5, 6), - 'rs1': const BitRange(7, 9), - 'imm[5:3]': const BitRange(10, 12), - 'funct3': const BitRange(13, 15), - }); -} - -/// Compressed S-Type RISC-V instruction -class CompressedSType extends InstructionType { - final int rs2; - final int imm2_6; - final int rs1; - final int imm5_3; - final int funct3; - - const CompressedSType({ - required super.opcode, - required this.rs2, - required this.imm2_6, - required this.rs1, - required this.imm5_3, - required this.funct3, - }); - - const CompressedSType.map(Map map) - : rs2 = map['rs2']!, - imm2_6 = map['imm[2:6]']!, - rs1 = map['rs1']!, - imm5_3 = map['imm[5:3]']!, - funct3 = map['funct3']!, - super.map(map); - - @override - int get imm { - final uimm2 = (imm2_6 & 0x1); - final uimm3 = (imm5_3 & 0x1); - final uimm4 = (imm5_3 >> 1) & 0x1; - final uimm5 = (imm5_3 >> 2) & 0x1; - return (uimm5 << 5) | (uimm4 << 4) | (uimm3 << 3) | (uimm2 << 2); - } - - @override - Map toMap() => { - 'opcode': opcode, - 'rs2': rs2, - 'imm[2:6]': imm2_6, - 'rs1': rs1, - 'imm[5:3]': imm5_3, - 'funct3': funct3, - }; - - static const BitStruct STRUCT = const BitStruct({ - 'opcode': CompressedInstruction.opcodeRange, - 'rs2': const BitRange(2, 4), - 'imm[2:6]': const BitRange(5, 6), - 'rs1': const BitRange(7, 9), - 'imm[5:3]': const BitRange(10, 12), - 'funct3': const BitRange(13, 15), - }); -} - -/// Compressed A-Type RISC-V instruction -class CompressedAType extends InstructionType { - final int rs2; - final int funct2; - final int rs1; - final int funct6; - - const CompressedAType({ - required super.opcode, - required this.rs2, - required this.funct2, - required this.rs1, - required this.funct6, - }); - - const CompressedAType.map(Map map) - : rs2 = map['rs2']!, - funct2 = map['funct2']!, - rs1 = map['rs1']!, - funct6 = map['funct6']!, - super.map(map); - - @override - Map toMap() => { - 'opcode': opcode, - 'rs2': rs2, - 'funct2': funct2, - 'rs1': rs1, - 'funct6': funct6, - }; - - static const BitStruct STRUCT = const BitStruct({ - 'opcode': CompressedInstruction.opcodeRange, - 'rs2': const BitRange(2, 4), - 'funct2': const BitRange(5, 6), - 'rs1': const BitRange(7, 9), - 'funct6': const BitRange(10, 15), - }); -} - -/// Compressed B-Type RISC-V instruction -class CompressedBType extends InstructionType { - final int offset1; - final int rs1; - final int offset2; - final int funct3; - - const CompressedBType({ - required super.opcode, - required this.offset1, - required this.rs1, - required this.offset2, - required this.funct3, - }); - - const CompressedBType.map(Map map) - : offset1 = map['offset1']!, - rs1 = map['rs1']!, - offset2 = map['offset2']!, - funct3 = map['funct3']!, - super.map(map); - - @override - int get imm => (offset2 << 5) | offset1; - - @override - Map toMap() => { - 'opcode': opcode, - 'offset1': offset1, - 'rs1': rs1, - 'offset2': offset2, - 'funct3': funct3, - }; - - static const BitStruct STRUCT = const BitStruct({ - 'opcode': CompressedInstruction.opcodeRange, - 'offset1': const BitRange(2, 6), - 'rs1': const BitRange(7, 9), - 'offset2': const BitRange(10, 12), - 'funct3': const BitRange(13, 15), - }); -} - -/// Compressed J-Type RISC-V instruction -class CompressedJType extends InstructionType { - final int value; - final int funct3; - - const CompressedJType({ - required super.opcode, - required this.value, - required this.funct3, - }); - - const CompressedJType.map(Map map) - : value = map['value']!, - funct3 = map['funct3']!, - super.map(map); - - @override - int get imm => signExtend(value << 1, 12); - - @override - Map toMap() => { - 'opcode': opcode, - 'value': value, - 'funct3': funct3, - }; - - static const BitStruct STRUCT = const BitStruct({ - 'opcode': CompressedInstruction.opcodeRange, - 'value': const BitRange(2, 12), - 'funct3': const BitRange(13, 15), - }); -} - -class CompressedLwspType extends InstructionType { - final int imm0_4; - final int rd; - final int imm5; - final int funct3; - - const CompressedLwspType({ - required super.opcode, - required this.imm0_4, - required this.rd, - required this.imm5, - required this.funct3, - }); - - const CompressedLwspType.map(Map map) - : imm0_4 = map['imm[0:4]']!, - rd = map['rd']!, - imm5 = map['imm[5]']!, - funct3 = map['funct3']!, - super.map(map); - - @override - int get imm => - ((imm5 & 1) << 5) | - ((imm0_4 >> 4) & 1) << 4 | - ((imm0_4 >> 3) & 1) << 3 | - ((imm0_4 >> 2) & 1) << 2 | - ((imm0_4 >> 0) & 1) << 6; - - @override - Map toMap() => { - 'opcode': opcode, - 'imm[0:4]': imm0_4, - 'rd': rd, - 'imm[5]': imm5, - 'funct3': funct3, - }; - - static const BitStruct STRUCT = const BitStruct({ - 'opcode': CompressedInstruction.opcodeRange, - 'imm[0:4]': const BitRange(2, 6), - 'rd': const BitRange(7, 11), - 'imm[5]': const BitRange.single(12), - 'funct3': const BitRange(13, 15), - }); -} - -class CompressedSwspType extends InstructionType { - final int rs2; - final int _imm; - - const CompressedSwspType({ - required super.opcode, - required this.rs2, - required int imm, - required super.funct3, - }) : _imm = imm; - - const CompressedSwspType.map(Map map) - : rs2 = map['rs2']!, - _imm = map['imm']!, - super.map(map); - - @override - int get imm { - final imm2 = (_imm >> 2) & 1; - final imm3 = (_imm >> 3) & 1; - final imm4 = (_imm >> 4) & 1; - final imm5 = (_imm >> 5) & 1; - final imm6 = (_imm >> 1) & 1; - return (imm6 << 6) | (imm5 << 5) | (imm4 << 4) | (imm3 << 3) | (imm2 << 2); - } - - @override - Map toMap() => { - 'opcode': opcode, - 'rs2': rs2, - 'imm': _imm, - 'funct3': funct3!, - }; - - static const BitStruct STRUCT = const BitStruct({ - 'opcode': CompressedInstruction.opcodeRange, - 'rs2': const BitRange(2, 6), - 'imm': const BitRange(7, 12), - 'funct3': const BitRange(13, 15), - }); -} - -class CompressedCbType extends InstructionType { - final int shamt; - final int shamt5; - final int rs1; - - const CompressedCbType({ - required super.opcode, - required this.shamt, - required this.shamt5, - required super.funct2, - required this.rs1, - required super.funct3, - }); - - const CompressedCbType.map(Map map) - : shamt = map['shamt']!, - rs1 = map['rs1']!, - shamt5 = map['shamt5']!, - super.map(map); - - @override - int get imm => shamt; - - @override - Map toMap() => { - 'opcode': opcode, - 'shamt': shamt, - 'rs1': rs1, - 'funct2': funct2!, - 'shamt5': shamt5, - 'funct3': funct3!, - }; - - static const BitStruct STRUCT = const BitStruct({ - 'opcode': CompressedInstruction.opcodeRange, - 'shamt': const BitRange(2, 7), - 'rs1': const BitRange(7, 10), - 'funct2': const BitRange(10, 11), - 'shamt5': const BitRange.single(12), - 'funct3': const BitRange(13, 15), - }); -} - -/// Compressed RISC-V instruction -class CompressedInstruction { - final InstructionType value; - - const CompressedInstruction.r(CompressedRType r) : value = r; - const CompressedInstruction.i(CompressedIType i) : value = i; - const CompressedInstruction.ss(CompressedSSType ss) : value = ss; - const CompressedInstruction.wi(CompressedWIType wi) : value = wi; - const CompressedInstruction.l(CompressedLType l) : value = l; - const CompressedInstruction.s(CompressedSType s) : value = s; - const CompressedInstruction.a(CompressedAType a) : value = a; - const CompressedInstruction.b(CompressedBType b) : value = b; - const CompressedInstruction.j(CompressedJType j) : value = j; - const CompressedInstruction.lwsp(CompressedLwspType lwsp) : value = lwsp; - const CompressedInstruction.swsp(CompressedSwspType swsp) : value = swsp; - const CompressedInstruction.cb(CompressedCbType cb) : value = cb; - - int get opcode => value.opcode; - Map toMap() => value.toMap(); - - BitStruct get struct { - if (value is CompressedRType) return CompressedRType.STRUCT; - if (value is CompressedIType) return CompressedIType.STRUCT; - if (value is CompressedSSType) return CompressedSSType.STRUCT; - if (value is CompressedWIType) return CompressedWIType.STRUCT; - if (value is CompressedLType) return CompressedLType.STRUCT; - if (value is CompressedSType) return CompressedSType.STRUCT; - if (value is CompressedAType) return CompressedAType.STRUCT; - if (value is CompressedBType) return CompressedBType.STRUCT; - if (value is CompressedJType) return CompressedJType.STRUCT; - if (value is CompressedLwspType) return CompressedLwspType.STRUCT; - if (value is CompressedSwspType) return CompressedSwspType.STRUCT; - if (value is CompressedCbType) return CompressedCbType.STRUCT; - - throw 'Unreachable'; - } - - @override - String toString() => value.toString(); - - static const opcodeRange = const BitRange(0, 1); -} diff --git a/packages/riscv/lib/src/extensions/c/ops.dart b/packages/riscv/lib/src/extensions/c/ops.dart deleted file mode 100644 index 7e8bf06..0000000 --- a/packages/riscv/lib/src/extensions/c/ops.dart +++ /dev/null @@ -1,370 +0,0 @@ -import '../../ops.dart'; -import '../../riscv_isa_base.dart'; -import 'decode.dart'; -import 'isa.dart'; - -/// RVC extension -/// -/// {@category extensions} -const rvc = RiscVExtension( - [ - Operation( - mnemonic: 'c.addi4spn', - opcode: 0x0, - funct3: 0x0, - struct: CompressedWIType.STRUCT, - constructor: CompressedWIType.map, - microcode: [ - ValidateFieldMicroOp(MicroOpCondition.ne, MicroOpField.imm, 0), - AluMicroOp(MicroOpAluFunct.add, MicroOpField.sp, MicroOpField.imm), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu, offset: 8), - UpdatePCMicroOp(MicroOpField.pc, offset: 2), - ], - ), - Operation( - mnemonic: 'c.addi', - opcode: 0x1, - funct3: 0x0, - struct: CompressedIType.STRUCT, - constructor: CompressedIType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - AluMicroOp(MicroOpAluFunct.add, MicroOpField.rs1, MicroOpField.imm), - ModifyLatchMicroOp(MicroOpField.rs1, MicroOpSource.rs1, false), - WriteRegisterMicroOp(MicroOpField.rs1, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 2), - ], - ), - Operation( - mnemonic: 'c.andi', - opcode: 0x1, - funct3: 0x7, - struct: CompressedBType.STRUCT, - constructor: CompressedBType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1, offset: 8), - AluMicroOp(MicroOpAluFunct.and, MicroOpField.rs1, MicroOpField.imm), - ModifyLatchMicroOp(MicroOpField.rs1, MicroOpSource.rs1, false), - WriteRegisterMicroOp(MicroOpField.rs1, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 2), - ], - ), - Operation( - mnemonic: 'c.and', - opcode: 0x1, - funct2: 0x3, - funct6: 0x23, - struct: CompressedAType.STRUCT, - constructor: CompressedAType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1, offset: 8), - ReadRegisterMicroOp(MicroOpField.rs2, offset: 8), - AluMicroOp(MicroOpAluFunct.and, MicroOpField.rs1, MicroOpField.rs2), - ModifyLatchMicroOp(MicroOpField.rs1, MicroOpSource.rs1, false), - WriteRegisterMicroOp(MicroOpField.rs1, MicroOpSource.alu, offset: 8), - UpdatePCMicroOp(MicroOpField.pc, offset: 2), - ], - ), - Operation( - mnemonic: 'c.lw', - opcode: 0x0, - funct3: 0x2, - struct: CompressedLType.STRUCT, - constructor: CompressedLType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1, offset: 8), - MemLoadMicroOp( - base: MicroOpField.rs1, - size: MicroOpMemSize.word, - unsigned: true, - dest: MicroOpField.rs2, - ), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.rs2, offset: 8), - UpdatePCMicroOp(MicroOpField.pc, offset: 2), - ], - ), - Operation( - mnemonic: 'c.sw', - opcode: 0x0, - funct3: 0x6, - struct: CompressedSType.STRUCT, - constructor: CompressedSType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1, offset: 8), - ReadRegisterMicroOp(MicroOpField.rs2, offset: 8), - MemStoreMicroOp( - base: MicroOpField.rs1, - src: MicroOpField.rs2, - size: MicroOpMemSize.word, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 2), - ], - ), - Operation( - mnemonic: 'c.j', - opcode: 0x1, - funct3: 0x5, - struct: CompressedJType.STRUCT, - constructor: CompressedJType.map, - microcode: [ - WriteRegisterMicroOp(MicroOpField.pc, MicroOpSource.imm), - UpdatePCMicroOp(MicroOpField.pc, offsetField: MicroOpField.imm), - ], - ), - Operation( - mnemonic: 'c.li', - opcode: 0x1, - funct3: 0x2, - struct: CompressedIType.STRUCT, - constructor: CompressedIType.map, - microcode: [ - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.imm), - UpdatePCMicroOp(MicroOpField.pc, offset: 2), - ], - ), - Operation( - mnemonic: 'c.jr', - opcode: 0x2, - funct4: 0x8, - struct: CompressedRType.STRUCT, - constructor: CompressedRType.map, - zeroFields: ['rs2'], - nonZeroFields: ['rs1'], - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1, offset: 0), - UpdatePCMicroOp(MicroOpField.rs1, offsetField: MicroOpField.rs1), - ], - ), - Operation( - mnemonic: 'c.mv', - opcode: 0x2, - funct4: 0x8, - struct: CompressedRType.STRUCT, - constructor: CompressedRType.map, - nonZeroFields: ['rs1', 'rs2'], - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs2), - WriteRegisterMicroOp(MicroOpField.rs1, MicroOpSource.rs2), - UpdatePCMicroOp(MicroOpField.pc, offset: 2), - ], - ), - Operation( - mnemonic: 'c.lwsp', - opcode: 0x2, - funct3: 0x2, - struct: CompressedLwspType.STRUCT, - constructor: CompressedLwspType.map, - microcode: [ - MemLoadMicroOp( - base: MicroOpField.sp, - size: MicroOpMemSize.word, - unsigned: true, - dest: MicroOpField.rs1, - ), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.rs1), - UpdatePCMicroOp(MicroOpField.pc, offset: 2), - ], - ), - Operation( - mnemonic: 'c.srli', - opcode: 0x1, - funct2: 0, - funct3: 0x4, - struct: CompressedCbType.STRUCT, - constructor: CompressedCbType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1, offset: 8), - AluMicroOp(MicroOpAluFunct.srl, MicroOpField.rs1, MicroOpField.imm), - ModifyLatchMicroOp(MicroOpField.rs1, MicroOpSource.rs1, false), - WriteRegisterMicroOp(MicroOpField.rs1, MicroOpSource.alu, offset: 8), - UpdatePCMicroOp(MicroOpField.pc, offset: 2), - ], - ), - Operation( - mnemonic: 'c.srai', - opcode: 0x1, - funct2: 1, - funct3: 0x4, - struct: CompressedCbType.STRUCT, - constructor: CompressedCbType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - AluMicroOp(MicroOpAluFunct.sra, MicroOpField.rs1, MicroOpField.imm), - ModifyLatchMicroOp(MicroOpField.rs1, MicroOpSource.rs1, false), - WriteRegisterMicroOp(MicroOpField.rs1, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 2), - ], - ), - Operation( - mnemonic: 'c.sub', - opcode: 0x1, - funct6: 0x4, - struct: CompressedAType.STRUCT, - constructor: CompressedAType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1, offset: 8), - ReadRegisterMicroOp(MicroOpField.rs2, offset: 8), - AluMicroOp(MicroOpAluFunct.sub, MicroOpField.rs1, MicroOpField.rs2), - WriteRegisterMicroOp(MicroOpField.rs1, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 2), - ], - ), - Operation( - mnemonic: 'c.xor', - opcode: 0x1, - funct6: 0x4, - struct: CompressedAType.STRUCT, - constructor: CompressedAType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1, offset: 8), - ReadRegisterMicroOp(MicroOpField.rs2, offset: 8), - AluMicroOp(MicroOpAluFunct.xor, MicroOpField.rs1, MicroOpField.rs2), - WriteRegisterMicroOp(MicroOpField.rs1, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 2), - ], - ), - Operation( - mnemonic: 'c.or', - opcode: 0x1, - funct6: 0x35, - struct: CompressedAType.STRUCT, - constructor: CompressedAType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1, offset: 8), - ReadRegisterMicroOp(MicroOpField.rs2, offset: 8), - AluMicroOp(MicroOpAluFunct.or, MicroOpField.rs1, MicroOpField.rs2), - WriteRegisterMicroOp(MicroOpField.rs1, MicroOpSource.alu, offset: 8), - UpdatePCMicroOp(MicroOpField.pc, offset: 2), - ], - ), - Operation( - mnemonic: 'c.addi16sp', - opcode: 0x1, - funct3: 0x3, - struct: CompressedIType.STRUCT, - constructor: CompressedIType.map, - zeroFields: ['rs1'], - microcode: [ - AluMicroOp(MicroOpAluFunct.add, MicroOpField.sp, MicroOpField.imm), - WriteRegisterMicroOp(MicroOpField.sp, MicroOpSource.alu, offset: 8), - UpdatePCMicroOp(MicroOpField.pc, offset: 2), - ], - ), - Operation( - mnemonic: 'c.lui', - opcode: 0x1, - funct3: 0x3, - struct: CompressedIType.STRUCT, - constructor: CompressedIType.map, - nonZeroFields: ['rs1'], - microcode: [ - SetFieldMicroOp(MicroOpField.rs1, 12), - AluMicroOp(MicroOpAluFunct.sll, MicroOpField.imm, MicroOpField.rs1), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu, offset: 8), - UpdatePCMicroOp(MicroOpField.pc, offset: 2), - ], - ), - Operation( - mnemonic: 'c.beqz', - opcode: 0x1, - funct3: 0x6, - struct: CompressedBType.STRUCT, - constructor: CompressedBType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1, offset: 8), - BranchIfMicroOp( - MicroOpCondition.eq, - MicroOpSource.rs1, - offsetField: MicroOpField.imm, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 2), - ], - ), - Operation( - mnemonic: 'c.bnez', - opcode: 0x1, - funct3: 0x7, - struct: CompressedBType.STRUCT, - constructor: CompressedBType.map, - microcode: [ - BranchIfMicroOp( - MicroOpCondition.ne, - MicroOpSource.rs1, - offsetField: MicroOpField.imm, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 2), - ], - ), - Operation( - mnemonic: 'c.slli', - opcode: 0x2, - funct3: 0x0, - struct: CompressedIType.STRUCT, - constructor: CompressedIType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1, offset: 8), - AluMicroOp(MicroOpAluFunct.sll, MicroOpField.rs1, MicroOpField.imm), - WriteRegisterMicroOp(MicroOpField.rs1, MicroOpSource.alu, offset: 8), - UpdatePCMicroOp(MicroOpField.pc, offset: 2), - ], - ), - Operation( - mnemonic: 'c.jalr', - opcode: 0x2, - funct4: 0x9, - struct: CompressedRType.STRUCT, - constructor: CompressedRType.map, - zeroFields: ['rs2'], - nonZeroFields: ['rs1'], - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - WriteLinkRegisterMicroOp(link: MicroOpLink.ra, pcOffset: 2), - UpdatePCMicroOp(MicroOpField.rs1, offsetField: MicroOpField.rs1), - ], - ), - Operation( - mnemonic: 'c.add', - opcode: 0x2, - funct4: 0x9, - struct: CompressedRType.STRUCT, - constructor: CompressedRType.map, - nonZeroFields: ['rs1', 'rs2'], - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AluMicroOp(MicroOpAluFunct.add, MicroOpField.rs1, MicroOpField.rs2), - ModifyLatchMicroOp(MicroOpField.rs1, MicroOpSource.rs1, false), - WriteRegisterMicroOp(MicroOpField.rs1, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 2), - ], - ), - Operation( - mnemonic: 'c.ebreak', - opcode: 0x2, - funct3: 0x4, - struct: CompressedRType.STRUCT, - constructor: CompressedRType.map, - zeroFields: ['rs1', 'rs2'], - microcode: [TrapMicroOp.one(Trap.breakpoint)], - ), - Operation( - mnemonic: 'c.swsp', - opcode: 0x2, - funct3: 0x6, - struct: CompressedSwspType.STRUCT, - constructor: CompressedSwspType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs2), - MemStoreMicroOp( - base: MicroOpField.sp, - src: MicroOpField.rs2, - size: MicroOpMemSize.word, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 2), - ], - ), - ], - mask: 1 << 2, - name: 'RVC', - key: 'C', -); diff --git a/packages/riscv/lib/src/extensions/m.dart b/packages/riscv/lib/src/extensions/m.dart deleted file mode 100644 index 509df62..0000000 --- a/packages/riscv/lib/src/extensions/m.dart +++ /dev/null @@ -1 +0,0 @@ -export 'm/ops.dart'; diff --git a/packages/riscv/lib/src/extensions/m/ops.dart b/packages/riscv/lib/src/extensions/m/ops.dart deleted file mode 100644 index 29a1e29..0000000 --- a/packages/riscv/lib/src/extensions/m/ops.dart +++ /dev/null @@ -1,220 +0,0 @@ -import '../../ops.dart'; -import '../../riscv_isa_base.dart'; -import '../../riscv_isa_decode.dart'; - -/// RV32M extension -/// -/// {@category extensions} -const rv32M = RiscVExtension( - [ - Operation( - mnemonic: 'mul', - opcode: 0x33, - funct3: 0x0, - funct7: 0x01, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AluMicroOp(MicroOpAluFunct.mul, MicroOpField.rs1, MicroOpField.rs2), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'mulh', - opcode: 0x33, - funct3: 0x1, - funct7: 0x01, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AluMicroOp(MicroOpAluFunct.mulh, MicroOpField.rs1, MicroOpField.rs2), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'mulhsu', - opcode: 0x33, - funct3: 0x2, - funct7: 0x01, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AluMicroOp(MicroOpAluFunct.mulhsu, MicroOpField.rs1, MicroOpField.rs2), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'mulhu', - opcode: 0x33, - funct3: 0x3, - funct7: 0x01, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AluMicroOp(MicroOpAluFunct.mulhu, MicroOpField.rs1, MicroOpField.rs2), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'div', - opcode: 0x33, - funct3: 0x4, - funct7: 0x01, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AluMicroOp(MicroOpAluFunct.div, MicroOpField.rs1, MicroOpField.rs2), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'divu', - opcode: 0x33, - funct3: 0x5, - funct7: 0x01, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AluMicroOp(MicroOpAluFunct.divu, MicroOpField.rs1, MicroOpField.rs2), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'rem', - opcode: 0x33, - funct3: 0x6, - funct7: 0x01, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AluMicroOp(MicroOpAluFunct.rem, MicroOpField.rs1, MicroOpField.rs2), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'remu', - opcode: 0x33, - funct3: 0x7, - funct7: 0x01, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AluMicroOp(MicroOpAluFunct.remu, MicroOpField.rs1, MicroOpField.rs2), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - ], - name: 'M', - key: 'M', - mask: 1 << 12, -); - -/// RV64M extension -/// -/// {@category extensions} -const rv64M = RiscVExtension( - [ - Operation( - mnemonic: 'mulw', - opcode: 0x3B, - funct3: 0x0, - funct7: 0x01, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AluMicroOp(MicroOpAluFunct.mulw, MicroOpField.rs1, MicroOpField.rs2), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'divw', - opcode: 0x3B, - funct3: 0x4, - funct7: 0x01, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AluMicroOp(MicroOpAluFunct.divw, MicroOpField.rs1, MicroOpField.rs2), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'divuw', - opcode: 0x3B, - funct3: 0x5, - funct7: 0x01, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AluMicroOp(MicroOpAluFunct.divuw, MicroOpField.rs1, MicroOpField.rs2), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'remw', - opcode: 0x3B, - funct3: 0x6, - funct7: 0x01, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AluMicroOp(MicroOpAluFunct.remw, MicroOpField.rs1, MicroOpField.rs2), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'remuw', - opcode: 0x3B, - funct3: 0x7, - funct7: 0x01, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AluMicroOp(MicroOpAluFunct.remuw, MicroOpField.rs1, MicroOpField.rs2), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - ], - name: 'M', - key: 'M', - mask: 1 << 12, -); diff --git a/packages/riscv/lib/src/extensions/zicsr.dart b/packages/riscv/lib/src/extensions/zicsr.dart deleted file mode 100644 index 27ca41a..0000000 --- a/packages/riscv/lib/src/extensions/zicsr.dart +++ /dev/null @@ -1,4 +0,0 @@ -export 'zicsr/decode.dart'; -export 'zicsr/encode.dart'; -export 'zicsr/isa.dart'; -export 'zicsr/ops.dart'; diff --git a/packages/riscv/lib/src/extensions/zicsr/decode.dart b/packages/riscv/lib/src/extensions/zicsr/decode.dart deleted file mode 100644 index 9378f4d..0000000 --- a/packages/riscv/lib/src/extensions/zicsr/decode.dart +++ /dev/null @@ -1,13 +0,0 @@ -import '../../helpers.dart'; -import '../../riscv_isa_decode.dart'; -import 'isa.dart'; - -extension SystemITypeDecode on SystemIType { - static SystemIType decode(int instr) => - SystemIType.map(SystemIType.STRUCT.decode(instr)); -} - -extension SystemRTypeDecode on SystemRType { - static SystemRType decode(int instr) => - SystemRType.map(SystemRType.STRUCT.decode(instr)); -} diff --git a/packages/riscv/lib/src/extensions/zicsr/encode.dart b/packages/riscv/lib/src/extensions/zicsr/encode.dart deleted file mode 100644 index 83487a6..0000000 --- a/packages/riscv/lib/src/extensions/zicsr/encode.dart +++ /dev/null @@ -1,9 +0,0 @@ -import 'isa.dart'; - -extension SystemITypeEncode on SystemIType { - int encode() => SystemIType.STRUCT.encode(toMap()); -} - -extension SystemRTypeEncode on SystemRType { - int encode() => SystemRType.STRUCT.encode(toMap()); -} diff --git a/packages/riscv/lib/src/extensions/zicsr/isa.dart b/packages/riscv/lib/src/extensions/zicsr/isa.dart deleted file mode 100644 index 41e7ddc..0000000 --- a/packages/riscv/lib/src/extensions/zicsr/isa.dart +++ /dev/null @@ -1,185 +0,0 @@ -import '../../riscv_isa_base.dart'; -import '../../helpers.dart'; - -enum CsrAddress { - ustatus(0x000), - uie(0x004), - utvec(0x005), - uscratch(0x040), - uepc(0x041), - ucause(0x042), - utval(0x043), - uip(0x044), - - sstatus(0x100), - sedeleg(0x102), - sideleg(0x103), - sie(0x104), - stvec(0x105), - scounteren(0x106), - - sscratch(0x140), - sepc(0x141), - scause(0x142), - stval(0x143), - sip(0x144), - - satp(0x180), - - mvendorid(0xF11), - marchid(0xF12), - mimpid(0xF13), - mhartid(0xF14), - - mstatus(0x300), - misa(0x301), - medeleg(0x302), - mideleg(0x303), - mie(0x304), - mtvec(0x305), - mcounteren(0x306), - - mscratch(0x340), - mepc(0x341), - mcause(0x342), - mtval(0x343), - mip(0x344), - pmpcfg0(0x3A0), - pmpcfg1(0x3A1), - pmpcfg2(0x3A2), - pmpcfg3(0x3A3), - pmpaddr0(0x3B0), - pmpaddr1(0x3B1), - pmpaddr2(0x3B2), - pmpaddr3(0x3B3), - pmpaddr4(0x3B4), - pmpaddr5(0x3B5), - pmpaddr6(0x3B6), - pmpaddr7(0x3B7), - - mcycle(0xB00), - minstret(0xB02), - mhpmcounter3(0xB03), - mhpmcounter4(0xB04), - mhpmcounter5(0xB05), - mhpmcounter6(0xB06), - mhpmcounter7(0xB07), - mhpmcounter8(0xB08), - mhpmcounter9(0xB09), - mhpmcounter10(0xB0A), - mhpmcounter11(0xB0B), - - mcycleh(0xB80), - minstreth(0xB82), - - mhpmevent3(0x323), - mhpmevent4(0x324), - mhpmevent5(0x325), - mhpmevent6(0x326), - mhpmevent7(0x327), - mhpmevent8(0x328), - mhpmevent9(0x329), - mhpmevent10(0x32A), - mhpmevent11(0x32B); - - const CsrAddress(this.address); - - final int address; - - static CsrAddress? find(int addr) { - for (final csr in CsrAddress.values) { - if (csr.address == addr) return csr; - } - - return null; - } -} - -class SystemIType extends InstructionType { - final int _imm; - - final int rd; - final int rs1; - - const SystemIType({ - required super.opcode, - required this.rd, - required super.funct3, - required this.rs1, - required int imm, - }) : _imm = imm; - - const SystemIType.map(Map map) - : rd = map['rd']!, - rs1 = map['rs1']!, - _imm = map['imm']!, - super.map(map); - - @override - int get imm => _imm; - - @override - Map toMap() => { - 'opcode': opcode, - 'rd': rd, - 'funct3': funct3!, - 'rs1': rs1, - 'imm': imm, - }; - - @override - String toString() => - 'SystemIType(opcode: $opcode, rd: $rd, funct3: $funct3, rs1: $rs1, imm: $imm)'; - - static const BitStruct STRUCT = BitStruct({ - 'opcode': Instruction.opcodeRange, - 'rd': BitRange(7, 11), - 'funct3': BitRange(12, 14), - 'rs1': BitRange(15, 19), - 'imm': BitRange(20, 31), - }); -} - -class SystemRType extends InstructionType { - final int rd; - final int rs1; - final int rs2; - - const SystemRType({ - required super.opcode, - required this.rd, - required super.funct3, - required this.rs1, - required this.rs2, - required super.funct7, - }); - - const SystemRType.map(Map map) - : rd = map['rd']!, - rs1 = map['rs1']!, - rs2 = map['rs2']!, - super.map(map); - - @override - Map toMap() => { - 'opcode': opcode, - 'rd': rd, - 'funct3': funct3!, - 'rs1': rs1, - 'rs2': rs2, - 'funct7': funct7!, - }; - - @override - String toString() => - 'SystemRType(opcode: $opcode, rd: $rd, funct3: $funct3, rs1: $rs1, rs2: $rs2, funct7: $funct7)'; - - static const BitStruct STRUCT = BitStruct({ - 'opcode': Instruction.opcodeRange, - 'rd': BitRange(7, 11), - 'funct3': BitRange(12, 14), - 'rs1': BitRange(15, 19), - 'rs2': BitRange(20, 24), - 'funct7': BitRange(25, 31), - }); -} diff --git a/packages/riscv/lib/src/extensions/zicsr/ops.dart b/packages/riscv/lib/src/extensions/zicsr/ops.dart deleted file mode 100644 index 827f3ff..0000000 --- a/packages/riscv/lib/src/extensions/zicsr/ops.dart +++ /dev/null @@ -1,106 +0,0 @@ -import '../../ops.dart'; -import '../../riscv_isa_base.dart'; -import 'decode.dart'; -import 'isa.dart'; - -/// 32-bit Zicsr extension -/// -/// {@category extensions} -const rv32Zicsr = RiscVExtension( - [ - Operation( - mnemonic: 'csrrw', - opcode: 0x73, - funct3: 0x1, - struct: SystemIType.STRUCT, - constructor: SystemIType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadCsrMicroOp(MicroOpField.imm), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.imm), - ModifyLatchMicroOp(MicroOpField.imm, MicroOpSource.imm, false), - WriteCsrMicroOp(MicroOpField.imm, MicroOpSource.rs1), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'csrrs', - opcode: 0x73, - funct3: 0x2, - struct: SystemIType.STRUCT, - constructor: SystemIType.map, - microcode: [ - ReadCsrMicroOp(MicroOpField.imm), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.imm), - ReadRegisterMicroOp(MicroOpField.rs1), - AluMicroOp(MicroOpAluFunct.or, MicroOpField.imm, MicroOpField.rs1), - ModifyLatchMicroOp(MicroOpField.imm, MicroOpSource.imm, false), - WriteCsrMicroOp(MicroOpField.imm, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'csrrc', - opcode: 0x73, - funct3: 0x3, - struct: SystemIType.STRUCT, - constructor: SystemIType.map, - microcode: [ - ReadCsrMicroOp(MicroOpField.imm), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.imm), - ReadRegisterMicroOp(MicroOpField.rs1), - BranchIfMicroOp(MicroOpCondition.eq, MicroOpSource.rs1, offset: 2), - AluMicroOp(MicroOpAluFunct.masked, MicroOpField.imm, MicroOpField.rs1), - ModifyLatchMicroOp(MicroOpField.imm, MicroOpSource.imm, false), - WriteCsrMicroOp(MicroOpField.imm, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'csrrwi', - opcode: 0x73, - funct3: 0x5, - struct: SystemIType.STRUCT, - constructor: SystemIType.map, - microcode: [ - ReadCsrMicroOp(MicroOpField.imm), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.imm), - ModifyLatchMicroOp(MicroOpField.imm, MicroOpSource.imm, false), - WriteCsrMicroOp(MicroOpField.imm, MicroOpSource.rs1), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'csrrsi', - opcode: 0x73, - funct3: 0x6, - struct: SystemIType.STRUCT, - constructor: SystemIType.map, - microcode: [ - ReadCsrMicroOp(MicroOpField.imm), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.imm), - AluMicroOp(MicroOpAluFunct.or, MicroOpField.imm, MicroOpField.rs1), - ModifyLatchMicroOp(MicroOpField.imm, MicroOpSource.imm, false), - WriteCsrMicroOp(MicroOpField.imm, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'csrrci', - opcode: 0x73, - funct3: 0x7, - struct: SystemIType.STRUCT, - constructor: SystemIType.map, - microcode: [ - ReadCsrMicroOp(MicroOpField.imm), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.imm), - AluMicroOp(MicroOpAluFunct.masked, MicroOpField.imm, MicroOpField.rs1), - ModifyLatchMicroOp(MicroOpField.imm, MicroOpSource.imm, false), - WriteCsrMicroOp(MicroOpField.imm, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - ], - name: 'Zicsr', - key: '_zicsr', -); diff --git a/packages/riscv/lib/src/helpers.dart b/packages/riscv/lib/src/helpers.dart deleted file mode 100644 index d20fb8e..0000000 --- a/packages/riscv/lib/src/helpers.dart +++ /dev/null @@ -1,104 +0,0 @@ -class BitRange { - final int start; - final int end; - - const BitRange(this.start, this.end) - : assert(start <= end, 'start must be greater than or equal to end'); - const BitRange.single(this.start) : end = start; - - int get width => end - start + 1; - int get mask => (1 << width) - 1; - - BigInt get bigMask => (BigInt.one << width) - BigInt.one; - - int encode(int value) => (value & mask) << start; - int decode(int value) => (value >> start) & mask; - - BigInt bigEncode(BigInt value) => (value & bigMask) << start; - BigInt bigDecode(BigInt value) => (value >> start) & bigMask; - - @override - String toString() => 'BitRange($start, $end)'; -} - -class BitStruct { - final Map mapping; - - const BitStruct(this.mapping); - - Map decode(int value) { - final result = {}; - mapping.forEach((name, range) { - result[name] = range!.decode(value); - }); - return result; - } - - int encode(Map fields) { - int result = 0; - fields.forEach((name, val) { - final range = mapping[name]; - result |= range!.encode(val); - }); - return result; - } - - Map bigDecode(BigInt value) { - final result = {}; - mapping.forEach((name, range) { - result[name] = range!.bigDecode(value).toInt(); - }); - return result; - } - - BigInt bigEncode(Map fields) { - BigInt result = BigInt.zero; - fields.forEach((name, val) { - final range = mapping[name]; - result |= range!.bigEncode(BigInt.from(val)); - }); - return result; - } - - int getField(int value, String name) { - final range = mapping[name]; - return range!.decode(value); - } - - int setField(int value, String name, int fieldValue) { - final range = mapping[name]; - value &= ~(range!.mask << range!.start); - value |= range!.encode(fieldValue); - return value; - } - - int get mask { - var map = {}; - for (final field in mapping.entries) { - map[field.key] = field.value.mask; - } - return encode(map); - } - - int get width { - var i = 0; - mapping.forEach((name, val) { - i = (val.end + 1) > i ? (val.end + 1) : i; - }); - return i; - } - - @override - String toString() => 'BitStruct($mapping)'; -} - -int signExtend(int value, int bits) { - final mask = (1 << bits) - 1; - value &= mask; - final signBit = 1 << (bits - 1); - if ((value & signBit) != 0) { - return value | ~mask; - } else { - return value; - } -} diff --git a/packages/riscv/lib/src/ops.dart b/packages/riscv/lib/src/ops.dart deleted file mode 100644 index d343984..0000000 --- a/packages/riscv/lib/src/ops.dart +++ /dev/null @@ -1,1637 +0,0 @@ -import 'helpers.dart'; -import 'riscv_isa_base.dart'; - -/// Full table mapping micro-op funct -> encoder/decoder. -const kMicroOpTable = [ - MicroOpEncoding( - funct: WriteCsrMicroOp.funct, - struct: WriteCsrMicroOp.struct, - constructor: WriteCsrMicroOp.map, - ), - MicroOpEncoding( - funct: ReadRegisterMicroOp.funct, - struct: ReadRegisterMicroOp.struct, - constructor: ReadRegisterMicroOp.map, - ), - MicroOpEncoding( - funct: WriteRegisterMicroOp.funct, - struct: WriteRegisterMicroOp.struct, - constructor: WriteRegisterMicroOp.map, - ), - MicroOpEncoding( - funct: ModifyLatchMicroOp.funct, - struct: ModifyLatchMicroOp.struct, - constructor: ModifyLatchMicroOp.map, - ), - MicroOpEncoding( - funct: AluMicroOp.funct, - struct: AluMicroOp.struct, - constructor: AluMicroOp.map, - ), - MicroOpEncoding( - funct: BranchIfMicroOp.funct, - struct: BranchIfMicroOp.struct, - constructor: BranchIfMicroOp.map, - ), - MicroOpEncoding( - funct: UpdatePCMicroOp.funct, - struct: UpdatePCMicroOp.struct, - constructor: UpdatePCMicroOp.map, - ), - MicroOpEncoding( - funct: MemLoadMicroOp.funct, - struct: MemLoadMicroOp.struct, - constructor: MemLoadMicroOp.map, - ), - MicroOpEncoding( - funct: MemStoreMicroOp.funct, - struct: MemStoreMicroOp.struct, - constructor: MemStoreMicroOp.map, - ), - MicroOpEncoding( - funct: TrapMicroOp.funct, - struct: TrapMicroOp.struct, - constructor: TrapMicroOp.map, - ), - MicroOpEncoding( - funct: TlbFenceMicroOp.funct, - struct: TlbFenceMicroOp.struct, - constructor: TlbFenceMicroOp.map, - ), - MicroOpEncoding( - funct: TlbInvalidateMicroOp.funct, - struct: TlbInvalidateMicroOp.struct, - constructor: TlbInvalidateMicroOp.map, - ), - MicroOpEncoding( - funct: FenceMicroOp.funct, - struct: FenceMicroOp.struct, - constructor: FenceMicroOp.map, - ), - MicroOpEncoding( - funct: ReturnMicroOp.funct, - struct: ReturnMicroOp.struct, - constructor: ReturnMicroOp.map, - ), - MicroOpEncoding( - funct: WriteLinkRegisterMicroOp.funct, - struct: WriteLinkRegisterMicroOp.struct, - constructor: WriteLinkRegisterMicroOp.map, - ), - MicroOpEncoding( - funct: InterruptHoldMicroOp.funct, - struct: InterruptHoldMicroOp.struct, - constructor: InterruptHoldMicroOp.map, - ), - MicroOpEncoding( - funct: LoadReservedMicroOp.funct, - struct: LoadReservedMicroOp.struct, - constructor: LoadReservedMicroOp.map, - ), - MicroOpEncoding( - funct: StoreConditionalMicroOp.funct, - struct: StoreConditionalMicroOp.struct, - constructor: StoreConditionalMicroOp.map, - ), - MicroOpEncoding( - funct: AtomicMemoryMicroOp.funct, - struct: AtomicMemoryMicroOp.struct, - constructor: AtomicMemoryMicroOp.map, - ), - MicroOpEncoding( - funct: ValidateFieldMicroOp.funct, - struct: ValidateFieldMicroOp.struct, - constructor: ValidateFieldMicroOp.map, - ), - MicroOpEncoding( - funct: SetFieldMicroOp.funct, - struct: SetFieldMicroOp.struct, - constructor: SetFieldMicroOp.map, - ), - MicroOpEncoding( - funct: ReadCsrMicroOp.funct, - struct: ReadCsrMicroOp.struct, - constructor: ReadCsrMicroOp.map, - ), -]; - -/// {@category microcode} -class MicroOpEncoding { - final int funct; - final BitStruct Function(Mxlen) struct; - final T Function(Map) constructor; - - const MicroOpEncoding({ - required this.funct, - required this.struct, - required this.constructor, - }); - - BigInt encode(T op, Mxlen mxlen) => struct(mxlen).bigEncode(op.toMap()); - - T decode(BigInt value, Mxlen mxlen) => - constructor(struct(mxlen).bigDecode(value)); -} - -/// {@category microcode} -sealed class MicroOp { - const MicroOp(); - - Map toMap() => {}; - - static const functRange = BitRange(0, 4); -} - -/// {@category microcode} -enum MicroOpCondition { - eq(0), - ne(1), - lt(2), - gt(3), - ge(4), - le(5); - - const MicroOpCondition(this.value); - - final int value; - - static const int width = 3; -} - -/// {@category microcode} -enum MicroOpAluFunct { - add(0), - sub(1), - mul(2), - and(3), - or(4), - xor(5), - sll(6), - srl(7), - sra(8), - slt(9), - sltu(10), - masked(11), - mulh(12), - mulhsu(13), - mulhu(14), - div(15), - divu(16), - rem(17), - remu(18), - mulw(19), - divw(20), - divuw(21), - remw(22), - remuw(23); - - const MicroOpAluFunct(this.value); - - final int value; - - static const int width = 5; -} - -/// {@category microcode} -enum MicroOpAtomicFunct { - add(0), - swap(1), - xor(2), - and(3), - or(4), - min(5), - max(6), - minu(7), - maxu(8); - - const MicroOpAtomicFunct(this.value); - - final int value; - - static const int width = 4; -} - -/// {@category microcode} -enum MicroOpSource { - alu(0), - imm(1), - rs1(2), - rs2(3), - sp(4), - rd(5), - pc(6); - - const MicroOpSource(this.value); - - final int value; - - static const int width = 3; -} - -/// {@category microcode} -enum MicroOpField { - rd(0), - rs1(1), - rs2(2), - imm(3), - pc(4), - sp(5); - - const MicroOpField(this.value); - - final int value; - - static const int width = 3; -} - -/// {@category microcode} -enum MicroOpLink { - ra(0, Register.x1, null), - rd(1, null, MicroOpSource.rd); - - const MicroOpLink(this.value, this.reg, this.source); - - final int value; - final Register? reg; - final MicroOpSource? source; - - static const int width = 1; -} - -/// {@category microcode} -enum MicroOpMemSize { - byte(0, 1), - half(1, 2), - word(2, 4), - dword(3, 8); - - const MicroOpMemSize(this.value, this.bytes); - - final int value; - final int bytes; - - int get bits => bytes * 8; - - static const int width = 2; -} - -/// {@category microcode} -class WriteCsrMicroOp extends MicroOp { - final MicroOpField field; - final MicroOpSource source; - final int offset; - - const WriteCsrMicroOp(this.field, this.source, {this.offset = 0}); - - const WriteCsrMicroOp.map(Map m) - : field = MicroOpField.values[m['field']!], - source = MicroOpSource.values[m['source']!], - offset = m['offset'] ?? 0; - - @override - Map toMap() => { - 'funct': funct, - 'field': field.value, - 'source': source.value, - 'offset': offset, - }; - - @override - String toString() => 'WriteCsrMicroOp($field, $source, offset: $offset)'; - - static const int funct = 1; - - static BitStruct struct(Mxlen mxlen) => BitStruct({ - 'funct': MicroOp.functRange, - 'field': const BitRange(5, 7), - 'source': const BitRange(8, 10), - 'offset': BitRange(11, 11 + mxlen.size), - }); -} - -/// {@category microcode} -class ReadRegisterMicroOp extends MicroOp { - final MicroOpField source; - final int offset; - final int valueOffset; - - const ReadRegisterMicroOp( - this.source, { - this.offset = 0, - this.valueOffset = 0, - }); - - const ReadRegisterMicroOp.map(Map m) - : source = MicroOpField.values[m['source']!], - offset = m['offset'] ?? 0, - valueOffset = m['valueOffset'] ?? 0; - - @override - Map toMap() => { - 'funct': funct, - 'source': source.value, - 'offset': offset, - 'valueOffset': valueOffset, - }; - - @override - String toString() => - 'ReadRegisterMicroOp($source, offset: $offset, valueOffset: $valueOffset)'; - - static const int funct = 2; - - static BitStruct struct(Mxlen mxlen) => BitStruct({ - 'funct': MicroOp.functRange, - 'source': const BitRange(5, 7), - 'offset': BitRange(8, 8 + mxlen.size - 1), - 'valueOffset': BitRange(8 + mxlen.size, 8 + (mxlen.size * 2) - 1), - }); -} - -/// {@category microcode} -class WriteRegisterMicroOp extends MicroOp { - final MicroOpField field; - final MicroOpSource source; - final int offset; - final int valueOffset; - - const WriteRegisterMicroOp( - this.field, - this.source, { - this.offset = 0, - this.valueOffset = 0, - }); - - const WriteRegisterMicroOp.map(Map m) - : field = MicroOpField.values[m['field']!], - source = MicroOpSource.values[m['source']!], - offset = m['offset'] ?? 0, - valueOffset = m['valueOffset'] ?? 0; - - @override - Map toMap() => { - 'funct': funct, - 'field': field.value, - 'source': source.value, - 'offset': offset, - 'valueOffset': valueOffset, - }; - - @override - String toString() => - 'WriteRegisterMicroOp($field, $source, offset: $offset, valueOffset: $valueOffset)'; - - static const int funct = 3; - - static BitStruct struct(Mxlen mxlen) => BitStruct({ - 'funct': MicroOp.functRange, - 'field': const BitRange(5, 7), - 'source': const BitRange(8, 10), - 'offset': BitRange(11, 11 + mxlen.size - 1), - 'valueOffset': BitRange(11 + mxlen.size, 11 + (mxlen.size * 2) - 1), - }); -} - -/// {@category microcode} -class ModifyLatchMicroOp extends MicroOp { - final MicroOpField field; - final MicroOpSource source; - final bool replace; - - const ModifyLatchMicroOp(this.field, this.source, this.replace); - - const ModifyLatchMicroOp.map(Map m) - : field = MicroOpField.values[m['field']!], - source = MicroOpSource.values[m['source']!], - replace = (m['replace'] ?? 0) != 0; - - @override - Map toMap() => { - 'funct': funct, - 'field': field.value, - 'source': source.value, - 'replace': replace ? 1 : 0, - }; - - @override - String toString() => 'ModifyLatchMicroOp($field, $source, $replace)'; - - static const int funct = 4; - - static BitStruct struct(Mxlen _) => BitStruct({ - 'funct': MicroOp.functRange, - 'field': const BitRange(5, 7), - 'source': const BitRange(8, 10), - 'replace': BitRange.single(11), - }); -} - -/// {@category microcode} -class AluMicroOp extends MicroOp { - final MicroOpAluFunct alu; - final MicroOpField a; - final MicroOpField b; - - const AluMicroOp(this.alu, this.a, this.b); - - const AluMicroOp.map(Map m) - : alu = MicroOpAluFunct.values[m['alu']!], - a = MicroOpField.values[m['a']!], - b = MicroOpField.values[m['b']!]; - - @override - Map toMap() => { - 'funct': funct, - 'alu': alu.value, - 'a': a.value, - 'b': b.value, - }; - - @override - String toString() => 'AluMicroOp($alu, $a, $b)'; - - static const int funct = 5; - - static BitStruct struct(Mxlen _) => BitStruct({ - 'funct': MicroOp.functRange, - 'alu': const BitRange(5, 9), - 'a': const BitRange(10, 12), - 'b': const BitRange(13, 15), - }); -} - -/// {@category microcode} -class BranchIfMicroOp extends MicroOp { - final MicroOpCondition condition; - final MicroOpSource target; - final int offset; - final MicroOpField? offsetField; - - const BranchIfMicroOp( - this.condition, - this.target, { - this.offset = 0, - this.offsetField, - }); - - const BranchIfMicroOp.map(Map m) - : condition = MicroOpCondition.values[m['condition']!], - target = MicroOpSource.values[m['target']!], - offset = m['offset'] ?? 0, - offsetField = (m['hasField'] ?? 0) != 0 - ? MicroOpField.values[m['offsetField']!] - : null; - - @override - Map toMap() => { - 'funct': funct, - 'condition': condition.value, - 'target': target.value, - 'hasField': offsetField != null ? 1 : 0, - 'offsetField': offsetField?.value ?? 0, - 'offset': offset, - }; - - @override - String toString() => - 'BranchIfMicroOp($condition, $target, $offset, $offsetField)'; - - static const int funct = 6; - - static BitStruct struct(Mxlen mxlen) => BitStruct({ - 'funct': MicroOp.functRange, - 'condition': const BitRange(5, 7), - 'target': const BitRange(8, 10), - 'hasField': const BitRange.single(11), - 'offsetField': const BitRange(12, 14), - 'offset': BitRange(15, 15 + mxlen.size - 1), - }); -} - -/// {@category microcode} -class UpdatePCMicroOp extends MicroOp { - final MicroOpField source; - final int offset; - final MicroOpSource? offsetSource; - final MicroOpField? offsetField; - final bool absolute; - final bool align; - - const UpdatePCMicroOp( - this.source, { - this.offset = 0, - this.offsetField, - this.offsetSource, - this.absolute = false, - this.align = false, - }); - - const UpdatePCMicroOp.map(Map m) - : source = MicroOpField.values[m['source']!], - offset = m['offset'] ?? 0, - offsetSource = (m['hasSource'] ?? 0) != 0 - ? MicroOpSource.values[m['offsetSource']!] - : null, - offsetField = (m['hasField'] ?? 0) != 0 - ? MicroOpField.values[m['offsetField']!] - : null, - absolute = (m['absolute'] ?? 0) != 0, - align = (m['align'] ?? 0) != 0; - - @override - Map toMap() => { - 'funct': funct, - 'source': source.value, - 'hasSource': offsetSource != null ? 1 : 0, - 'hasField': offsetField != null ? 1 : 0, - 'offsetSource': offsetSource?.value ?? 0, - 'offsetField': offsetField?.value ?? 0, - 'absolute': absolute ? 1 : 0, - 'align': align ? 1 : 0, - 'offset': offset, - }; - - @override - String toString() => - 'UpdatePCMicroOp($source, $offset, $offsetField, $offsetSource, absolute: $absolute, align: $align)'; - - static const int funct = 7; - - static BitStruct struct(Mxlen mxlen) => BitStruct({ - 'funct': MicroOp.functRange, - 'source': const BitRange(5, 8), - 'hasSource': const BitRange.single(9), - 'hasField': const BitRange.single(10), - 'offsetField': const BitRange(11, 13), - 'offsetSource': const BitRange(14, 16), - 'absolute': const BitRange.single(17), - 'align': const BitRange.single(18), - 'offset': BitRange(19, 19 + mxlen.size - 1), - }); -} - -/// {@category microcode} -class MemLoadMicroOp extends MicroOp { - final MicroOpField base; - final MicroOpMemSize size; - final bool unsigned; - final MicroOpField dest; - - const MemLoadMicroOp({ - required this.base, - required this.size, - this.unsigned = true, - required this.dest, - }); - - const MemLoadMicroOp.map(Map m) - : base = MicroOpField.values[m['base']!], - size = MicroOpMemSize.values[m['size']!], - unsigned = (m['unsigned'] ?? 0) != 0, - dest = MicroOpField.values[m['dest']!]; - - @override - Map toMap() => { - 'funct': funct, - 'base': base.value, - 'dest': dest.value, - 'size': size.value, - 'unsigned': unsigned ? 1 : 0, - }; - - @override - String toString() => - 'MemLoadMicroOp($base, $size, ${unsigned ? 'unsigned' : 'signed'}, $dest)'; - - static const int funct = 8; - - static BitStruct struct(Mxlen _) => BitStruct({ - 'funct': MicroOp.functRange, - 'base': const BitRange(5, 7), - 'dest': const BitRange(8, 10), - 'size': const BitRange(11, 12), - 'unsigned': BitRange.single(13), - }); -} - -/// {@category microcode} -class MemStoreMicroOp extends MicroOp { - final MicroOpField base; - final MicroOpField src; - final MicroOpMemSize size; - - const MemStoreMicroOp({ - required this.base, - required this.src, - required this.size, - }); - - const MemStoreMicroOp.map(Map m) - : base = MicroOpField.values[m['base']!], - src = MicroOpField.values[m['src']!], - size = MicroOpMemSize.values[m['size']!]; - - @override - Map toMap() => { - 'funct': funct, - 'base': base.value, - 'src': src.value, - 'size': size.value, - }; - - @override - String toString() => 'MemStoreMicroOp($base, $src, $size)'; - - static const int funct = 9; - - static BitStruct struct(Mxlen _) => BitStruct({ - 'funct': MicroOp.functRange, - 'base': const BitRange(5, 7), - 'src': const BitRange(8, 10), - 'size': const BitRange(11, 12), - }); -} - -/// {@category microcode} -class TrapMicroOp extends MicroOp { - final Trap kindMachine; - final Trap? kindSupervisor; - final Trap? kindUser; - - const TrapMicroOp(this.kindMachine, this.kindSupervisor, this.kindUser); - - const TrapMicroOp.one(this.kindMachine) - : kindSupervisor = null, - kindUser = null; - - const TrapMicroOp.map(Map m) - : kindMachine = Trap.values[m['machine']!], - kindSupervisor = (m['hasSupervisor'] ?? 0) != 0 - ? Trap.values[m['supervisor']!] - : null, - kindUser = (m['hasUser'] ?? 0) != 0 ? Trap.values[m['user']!] : null; - - @override - Map toMap() => { - 'funct': funct, - 'machine': kindMachine.index, - 'supervisor': kindSupervisor?.index ?? kindMachine.index, - 'user': kindSupervisor?.index ?? kindMachine.index, - }; - - @override - String toString() => 'TrapMicroOp($kindMachine, $kindSupervisor, $kindUser)'; - - static const int funct = 10; - - static BitStruct struct(Mxlen _) => BitStruct({ - 'funct': MicroOp.functRange, - 'machine': const BitRange(5, 9), - 'supervisor': const BitRange(10, 14), - 'user': const BitRange(15, 19), - }); -} - -/// {@category microcode} -class TlbFenceMicroOp extends MicroOp { - const TlbFenceMicroOp(); - - const TlbFenceMicroOp.map(Map _); - - @override - Map toMap() => {'funct': funct}; - - @override - String toString() => 'TlbFenceMicroOp()'; - - static const int funct = 11; - - static BitStruct struct(Mxlen _) => BitStruct({'funct': MicroOp.functRange}); -} - -/// {@category microcode} -class TlbInvalidateMicroOp extends MicroOp { - final MicroOpField addrField; - final MicroOpField asidField; - - const TlbInvalidateMicroOp({ - required this.addrField, - required this.asidField, - }); - - const TlbInvalidateMicroOp.map(Map m) - : addrField = MicroOpField.values[m['addrField']!], - asidField = MicroOpField.values[m['asidField']!]; - - @override - Map toMap() => { - 'funct': funct, - 'addrField': addrField.value, - 'asidField': asidField.value, - }; - - @override - String toString() => - 'TlbInvalidateMicroOp(addrField: $addrField, asidField: $asidField)'; - - static const int funct = 12; - - static BitStruct struct(Mxlen _) => BitStruct({ - 'funct': MicroOp.functRange, - 'addrField': const BitRange(5, 8), - 'asidField': const BitRange(9, 12), - }); -} - -/// {@category microcode} -class FenceMicroOp extends MicroOp { - const FenceMicroOp(); - - const FenceMicroOp.map(Map _); - - @override - Map toMap() => {'funct': funct}; - - @override - String toString() => 'FenceMicroOp()'; - - static const int funct = 13; - - static BitStruct struct(Mxlen _) => BitStruct({'funct': MicroOp.functRange}); -} - -/// {@category microcode} -class ReturnMicroOp extends MicroOp { - final PrivilegeMode mode; - - const ReturnMicroOp(this.mode); - - ReturnMicroOp.map(Map m) - : mode = PrivilegeMode.find(m['mode']!)!; - - @override - Map toMap() => {'funct': funct, 'mode': mode.id}; - - @override - String toString() => 'ReturnMicroOp($mode)'; - - static const int funct = 14; - - static BitStruct struct(Mxlen _) => - BitStruct({'funct': MicroOp.functRange, 'mode': const BitRange(5, 7)}); -} - -/// {@category microcode} -class WriteLinkRegisterMicroOp extends MicroOp { - final MicroOpLink link; - final int pcOffset; - - const WriteLinkRegisterMicroOp({required this.link, required this.pcOffset}); - - const WriteLinkRegisterMicroOp.map(Map m) - : link = MicroOpLink.values[m['link']!], - pcOffset = m['pcOffset'] ?? 0; - - @override - Map toMap() => { - 'funct': funct, - 'link': link.value, - 'pcOffset': pcOffset, - }; - - @override - String toString() => 'WriteLinkRegisterMicroOp($link, $pcOffset)'; - - static const int funct = 15; - - static BitStruct struct(Mxlen mxlen) => BitStruct({ - 'funct': MicroOp.functRange, - 'link': const BitRange.single(5), - 'pcOffset': BitRange(6, 6 + mxlen.size - 1), - }); -} - -/// {@category microcode} -class InterruptHoldMicroOp extends MicroOp { - const InterruptHoldMicroOp(); - - const InterruptHoldMicroOp.map(Map _); - - @override - Map toMap() => {'funct': funct}; - - @override - String toString() => 'InterruptHoldMicroOp()'; - - static const int funct = 16; - - static BitStruct struct(Mxlen _) => BitStruct({'funct': MicroOp.functRange}); -} - -/// {@category microcode} -class LoadReservedMicroOp extends MicroOp { - final MicroOpField base; - final MicroOpField dest; - final MicroOpMemSize size; - - const LoadReservedMicroOp(this.base, this.dest, this.size); - - const LoadReservedMicroOp.map(Map m) - : base = MicroOpField.values[m['base']!], - dest = MicroOpField.values[m['dest']!], - size = MicroOpMemSize.values[m['size']!]; - - @override - Map toMap() => { - 'funct': funct, - 'base': base.value, - 'dest': dest.value, - 'size': size.value, - }; - - @override - String toString() => 'LoadReservedMicroOp($base, $dest, $size)'; - - static const int funct = 17; - - static BitStruct struct(Mxlen _) => BitStruct({ - 'funct': MicroOp.functRange, - 'base': const BitRange(5, 8), - 'dest': const BitRange(9, 12), - 'size': const BitRange(13, 14), - }); -} - -/// {@category microcode} -class StoreConditionalMicroOp extends MicroOp { - final MicroOpField base; - final MicroOpField src; - final MicroOpField dest; - final MicroOpMemSize size; - - const StoreConditionalMicroOp({ - required this.base, - required this.src, - required this.dest, - required this.size, - }); - - const StoreConditionalMicroOp.map(Map m) - : base = MicroOpField.values[m['base']!], - src = MicroOpField.values[m['src']!], - dest = MicroOpField.values[m['dest']!], - size = MicroOpMemSize.values[m['size']!]; - - @override - Map toMap() => { - 'funct': funct, - 'base': base.value, - 'src': src.value, - 'dest': dest.value, - 'size': size.value, - }; - - @override - String toString() => 'StoreConditionalMicroOp($base, $src, $dest, $size)'; - - static const int funct = 18; - - static BitStruct struct(Mxlen _) => BitStruct({ - 'funct': MicroOp.functRange, - 'base': const BitRange(5, 8), - 'src': const BitRange(9, 12), - 'dest': const BitRange(13, 16), - 'size': const BitRange(17, 18), - }); -} - -/// {@category microcode} -class AtomicMemoryMicroOp extends MicroOp { - final MicroOpAtomicFunct afunct; - final MicroOpField base; - final MicroOpField src; - final MicroOpField dest; - final MicroOpMemSize size; - - const AtomicMemoryMicroOp({ - required MicroOpAtomicFunct funct, - required this.base, - required this.src, - required this.dest, - required this.size, - }) : afunct = funct; - - const AtomicMemoryMicroOp.map(Map m) - : afunct = MicroOpAtomicFunct.values[m['afunct']!], - base = MicroOpField.values[m['base']!], - src = MicroOpField.values[m['src']!], - dest = MicroOpField.values[m['dest']!], - size = MicroOpMemSize.values[m['size']!]; - - @override - Map toMap() => { - 'funct': AtomicMemoryMicroOp.funct, - 'afunct': afunct.value, - 'base': base.value, - 'src': src.value, - 'dest': dest.value, - 'size': size.value, - }; - - @override - String toString() => - 'AtomicMemoryMicroOp($afunct, $base, $src, $dest, $size)'; - - static const int funct = 19; - - static BitStruct struct(Mxlen _) => BitStruct({ - 'funct': MicroOp.functRange, - 'afunct': const BitRange(5, 8), - 'base': const BitRange(9, 12), - 'src': const BitRange(13, 16), - 'dest': const BitRange(17, 20), - 'size': const BitRange(21, 22), - }); -} - -/// {@category microcode} -class ValidateFieldMicroOp extends MicroOp { - final MicroOpCondition condition; - final MicroOpField field; - final int value; - - const ValidateFieldMicroOp(this.condition, this.field, this.value); - - const ValidateFieldMicroOp.map(Map m) - : condition = MicroOpCondition.values[m['condition']!], - field = MicroOpField.values[m['field']!], - value = m['value'] ?? 0; - - @override - Map toMap() => { - 'funct': funct, - 'condition': condition.value, - 'field': field.value, - 'value': value, - }; - - @override - String toString() => 'ValidateFieldMicroOp($condition, $field, $value)'; - - static const int funct = 20; - - static BitStruct struct(Mxlen mxlen) => BitStruct({ - 'funct': MicroOp.functRange, - 'condition': const BitRange(5, 7), - 'field': const BitRange(8, 10), - 'value': BitRange(10, 10 + mxlen.size - 1), - }); -} - -/// {@category microcode} -class SetFieldMicroOp extends MicroOp { - final MicroOpField field; - final int value; - - const SetFieldMicroOp(this.field, this.value); - - const SetFieldMicroOp.map(Map m) - : field = MicroOpField.values[m['field']!], - value = m['value'] ?? 0; - - @override - Map toMap() => { - 'funct': funct, - 'field': field.value, - 'value': value, - }; - - @override - String toString() => 'SetFieldMicroOp($field, $value)'; - - static const int funct = 21; - - static BitStruct struct(Mxlen mxlen) => BitStruct({ - 'funct': MicroOp.functRange, - 'field': const BitRange(5, 7), - 'value': BitRange(8, 8 + mxlen.size - 1), - }); -} - -/// {@category microcode} -class ReadCsrMicroOp extends MicroOp { - final MicroOpField source; - - const ReadCsrMicroOp(this.source); - - const ReadCsrMicroOp.map(Map m) - : source = MicroOpField.values[m['source']!]; - - @override - Map toMap() => {'funct': funct, 'source': source.value}; - - @override - String toString() => 'ReadCsrMicroOp($source)'; - - static const int funct = 22; - - static BitStruct struct(Mxlen _) => - BitStruct({'funct': MicroOp.functRange, 'source': const BitRange(5, 7)}); -} - -class OperationDecodePattern { - final int mask; - final int value; - final int opIndex; - final int type; - final int nzfMask; - final int zfMask; - - const OperationDecodePattern( - this.mask, - this.value, - this.opIndex, - this.type, - this.nzfMask, - this.zfMask, - ); - - OperationDecodePattern.map(Map m) - : mask = m['mask']!, - value = m['value']!, - opIndex = m['opIndex']!, - type = m['type']!, - nzfMask = m['nzfMask']!, - zfMask = m['zfMask']!; - - OperationDecodePattern copyWith({int? opIndex, int? type}) => - OperationDecodePattern( - mask, - value, - opIndex ?? this.opIndex, - type ?? this.type, - nzfMask, - zfMask, - ); - - Map toMap() => { - 'mask': mask, - 'value': value, - 'opIndex': opIndex, - 'type': type, - 'nzfMask': nzfMask, - 'zfMask': zfMask, - }; - - BigInt encode(int opIndexWidth, int typeWidth, Map fields) => - struct(opIndexWidth, typeWidth, fields).bigEncode(toMap()); - - @override - String toString() => - 'OperationDecodePattern($mask, $value, $opIndex, $type, $nzfMask, $zfMask)'; - - static BitStruct struct( - int opIndexWidth, - int typeWidth, - Map fields, - ) { - final mapping = {}; - mapping['mask'] = BitRange(0, 31); - mapping['value'] = BitRange(32, 63); - mapping['opIndex'] = BitRange(64, 64 + opIndexWidth - 1); - mapping['type'] = BitRange( - 64 + opIndexWidth, - 64 + opIndexWidth + typeWidth - 1, - ); - mapping['nzfMask'] = BitRange( - 64 + opIndexWidth + typeWidth, - 64 + opIndexWidth + typeWidth + 31, - ); - mapping['zfMask'] = BitRange( - 64 + opIndexWidth + typeWidth + 32, - 64 + opIndexWidth + typeWidth + 32 + 31, - ); - return BitStruct(mapping); - } - - static OperationDecodePattern decode( - int opIndexWidth, - int typeWidth, - Map indices, - BigInt value, - ) => OperationDecodePattern.map( - struct(opIndexWidth, typeWidth, indices).bigDecode(value), - ); -} - -/// {@category microcode} -class Operation { - final String mnemonic; - final int opcode; - final int? funct2; - final int? funct3; - final int? funct4; - final int? funct6; - final int? funct7; - final int? funct12; - final BitStruct struct; - final T Function(Map) constructor; - final List nonZeroFields; - final List zeroFields; - final List allowedLevels; - final List microcode; - - const Operation({ - required this.mnemonic, - required this.opcode, - this.funct2, - this.funct3, - this.funct4, - this.funct6, - this.funct7, - this.funct12, - this.nonZeroFields = const [], - this.zeroFields = const [], - required this.struct, - required this.constructor, - this.allowedLevels = PrivilegeMode.values, - this.microcode = const [], - }); - - Map get indexedMicrocode { - final map = {}; - var i = 0; - for (final mop in microcode) { - map[i++] = mop; - } - return map; - } - - OperationDecodePattern decodePattern(int index, Map typeMap) { - var mask = 0; - var value = 0; - - void bind(BitRange range, int? fieldValue, {bool nonZero = false}) { - if (fieldValue == null && !nonZero) return; - - final shiftedMask = range.mask << range.start; - mask |= shiftedMask; - - if (fieldValue != null) value |= (fieldValue << range.start); - } - - bind(struct.mapping['opcode']!, opcode); - - if (funct2 != null) bind(struct.mapping['funct2']!, funct2); - - if (funct3 != null && struct.mapping['funct3'] != null) { - bind(struct.mapping['funct3']!, funct3); - } - - if (funct4 != null) bind(struct.mapping['funct4']!, funct4); - - if (funct6 != null) bind(struct.mapping['funct6']!, funct6); - - if (funct7 != null && struct.mapping['funct7'] != null) { - bind(struct.mapping['funct7']!, funct7); - } - - if (funct12 != null) bind(struct.mapping['funct12']!, funct12); - - int nzfMask = 0; - - for (final f in nonZeroFields) { - if (!struct.mapping.containsKey(f)) { - throw '$mnemonic instruction does not have field $f'; - } - - final r = struct.mapping[f]!; - nzfMask |= (r.mask << r.start); - } - - int zfMask = 0; - - for (final f in zeroFields) { - if (!struct.mapping.containsKey(f)) { - throw '$mnemonic instruction does not have field $f'; - } - - final r = struct.mapping[f]!; - zfMask |= (r.mask << r.start); - } - - mask |= zfMask; - - return OperationDecodePattern( - mask, - value, - index, - typeMap[Microcode.instrType(this)]!, - nzfMask, - zfMask, - ); - } - - bool _mapMatch(Map map) { - if (map['opcode'] != opcode) return false; - if (map['funct2'] != funct2) return false; - if (map['funct3'] != funct3) return false; - if (map['funct4'] != funct4) return false; - if (map['funct6'] != funct6) return false; - if (map['funct7'] != funct7) return false; - if (map['funct12'] != funct12) return false; - - for (final field in nonZeroFields) { - if (map[field] == 0) return false; - } - - for (final field in zeroFields) { - if (map[field] != 0) return false; - } - return true; - } - - Map? mapDecode(int instr) { - final decoded = struct.decode(instr); - if (!_mapMatch(decoded)) return null; - return decoded; - } - - T? decode(int instr) { - final m = mapDecode(instr); - if (m == null) return null; - return constructor(m); - } - - bool matches(InstructionType instr) => _mapMatch(instr.toMap()); - - int mopWidth(Mxlen mxlen) => microcode - .map((mop) { - final m = mop.toMap(); - final funct = m['funct']!; - final e = kMicroOpTable.firstWhere((e) => e.funct == funct); - return e.struct(mxlen).width; - }) - .fold(0, (a, b) => a > b ? a : b); - - List mopEncode(Mxlen mxlen) => [ - BigInt.from(microcode.length), - ...microcode.map((mop) { - final m = mop.toMap(); - final funct = m['funct']!; - final e = kMicroOpTable.firstWhere((e) => e.funct == funct); - return e.struct(mxlen).bigEncode(m); - }), - ]; - - @override - String toString() => - 'Operation(mnemonic: $mnemonic, opcode: $opcode, funct2: $funct2,' - ' funct3: $funct3, funct4: $funct4, funct6: $funct6, funct7: $funct7,' - ' funct12: $funct12, decode: $decode, allowedLevels: $allowedLevels,' - ' microcode: $microcode)'; -} - -/// {@category microcode} -class RiscVExtension { - final List> operations; - final String? name; - final String? key; - final int mask; - - const RiscVExtension(this.operations, {this.name, this.key, this.mask = 0}); - - Operation? findOperation( - int opcode, - int funct3, [ - int? funct7, - ]) { - for (final op in operations) { - if (op.opcode == opcode && - op.funct3 == funct3 && - (op.funct7 == null || op.funct7 == funct7)) { - return op; - } - } - return null; - } - - Map get typeStructs { - Map result = {}; - for (final op in operations) { - final t = Microcode.instrType(op); - if (result.containsKey(t)) continue; - result[t] = op.struct; - } - return result; - } - - Map get typeMap => Map.fromEntries( - typeStructs.entries.indexed.map((e) => MapEntry(e.$2.key, e.$1)), - ); - - List get decodePattern { - List result = []; - var i = 0; - for (final op in operations) { - result.add(op.decodePattern(i, typeMap)); - i += op.microcode.length + 1; - } - return result; - } - - Map> get decodeMap { - // NOTE: we probably should loop through the operations and patterns to ensure coherency. - return Map.fromIterables(decodePattern, operations); - } - - @override - String toString() => name ?? 'RiscVExtension($operations, mask: $mask)'; -} - -class MicroOpSeq { - final List ops; - - const MicroOpSeq(this.ops); - - @override - bool operator ==(Object other) => - other is MicroOpSeq && - other.ops.length == ops.length && - _equalLists(other.ops, ops); - - @override - int get hashCode => ops.fold(0, (h, e) => h * 31 + e.hashCode); - - static bool _equalLists(List a, List b) { - for (var i = 0; i < a.length; i++) { - if (a[i] != b[i]) return false; - } - return true; - } - - @override - String toString() => ops.toString(); -} - -/// {@category microcode} -class Microcode { - final Map> map; - - const Microcode(this.map); - - int get patternWidth => OperationDecodePattern.struct( - opIndices.length.bitLength, - typeStructs.length.bitLength, - fieldIndices, - ).width; - - int get opIndexWidth => - decodeLookup.keys.fold(0, (a, b) => a > b ? a : b).bitLength; - - int mopWidth(Mxlen mxlen) => map.values - .map((op) => op.mopWidth(mxlen)) - .fold(0, (a, b) => a > b ? a : b); - - int mopIndexWidth(Mxlen mxlen) => encodedMops(mxlen).length.bitLength; - - List encodedMops(Mxlen mxlen) => map.values - .map((m) => m.mopEncode(mxlen)) - .fold([], (a, b) => [...a, ...b]); - - Map get decodeLookup { - Map result = {}; - var i = 0; - for (final e in map.entries) { - result[i] = e.key.copyWith(opIndex: i); - i += e.value.microcode.length + 1; - } - return result; - } - - Map> get execLookup { - Map> result = {}; - var i = 0; - for (final op in map.values) { - result[i] = op; - i += op.microcode.length + 1; - } - return result; - } - - Map get typeStructs { - Map result = {}; - for (final op in map.values) { - final t = instrType(op); - if (result.containsKey(t)) continue; - result[t] = op.struct; - } - return result; - } - - Map get typeMap => Map.fromEntries( - typeStructs.entries.indexed.map((e) => MapEntry(e.$2.key, e.$1)), - ); - - List get encodedPatterns { - List result = []; - for (final pattern in decodeLookup.values) { - result.add( - pattern.encode( - opIndices.length.bitLength, - typeMap.length.bitLength, - fieldIndices, - ), - ); - } - return result; - } - - Map get fieldIndices { - final map = {}; - int i = 0; - for (final entry in this.map.entries) { - final struct = entry.value.struct; - for (final field in struct.mapping.entries) { - map.putIfAbsent(field.key, () => i++); - } - } - return map.map((k, v) => MapEntry(v, k)); - } - - Map<(int instrIdx, int step), MicroOp> get microOpAt { - final table = <(int, int), MicroOp>{}; - - for (final entry in microOpsByInstrIndex.entries) { - final instrIdx = entry.key; - final seq = entry.value; - for (var i = 0; i < seq.length; i++) { - table[(instrIdx, i)] = seq[i]; - } - } - - return table; - } - - Map> get microOpsByTypeIndex { - final result = >{}; - for (final op in map.values) { - for (final mop in op.microcode) { - final idx = opIndices[mop.runtimeType.toString()]!; - (result[idx] ??= []).add(mop); - } - } - return result; - } - - Map> get microOpsByInstrIndex { - final result = >{}; - for (final entry in indices.entries) { - final pattern = entry.key; - final instrIdx = entry.value; - result[instrIdx] = map[pattern]!.microcode; - } - return result; - } - - Map get microOpSequences { - final result = {}; - for (final entry in indices.entries) { - final pattern = entry.key; - final instrIdx = entry.value; - - final op = map[pattern]!; - final seq = MicroOpSeq( - op.microcode - .map((mop) => opIndices[mop.runtimeType.toString()]!) - .toList(), - ); - - result[instrIdx] = seq; - } - return result; - } - - Map get microOpIndices { - final result = {}; - var i = 0; - for (final op in map.values) { - final ilist = MicroOpSeq( - op.microcode - .map((mop) => opIndices[mop.runtimeType.toString()]!) - .toList(), - ); - if (result.containsKey(ilist)) continue; - - result[ilist] = i++; - } - return result; - } - - Map get opIndices { - final result = {}; - var i = 0; - for (final op in map.values) { - for (final mop in op.microcode) { - final key = mop.runtimeType.toString(); - if (result.containsKey(key)) continue; - result[key] = i++; - } - } - return result; - } - - Map get indices { - final result = {}; - var i = 0; - for (final key in map.keys) { - result[key] = i++; - } - return result; - } - - Map> get fields { - final result = >{}; - for (final entry in map.entries) { - final struct = entry.value.struct; - for (final field in struct.mapping.entries) { - result[field.key] ??= {}; - result[field.key]![entry.key] = field.value; - } - } - return result; - } - - Operation? lookup(int instr) { - for (final entry in map.entries) { - final nzfMatch = - entry.key.nzfMask == 0 || (instr & entry.key.nzfMask) != 0; - final zfMatch = entry.key.zfMask == 0 || (instr & entry.key.zfMask) == 0; - if ((instr & entry.key.mask) == entry.key.value && nzfMatch && zfMatch) { - return entry.value; - } - } - return null; - } - - InstructionType? decode(int instr) { - final op = lookup(instr); - if (op == null) return null; - return op.decode(instr); - } - - /// Builds the operations list - /// - /// This generates a list of all the operations. - static List> buildOperations( - List extensions, - ) { - final list = >[]; - for (final ext in extensions) { - list.addAll(ext.operations); - } - return list; - } - - /// Builds a decode pattern list - /// - /// This generates a list of all the operations decode patterns. - /// It is necessary for the microcode selection circuitry. - static List buildDecodePattern( - List extensions, - ) { - final list = []; - var i = 0; - for (final ext in extensions) { - final patterns = ext.decodePattern; - - for (final e in patterns.indexed) { - list.add(e.$2.copyWith(opIndex: i)); - i += ext.operations[e.$1].microcode.length + 1; - } - } - return list; - } - - /// Builds the decode map - /// - /// This generates the decode map which resolves decode patterns to operations. - static Map> buildDecodeMap( - List extensions, - ) { - final patterns = buildDecodePattern(extensions); - final operations = buildOperations(extensions); - // NOTE: we probably should loop through the operations and patterns to ensure coherency. - return Map.fromIterables(patterns, operations); - } - - static String instrType(Operation i) { - final name = i.runtimeType.toString(); - return name.substring(10, name.length - 1); - } - - static String mopType(MicroOpEncoding i) { - final name = i.runtimeType.toString(); - return name.substring(16, name.length - 8); - } -} diff --git a/packages/riscv/lib/src/privilege.dart b/packages/riscv/lib/src/privilege.dart deleted file mode 100644 index 062f5ba..0000000 --- a/packages/riscv/lib/src/privilege.dart +++ /dev/null @@ -1,105 +0,0 @@ -import 'helpers.dart'; -import 'riscv_isa_base.dart'; -import 'riscv_isa_decode.dart'; -import 'ops.dart'; - -class SystemType extends InstructionType { - final int rd; - final int rs1; - - const SystemType({ - required super.opcode, - required this.rd, - required super.funct3, - required this.rs1, - required super.funct12, - }); - - const SystemType.map(Map map) - : rd = map['rd']!, - rs1 = map['rs1']!, - super.map(map); - - @override - int get imm => funct12!; - - @override - Map toMap() => { - 'opcode': opcode, - 'rd': rd, - 'funct3': funct3!, - 'rs1': rs1, - 'funct12': funct12!, - }; - - @override - String toString() => - 'SystemType(opcode: $opcode, rd: $rd, funct3: $funct3, rs1: $rs1, funct12: $funct12)'; - - static const BitStruct STRUCT = BitStruct({ - 'opcode': Instruction.opcodeRange, - 'rd': BitRange(7, 11), - 'funct3': BitRange(12, 14), - 'rs1': BitRange(15, 19), - 'funct12': BitRange(20, 31), - }); - - static SystemType decode(int instr) => - SystemType.map(SystemType.STRUCT.decode(instr)); -} - -/// 32-bit base privilege extension -/// -/// {@category extensions} -const rv32BasePrivilege = RiscVExtension([ - Operation( - mnemonic: 'mret', - opcode: 0x73, - funct3: 0x0, - funct12: 0x302, - struct: SystemType.STRUCT, - constructor: SystemType.map, - allowedLevels: [PrivilegeMode.machine], - microcode: [ReturnMicroOp(PrivilegeMode.machine)], - ), - Operation( - mnemonic: 'sret', - opcode: 0x73, - funct3: 0x0, - funct12: 0x102, - struct: SystemType.STRUCT, - constructor: SystemType.map, - allowedLevels: [PrivilegeMode.supervisor, PrivilegeMode.machine], - microcode: [ReturnMicroOp(PrivilegeMode.supervisor)], - ), - Operation( - mnemonic: 'wfi', - opcode: 0x73, - funct3: 0x0, - funct7: 0x08, - struct: SystemType.STRUCT, - constructor: SystemType.map, - microcode: [ - const InterruptHoldMicroOp(), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'sfence.vma', - opcode: 0x73, - funct3: 0x1, - struct: SType.STRUCT, - constructor: SType.map, - allowedLevels: [PrivilegeMode.supervisor, PrivilegeMode.machine], - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - TlbFenceMicroOp(), - TlbInvalidateMicroOp( - addrField: MicroOpField.rs1, - asidField: MicroOpField.rs2, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), -]); diff --git a/packages/riscv/lib/src/riscv_isa_base.dart b/packages/riscv/lib/src/riscv_isa_base.dart deleted file mode 100644 index e8d7b5e..0000000 --- a/packages/riscv/lib/src/riscv_isa_base.dart +++ /dev/null @@ -1,645 +0,0 @@ -import 'helpers.dart'; - -const int kInstructionBits = 32; -const int kInstructionBytes = kInstructionBits ~/ 8; - -enum PrivilegeMode { - machine(3), - supervisor(1), - user(0); - - const PrivilegeMode(this.id); - - final int id; - - static PrivilegeMode? find(int id) { - for (final mode in PrivilegeMode.values) { - if (mode.id == id) return mode; - } - return null; - } -} - -enum Trap { - instructionMisaligned(0, 0, 0, false), - instructionAccessFault(1, 1, 1, false), - illegal(2, 2, 2, false), - breakpoint(3, 3, 3, false), - - misalignedLoad(4, 4, 4, false), - loadAccess(5, 5, 5, false), - - misalignedStore(6, 6, 6, false), - storeAccess(7, 7, 7, false), - - ecallU(8, 8, 8, false), - ecallS(9, 9, 9, false), - ecallM(11, 11, 11, false), - - instructionPageFault(12, 12, 12, false), - loadPageFault(13, 13, 13, false), - storePageFault(15, 15, 15, false), - - userSoftware(0, 0, 0, true), - supervisorSoftware(1, 1, 1, true), - machineSoftware(3, 3, 3, true), - - userTimer(4, 4, 4, true), - supervisorTimer(5, 5, 5, true), - machineTimer(7, 7, 7, true), - - userExternal(8, 8, 8, true), - supervisorExternal(9, 9, 9, true), - machineExternal(11, 11, 11, true); - - final int mcauseCode; - final int scauseCode; - final int ucauseCode; - final bool interrupt; - - const Trap(this.mcauseCode, this.scauseCode, this.ucauseCode, this.interrupt); - - int mcause(int xlen) => (interrupt ? (1 << (xlen - 1)) : 0) | mcauseCode; - int scause(int xlen) => (interrupt ? (1 << (xlen - 1)) : 0) | scauseCode; - int ucause(int xlen) => (interrupt ? (1 << (xlen - 1)) : 0) | ucauseCode; -} - -enum PagingMode { - bare( - 0, - levels: 0, - vpnBits: 0, - pteBytes: 0, - ppnBits: const [], - supportedMxlens: [Mxlen.mxlen_32, Mxlen.mxlen_64], - ), - sv32( - 1, - levels: 2, - vpnBits: 10, - pteBytes: 4, - ppnBits: const [10, 12], - supportedMxlens: [Mxlen.mxlen_32, Mxlen.mxlen_64], - ), - sv39( - 8, - levels: 3, - vpnBits: 9, - pteBytes: 8, - ppnBits: const [9, 9, 26], - supportedMxlens: [Mxlen.mxlen_64], - ), - sv48( - 9, - levels: 4, - vpnBits: 9, - pteBytes: 8, - ppnBits: const [9, 9, 9, 17], - supportedMxlens: [Mxlen.mxlen_64], - ), - sv57( - 10, - levels: 5, - vpnBits: 9, - pteBytes: 8, - ppnBits: const [9, 9, 9, 9, 8], - supportedMxlens: [Mxlen.mxlen_64], - ); - - const PagingMode( - this.id, { - required this.levels, - required this.vpnBits, - required this.pteBytes, - required this.ppnBits, - required this.supportedMxlens, - }); - - final int id; - final int levels; - final int vpnBits; - final int pteBytes; - final List ppnBits; - final List supportedMxlens; - - int get totalPpnBits => ppnBits.fold(0, (a, b) => a + b); - - bool isSupported(Mxlen mxlen) => supportedMxlens.contains(mxlen); - - int ppnPhysShift(int i) => 12 + (vpnBits * i); - - int ppnShift(int index) { - int shift = 12; - for (int i = 0; i < index; i++) { - shift += ppnBits[i]; - } - return shift; - } - - bool isSuperpageLevel(int level) => level < levels - 1; - - static PagingMode? fromId(int id) { - for (final mode in PagingMode.values) { - if (mode.id == id) return mode; - } - - return null; - } -} - -abstract class InstructionType { - /// The opcode which to execute - final int opcode; - final int? funct2; - final int? funct3; - final int? funct4; - final int? funct6; - final int? funct7; - final int? funct12; - - const InstructionType({ - required this.opcode, - this.funct2, - this.funct3, - this.funct4, - this.funct6, - this.funct7, - this.funct12, - }); - - const InstructionType.map(Map map) - : opcode = map['opcode']!, - funct2 = map['funct2'], - funct3 = map['funct3'], - funct4 = map['funct4'], - funct6 = map['funct6'], - funct7 = map['funct7'], - funct12 = map['funct12']; - - int get imm => 0; - - bool matches( - int bOpcode, - int? bFunct2, - int? bFunct3, - int? bFunct4, - int? bFunct6, - int? bFunct7, - int? bFunct12, - ) => - opcode == bOpcode && - funct2 == bFunct2 && - funct3 == bFunct3 && - funct4 == bFunct4 && - funct6 == bFunct6 && - funct7 == bFunct7 && - funct12 == bFunct12; - - Map toMap(); - - @override - String toString() => - '${runtimeType.toString()}${toMap().entries.map((entry) => '${entry.key}: ${entry.value}')}'; -} - -/// R-Type RISC-V instruction -class RType extends InstructionType { - /// The result-data register - final int rd; - - /// Data 1 - final int rs1; - - /// Data 2 - final int rs2; - - const RType({ - required super.opcode, - required this.rd, - required super.funct3, - required this.rs1, - required this.rs2, - required super.funct7, - }); - - const RType.map(Map map) - : rd = map['rd']!, - rs1 = map['rs1']!, - rs2 = map['rs2']!, - super.map(map); - - @override - Map toMap() => { - 'opcode': opcode, - 'rd': rd, - 'funct3': funct3!, - 'rs1': rs1, - 'rs2': rs2, - 'funct7': funct7!, - }; - - @override - String toString() => - 'RType(opcode: $opcode, rd: $rd, funct3: $funct3, rs1: $rs1, rs2: $rs2, funct7: $funct7)'; - - static const BitStruct STRUCT = const BitStruct({ - 'opcode': Instruction.opcodeRange, - 'rd': const BitRange(7, 11), - 'funct3': const BitRange(12, 14), - 'rs1': const BitRange(15, 19), - 'rs2': const BitRange(20, 24), - 'funct7': const BitRange(25, 31), - }); -} - -/// I-Type RISC-V instruction -class IType extends InstructionType { - final int _imm; - - /// The result-data register - final int rd; - - /// Data 1 - final int rs1; - - const IType({ - required super.opcode, - required this.rd, - required super.funct3, - required this.rs1, - required int imm, - }) : _imm = imm; - - const IType.map(Map map) - : rd = map['rd']!, - rs1 = map['rs1']!, - _imm = map['imm']!, - super.map(map); - - @override - int get imm { - int value = _imm & 0xFFF; // 12-bit imm - if ((value & 0x800) != 0) { - value |= ~0xFFF; // sign extend - } - return value; - } - - @override - Map toMap() => { - 'opcode': opcode, - 'rd': rd, - 'funct3': funct3!, - 'rs1': rs1, - 'imm': imm, - }; - - @override - String toString() => - 'IType(opcode: $opcode, rd: $rd, funct3: $funct3, rs1: $rs1, imm: $imm)'; - - static const BitStruct STRUCT = const BitStruct({ - 'opcode': Instruction.opcodeRange, - 'rd': const BitRange(7, 11), - 'funct3': const BitRange(12, 14), - 'rs1': const BitRange(15, 19), - 'imm': const BitRange(20, 31), - }); -} - -/// S-Type RISC-V instruction -class SType extends InstructionType { - /// Bits 0:4 of the immediate - final int imm4_0; - - /// Data 1 - final int rs1; - - /// Data 2 - final int rs2; - - /// Bits 5:11 of the immediate - final int imm11_5; - - const SType({ - required super.opcode, - required this.imm4_0, - required super.funct3, - required this.rs1, - required this.rs2, - required this.imm11_5, - }); - - const SType.map(Map map) - : imm4_0 = map['imm[4:0]']!, - rs1 = map['rs1']!, - rs2 = map['rs2']!, - imm11_5 = map['imm[11:5]']!, - super.map(map); - - @override - int get imm { - var value = (imm11_5 << 5) | imm4_0; - - if ((value & 0x800) != 0) { - value |= ~0xFFFFF000; - } - - return value; - } - - @override - Map toMap() => { - 'opcode': opcode, - 'imm[4:0]': imm4_0, - 'funct3': funct3!, - 'rs1': rs1, - 'rs2': rs2, - 'imm[11:5]': imm11_5, - }; - - @override - String toString() => - 'SType(opcode: $opcode, imm[4:0]: $imm4_0, funct3: $funct3, rs1: $rs1, rs2: $rs2, imm[11:5]: $imm11_5)'; - - static const BitStruct STRUCT = const BitStruct({ - 'opcode': Instruction.opcodeRange, - 'imm[4:0]': const BitRange(7, 11), - 'funct3': const BitRange(12, 14), - 'rs1': const BitRange(15, 19), - 'rs2': const BitRange(20, 24), - 'imm[11:5]': const BitRange(25, 31), - }); -} - -/// B-Type RISC-V instruction -class BType extends InstructionType { - final int imm11; - final int imm4_1; - final int rs1; - final int rs2; - final int imm10_5; - final int imm12; - - const BType({ - required super.opcode, - required this.imm11, - required this.imm4_1, - required super.funct3, - required this.rs1, - required this.rs2, - required this.imm10_5, - required this.imm12, - }); - - const BType.map(Map map) - : imm11 = map['imm[11]']!, - imm4_1 = map['imm[4:1]']!, - rs1 = map['rs1']!, - rs2 = map['rs2']!, - imm10_5 = map['imm[10:5]']!, - imm12 = map['imm[12]']!, - super.map(map); - - @override - int get imm { - int value = (imm12 << 12) | (imm11 << 11) | (imm10_5 << 5) | (imm4_1 << 1); - - if ((value & 0x1000) != 0) value |= ~0x1FFF; - return value; - } - - @override - Map toMap() => { - 'opcode': opcode, - 'imm[11]': imm11, - 'imm[4:1]': imm4_1, - 'funct3': funct3!, - 'rs1': rs1, - 'rs2': rs2, - 'imm[10:5]': imm10_5, - 'imm[12]': imm12, - }; - - @override - String toString() => - 'BType(opcode: $opcode, imm[11]: $imm11, imm[4:1]: $imm4_1, funct3: $funct3, rs1: $rs1, rs2: $rs2, imm[10:5]: $imm10_5, imm[12]: $imm12)'; - - static const BitStruct STRUCT = const BitStruct({ - 'opcode': Instruction.opcodeRange, - 'imm[11]': const BitRange.single(7), - 'imm[4:1]': const BitRange(8, 11), - 'funct3': const BitRange(12, 14), - 'rs1': const BitRange(15, 19), - 'rs2': const BitRange(20, 24), - 'imm[10:5]': const BitRange(25, 30), - 'imm[12]': const BitRange.single(31), - }); -} - -/// U-Type RISC-V instruction -class UType extends InstructionType { - /// The result-data register - final int rd; - - /// The immediate value - final int shifted_imm; - - const UType({required super.opcode, required this.rd, required int imm}) - : shifted_imm = imm >> 12, - super(funct3: 0); - - UType.map(Map map) - : rd = map['rd']!, - shifted_imm = map['imm']!, - super.map({...map, 'funct3': 0}); - - @override - int get imm => shifted_imm << 12; - - @override - bool matches( - int bOpcode, - int? bFunct2, - int? bFunct3, - int? bFunct4, - int? bFunct6, - int? bFunct7, - int? bFunct12, - ) => - opcode == bOpcode && - bFunct2 == null && - bFunct3 == null && - bFunct4 == null && - bFunct6 == null && - bFunct7 == null && - bFunct12 == null; - - @override - Map toMap() => {'opcode': opcode, 'rd': rd, 'imm': shifted_imm}; - - @override - String toString() => 'UType(opcode: $opcode, rd: $rd, imm: $shifted_imm)'; - - static const BitStruct STRUCT = const BitStruct({ - 'opcode': Instruction.opcodeRange, - 'rd': const BitRange(7, 11), - 'imm': const BitRange(12, 31), - }); -} - -/// J-Type RISC-V instruction -class JType extends InstructionType { - final int rd; - final int imm19_12; - final int imm11; - final int imm10_1; - final int imm20; - - const JType({ - required super.opcode, - required this.rd, - required this.imm19_12, - required this.imm11, - required this.imm10_1, - required this.imm20, - }); - - const JType.map(Map map) - : rd = map['rd']!, - imm19_12 = map['imm[19:12]']!, - imm11 = map['imm[11]']!, - imm10_1 = map['imm[10:1]']!, - imm20 = map['imm[20]']!, - super.map(map); - - @override - int get imm { - int value = - (imm20 << 20) | (imm19_12 << 12) | (imm11 << 11) | (imm10_1 << 1); - if ((value & 0x100000) != 0) value |= ~0x1FFFFF; - return value; - } - - @override - bool matches( - int bOpcode, - int? _bFunct2, - int? _bFunct3, - int? _bFunct4, - int? _bFunct6, - int? _bFunct7, - int? _bFunct12, - ) => opcode == bOpcode; - - @override - Map toMap() => { - 'opcode': opcode, - 'rd': rd, - 'imm[19:12]': imm19_12, - 'imm[11]': imm11, - 'imm[10:1]': imm10_1, - 'imm[20]': imm20, - }; - - static const BitStruct STRUCT = const BitStruct({ - 'opcode': Instruction.opcodeRange, - 'rd': const BitRange(7, 11), - 'imm[19:12]': const BitRange(12, 19), - 'imm[11]': const BitRange.single(20), - 'imm[10:1]': const BitRange(21, 30), - 'imm[20]': const BitRange.single(31), - }); -} - -/// RISC-V instruction -class Instruction { - final InstructionType value; - - const Instruction.r(RType r) : value = r; - const Instruction.i(IType i) : value = i; - const Instruction.s(SType s) : value = s; - const Instruction.b(BType b) : value = b; - const Instruction.u(UType u) : value = u; - const Instruction.j(JType j) : value = j; - - int get opcode => value.opcode; - Map toMap() => value.toMap(); - - BitStruct get struct { - if (value is RType) return RType.STRUCT; - if (value is IType) return IType.STRUCT; - if (value is SType) return SType.STRUCT; - if (value is BType) return BType.STRUCT; - if (value is UType) return UType.STRUCT; - if (value is JType) return JType.STRUCT; - - throw 'Unreachable'; - } - - @override - String toString() => value.toString(); - - static const opcodeRange = const BitRange(0, 6); -} - -enum Register { - x0(0, 'zero'), - x1(1, 'ra'), - x2(2, 'sp'), - x3(3, 'gp'), - x4(4, 'tp'), - x5(5, 't0'), - x6(6, 't1'), - x7(7, 't2'), - x8(8, 's0'), - x9(9, 's1'), - x10(10, 'a0'), - x11(11, 'a1'), - x12(12, 'a2'), - x13(13, 'a3'), - x14(14, 'a4'), - x15(15, 'a5'), - x16(16, 'a6'), - x17(17, 'a7'), - x18(18, 's2'), - x19(19, 's3'), - x20(20, 's4'), - x21(21, 's5'), - x22(22, 's6'), - x23(23, 's7'), - x24(24, 's8'), - x25(25, 's9'), - x26(26, 's10'), - x27(27, 's11'), - x28(28, 't3'), - x29(29, 't4'), - x30(30, 't5'), - x31(31, 't6'); - - const Register(this.value, this.abi); - - final int value; - final String abi; -} - -enum Mxlen { - mxlen_32(32, 1 << 30, 0x003F_FFFF, 0x3FF, 22), - mxlen_64(64, 1 << 62, 0x0FFF_FFFF_FFFF, 0xF, 60); - - const Mxlen( - this.size, - this.misa, - this.satpPpnMask, - this.satpModeMask, - this.satpModeShift, - ); - - final int size; - final int misa; - final int satpPpnMask; - final int satpModeMask; - final int satpModeShift; - - int get width => size ~/ 8; -} diff --git a/packages/riscv/lib/src/riscv_isa_decode.dart b/packages/riscv/lib/src/riscv_isa_decode.dart deleted file mode 100644 index 727b465..0000000 --- a/packages/riscv/lib/src/riscv_isa_decode.dart +++ /dev/null @@ -1,67 +0,0 @@ -import 'riscv_isa_base.dart'; - -class DecodeException implements Exception { - final int opcode; - final int? funct; - - const DecodeException(this.opcode, this.funct); - - @override - String toString() => "Decode exception: $opcode, function: $funct"; -} - -extension RTypeDecode on RType { - static RType decode(int instr) => RType.map(RType.STRUCT.decode(instr)); -} - -extension ITypeDecode on IType { - static IType decode(int instr) => IType.map(IType.STRUCT.decode(instr)); -} - -extension STypeDecode on SType { - static SType decode(int instr) => SType.map(SType.STRUCT.decode(instr)); -} - -extension BTypeDecode on BType { - static BType decode(int instr) => BType.map(BType.STRUCT.decode(instr)); -} - -extension UTypeDecode on UType { - static UType decode(int instr) => UType.map(UType.STRUCT.decode(instr)); -} - -extension JTypeDecode on JType { - static JType decode(int instr) => JType.map(JType.STRUCT.decode(instr)); -} - -extension InstructionDecode on Instruction { - static Instruction decode(int instr) { - int opcode = instr & 0x7F; - - switch (opcode) { - case 0x33: - return Instruction.r(RTypeDecode.decode(instr)); - - case 0x13: - case 0x03: - case 0x67: - case 0x73: - return Instruction.i(ITypeDecode.decode(instr)); - - case 0x23: - return Instruction.s(STypeDecode.decode(instr)); - case 0x63: - return Instruction.b(BTypeDecode.decode(instr)); - - case 0x37: - case 0x17: - return Instruction.u(UTypeDecode.decode(instr)); - - case 0x6F: - return Instruction.j(JTypeDecode.decode(instr)); - - default: - throw DecodeException(opcode, null); - } - } -} diff --git a/packages/riscv/lib/src/riscv_isa_encode.dart b/packages/riscv/lib/src/riscv_isa_encode.dart deleted file mode 100644 index 16bc132..0000000 --- a/packages/riscv/lib/src/riscv_isa_encode.dart +++ /dev/null @@ -1,25 +0,0 @@ -import 'riscv_isa_base.dart'; - -extension RTypeEncode on RType { - int encode() => RType.STRUCT.encode(toMap()); -} - -extension ITypeEncode on IType { - int encode() => IType.STRUCT.encode(toMap()); -} - -extension STypeEncode on SType { - int encode() => SType.STRUCT.encode(toMap()); -} - -extension BTypeEncode on BType { - int encode() => BType.STRUCT.encode(toMap()); -} - -extension UTypeEncode on UType { - int encode() => UType.STRUCT.encode(toMap()); -} - -extension InstructionEncode on Instruction { - int encode() => struct.encode(toMap()); -} diff --git a/packages/riscv/lib/src/rv32i.dart b/packages/riscv/lib/src/rv32i.dart deleted file mode 100644 index 7917d5d..0000000 --- a/packages/riscv/lib/src/rv32i.dart +++ /dev/null @@ -1,603 +0,0 @@ -import 'riscv_isa_base.dart'; -import 'riscv_isa_decode.dart'; -import 'ops.dart'; - -/// RV32I extension -/// -/// {@category extensions} -const rv32i = RiscVExtension( - [ - Operation( - mnemonic: 'lui', - opcode: 0x37, - struct: UType.STRUCT, - constructor: UType.map, - microcode: [ - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.imm), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'auipc', - opcode: 0x17, - struct: UType.STRUCT, - constructor: UType.map, - microcode: [ - AluMicroOp(MicroOpAluFunct.add, MicroOpField.pc, MicroOpField.imm), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'jal', - opcode: 0x6F, - struct: JType.STRUCT, - constructor: JType.map, - microcode: [ - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.pc, valueOffset: 4), - UpdatePCMicroOp( - MicroOpField.pc, - offsetField: MicroOpField.imm, - align: true, - ), - ], - ), - Operation( - mnemonic: 'jalr', - opcode: 0x67, - funct3: 0x0, - struct: IType.STRUCT, - constructor: IType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - AluMicroOp(MicroOpAluFunct.add, MicroOpField.rs1, MicroOpField.imm), - WriteLinkRegisterMicroOp(link: MicroOpLink.rd, pcOffset: 4), - UpdatePCMicroOp( - MicroOpField.pc, - offsetSource: MicroOpSource.alu, - absolute: true, - align: true, - ), - ], - ), - Operation( - mnemonic: 'beq', - opcode: 0x63, - funct3: 0x0, - struct: BType.STRUCT, - constructor: BType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AluMicroOp(MicroOpAluFunct.sub, MicroOpField.rs1, MicroOpField.rs2), - BranchIfMicroOp( - MicroOpCondition.eq, - MicroOpSource.alu, - offsetField: MicroOpField.imm, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'bne', - opcode: 0x63, - funct3: 0x1, - struct: BType.STRUCT, - constructor: BType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AluMicroOp(MicroOpAluFunct.sub, MicroOpField.rs1, MicroOpField.rs2), - BranchIfMicroOp( - MicroOpCondition.ne, - MicroOpSource.alu, - offsetField: MicroOpField.imm, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'blt', - opcode: 0x63, - funct3: 0x2, - struct: BType.STRUCT, - constructor: BType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AluMicroOp(MicroOpAluFunct.slt, MicroOpField.rs1, MicroOpField.rs2), - BranchIfMicroOp( - MicroOpCondition.ne, - MicroOpSource.alu, - offsetField: MicroOpField.imm, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'bge', - opcode: 0x63, - funct3: 0x5, - struct: BType.STRUCT, - constructor: BType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AluMicroOp(MicroOpAluFunct.slt, MicroOpField.rs1, MicroOpField.rs2), - BranchIfMicroOp( - MicroOpCondition.eq, - MicroOpSource.alu, - offsetField: MicroOpField.imm, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'bltu', - opcode: 0x63, - funct3: 0x6, - struct: BType.STRUCT, - constructor: BType.map, - microcode: [ - AluMicroOp(MicroOpAluFunct.sltu, MicroOpField.rs1, MicroOpField.rs2), - BranchIfMicroOp( - MicroOpCondition.ne, - MicroOpSource.alu, - offsetField: MicroOpField.imm, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'bgeu', - opcode: 0x63, - funct3: 0x7, - struct: BType.STRUCT, - constructor: BType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AluMicroOp(MicroOpAluFunct.sltu, MicroOpField.rs1, MicroOpField.rs2), - BranchIfMicroOp( - MicroOpCondition.eq, - MicroOpSource.alu, - offsetField: MicroOpField.imm, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'lb', - opcode: 0x03, - funct3: 0x0, - struct: IType.STRUCT, - constructor: IType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - MemLoadMicroOp( - base: MicroOpField.rs1, - size: MicroOpMemSize.byte, - unsigned: false, - dest: MicroOpField.rs2, - ), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.rs2), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'lh', - opcode: 0x03, - funct3: 0x1, - struct: IType.STRUCT, - constructor: IType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - MemLoadMicroOp( - base: MicroOpField.rs1, - size: MicroOpMemSize.half, - unsigned: false, - dest: MicroOpField.rs2, - ), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.rs2), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'lw', - opcode: 0x03, - funct3: 0x2, - struct: IType.STRUCT, - constructor: IType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - MemLoadMicroOp( - base: MicroOpField.rs1, - size: MicroOpMemSize.word, - unsigned: false, - dest: MicroOpField.rs2, - ), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.rs2), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'lbu', - opcode: 0x03, - funct3: 0x4, - struct: IType.STRUCT, - constructor: IType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - MemLoadMicroOp( - base: MicroOpField.rs1, - size: MicroOpMemSize.byte, - unsigned: true, - dest: MicroOpField.rs2, - ), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.rs2), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'lhu', - opcode: 0x03, - funct3: 0x5, - struct: IType.STRUCT, - constructor: IType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - MemLoadMicroOp( - base: MicroOpField.rs1, - size: MicroOpMemSize.half, - unsigned: true, - dest: MicroOpField.rd, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'sb', - opcode: 0x23, - funct3: 0x0, - struct: SType.STRUCT, - constructor: SType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - MemStoreMicroOp( - base: MicroOpField.rs1, - src: MicroOpField.rs2, - size: MicroOpMemSize.byte, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'sh', - opcode: 0x23, - funct3: 0x1, - struct: SType.STRUCT, - constructor: SType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - MemStoreMicroOp( - base: MicroOpField.rs1, - src: MicroOpField.rs2, - size: MicroOpMemSize.half, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'sw', - opcode: 0x23, - funct3: 0x2, - struct: SType.STRUCT, - constructor: SType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - MemStoreMicroOp( - base: MicroOpField.rs1, - src: MicroOpField.rs2, - size: MicroOpMemSize.word, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'addi', - opcode: 0x13, - funct3: 0x0, - struct: IType.STRUCT, - constructor: IType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - AluMicroOp(MicroOpAluFunct.add, MicroOpField.rs1, MicroOpField.imm), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'slti', - opcode: 0x13, - funct3: 0x2, - struct: IType.STRUCT, - constructor: IType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - AluMicroOp(MicroOpAluFunct.slt, MicroOpField.rs1, MicroOpField.imm), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'sltiu', - opcode: 0x13, - funct3: 0x3, - struct: IType.STRUCT, - constructor: IType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - AluMicroOp(MicroOpAluFunct.sltu, MicroOpField.rs1, MicroOpField.imm), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'xori', - opcode: 0x13, - funct3: 0x4, - struct: IType.STRUCT, - constructor: IType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - AluMicroOp(MicroOpAluFunct.xor, MicroOpField.rs1, MicroOpField.imm), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'ori', - opcode: 0x13, - funct3: 0x6, - struct: IType.STRUCT, - constructor: IType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - AluMicroOp(MicroOpAluFunct.or, MicroOpField.rs1, MicroOpField.imm), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'andi', - opcode: 0x13, - funct3: 0x7, - struct: IType.STRUCT, - constructor: IType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - AluMicroOp(MicroOpAluFunct.and, MicroOpField.rs1, MicroOpField.imm), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'slli', - opcode: 0x13, - funct3: 0x1, - struct: IType.STRUCT, - constructor: IType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - AluMicroOp(MicroOpAluFunct.sll, MicroOpField.rs1, MicroOpField.imm), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'srli', - opcode: 0x13, - funct3: 0x5, - struct: IType.STRUCT, - constructor: IType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - AluMicroOp(MicroOpAluFunct.srl, MicroOpField.rs1, MicroOpField.imm), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'srai', - opcode: 0x13, - funct3: 0x5, - funct7: 0x20, - struct: IType.STRUCT, - constructor: IType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - AluMicroOp(MicroOpAluFunct.sra, MicroOpField.rs1, MicroOpField.imm), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'add', - opcode: 0x33, - funct3: 0x0, - funct7: 0x00, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AluMicroOp(MicroOpAluFunct.add, MicroOpField.rs1, MicroOpField.rs2), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'sub', - opcode: 0x33, - funct3: 0x0, - funct7: 0x20, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AluMicroOp(MicroOpAluFunct.sub, MicroOpField.rs1, MicroOpField.rs2), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'sll', - opcode: 0x33, - funct3: 0x1, - funct7: 0x00, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - AluMicroOp(MicroOpAluFunct.sll, MicroOpField.rs1, MicroOpField.rs2), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'slt', - opcode: 0x33, - funct3: 0x2, - funct7: 0x00, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AluMicroOp(MicroOpAluFunct.slt, MicroOpField.rs1, MicroOpField.rs2), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'sltu', - opcode: 0x33, - funct3: 0x3, - funct7: 0x00, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AluMicroOp(MicroOpAluFunct.sltu, MicroOpField.rs1, MicroOpField.rs2), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'xor', - opcode: 0x33, - funct3: 0x4, - funct7: 0x00, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AluMicroOp(MicroOpAluFunct.xor, MicroOpField.rs1, MicroOpField.rs2), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'srl', - opcode: 0x33, - funct3: 0x5, - funct7: 0x00, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AluMicroOp(MicroOpAluFunct.srl, MicroOpField.rs1, MicroOpField.rs2), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'sra', - opcode: 0x33, - funct3: 0x5, - funct7: 0x20, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AluMicroOp(MicroOpAluFunct.sra, MicroOpField.rs1, MicroOpField.rs2), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'or', - opcode: 0x33, - funct3: 0x6, - funct7: 0x00, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AluMicroOp(MicroOpAluFunct.or, MicroOpField.rs1, MicroOpField.rs2), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'and', - opcode: 0x33, - funct3: 0x7, - funct7: 0x00, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AluMicroOp(MicroOpAluFunct.and, MicroOpField.rs1, MicroOpField.rs2), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'fence', - opcode: 0x0F, - funct3: 0x0, - struct: IType.STRUCT, - constructor: IType.map, - microcode: [FenceMicroOp(), UpdatePCMicroOp(MicroOpField.pc, offset: 4)], - ), - Operation( - mnemonic: 'ecall', - opcode: 0x73, - funct3: 0x0, - struct: IType.STRUCT, - constructor: IType.map, - microcode: [TrapMicroOp(Trap.ecallM, Trap.ecallS, Trap.ecallU)], - ), - Operation( - mnemonic: 'ebreak', - opcode: 0x73, - funct3: 0x0, - struct: IType.STRUCT, - constructor: IType.map, - microcode: [TrapMicroOp.one(Trap.breakpoint)], - ), - ], - name: 'RV32I', - key: 'I', - mask: 1 << 8, -); diff --git a/packages/riscv/lib/src/rv64i.dart b/packages/riscv/lib/src/rv64i.dart deleted file mode 100644 index 197ee12..0000000 --- a/packages/riscv/lib/src/rv64i.dart +++ /dev/null @@ -1,192 +0,0 @@ -import 'riscv_isa_base.dart'; -import 'riscv_isa_decode.dart'; -import 'ops.dart'; - -/// RV64I extension -/// -/// {@category extensions} -const rv64i = RiscVExtension( - [ - Operation( - mnemonic: 'lwu', - opcode: 0x03, - funct3: 0x6, - struct: IType.STRUCT, - constructor: IType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - MemLoadMicroOp( - base: MicroOpField.rs1, - size: MicroOpMemSize.word, - unsigned: true, - dest: MicroOpField.rd, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'ld', - opcode: 0x03, - funct3: 0x3, - struct: IType.STRUCT, - constructor: IType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - MemLoadMicroOp( - base: MicroOpField.rs1, - size: MicroOpMemSize.dword, - unsigned: true, - dest: MicroOpField.rd, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'sd', - opcode: 0x23, - funct3: 0x3, - struct: SType.STRUCT, - constructor: SType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - MemStoreMicroOp( - base: MicroOpField.rs1, - src: MicroOpField.rs2, - size: MicroOpMemSize.dword, - ), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'addiw', - opcode: 0x1B, - funct3: 0x0, - struct: IType.STRUCT, - constructor: IType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - AluMicroOp(MicroOpAluFunct.add, MicroOpField.rs1, MicroOpField.imm), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'slliw', - opcode: 0x1B, - funct3: 0x1, - struct: IType.STRUCT, - constructor: IType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - AluMicroOp(MicroOpAluFunct.sll, MicroOpField.rs1, MicroOpField.imm), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'srliw', - opcode: 0x1B, - funct3: 0x5, - struct: IType.STRUCT, - constructor: IType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - AluMicroOp(MicroOpAluFunct.srl, MicroOpField.rs1, MicroOpField.imm), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'sraiw', - opcode: 0x1B, - funct3: 0x5, - funct7: 0x20, - struct: IType.STRUCT, - constructor: IType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - AluMicroOp(MicroOpAluFunct.sra, MicroOpField.rs1, MicroOpField.imm), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'addw', - opcode: 0x3B, - funct3: 0x0, - funct7: 0x00, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AluMicroOp(MicroOpAluFunct.add, MicroOpField.rs1, MicroOpField.rs2), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'subw', - opcode: 0x3B, - funct3: 0x0, - funct7: 0x20, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AluMicroOp(MicroOpAluFunct.sub, MicroOpField.rs1, MicroOpField.rs2), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'sllw', - opcode: 0x3B, - funct3: 0x1, - funct7: 0x00, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AluMicroOp(MicroOpAluFunct.sll, MicroOpField.rs1, MicroOpField.rs2), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'srlw', - opcode: 0x3B, - funct3: 0x5, - funct7: 0x00, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AluMicroOp(MicroOpAluFunct.srl, MicroOpField.rs1, MicroOpField.rs2), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - Operation( - mnemonic: 'sraw', - opcode: 0x3B, - funct3: 0x5, - funct7: 0x20, - struct: RType.STRUCT, - constructor: RType.map, - microcode: [ - ReadRegisterMicroOp(MicroOpField.rs1), - ReadRegisterMicroOp(MicroOpField.rs2), - AluMicroOp(MicroOpAluFunct.sra, MicroOpField.rs1, MicroOpField.rs2), - WriteRegisterMicroOp(MicroOpField.rd, MicroOpSource.alu), - UpdatePCMicroOp(MicroOpField.pc, offset: 4), - ], - ), - ], - name: 'RV64I', - key: 'I', - mask: 1 << 8, -); diff --git a/packages/riscv/pubspec.yaml b/packages/riscv/pubspec.yaml deleted file mode 100644 index ac421e5..0000000 --- a/packages/riscv/pubspec.yaml +++ /dev/null @@ -1,17 +0,0 @@ -name: riscv -description: RISC-V as a library -version: 1.0.0 -resolution: workspace -# repository: https://github.com/my_org/my_repo - -environment: - sdk: ^3.9.3 - -# Add regular dependencies here. -dependencies: - # path: ^1.9.0 - -dev_dependencies: - lints: ^6.0.0 - test: ^1.28.0 - dartdoc: ^9.0.0 diff --git a/packages/riscv/test/rv32i_test.dart b/packages/riscv/test/rv32i_test.dart deleted file mode 100644 index e9512bc..0000000 --- a/packages/riscv/test/rv32i_test.dart +++ /dev/null @@ -1,94 +0,0 @@ -import 'package:riscv/riscv.dart'; -import 'package:test/test.dart'; - -void main() { - group('Decode RV32I', () { - test('Decode map', () { - final mc = Microcode(rv32i.decodeMap); - final lookup = {0x002081B3: 'add', 0x00A08293: 'addi'}; - - for (final entry in lookup.entries) { - expect(mc.lookup(entry.key)!.mnemonic, equals(entry.value)); - } - }); - - test('R-type: add x3, x1, x2', () { - const instr = 0x002081B3; - final decoded = InstructionDecode.decode(instr); - - expect(decoded.value, isA()); - final r = decoded.value as RType; - - expect(r.opcode, equals(0x33)); - expect(r.rd, equals(3)); - expect(r.rs1, equals(1)); - expect(r.rs2, equals(2)); - expect(r.funct3, equals(0x0)); - expect(r.funct7, equals(0x00)); - }); - - test('I-type: addi x5, x1, 10', () { - const instr = 0x00A08293; - final decoded = InstructionDecode.decode(instr); - - expect(decoded.value, isA()); - final i = decoded.value as IType; - - expect(i.opcode, equals(0x13)); - expect(i.rd, equals(5)); - expect(i.rs1, equals(1)); - expect(i.funct3, equals(0x0)); - expect(i.imm, equals(10)); - }); - - test('S-type: sw x2, 12(x1)', () { - const instr = 0x0020A623; - final decoded = InstructionDecode.decode(instr); - - expect(decoded.value, isA()); - final s = decoded.value as SType; - - expect(s.opcode, equals(0x23)); - expect(s.rs1, equals(1)); - expect(s.rs2, equals(2)); - expect(s.funct3, equals(0x2)); - expect(s.imm, equals(12)); - }); - - test('B-type: beq x1, x2, offset=8', () { - const instr = 0x00208663; - final decoded = InstructionDecode.decode(instr); - - expect(decoded.value, isA()); - final b = decoded.value as BType; - - expect(b.opcode, equals(0x63)); - expect(b.rs1, equals(1)); - expect(b.rs2, equals(2)); - expect(b.funct3, equals(0x0)); - }); - - test('U-type: lui x5, 0x12345000', () { - const instr = 0x123452B7; - final decoded = InstructionDecode.decode(instr); - - expect(decoded.value, isA()); - final u = decoded.value as UType; - - expect(u.opcode, equals(0x37)); - expect(u.rd, equals(5)); - expect(u.imm, equals(0x12345000)); - }); - - test('J-type: jal x1, 0x100', () { - const instr = 0x000100EF; - final decoded = InstructionDecode.decode(instr); - - expect(decoded.value, isA()); - final j = decoded.value as JType; - - expect(j.opcode, equals(0x6F)); - expect(j.rd, equals(1)); - }); - }); -} diff --git a/packages/riscv/test/rv64i_test.dart b/packages/riscv/test/rv64i_test.dart deleted file mode 100644 index d4b3bd1..0000000 --- a/packages/riscv/test/rv64i_test.dart +++ /dev/null @@ -1,72 +0,0 @@ -import 'package:riscv/riscv.dart'; -import 'package:test/test.dart'; - -void main() { - group('Decode RV64I', () { - test('I-type: addiw x10, x11, 1', () { - const instr = 0x0015851B; - final i = ITypeDecode.decode(instr); - expect(i.opcode, equals(0x1B)); - expect(i.rd, equals(10)); - expect(i.rs1, equals(11)); - expect(i.funct3, equals(0)); - expect(i.imm, equals(1)); - }); - - test('I-type: slli x5, x6, 3', () { - const instr = 0x00331293; - final i = ITypeDecode.decode(instr); - expect(i.opcode, equals(0x13)); - expect(i.rd, equals(5)); - expect(i.rs1, equals(6)); - expect(i.funct3, equals(1)); - expect(i.imm, equals(3)); - }); - - test('I-type: ld x8, 16(x9)', () { - const instr = 0x0104B403; - final i = ITypeDecode.decode(instr); - expect(i.opcode, equals(0x03)); - expect(i.rd, equals(8)); - expect(i.rs1, equals(9)); - expect(i.funct3, equals(3)); - expect(i.imm, equals(16)); - }); - - test('S-type: sd x5, 8(x6)', () { - const instr = 0x00533423; - final s = STypeDecode.decode(instr); - expect(s.opcode, equals(0x23)); - expect(s.rs1, equals(6)); - expect(s.rs2, equals(5)); - expect(s.funct3, equals(3)); - expect(s.imm, equals(8)); - }); - - test('U-type: lui x10, 0x12345000', () { - const instr = 0x12345537; - final u = UTypeDecode.decode(instr); - expect(u.opcode, equals(0x37)); - expect(u.rd, equals(10)); - expect(u.imm, equals(0x12345000)); - }); - - test('J-type: jal x1, 0x00000010', () { - const instr = 0x010000EF; - final j = JTypeDecode.decode(instr); - expect(j.opcode, equals(0x6F)); - expect(j.rd, equals(1)); - expect(j.imm, equals(16)); - }); - - test('B-type: beq x1, x2, 8', () { - const instr = 0x00208463; - final b = BTypeDecode.decode(instr); - expect(b.opcode, equals(0x63)); - expect(b.rs1, equals(1)); - expect(b.rs2, equals(2)); - expect(b.funct3, equals(0)); - expect(b.imm, equals(8)); - }); - }); -} diff --git a/packages/riscv/test/rvc_test.dart b/packages/riscv/test/rvc_test.dart deleted file mode 100644 index bbb3bc7..0000000 --- a/packages/riscv/test/rvc_test.dart +++ /dev/null @@ -1,87 +0,0 @@ -import 'package:riscv/riscv.dart'; -import 'package:test/test.dart'; - -void main() { - group('Decode RVC', () { - test('WI-type: c.addi4spn x8, 16(sp)', () { - const instr = 0x0020; - final decoded = CompressedInstructionDecode.decode(instr); - - expect(decoded.value, isA()); - final wi = decoded.value as CompressedWIType; - - expect(wi.rd, equals(0)); - expect(wi.imm, equals(1)); - expect(wi.funct3, equals(0)); - }); - - test('L-type: c.lw x9, 8(x2)', () { - const instr = 0x4224; - final decoded = CompressedInstructionDecode.decode(instr); - - expect(decoded.value, isA()); - final cl = decoded.value as CompressedLType; - - expect(cl.funct3, equals(2)); - expect(cl.rs1, equals(4)); - expect(cl.rd, equals(1)); - }); - - test('S-type: c.sw x9, 8(x2)', () { - const instr = 0xC204; - final decoded = CompressedInstructionDecode.decode(instr); - - expect(decoded.value, isA()); - final cs = decoded.value as CompressedSType; - - expect(cs.funct3, equals(6)); - expect(cs.rs1, equals(4)); - expect(cs.rs2, equals(1)); - }); - - test('I-type: c.addi x1, 1', () { - const instr = 0x0085; - final decoded = CompressedInstructionDecode.decode(instr); - - expect(decoded.value, isA()); - final ci = decoded.value as CompressedIType; - - expect(ci.funct3, equals(0)); - expect(ci.rs1, equals(1)); - expect(ci.imm4_0, equals(1)); - }); - - test('J-type: c.j 0x4', () { - const instr = 0xA011; - final decoded = CompressedInstructionDecode.decode(instr); - - expect(decoded.value, isA()); - final cj = decoded.value as CompressedJType; - - expect(cj.funct3, equals(5)); - expect(cj.value, isNonZero); - }); - - test('A-type: c.and x8, x9', () { - const instr = 0x8CE1; - final decoded = CompressedInstructionDecode.decode(instr); - - expect(decoded.value, isA()); - final ca = decoded.value as CompressedAType; - - expect(ca.rs1, equals(1)); - expect(ca.rs2, equals(0)); - }); - - test('SS-type: c.swsp x5, 12(sp)', () { - const instr = 0xC616; - final decoded = CompressedInstructionDecode.decode(instr); - - expect(decoded.value, isA()); - final css = decoded.value as CompressedSSType; - - expect(css.rs2, equals(5)); - expect(css.imm, isPositive); - }); - }); -} diff --git a/packages/river/analysis_options.yaml b/packages/river/analysis_options.yaml index dee8927..f5d48c9 100644 --- a/packages/river/analysis_options.yaml +++ b/packages/river/analysis_options.yaml @@ -1,30 +1,2 @@ -# This file configures the static analysis results for your project (errors, -# warnings, and lints). -# -# This enables the 'recommended' set of lints from `package:lints`. -# This set helps identify many issues that may lead to problems when running -# or consuming Dart code, and enforces writing Dart using a single, idiomatic -# style and format. -# -# If you want a smaller set of lints you can change this to specify -# 'package:lints/core.yaml'. These are just the most critical lints -# (the recommended set includes the core lints). -# The core lints are also what is used by pub.dev for scoring packages. - -include: package:lints/recommended.yaml - -# Uncomment the following section to specify additional rules. - -# linter: -# rules: -# - camel_case_types - -# analyzer: -# exclude: -# - path/to/excluded/files/** - -# For more information about the core and recommended set of lints, see -# https://dart.dev/go/core-lints - -# For additional information about configuring this file, see -# https://dart.dev/guides/language/analysis-options +# Inherits the workspace production analysis baseline. +include: ../../analysis_options.yaml diff --git a/packages/river/lib/river.dart b/packages/river/lib/river.dart index 9503f5e..80c2a44 100644 --- a/packages/river/lib/river.dart +++ b/packages/river/lib/river.dart @@ -1,10 +1,10 @@ library; -export 'src/bus.dart'; -export 'src/cache.dart'; -export 'src/clock.dart'; -export 'src/dev.dart'; +export 'package:harbor/harbor.dart' hide PrivilegeMode; + +export 'src/csr_address.dart'; +export 'src/fp_extra.dart'; export 'src/impl.dart'; -export 'src/interconnect.dart'; -export 'src/mem.dart'; +export 'src/profiles.dart'; +export 'src/register.dart'; export 'src/river_base.dart'; diff --git a/packages/river/lib/src/bus.dart b/packages/river/lib/src/bus.dart deleted file mode 100644 index 13621ed..0000000 --- a/packages/river/lib/src/bus.dart +++ /dev/null @@ -1,92 +0,0 @@ -import 'dev.dart'; - -enum BusArbitration { fixed, roundRobin, priority } - -class BusAddressRange { - final int start; - final int size; - - const BusAddressRange(this.start, this.size); - - BusAddressRange.from(BusAddressRange base, {int offset = 0, int? size}) - : start = base.start + offset, - size = size ?? base.size; - - bool contains(int addr) => addr >= start && addr < end; - - int get end => start + size; - - BusAddressRange shift({int offset = 0, int? size}) => - BusAddressRange(start + offset, size ?? this.size); - - @override - String toString() => 'BusAddressRange(start: $start, end: $end, size: $size)'; -} - -abstract class BusPort { - String get name; - - const BusPort(); - - bool inRange(int addr); - - @override - String toString() => 'BusPort($name)'; -} - -class BusClientPort extends BusPort { - @override - final String name; - - final BusAddressRange range; - final DeviceAccessor accessor; - - const BusClientPort({ - required this.name, - required this.range, - required this.accessor, - }); - - factory BusClientPort.simple({ - required String name, - required BusAddressRange range, - required Map fields, - }) => BusClientPort( - name: name, - range: range, - accessor: DeviceAccessor(name, fields), - ); - - @override - bool inRange(int addr) => range.contains(addr); - - @override - String toString() => - 'BusClientPort(name: $name, range: $range, accessor: $accessor)'; -} - -class BusHostPort extends BusPort { - @override - final String name; - - const BusHostPort(this.name); - - @override - bool inRange(int addr) => false; - - @override - String toString() => 'BusHostPort($name)'; -} - -class BusRead { - final int addr; - final int width; - const BusRead(this.addr, {this.width = 4}); -} - -class BusWrite { - final int addr; - final int width; - - const BusWrite(this.addr, {this.width = 4}); -} diff --git a/packages/river/lib/src/cache.dart b/packages/river/lib/src/cache.dart deleted file mode 100644 index c1353d8..0000000 --- a/packages/river/lib/src/cache.dart +++ /dev/null @@ -1,53 +0,0 @@ -import 'bus.dart'; -import 'dev.dart'; - -class Cache { - final int size; - final int lineSize; - final int ways; - - const Cache({required this.size, required this.lineSize, required this.ways}); - - int get lines => size ~/ lineSize; - - @override - String toString() => 'Cache(size: $size, lineSize: $lineSize, ways: $ways)'; -} - -class L1iCache extends Cache { - const L1iCache({ - required super.size, - required super.lineSize, - required super.ways, - }); -} - -class L1dCache extends Cache { - const L1dCache({ - required super.size, - required super.lineSize, - required super.ways, - }); -} - -class L1Cache { - final L1iCache? i; - final L1dCache d; - - const L1Cache({required this.i, required this.d}); - - const L1Cache.unified(this.d) : i = null; - - L1Cache.split({ - required int iSize, - required int dSize, - required int ways, - required int lineSize, - }) : i = L1iCache(size: iSize, lineSize: lineSize, ways: ways), - d = L1dCache(size: dSize, lineSize: lineSize, ways: ways); - - bool get unified => i == null; - - @override - String toString() => 'L1Cache(i: $i, d: $d)'; -} diff --git a/packages/river/lib/src/clock.dart b/packages/river/lib/src/clock.dart deleted file mode 100644 index 0b8084c..0000000 --- a/packages/river/lib/src/clock.dart +++ /dev/null @@ -1,71 +0,0 @@ -class ClockConfig { - final String name; - final double baseFreqHz; - final List divisors; - - const ClockConfig({ - required this.name, - required this.baseFreqHz, - this.divisors = const [], - }); - - double frequencyForDivisor(double divisor) => baseFreqHz / divisor; - - @override - String toString() => - 'ClockConfig(name: $name, baseFreqHz: $baseFreqHz, divisors: $divisors)'; -} - -class ClockDomainConfig { - final String name; - final String? source; - final double freqHz; - final double? divider; - final List divisors; - - const ClockDomainConfig({ - required this.name, - required this.freqHz, - this.source, - this.divider, - this.divisors = const [], - }); - - ClockConfig get clock => - ClockConfig(name: name, baseFreqHz: freqHz, divisors: divisors); - - ClockDomain getDomain({List consumers = const []}) => ClockDomain( - name: name, - source: source, - freqHz: freqHz, - divider: divider, - consumers: consumers, - ); - - static ClockDomainConfig? from(dynamic value) { - if (value is ClockDomainConfig) return value as ClockDomainConfig; - // TODO: add a way to parse value if it a string - return null; - } -} - -class ClockDomain { - final String name; - final double freqHz; - final String? source; - final double? divider; - final List consumers; - - const ClockDomain({ - required this.name, - required this.freqHz, - this.source, - this.divider, - this.consumers = const [], - }); - - @override - String toString() => - 'ClockDomain(name: $name, freqHz: $freqHz, ' - 'source: $source, divider: $divider, consumers: $consumers)'; -} diff --git a/packages/river/lib/src/csr_address.dart b/packages/river/lib/src/csr_address.dart new file mode 100644 index 0000000..247d1cc --- /dev/null +++ b/packages/river/lib/src/csr_address.dart @@ -0,0 +1,157 @@ +/// CSR address constants for the RISC-V emulator. +/// +/// Maps standard RISC-V CSR names to their addresses. +enum CsrAddress { + // Machine Information + mvendorid(0xF11), + marchid(0xF12), + mimpid(0xF13), + mhartid(0xF14), + mconfigptr(0xF15), + + // Machine Trap Setup + mstatus(0x300), + misa(0x301), + medeleg(0x302), + mideleg(0x303), + mie(0x304), + mtvec(0x305), + mcounteren(0x306), + mstatush(0x310), + + // Machine Trap Handling + mscratch(0x340), + mepc(0x341), + mcause(0x342), + mtval(0x343), + mip(0x344), + + // Machine Counter/Timer + mcycle(0xB00), + minstret(0xB02), + + // Supervisor Trap Setup + sstatus(0x100), + sie(0x104), + stvec(0x105), + scounteren(0x106), + + // Supervisor Trap Handling + sscratch(0x140), + sepc(0x141), + scause(0x142), + stval(0x143), + sip(0x144), + + // Supervisor Address Translation + satp(0x180), + + // Hypervisor Trap Setup + hstatus(0x600), + hedeleg(0x602), + hideleg(0x603), + hie(0x604), + hcounteren(0x606), + hgeie(0x607), + + // Hypervisor Trap Handling + htval(0x643), + hip(0x644), + hvip(0x645), + htinst(0x64A), + hgeip(0xE12), + + // Hypervisor Configuration / Timer / Translation + henvcfg(0x60A), + htimedelta(0x605), + hgatp(0x680), + + // Virtual Supervisor (VS-mode) CSRs + vsstatus(0x200), + vsie(0x204), + vstvec(0x205), + vsscratch(0x240), + vsepc(0x241), + vscause(0x242), + vstval(0x243), + vsip(0x244), + vsatp(0x280), + + // State Enable (Smstateen / Ssstateen) + mstateen0(0x30C), + mstateen1(0x30D), + mstateen2(0x30E), + mstateen3(0x30F), + sstateen0(0x10C), + sstateen1(0x10D), + sstateen2(0x10E), + sstateen3(0x10F), + hstateen0(0x60C), + hstateen1(0x60D), + hstateen2(0x60E), + hstateen3(0x60F), + + // User Trap Setup + ustatus(0x000), + uie(0x004), + utvec(0x005), + + // User Trap Handling + uscratch(0x040), + uepc(0x041), + ucause(0x042), + utval(0x043), + uip(0x044), + + // User Counter/Timer (read-only) + cycle(0xC00), + time(0xC01), + instret(0xC02), + + // Vector (V) extension + vstart(0x008), + vxsat(0x009), + vxrm(0x00A), + vcsr(0x00F), + vl(0xC20), + vtype(0xC21), + vlenb(0xC22), + + // River custom M-mode CSRs (0x7C0-0x7FF) + rcachectl(0x7C0), + rcacheaddr(0x7C1), + rcachesize(0x7C2), + // Pipeline / speculation control. WARL, reset 0. Bit fields: + // [0] SSBD - disable speculative store-bypass (force LSQ conservative) + // [1] BPD - disable branch prediction (force not-taken) + // [2] SERIALIZE- fence-like serialize of speculative execution + // [3] DTLBFC - flush the data TLB on every context switch + rpipelinectl(0x7C3), + // Microcode update (patchable microcode ROM). A ROM row can be wider than + // XLEN, so a patch is staged through [rmicrocodedata] in XLEN-bit chunks then + // committed. + // rmicrocodeaddr: ROM row index; bit[XLEN-1] selects exec(0) vs decode(1). + // rmicrocodedata: one XLEN-bit chunk of the row to stage. + // rmicrocodectl : write-pulse strobes (act for one cycle on any write): + // [0] PUSH - staging = (staging << XLEN) | rmicrocodedata + // [1] COMMIT- write staging into the selected ROM[rmicrocodeaddr] + // [2] CLEAR - staging = 0 + rmicrocodeaddr(0x7C4), + rmicrocodedata(0x7C5), + rmicrocodectl(0x7C6), + // Pipeline feature-discovery (machine read-only, 0xFC0). Bitmap from + // RiverCoreConfig (see RiverCoreConfig.rpipelineCap): OoO/dual/specfetch/ + // predictor/LSQ/forwarding/specLSQ/icache/paging. Writes trap (RO address). + rpipelinecap(0xFC0); + + final int address; + + const CsrAddress(this.address); + + static CsrAddress? find(int address) { + for (final csr in CsrAddress.values) { + if (csr.address == address) return csr; + } + return null; + } +} diff --git a/packages/river/lib/src/dev.dart b/packages/river/lib/src/dev.dart deleted file mode 100644 index 52a833a..0000000 --- a/packages/river/lib/src/dev.dart +++ /dev/null @@ -1,181 +0,0 @@ -import 'bus.dart'; -import 'clock.dart'; -import 'mem.dart'; -import 'river_base.dart'; - -class DevicePort { - final String name; - final int width; - final bool isOutput; - - const DevicePort(this.name, this.width, {this.isOutput = false}); - - @override - String toString() => 'DevicePort($name, $width, isOutput: $isOutput)'; -} - -class DeviceField { - final String name; - final int width; - final int? offset; - - const DeviceField(this.name, this.width, {this.offset}); - - @override - String toString() => 'DeviceField($name, $width, offset: $offset)'; -} - -enum DeviceAccessorType { memory, io, mixed } - -class DeviceAccessor { - final String path; - final Map fields; - final DeviceAccessorType type; - final BusAddressRange? memoryRange; - final BusAddressRange? ioRange; - - const DeviceAccessor( - this.path, - this.fields, { - this.type = DeviceAccessorType.io, - this.memoryRange, - this.ioRange, - }); - - int? fieldAddress(String name) { - var offset = 0; - for (final field in fields.values) { - final start = field.offset ?? offset; - final end = start + field.width; - - if (name == field.name) { - return start; - } - - offset = end; - } - return null; - } - - DeviceField? getField(int addr) { - var offset = 0; - for (final field in fields.values) { - final start = field.offset ?? offset; - final end = start + field.width; - - if (addr >= start && addr < end) { - return field; - } - - offset = end; - } - return null; - } - - List getFields(int addr, int width) { - final end = addr + width; - - var offset = 0; - List list = []; - for (final field in fields.values) { - final start = field.offset ?? offset; - final fieldEnd = start + field.width; - - final overlaps = (addr < fieldEnd) && (end > start); - if (overlaps) { - list.add(field); - } - - offset = fieldEnd; - } - return list; - } - - String? readPath(int addr) { - final field = getField(addr); - if (field == null) return null; - return '$path/${field.name}%read'; - } - - String? writePath(int addr) { - final field = getField(addr); - if (field == null) return null; - return '$path/${field.name}%write'; - } - - @override - String toString() => 'DeviceAccessor($path, $fields)'; -} - -class Device { - final String name; - final String compatible; - final BusAddressRange? range; - final List interrupts; - final List ports; - final DeviceAccessor? accessor; - final BusClientPort? clientPort; - final ClockConfig? clock; - - String get module => (runtimeType.toString() == 'Device') - ? compatible.replaceAll(',', '_') - : runtimeType.toString(); - - const Device({ - required this.name, - required this.compatible, - this.range, - this.interrupts = const [], - this.ports = const [], - this.accessor, - this.clientPort, - this.clock, - }); - - factory Device.simple({ - required String name, - required String compatible, - String? path, - BusAddressRange? range, - List interrupts = const [], - Map? fields, - DeviceAccessorType type = DeviceAccessorType.memory, - ClockConfig? clock, - List ports = const [], - }) { - path ??= '/$name'; - final accessor = fields != null - ? DeviceAccessor(path, fields, type: type) - : null; - final clientPort = fields != null && range != null - ? BusClientPort( - name: path, - range: range!, - accessor: DeviceAccessor(path, fields), - ) - : null; - - return Device( - name: name, - compatible: compatible, - range: range, - interrupts: interrupts, - accessor: accessor, - clientPort: clientPort, - clock: clock, - ports: ports, - ); - } - - MemoryBlock? get mmap { - if (range != null && accessor != null) { - return MemoryBlock(range!.start, range!.size, accessor!); - } - return null; - } - - @override - String toString() => - 'Device(name: \"$name\", compatible: \"$compatible\", range: $range,' - ' interrupts: $interrupts, ports: $ports, accessor: $accessor, clientPort: $clientPort, clock: $clock)'; -} diff --git a/packages/river/lib/src/fp_extra.dart b/packages/river/lib/src/fp_extra.dart new file mode 100644 index 0000000..27a7451 --- /dev/null +++ b/packages/river/lib/src/fp_extra.dart @@ -0,0 +1,135 @@ +import 'package:harbor/harbor.dart'; + +/// Supplementary F/D operations that Harbor's `rvF`/`rvD` extensions do not +/// yet define as instructions, but whose [RiscVFpuFunct] values already exist +/// (and which the emulator implements): sign-injection (fsgnj/fsgnjn/fsgnjx), +/// fmin/fmax, fclass, and the raw bit-move fmv. Kept on the river side so +/// Harbor stays untouched; add to a config's extension list alongside rvF/rvD. +/// +/// misaBit is null (mask 0) so this does not affect the reported misa, rvF/rvD +/// already set the F/D bits. All ops are OP-FP (opcode 0x53), distinguished by +/// funct7/funct3, with no collisions against the existing F/D encodings. + +const _fp32 = RiscVFloatRegFile(32); +const _fp64 = RiscVFloatRegFile(64); +const _int = RiscVIntRegFile(32); + +// Binary FP op (two FP sources, FP dest): fsgnj*/fmin/fmax. +RiscVOperation _binFp( + String mnemonic, + int funct7, + int funct3, + RiscVFpuFunct funct, + RiscVFloatRegFile fp, { + required bool dp, +}) => RiscVOperation( + mnemonic: mnemonic, + opcode: 0x53, + funct7: funct7, + funct3: funct3, + format: rType, + resources: [ + RfResource(fp, rs1), + RfResource(fp, rs2), + RfResource(fp, rd), + FpuResource(), + ], + microcode: [ + RiscVReadRegister(RiscVMicroOpField.rs1), + RiscVReadRegister(RiscVMicroOpField.rs2), + RiscVFpuOp( + funct, + RiscVMicroOpField.rs1, + RiscVMicroOpField.rd, + b: RiscVMicroOpField.rs2, + doublePrecision: dp, + ), + RiscVWriteRegister(RiscVMicroOpField.rd, RiscVMicroOpSource.rd), + RiscVUpdatePc(RiscVMicroOpField.pc, offset: 4), + ], +); + +// Unary FP->int op: fclass, fmv.x.w/fmv.x.d. +RiscVOperation _fpToInt( + String mnemonic, + int funct7, + int funct3, + RiscVFpuFunct funct, + RiscVFloatRegFile fp, { + required bool dp, +}) => RiscVOperation( + mnemonic: mnemonic, + opcode: 0x53, + funct7: funct7, + funct3: funct3, + format: rType, + resources: [RfResource(fp, rs1), RfResource(_int, rd), FpuResource()], + microcode: [ + RiscVReadRegister(RiscVMicroOpField.rs1), + RiscVFpuOp( + funct, + RiscVMicroOpField.rs1, + RiscVMicroOpField.rd, + doublePrecision: dp, + ), + RiscVWriteRegister(RiscVMicroOpField.rd, RiscVMicroOpSource.rd), + RiscVUpdatePc(RiscVMicroOpField.pc, offset: 4), + ], +); + +// Unary int->FP op: fmv.w.x/fmv.d.x (raw bit move). +RiscVOperation _intToFp( + String mnemonic, + int funct7, + int funct3, + RiscVFloatRegFile fp, { + required bool dp, +}) => RiscVOperation( + mnemonic: mnemonic, + opcode: 0x53, + funct7: funct7, + funct3: funct3, + format: rType, + resources: [RfResource(_int, rs1), RfResource(fp, rd), FpuResource()], + microcode: [ + RiscVReadRegister(RiscVMicroOpField.rs1), + RiscVFpuOp( + RiscVFpuFunct.fmv, + RiscVMicroOpField.rs1, + RiscVMicroOpField.rd, + doublePrecision: dp, + ), + RiscVWriteRegister(RiscVMicroOpField.rd, RiscVMicroOpSource.rd), + RiscVUpdatePc(RiscVMicroOpField.pc, offset: 4), + ], +); + +/// Supplementary single-precision (F) ops. +final RiscVExtension rvFExtra = RiscVExtension( + name: 'Fx', + operations: [ + _binFp('fsgnj.s', 0x10, 0x0, RiscVFpuFunct.fsgnj, _fp32, dp: false), + _binFp('fsgnjn.s', 0x10, 0x1, RiscVFpuFunct.fsgnjn, _fp32, dp: false), + _binFp('fsgnjx.s', 0x10, 0x2, RiscVFpuFunct.fsgnjx, _fp32, dp: false), + _binFp('fmin.s', 0x14, 0x0, RiscVFpuFunct.fmin, _fp32, dp: false), + _binFp('fmax.s', 0x14, 0x1, RiscVFpuFunct.fmax, _fp32, dp: false), + _fpToInt('fclass.s', 0x70, 0x1, RiscVFpuFunct.fclass, _fp32, dp: false), + _fpToInt('fmv.x.w', 0x70, 0x0, RiscVFpuFunct.fmv, _fp32, dp: false), + _intToFp('fmv.w.x', 0x78, 0x0, _fp32, dp: false), + ], +); + +/// Supplementary double-precision (D) ops. +final RiscVExtension rvDExtra = RiscVExtension( + name: 'Dx', + operations: [ + _binFp('fsgnj.d', 0x11, 0x0, RiscVFpuFunct.fsgnj, _fp64, dp: true), + _binFp('fsgnjn.d', 0x11, 0x1, RiscVFpuFunct.fsgnjn, _fp64, dp: true), + _binFp('fsgnjx.d', 0x11, 0x2, RiscVFpuFunct.fsgnjx, _fp64, dp: true), + _binFp('fmin.d', 0x15, 0x0, RiscVFpuFunct.fmin, _fp64, dp: true), + _binFp('fmax.d', 0x15, 0x1, RiscVFpuFunct.fmax, _fp64, dp: true), + _fpToInt('fclass.d', 0x71, 0x1, RiscVFpuFunct.fclass, _fp64, dp: true), + _fpToInt('fmv.x.d', 0x71, 0x0, RiscVFpuFunct.fmv, _fp64, dp: true), + _intToFp('fmv.d.x', 0x79, 0x0, _fp64, dp: true), + ], +); diff --git a/packages/river/lib/src/impl.dart b/packages/river/lib/src/impl.dart index 4f53314..964a398 100644 --- a/packages/river/lib/src/impl.dart +++ b/packages/river/lib/src/impl.dart @@ -1,29 +1 @@ -import 'impl/core.dart'; -import 'impl/soc.dart'; -import 'river_base.dart'; - export 'impl/core.dart'; -export 'impl/devices.dart'; -export 'impl/soc.dart'; - -enum RiverPlatformChoice { - alpha('alpha', RiverSoCChoice.creek_v1), - icesugar('icesugar', RiverSoCChoice.stream_v1); - - const RiverPlatformChoice(this.name, this.soc); - - final String name; - final RiverSoCChoice soc; - - RiverCoreChoice get core => soc.core; - - RiverSoC? configureSoC(Map options) => - soc.configure({...options, 'platform': name}); - - static RiverPlatformChoice? getChoice(String name) { - for (final choice in RiverPlatformChoice.values) { - if (choice.name == name) return choice; - } - return null; - } -} diff --git a/packages/river/lib/src/impl/core.dart b/packages/river/lib/src/impl/core.dart index 7c7ee40..f17deb8 100644 --- a/packages/river/lib/src/impl/core.dart +++ b/packages/river/lib/src/impl/core.dart @@ -1,17 +1 @@ export 'core/v1.dart'; - -enum RiverCoreChoice { - rc1_s('rc1.s'), - rc1_n('rc1.n'); - - const RiverCoreChoice(this.name); - - final String name; - - static RiverCoreChoice? getChoice(String name) { - for (final choice in RiverCoreChoice.values) { - if (choice.name == name) return choice; - } - return null; - } -} diff --git a/packages/river/lib/src/impl/core/v1.dart b/packages/river/lib/src/impl/core/v1.dart index 98d20f1..091df6b 100644 --- a/packages/river/lib/src/impl/core/v1.dart +++ b/packages/river/lib/src/impl/core/v1.dart @@ -1,16 +1,25 @@ -import 'package:riscv/riscv.dart'; -import '../../clock.dart'; -import '../../mem.dart'; +import 'package:harbor/harbor.dart'; import '../../river_base.dart'; +import '../../fp_extra.dart'; -/// RC1 - River Core V1 -class RiverCoreV1 extends RiverCore { - /// RC1.n - River Core V1 nano - /// - /// A RV32IC core using the River design. - const RiverCoreV1.nano({ +/// V1 core tier definitions. +/// +/// Each tier is a complete identity: ISA, supervisor/user, and pipeline +/// personality (execution mode + issue width) are all set by the tier and not +/// overridable. To experiment with a different pipeline configuration, define +/// a new tier rather than punching a hole through an existing one. +class RiverCoreConfigV1 extends RiverCoreConfig { + /// Default split L1 for the cache-bearing RC1 tiers: direct-mapped with + /// single-word lines, so each miss is one paced memory read rather than a + /// burst. Boards may override via the tier's `l1cache` parameter. + static HarborL1CacheConfig _rc1L1() => + HarborL1CacheConfig.split(iSize: 64, dSize: 256, ways: 1, lineSize: 8); + + /// RC1.n - River Core V1 nano (RV32IC), in-order single-issue, MCU tier + /// (e.g. iCESugar up5k). Lean and FPGA-friendly. + RiverCoreConfigV1.nano({ super.vendorId = 0, - super.archId = 0, + super.archId = riverArchId, super.hartId = 0, super.resetVector = 0, required super.mmu, @@ -18,19 +27,24 @@ class RiverCoreV1 extends RiverCore { required super.clock, super.l1cache, }) : super( - mxlen: Mxlen.mxlen_32, - extensions: const [rvc, rv32i], + mxlen: RiscVMxlen.rv32, + extensions: [rvC, rv32i], hasSupervisor: false, hasUser: false, type: RiverCoreType.mcu, + executionMode: ExecutionMode.inOrder, + issueWidth: IssueWidth.single, + // MCU tier: no L1 cache, area-first. Microcode datapath (ROM + one + // shared ALU) instead of the static per-instruction fabric: smaller + // area, slower per instruction. + microcodeMode: MicrocodeMode.full, ); - /// RC1.mi - River Core V1 micro - /// - /// A RV32IMAC core using the River design. - const RiverCoreV1.micro({ + /// RC1.mi - River Core V1 micro (RV32IMAC_Zicsr_Zifencei), in-order + /// single-issue, embedded general-purpose tier. + RiverCoreConfigV1.micro({ super.vendorId = 0, - super.archId = 0, + super.archId = riverArchId, super.hartId = 0, super.resetVector = 0, required super.mmu, @@ -38,42 +52,116 @@ class RiverCoreV1 extends RiverCore { required super.clock, super.l1cache, }) : super( - mxlen: Mxlen.mxlen_32, - extensions: const [ - rvc, - rv32Zicsr, - rv32BasePrivilege, - rv32M, - rv32Atomics, + mxlen: RiscVMxlen.rv32, + extensions: [rvC, rvZicsr, rvZifencei, rvM, rvA, rvPriv, rv32i], + type: RiverCoreType.general, + executionMode: ExecutionMode.inOrder, + issueWidth: IssueWidth.single, + // Embedded tier: no L1 cache (l1cache stays null), area-first. + ); + + /// RC1.s - River Core V1 small (RV64IMAC_Zicsr_Zifencei), in-order + /// single-issue, RV64 general-purpose tier. + RiverCoreConfigV1.small({ + super.vendorId = 0, + super.archId = riverArchId, + super.hartId = 0, + super.resetVector = 0, + required super.mmu, + required super.interrupts, + required super.clock, + HarborL1CacheConfig? l1cache, + }) : super( + l1cache: l1cache ?? _rc1L1(), + mxlen: RiscVMxlen.rv64, + extensions: [rvC, rvZicsr, rvZifencei, rvM, rvA, rvPriv, rv64i, rv32i], + type: RiverCoreType.general, + executionMode: ExecutionMode.inOrder, + issueWidth: IssueWidth.single, + // Split L1 (see [_rc1L1]) is part of this tier: single-word fills mean + // DRAM sees only paced reads, a correctness lever on creek's DDR PHY, + // not just a perf choice. Microcode datapath (shared ALU) over the + // static fabric: ~12k vs ~21k LUT on small FPGAs. + microcodeMode: MicrocodeMode.full, + ); + + /// RC1.f - River Core V1 full (RV64GC_Zicsr_Zifencei), in-order single-issue, + /// the RV64 application tier with hardware floating point (G = IMAFD). Same + /// scalar personality as [small]; adds F/D. See docs/core/design.md. + RiverCoreConfigV1.full({ + super.vendorId = 0, + super.archId = riverArchId, + super.hartId = 0, + super.resetVector = 0, + required super.mmu, + required super.interrupts, + required super.clock, + HarborL1CacheConfig? l1cache, + }) : super( + l1cache: l1cache ?? _rc1L1(), + mxlen: RiscVMxlen.rv64, + extensions: [ + rvC, + rvZicsr, + rvZifencei, + rvM, + rvA, + rvF, + rvD, + rvFExtra, + rvDExtra, + rvPriv, + rv64i, rv32i, ], type: RiverCoreType.general, + executionMode: ExecutionMode.inOrder, + issueWidth: IssueWidth.single, + // Same scalar personality as [small] (+ F/D), so it carries the same + // L1 caches (see [_rc1L1]). ); - /// RC1.s - River Core V1 small - /// - /// A RV64IMAC core using the River design. - const RiverCoreV1.small({ + /// RC1.ma - River Core V1 macro (RV64GC_Zba_Zbb_Zbs): out-of-order, + /// dual-issue RV64GC, the big-chip superscalar tier (docs/core/design.md). + /// The CompressedFetchBuffer + InstructionAligner co-dispatch two + /// variable-length instructions per cycle; the static decoder handles RVC. + RiverCoreConfigV1.macro({ super.vendorId = 0, - super.archId = 0, + super.archId = riverArchId, super.hartId = 0, super.resetVector = 0, required super.mmu, required super.interrupts, required super.clock, - super.l1cache, + HarborL1CacheConfig? l1cache, }) : super( - mxlen: Mxlen.mxlen_64, - extensions: const [ - rvc, - rv32Zicsr, - rv32BasePrivilege, - rv32M, - rv64M, - rv32Atomics, - rv64Atomics, + l1cache: l1cache ?? _rc1L1(), + mxlen: RiscVMxlen.rv64, + // Base ISA first: the OoO static decoder takes the first matching + // pattern, and Zba/Zbb/Zbs share OP-IMM/OP opcodes with the base ALU + // ops, so base-first gives plain add/addi decode priority. + extensions: [ + rv64i, rv32i, + rvC, + rvZicsr, + rvZifencei, + rvM, + rvA, + rvPriv, + rvF, + rvD, + rvFExtra, + rvDExtra, + rvZba, + rvZbb, + rvZbs, ], type: RiverCoreType.general, + executionMode: ExecutionMode.outOfOrder, + speculativeFetch: true, + issueWidth: IssueWidth.dual, + // OoO dual-issue: L1 caches (see [_rc1L1]) are part of the tier; the + // I-cache runs dual-port (both fetch lanes), wired from issueWidth. ); } diff --git a/packages/river/lib/src/impl/devices.dart b/packages/river/lib/src/impl/devices.dart deleted file mode 100644 index ee3c99a..0000000 --- a/packages/river/lib/src/impl/devices.dart +++ /dev/null @@ -1,4 +0,0 @@ -export 'devices/clint.dart'; -export 'devices/dram.dart'; -export 'devices/plic.dart'; -export 'devices/uart.dart'; diff --git a/packages/river/lib/src/impl/devices/clint.dart b/packages/river/lib/src/impl/devices/clint.dart deleted file mode 100644 index 19b2fb1..0000000 --- a/packages/river/lib/src/impl/devices/clint.dart +++ /dev/null @@ -1,23 +0,0 @@ -import 'package:riscv/riscv.dart'; - -import '../../bus.dart'; -import '../../clock.dart'; -import '../../dev.dart'; - -class RiscVClint extends Device { - RiscVClint({ - required String name, - required int address, - required ClockConfig clock, - }) : super( - name: name, - compatible: 'river,clint', - range: BusAddressRange(address, 0x00010000), - clock: clock, - accessor: DeviceAccessor('/$name', const { - 0: DeviceField('msip', 4, offset: 0), - 1: DeviceField('mtimecmp', 8, offset: 0x4000), - 2: DeviceField('mtime', 8, offset: 0xBFF8), - }, type: DeviceAccessorType.io), - ); -} diff --git a/packages/river/lib/src/impl/devices/dram.dart b/packages/river/lib/src/impl/devices/dram.dart deleted file mode 100644 index 2e46262..0000000 --- a/packages/river/lib/src/impl/devices/dram.dart +++ /dev/null @@ -1,95 +0,0 @@ -import 'package:riscv/riscv.dart'; - -import '../../bus.dart'; -import '../../clock.dart'; -import '../../dev.dart'; - -/// A DRAM controller for River -class RiverDram extends Device { - final int maxSize; - final int channels; - - RiverDram({ - required String name, - required int address, - required this.maxSize, - required this.channels, - required ClockConfig clock, - }) : super( - name: name, - compatible: 'river,dram', - range: BusAddressRange(address, (8 + (23 * channels)) + maxSize), - clock: clock, - accessor: DeviceAccessor( - '/$name', - { - 0: DeviceField('ctrl', 1), - 1: DeviceField('status', 1), - 2: DeviceField('size', 4), - 3: DeviceField('training_ctrl', 1), - 4: DeviceField('training_status', 1), - for (int i = 0; i < channels; i++) ...{ - (5 + (i * 9)): DeviceField('config$i', 2), - (6 + (i * 9)): DeviceField('timing$i', 2), - (7 + (i * 9)): DeviceField('train0_$i', 2), - (8 + (i * 9)): DeviceField('train1_$i', 2), - (9 + (i * 9)): DeviceField('vendor_$i', 2), - (10 + (i * 9)): DeviceField('device_$i', 2), - (11 + (i * 9)): DeviceField('type_$i', 1), - (12 + (i * 9)): DeviceField('speed_$i', 2), - (13 + (i * 9)): DeviceField('serial_$i', 8), - }, - }, - type: DeviceAccessorType.mixed, - memoryRange: BusAddressRange( - 8 + (23 * channels), - (8 + (23 * channels)) + maxSize, - ), - ioRange: BusAddressRange(0, 8 + (23 * channels)), - ), - ); - - static const ctrl = BitStruct({ - 'enable': BitRange.single(0), - 'reset': BitRange.single(1), - 'warmup': BitRange.single(2), - 'refresh': BitRange.single(3), - 'scrub': BitRange.single(4), - 'ecc': BitRange.single(5), - }); - - static const status = BitStruct({ - 'ready': BitRange.single(0), - 'training': BitRange.single(1), - 'error': BitRange.single(2), - 'reset': BitRange.single(3), - 'powered': BitRange.single(4), - 'ecc': BitRange.single(5), - }); - - static const trainingCtrl = BitStruct({ - 'start': BitRange.single(0), - 'abort': BitRange.single(1), - }); - - static const trainingStatus = BitStruct({ - 'busy': BitRange.single(0), - 'done': BitRange.single(1), - 'fail': BitRange.single(2), - }); - - static const train0 = BitStruct({ - 'dq_delay': BitRange(0, 5), - 'dqs_delay': BitRange(6, 11), - 'rd_level': BitRange.single(12), - 'wr_level': BitRange.single(13), - 'valid': BitRange.single(15), - }); - - static const train1 = BitStruct({ - 'vref': BitRange(0, 5), - 'odt': BitRange(6, 9), - 'drv': BitRange(10, 13), - 'valid': BitRange.single(15), - }); -} diff --git a/packages/river/lib/src/impl/devices/plic.dart b/packages/river/lib/src/impl/devices/plic.dart deleted file mode 100644 index 50e05c1..0000000 --- a/packages/river/lib/src/impl/devices/plic.dart +++ /dev/null @@ -1,48 +0,0 @@ -import 'package:riscv/riscv.dart'; - -import '../../bus.dart'; -import '../../clock.dart'; -import '../../dev.dart'; - -class RiscVPlic extends Device { - RiscVPlic({ - required String name, - required int address, - required ClockConfig clock, - required int interrupt, - int hartCount = 1, - }) : super( - name: name, - compatible: 'riscv,plic', - range: BusAddressRange(address, 0x4000000), - interrupts: [interrupt], - clock: clock, - accessor: DeviceAccessor('/$name', { - 0: DeviceField('priority', 4, offset: 0), - 1: DeviceField('pending', 4, offset: 0x000100), - ...{ - for ( - int hart = 0, idx = 2; - hart < hartCount; - hart++, idx += 3 - ) ...{ - idx: DeviceField( - 'enable_cpu$hart', - 4, - offset: 0x00000200 + (hart * 0x80), - ), - idx + 1: DeviceField( - 'threshold_cpu$hart', - 4, - offset: 0x00200000 + (hart * 0x1000), - ), - idx + 2: DeviceField( - 'claim_cpu$hart', - 4, - offset: 0x00200004 + (hart * 0x1000), - ), - }, - }, - }, type: DeviceAccessorType.io), - ); -} diff --git a/packages/river/lib/src/impl/devices/uart.dart b/packages/river/lib/src/impl/devices/uart.dart deleted file mode 100644 index 222ef9e..0000000 --- a/packages/river/lib/src/impl/devices/uart.dart +++ /dev/null @@ -1,93 +0,0 @@ -import 'package:riscv/riscv.dart'; - -import '../../bus.dart'; -import '../../clock.dart'; -import '../../dev.dart'; - -/// A NS16550-compatible UART for River -class RiverUart extends Device { - RiverUart({ - required String name, - required int address, - required ClockConfig clock, - required int interrupt, - }) : super( - name: name, - compatible: 'river,uart', - interrupts: [interrupt], - range: BusAddressRange(address, 0x20), - clock: clock, - accessor: DeviceAccessor('/$name', const { - 0: DeviceField('rbr_thr_dll', 1), - 1: DeviceField('ier_dlm', 1), - 2: DeviceField('iir_fcr', 1), - 3: DeviceField('lcr', 1), - 4: DeviceField('mcr', 1), - 5: DeviceField('lsr', 1), - 6: DeviceField('msr', 1), - 7: DeviceField('scr', 1), - }, type: DeviceAccessorType.io), - ports: [DevicePort('rx', 1), DevicePort('tx', 1, isOutput: true)], - ); - - static const lcr = BitStruct({ - 'wordLength': BitRange(0, 2), - 'stopBits': BitRange.single(2), - 'parityEnable': BitRange.single(3), - 'evenParity': BitRange.single(4), - 'stickParity': BitRange.single(5), - 'breakEnable': BitRange.single(6), - 'dlab': BitRange.single(7), - }); - - static const ier = BitStruct({ - 'rxAvailable': BitRange.single(0), - 'txEmpty': BitRange.single(1), - 'lsr': BitRange.single(2), - 'msr': BitRange.single(3), - }); - - static const iir = BitStruct({ - 'interruptPending': BitRange.single(0), - 'interruptId': BitRange(1, 3), - 'fifoEnabled': BitRange(2, 6), - }); - - static const fcr = BitStruct({ - 'fifoEnable': BitRange.single(0), - 'rxReset': BitRange.single(1), - 'txReset': BitRange.single(2), - 'dmaMode': BitRange.single(3), - 'triggerLevel': BitRange(2, 6), - }); - - static const lsr = BitStruct({ - 'dataReady': BitRange.single(0), - 'overrunError': BitRange.single(1), - 'parityError': BitRange.single(2), - 'framingError': BitRange.single(3), - 'breakInterrupt': BitRange.single(4), - 'thrEmpty': BitRange.single(5), - 'tsrEmpty': BitRange.single(6), - 'fifoError': BitRange.single(7), - }); - - static const mcr = BitStruct({ - 'dtr': BitRange.single(0), - 'rts': BitRange.single(1), - 'out1': BitRange.single(2), - 'out2': BitRange.single(3), - 'loopback': BitRange.single(4), - }); - - static const msr = BitStruct({ - 'deltaCts': BitRange.single(0), - 'deltaDsr': BitRange.single(1), - 'deltaRi': BitRange.single(2), - 'deltaDcd': BitRange.single(3), - 'cts': BitRange.single(4), - 'dsr': BitRange.single(5), - 'ri': BitRange.single(6), - 'dcd': BitRange.single(7), - }); -} diff --git a/packages/river/lib/src/impl/soc.dart b/packages/river/lib/src/impl/soc.dart deleted file mode 100644 index 59bd80b..0000000 --- a/packages/river/lib/src/impl/soc.dart +++ /dev/null @@ -1,31 +0,0 @@ -import 'soc/creek.dart'; -import 'soc/stream.dart'; - -import 'core.dart' show RiverCoreChoice; -import '../river_base.dart'; - -export 'soc/creek.dart'; -export 'soc/stream.dart'; - -/// Possible choices for River SoC's -enum RiverSoCChoice { - creek_v1('creek-v1', RiverCoreChoice.rc1_s), - stream_v1('stream-v1', RiverCoreChoice.rc1_n); - - const RiverSoCChoice(this.name, this.core); - - final String name; - final RiverCoreChoice core; - - RiverSoC? configure(Map options) => switch (this) { - RiverSoCChoice.creek_v1 => CreekV1SoC.configure(options), - RiverSoCChoice.stream_v1 => StreamV1SoC.configure(options), - }; - - static RiverSoCChoice? getChoice(String name) { - for (final choice in RiverSoCChoice.values) { - if (choice.name == name) return choice; - } - return null; - } -} diff --git a/packages/river/lib/src/impl/soc/creek.dart b/packages/river/lib/src/impl/soc/creek.dart deleted file mode 100644 index 08f32e6..0000000 --- a/packages/river/lib/src/impl/soc/creek.dart +++ /dev/null @@ -1 +0,0 @@ -export 'creek/v1.dart'; diff --git a/packages/river/lib/src/impl/soc/creek/v1.dart b/packages/river/lib/src/impl/soc/creek/v1.dart deleted file mode 100644 index 405f76f..0000000 --- a/packages/river/lib/src/impl/soc/creek/v1.dart +++ /dev/null @@ -1,197 +0,0 @@ -import 'package:riscv/riscv.dart'; -import '../../devices/clint.dart'; -import '../../devices/dram.dart'; -import '../../devices/plic.dart'; -import '../../devices/uart.dart'; -import '../../core/v1.dart'; -import '../../../interconnect/base.dart'; -import '../../../interconnect/wishbone.dart'; -import '../../../bus.dart'; -import '../../../cache.dart'; -import '../../../clock.dart'; -import '../../../dev.dart'; -import '../../../mem.dart'; -import '../../../river_base.dart'; - -/// Creek V1 SoC -class CreekV1SoC extends RiverSoC { - final ClockDomainConfig sysclk; - final ClockDomainConfig lfclk; - final int flashSize; - final int dramSize; - final int l1Size; - final int l1iSize; - final int l1dSize; - - @override - List get devices => [ - RiscVClint(name: 'clint', address: 0x02000000, clock: sysclk.clock), - RiscVPlic( - name: 'plic', - address: 0x04000000, - clock: sysclk.clock, - interrupt: 0, - ), - RiverUart( - name: 'uart0', - address: 0x10000000, - clock: sysclk.clock, - interrupt: 1, - ), - Device.simple( - name: 'gpio', - compatible: 'river,gpio', - interrupts: const [2], - range: const BusAddressRange(0x10001000, 0x00001000), - fields: const { - 0: DeviceField('input', 4), - 1: DeviceField('output', 4), - 2: DeviceField('dir', 4), - }, - type: DeviceAccessorType.io, - clock: sysclk.clock, - ), - Device.simple( - name: 'flash', - compatible: 'river,flash', - range: BusAddressRange(0x20000000, flashSize), - type: DeviceAccessorType.memory, - fields: const {0: DeviceField('read', 4)}, - ), - RiverDram( - name: 'dram', - address: 0x7fffffe1, - maxSize: dramSize, - channels: 1, - clock: sysclk.clock, - ), - ]; - - @override - List get clients => - devices.map((dev) => dev.clientPort).nonNulls.toList(); - - @override - List get cores => [ - RiverCoreV1.small( - interrupts: const [ - InterruptController( - name: '/cpu0/interrupts', - baseAddr: 0x0C000000, - lines: interrupts, - ), - ], - mmu: Mmu(mxlen: Mxlen.mxlen_64, blocks: mmap), - clock: sysclk.clock, - l1cache: L1Cache.split( - iSize: l1iSize, - dSize: l1dSize, - ways: 4, - lineSize: 64, - ), - resetVector: 0x20000000, - ), - ]; - - @override - Interconnect get fabric => WishboneFabric( - arbitration: BusArbitration.priority, - hosts: const [BusHostPort('/cpu0')], - clients: clients, - ); - - @override - List get clocks => [ - sysclk.getDomain( - consumers: [ - '/cpu0', - ...devices - .where((dev) => dev.clock?.name == sysclk.name) - .map((dev) => dev.name) - .toList(), - ], - ), - lfclk.getDomain( - consumers: devices - .where((dev) => dev.clock?.name == lfclk.name) - .map((dev) => dev.name) - .toList(), - ), - ]; - - @override - List get ports => [ - const RiverPortMap('uart_rx', [4], {'uart0': 'rx'}), - const RiverPortMap('uart_tx', [6], {'uart0': 'tx'}, isOutput: true), - ]; - - List get mmap => - devices.map((dev) => dev.mmap).nonNulls.toList(); - - const CreekV1SoC({ - required this.sysclk, - required this.lfclk, - required this.flashSize, - required this.dramSize, - required this.l1iSize, - required this.l1dSize, - }) : l1Size = l1iSize + l1dSize; - - /// Alpha Creek V1 SoC - const CreekV1SoC.alpha({this.l1iSize = 0x10000, this.l1dSize = 0x10000}) - : sysclk = const ClockDomainConfig( - name: 'sysclk', - freqHz: 48e6, - divisors: const [1, 2, 4, 8], - ), - lfclk = const ClockDomainConfig( - name: 'lfclk', - freqHz: 10e3, - divisors: const [1, 2, 4, 8], - ), - flashSize = 0x01000000, - dramSize = 0x100000, - l1Size = 0x20000; - - static const List interrupts = [ - InterruptLine(irq: 1, source: '/uart0', target: '/cpu0'), - InterruptLine(irq: 2, source: '/gpio', target: '/cpu0'), - ]; - - static CreekV1SoC? configure(Map options) { - final l1iSize = options['l1iSize'] as int?; - final l1dSize = options['l1dSize'] as int?; - - if (options.containsKey('platform')) { - switch (options['platform']) { - case 'alpha': - return CreekV1SoC.alpha( - l1iSize: l1iSize ?? 0x10000, - l1dSize: l1dSize ?? 0x10000, - ); - default: - return null; - } - } - - final sysclk = - ClockDomainConfig.from(options['sysclk'] ?? (throw 'Missing sysclk')) ?? - (throw 'Invalid sysclk'); - final lfclk = - ClockDomainConfig.from(options['lfclk'] ?? (throw 'Missing lfclk')) ?? - (throw 'Invalid lfclk'); - final flashSize = - (options['flashSize'] ?? (throw 'Missing flash size')) as int; - final dramSize = - (options['dramSize'] ?? (throw 'Missing DRAM size')) as int; - - return CreekV1SoC( - sysclk: sysclk, - lfclk: lfclk, - flashSize: flashSize, - dramSize: dramSize, - l1iSize: l1iSize ?? (throw 'Missing l1i size'), - l1dSize: l1dSize ?? (throw 'Missing l1d size'), - ); - } -} diff --git a/packages/river/lib/src/impl/soc/stream.dart b/packages/river/lib/src/impl/soc/stream.dart deleted file mode 100644 index e7e8d7b..0000000 --- a/packages/river/lib/src/impl/soc/stream.dart +++ /dev/null @@ -1 +0,0 @@ -export 'stream/v1.dart'; diff --git a/packages/river/lib/src/impl/soc/stream/v1.dart b/packages/river/lib/src/impl/soc/stream/v1.dart deleted file mode 100644 index 3ff15b1..0000000 --- a/packages/river/lib/src/impl/soc/stream/v1.dart +++ /dev/null @@ -1,203 +0,0 @@ -import 'package:riscv/riscv.dart'; -import '../../devices/clint.dart'; -import '../../devices/plic.dart'; -import '../../devices/uart.dart'; -import '../../core/v1.dart'; -import '../../../interconnect/base.dart'; -import '../../../interconnect/wishbone.dart'; -import '../../../bus.dart'; -import '../../../cache.dart'; -import '../../../clock.dart'; -import '../../../dev.dart'; -import '../../../mem.dart'; -import '../../../river_base.dart'; - -/// Stream V1 SoC -/// -/// The Stream V1 SoC is a lightweight SoC designed to run on small FPGAs. -/// It is suitable for light embedded applications like LED controllers. -/// -/// The SoC has a single RC1.n core (RV32IC) on a wishbone interconnect. -/// It has an SRAM, UART, GPIO, PLIC, CLIC, and flash. -class StreamV1SoC extends RiverSoC { - final ClockDomainConfig sysclk; - final ClockDomainConfig lfclk; - final int flashSize; - final int sramSize; - final int l1Size; - final int l1iSize; - final int l1dSize; - - @override - List get devices => [ - RiscVClint(name: 'clint', address: 0x02000000, clock: sysclk.clock), - RiscVPlic( - name: 'plic', - address: 0x04000000, - clock: sysclk.clock, - interrupt: 0, - ), - RiverUart( - name: 'uart0', - address: 0x10000000, - clock: sysclk.clock, - interrupt: 1, - ), - Device.simple( - name: 'gpio', - compatible: 'river,gpio', - interrupts: const [2], - range: const BusAddressRange(0x10001000, 0x00001000), - fields: const { - 0: DeviceField('input', 4), - 1: DeviceField('output', 4), - 2: DeviceField('dir', 4), - }, - type: DeviceAccessorType.io, - clock: sysclk.clock, - ), - Device.simple( - name: 'flash', - compatible: 'river,flash', - range: BusAddressRange(0x20000000, flashSize), - type: DeviceAccessorType.memory, - fields: const {0: DeviceField('read', 4)}, - ), - Device.simple( - name: 'sram', - compatible: 'river,sram', - range: BusAddressRange(0x80000000, sramSize), - fields: const {0: DeviceField('data', 4)}, - type: DeviceAccessorType.memory, - clock: sysclk.clock, - ), - ]; - - @override - List get clients => - devices.map((dev) => dev.clientPort).nonNulls.toList(); - - @override - List get cores => [ - RiverCoreV1.nano( - interrupts: const [ - InterruptController( - name: '/cpu0/interrupts', - baseAddr: 0x0C000000, - lines: interrupts, - ), - ], - mmu: Mmu(mxlen: Mxlen.mxlen_32, blocks: mmap), - clock: sysclk.clock, - l1cache: L1Cache.split( - iSize: l1iSize, - dSize: l1dSize, - ways: 4, - lineSize: 64, - ), - resetVector: 0x20000000, - ), - ]; - - @override - Interconnect get fabric => WishboneFabric( - arbitration: BusArbitration.priority, - hosts: const [BusHostPort('/cpu0')], - clients: clients, - ); - - @override - List get clocks => [ - sysclk.getDomain( - consumers: [ - '/cpu0', - ...devices - .where((dev) => dev.clock?.name == sysclk.name) - .map((dev) => dev.name) - .toList(), - ], - ), - lfclk.getDomain( - consumers: devices - .where((dev) => dev.clock?.name == lfclk.name) - .map((dev) => dev.name) - .toList(), - ), - ]; - - @override - List get ports => [ - const RiverPortMap('uart_rx', [4], {'uart0': 'rx'}), - const RiverPortMap('uart_tx', [6], {'uart0': 'tx'}, isOutput: true), - ]; - - List get mmap => - devices.map((dev) => dev.mmap).nonNulls.toList(); - - const StreamV1SoC({ - required this.sysclk, - required this.lfclk, - required this.flashSize, - required this.sramSize, - required this.l1iSize, - required this.l1dSize, - }) : l1Size = l1iSize + l1dSize; - - /// Stream V1 SoC configured for the iCESugar - const StreamV1SoC.icesugar({this.l1iSize = 0x10000, this.l1dSize = 0x10000}) - : sysclk = const ClockDomainConfig( - name: 'sysclk', - freqHz: 48e6, - divisors: const [1, 2, 4, 8], - ), - lfclk = const ClockDomainConfig( - name: 'lfclk', - freqHz: 10e3, - divisors: const [1, 2, 4, 8], - ), - flashSize = 0x01000000, - sramSize = 0x100000, - l1Size = 0x20000; - - static const List interrupts = [ - InterruptLine(irq: 1, source: '/uart0', target: '/cpu0'), - InterruptLine(irq: 2, source: '/gpio', target: '/cpu0'), - ]; - - static StreamV1SoC? configure(Map options) { - final l1iSize = options['l1iSize'] as int?; - final l1dSize = options['l1dSize'] as int?; - - if (options.containsKey('platform')) { - switch (options['platform']) { - case 'icesugar': - return StreamV1SoC.icesugar( - l1iSize: l1iSize ?? 0x10000, - l1dSize: l1dSize ?? 0x10000, - ); - default: - return null; - } - } - - final sysclk = - ClockDomainConfig.from(options['sysclk'] ?? (throw 'Missing sysclk')) ?? - (throw 'Invalid sysclk'); - final lfclk = - ClockDomainConfig.from(options['lfclk'] ?? (throw 'Missing lfclk')) ?? - (throw 'Invalid lfclk'); - final flashSize = - (options['flashSize'] ?? (throw 'Missing flash size')) as int; - final sramSize = - (options['sramSize'] ?? (throw 'Missing SRAM size')) as int; - - return StreamV1SoC( - sysclk: sysclk, - lfclk: lfclk, - flashSize: flashSize, - sramSize: sramSize, - l1iSize: l1iSize ?? (throw 'Missing l1i size'), - l1dSize: l1dSize ?? (throw 'Missing l1d size'), - ); - } -} diff --git a/packages/river/lib/src/interconnect.dart b/packages/river/lib/src/interconnect.dart deleted file mode 100644 index 2b816f2..0000000 --- a/packages/river/lib/src/interconnect.dart +++ /dev/null @@ -1,2 +0,0 @@ -export 'interconnect/base.dart'; -export 'interconnect/wishbone.dart'; diff --git a/packages/river/lib/src/interconnect/base.dart b/packages/river/lib/src/interconnect/base.dart deleted file mode 100644 index a71f9eb..0000000 --- a/packages/river/lib/src/interconnect/base.dart +++ /dev/null @@ -1,83 +0,0 @@ -import '../bus.dart'; - -/// Transaction type -enum TransactionType { - /// A read transaction - /// - /// Reads data from the client to the host - read, - - /// A write transaction - /// - /// Takes data from the host and writes it to the client - write, -} - -/// Interconnect transaction -class Transaction { - /// Host port name - final String host; - - /// Client port name - final String client; - - /// Type of transaction to perform - final TransactionType type; - - /// Address on the client - final int address; - - /// Width of the data - final int width; - - const Transaction({ - required this.host, - required this.client, - required this.type, - required this.address, - required this.width, - }); - - const Transaction.read({ - required this.host, - required this.client, - required this.address, - required this.width, - }) : type = TransactionType.read; - - const Transaction.write({ - required this.host, - required this.client, - required this.address, - required this.width, - }) : type = TransactionType.read; -} - -/// Abstract interconnect interface -abstract class Interconnect { - /// Arbitration method on the interconnect - BusArbitration get arbitration; - - /// Host ports on the interconnect - List get hosts; - - /// Client ports on the interconnect - List get clients; - - const Interconnect(); - - BusClientPort? getClient(int addr) { - for (final client in clients) { - if (client.range.contains(addr)) { - return client; - } - } - return null; - } - - /// Creates a read transaction - Transaction? read(String hostName, BusRead req); - - /// Creates a write transaction - Transaction? write(String hostName, BusWrite req); -} diff --git a/packages/river/lib/src/interconnect/wishbone.dart b/packages/river/lib/src/interconnect/wishbone.dart deleted file mode 100644 index fa47e08..0000000 --- a/packages/river/lib/src/interconnect/wishbone.dart +++ /dev/null @@ -1,46 +0,0 @@ -import '../bus.dart'; -import 'base.dart'; - -class WishboneFabric extends Interconnect { - @override - final BusArbitration arbitration; - - final List clients; - final List hosts; - - const WishboneFabric({ - required this.arbitration, - required this.hosts, - required this.clients, - }); - - @override - Transaction? read(String hostName, BusRead req) { - final client = getClient(req.addr); - if (client == null) return null; - - return Transaction.read( - host: hostName, - client: client!.name, - address: req.addr, - width: req.width, - ); - } - - @override - Transaction? write(String hostName, BusWrite req) { - final client = getClient(req.addr); - if (client == null) return null; - - return Transaction.write( - host: hostName, - client: client!.name, - address: req.addr, - width: req.width, - ); - } - - @override - String toString() => - 'WishboneFabric(arbitration: $arbitration, hosts: $hosts, clients: $clients)'; -} diff --git a/packages/river/lib/src/mem.dart b/packages/river/lib/src/mem.dart deleted file mode 100644 index ffb1f67..0000000 --- a/packages/river/lib/src/mem.dart +++ /dev/null @@ -1,63 +0,0 @@ -import 'package:riscv/riscv.dart'; -import 'dev.dart'; - -enum MemoryAccess { instr, read, write } - -class MemoryError implements Exception { - final int address; - final MemoryAccess access; - - const MemoryError(this.address, this.access); -} - -class MemoryBlock { - final int start; - final int size; - final DeviceAccessor accessor; - - const MemoryBlock(this.start, this.size, this.accessor); - - int get end => start + size; - - String? access(int index, MemoryAccess access) { - if (index > size || index < start) return null; - - return switch (access) { - MemoryAccess.read => accessor.readPath(index), - MemoryAccess.write => accessor.writePath(index), - _ => null, - }; - } - - @override - String toString() => 'MemoryBlock($start, $size, $accessor)'; -} - -class Mmu { - final Mxlen mxlen; - final List blocks; - final bool hasPaging; - final bool hasSum; - final bool hasMxr; - - const Mmu({ - required this.mxlen, - required this.blocks, - this.hasPaging = true, - this.hasSum = false, - this.hasMxr = false, - }); - - String? access(int addr, MemoryAccess access) { - for (final block in blocks) { - if (block.start >= addr && block.end < addr) { - return block.access(block.end - addr, access); - } - } - - return null; - } - - @override - String toString() => 'Mmu(blocks: $blocks, hasPaging: $hasPaging)'; -} diff --git a/packages/river/lib/src/profiles.dart b/packages/river/lib/src/profiles.dart new file mode 100644 index 0000000..7201256 --- /dev/null +++ b/packages/river/lib/src/profiles.dart @@ -0,0 +1,108 @@ +import 'package:harbor/harbor.dart'; + +import 'fp_extra.dart'; + +/// RISC-V application-processor profile extension sets (RVA22 / RVA23). +/// +/// These are the canonical mandatory-extension lists used to build River core +/// configs and to check profile completeness. They live here, not in a core +/// tier file, because they describe the ISA profile, not any one core. + +/// RVA22U64 mandatory extension set (user-mode application profile). +/// +/// RV64GC base + counters, hint, bit-manip, and cache-management extensions. +/// The platform-integration extensions (Zic64b, Za64rs, Zicc*) carry no +/// instructions, they constrain the memory system and are satisfied by +/// construction; they are listed so the profile is explicit and checkable. +final List kRva22U64Extensions = [ + rv32i, + rv64i, + rvM, + rvA, + rvF, + rvD, + rvFExtra, // fsgnj/fmin/fmax/fclass/fmv.x.w/fmv.w.x (not in Harbor's rvF) + rvDExtra, // fsgnj/fmin/fmax/fclass/fmv.x.d/fmv.d.x (not in Harbor's rvD) + rvC, + rvZicsr, + rvZifencei, + rvZicntr, + rvZihpm, + rvZihintpause, + rvZba, + rvZbb, + rvZbs, + rvZicbom, + rvZicbop, + rvZicboz, + rvZic64b, + rvZa64rs, + rvZiccif, + rvZiccrse, + rvZiccamoa, + rvZicclsm, +]; + +/// RVA22S64 mandatory extension set = [kRva22U64Extensions] + supervisor mode +/// and the Sv* address-translation extensions (Sv39 paging is selected via the +/// MMU config, not an extension object). +final List kRva22S64Extensions = [ + ...kRva22U64Extensions, + rvPriv, + rvSvbare, + rvSvade, + rvSvinval, + rvSvnapot, + rvSvpbmt, +]; + +/// RVA23U64 mandatory extension set = RVA22U64 + vector, conditional-ops, +/// may-be-ops, additional compressed/FP, wait-on-reservation, and the +/// non-temporal/crypto hints. +/// +/// (Zacas, Svadu, and the state-enable extensions are now defined in Harbor; the +/// S-mode ones live in [kRva23S64Extensions].) +final List kRva23U64Extensions = [ + ...kRva22U64Extensions, + rvZfhmin, + rvZicond, + rvZimop, + rvZcmop, + rvZcb, + rvZacas, + rvZfa, + rvZawrs, + rvZihintntl, + rvZkt, + rvV, + rvZvfhmin, + rvZvbb, + rvZvkt, +]; + +/// RVA23S64 mandatory extension set = RVA23U64 + supervisor, with the RVA23 +/// supervisor additions Sstc (supervisor timer compare), Sscofpmf (counter +/// overflow), Svadu (hardware A/D update, which the MMU performs), and the +/// state-enable CSRs (Smstateen/Ssstateen). +final List kRva23S64Extensions = [ + ...kRva23U64Extensions, + rvPriv, + rvSvbare, + rvSvade, + rvSvadu, + rvSvinval, + rvSvnapot, + rvSvpbmt, + rvSstc, + rvSscofpmf, + rvSmstateen, + rvSsstateen, + rvH, // Hypervisor is mandatory in RVA23S64. +]; + +/// RVA23S64 minus the compressed (C) extension, used by the non-compressed +/// dual-issue tier, whose fixed-width fetch alignment requires 4-byte +/// instructions. (Not a standard RVA23 profile; a microarchitecture variant.) +final List kRva23S64ExtensionsNoC = kRva23S64Extensions + .where((e) => e.name != 'C') + .toList(); diff --git a/packages/river/lib/src/register.dart b/packages/river/lib/src/register.dart new file mode 100644 index 0000000..dc20ab8 --- /dev/null +++ b/packages/river/lib/src/register.dart @@ -0,0 +1,39 @@ +enum Register { + x0(0, 'zero'), + x1(1, 'ra'), + x2(2, 'sp'), + x3(3, 'gp'), + x4(4, 'tp'), + x5(5, 't0'), + x6(6, 't1'), + x7(7, 't2'), + x8(8, 's0'), + x9(9, 's1'), + x10(10, 'a0'), + x11(11, 'a1'), + x12(12, 'a2'), + x13(13, 'a3'), + x14(14, 'a4'), + x15(15, 'a5'), + x16(16, 'a6'), + x17(17, 'a7'), + x18(18, 's2'), + x19(19, 's3'), + x20(20, 's4'), + x21(21, 's5'), + x22(22, 's6'), + x23(23, 's7'), + x24(24, 's8'), + x25(25, 's9'), + x26(26, 's10'), + x27(27, 's11'), + x28(28, 't3'), + x29(29, 't4'), + x30(30, 't5'), + x31(31, 't6'); + + const Register(this.value, this.abi); + + final int value; + final String abi; +} diff --git a/packages/river/lib/src/river_base.dart b/packages/river/lib/src/river_base.dart index f700851..c108d6d 100644 --- a/packages/river/lib/src/river_base.dart +++ b/packages/river/lib/src/river_base.dart @@ -1,20 +1,9 @@ -import 'package:riscv/riscv.dart'; -import 'interconnect/base.dart'; -import 'bus.dart'; -import 'cache.dart'; -import 'clock.dart'; -import 'dev.dart'; -import 'mem.dart'; - -/// In-Core Scaler Version +import 'package:harbor/harbor.dart'; + enum IcsVersion { v1 } -/// Defines the type of workloads the core is designed for enum RiverCoreType { - /// Microcontroller mcu(hasCsrs: true), - - /// General purpose compute general(hasCsrs: true); const RiverCoreType({required this.hasCsrs}); @@ -22,42 +11,22 @@ enum RiverCoreType { final bool hasCsrs; } -/// Defines how a segment of the pipeline should be integrated with microcode -enum MicrocodePipelineMode { - /// Contains both microcoded and hard-coded - in_parallel, +enum MicrocodePipelineMode { inParallel, standalone, none } - /// Contains purely microcoded - standalone, - - /// Contains purely hard-coded - none, -} - -/// Defines the configuration mode of the microcode enum MicrocodeMode { - /// No microcode engine none(), - - /// Partial microcode engine parallelDecode( - onDecoder: MicrocodePipelineMode.in_parallel, + onDecoder: MicrocodePipelineMode.inParallel, onExec: MicrocodePipelineMode.standalone, ), - - /// Partial microcode engine parallelExec( onDecoder: MicrocodePipelineMode.standalone, - onExec: MicrocodePipelineMode.in_parallel, + onExec: MicrocodePipelineMode.inParallel, ), - - /// Partial microcode engine fullParallel( - onDecoder: MicrocodePipelineMode.in_parallel, - onExec: MicrocodePipelineMode.in_parallel, + onDecoder: MicrocodePipelineMode.inParallel, + onExec: MicrocodePipelineMode.inParallel, ), - - /// Full microcode engine full( onDecoder: MicrocodePipelineMode.standalone, onExec: MicrocodePipelineMode.standalone, @@ -72,13 +41,117 @@ enum MicrocodeMode { final MicrocodePipelineMode onExec; } -/// Method of performing the execution stage of the pipeline -enum ExecutionMode { - /// Execute all instructions in order - in_order, +enum ExecutionMode { inOrder, outOfOrder } + +/// Number of instructions the front-end issues per cycle. `dual` requires +/// [ExecutionMode.outOfOrder]: only the OoO backend's ROB and issue queue are +/// built 2-wide. +enum IssueWidth { + single(1), + dual(2); + + final int lanes; + const IssueWidth(this.lanes); +} + +/// Branch-prediction scheme for the speculative OoO front-end. A predicted-taken +/// branch redirects fetch at rename, so only a misprediction (caught at execute) +/// flushes. `none` is the baseline: predict not-taken, redirect at commit. +enum BranchPredictor { + /// No prediction: every taken branch/jump redirects at commit (a full flush). + none, + + /// Static backward-taken / forward-not-taken: conditional branches with a + /// negative displacement (loop back-edges) are predicted taken; forward ones + /// not-taken. JAL is always taken. No stored state. Cheap, good for loops. + btfn, + + /// Bimodal: a table of 2-bit saturating counters indexed by branch PC, + /// updated at branch resolution. Learns per-branch bias. + bimodal, +} + +/// Load-store queue scheme for the OoO core. `none` writes stores to the bus at +/// execute (out of program order, a memory-ordering gap). Each non-`none` level +/// buffers stores and drains them in program order at commit, adding more +/// aggressive load handling on top. +enum LoadStoreQueue { + /// No queue: a store drives the bus as soon as it issues from the IQ (current + /// behavior, kept for back-compat). Loads read the bus directly. + none, + + /// Buffer stores; the architectural write happens at commit, in program order. + /// A load that has any older store still in flight stalls until it drains, no + /// forwarding. Fixes store ordering with the least machinery. + storeQueue, + + /// As [storeQueue], plus store→load forwarding: a load takes its value from the + /// youngest older store to the same address when that store's data is ready. + /// Loads issue conservatively, they stall only when an older store's address + /// is still unknown (can't be disambiguated), never speculating past it. + forwarding, + + /// As [forwarding], but loads issue speculatively even past unknown-address + /// stores. A load queue records executed loads; when an older store later + /// resolves its address and aliases a younger already-executed load, that load + /// (and everything younger) is squashed and replayed via the ROB redirect path. + speculative, +} + +enum PrivilegeMode { + machine(3), + supervisor(1), + user(0); + + const PrivilegeMode(this.id); + + final int id; - /// Executes instructions out of order based on utilization of the individual execution units - out_of_order, + static PrivilegeMode? find(int id) { + for (final mode in PrivilegeMode.values) { + if (mode.id == id) return mode; + } + return null; + } +} + +enum Trap { + instructionMisaligned(0, false), + instructionAccessFault(1, false), + illegal(2, false), + breakpoint(3, false), + misalignedLoad(4, false), + loadAccess(5, false), + misalignedStore(6, false), + storeAccess(7, false), + ecallU(8, false), + ecallS(9, false), + ecallVS(10, false), + ecallM(11, false), + instructionPageFault(12, false), + loadPageFault(13, false), + storePageFault(15, false), + // Hypervisor (H) extension synchronous causes. + instructionGuestPageFault(20, false), + loadGuestPageFault(21, false), + virtualInstruction(22, false), + storeGuestPageFault(23, false), + userSoftware(0, true), + supervisorSoftware(1, true), + machineSoftware(3, true), + userTimer(4, true), + supervisorTimer(5, true), + machineTimer(7, true), + userExternal(8, true), + supervisorExternal(9, true), + machineExternal(11, true); + + final int causeCode; + final bool interrupt; + + const Trap(this.causeCode, this.interrupt); + + int cause(int xlen) => (interrupt ? (1 << (xlen - 1)) : 0) | causeCode; } class InterruptLine { @@ -113,30 +186,111 @@ class InterruptController { 'InterruptController(name: $name, baseAddr: $baseAddr, lines: $lines)'; } -/// A River RISC-V core -class RiverCore { +/// River's allocated RISC-V architecture ID (`marchid`), from the official +/// registry: https://github.com/riscv/riscv-isa-manual/blob/main/marchid.md +/// (Midstall Software, entry 49). This is the default [RiverCoreConfig.archId]. +const int riverArchId = 49; + +class RiverCoreConfig { final int vendorId; + + /// RISC-V `marchid` value. Defaults to [riverArchId] (River's registered + /// architecture ID); override only for a non-River derivative. final int archId; final int impId; final int hartId; final int resetVector; - final Mxlen mxlen; - final ClockConfig clock; + final RiscVMxlen mxlen; + final HarborClockConfig clock; final List extensions; final List interrupts; - final Mmu mmu; + final HarborMmuConfig mmu; final MicrocodeMode microcodeMode; final ExecutionMode executionMode; - final L1Cache? l1cache; + final IssueWidth issueWidth; + + /// Number of instructions retired (committed) per cycle. Independent of + /// [issueWidth] so a config can enable dual-commit (a second register write + /// port draining backlog after a multi-cycle op) without dual-dispatch, or + /// vice versa. Defaults to [issueWidth]. Dual commit requires OoO. + final IssueWidth commitWidth; + + /// Depth of the per-bank register-file write buffer. 0 (the default) means no + /// buffer: a same-bank commit collision stalls the younger write one cycle. + /// A depth >0 absorbs collisions into a FIFO (drained one/cycle, with read + /// bypass) so commit doesn't stall until the buffer fills. Only meaningful + /// when [commitWidth] is dual (a single write port never collides). + final int writeBufferDepth; + + /// Register-file read latency in cycles, or null to derive from the target + /// (1 for an ECP5 posedge-EBR build, 0 otherwise). A registered full-cycle + /// read keeps the regfile off the combinational ALU path so timing closes on + /// FPGAs with block-RAM register files, at the cost of one cycle per operand + /// read (the operand-read handshake absorbs it). Set explicitly to exercise + /// the +1 read pipeline in simulation with the flop register file (the EBR is + /// a blackbox with no sim model). + final int? regfileReadLatency; + + /// Whether the OoO front-end fetches speculatively. False (default) is + /// lockstep: the fetch PC advances only at commit, one instruction in flight + /// end-to-end (no overlap, dual-issue cannot fire). True advances fetch every + /// cycle, with ROB/IQ overlap and branch/exception redirect + flush. Requires + /// the OoO backend. + final bool speculativeFetch; + + /// Use the pipelined PREFETCH fetcher: fetches one instruction ahead into a + /// buffer so fetch latency overlaps decode/rename/alloc. Single-issue, + /// non-compressed, speculative OoO only for now. Default false (classic + /// FetchUnit). + final bool prefetchFetch; + + /// Prefetch instruction-FIFO depth (power of two >= 2). A deeper buffer hides + /// longer/burstier fetch stalls (e.g. icache line-fill misses): the consumer + /// drains the buffer while the next line fills. Only meaningful with + /// prefetchFetch=true. Default 2 (prefetch-one-ahead). + final int prefetchDepth; + + /// Maximum instruction-fetch reads kept in flight at once (>= 1). Hides fetch + /// latency: responses arrive every cycle in steady state instead of every + /// `latency` cycles, keeping the prefetch FIFO full. 1 (default) is classic + /// single-outstanding. Only meaningful with prefetchFetch=true, and only speeds + /// up when the downstream fetch port services multiple outstanding reads. + final int fetchOutstanding; + + /// Branch-prediction scheme (speculative OoO front-end only). Cuts the + /// per-branch redirect/flush penalty to just mispredictions. + final BranchPredictor branchPredictor; + + /// Load-store queue scheme (OoO only). `none` (default) keeps the legacy + /// store-at-execute path; the other levels buffer stores and drain them in + /// program order at commit. See [LoadStoreQueue]. + final LoadStoreQueue loadStoreQueue; + + /// Reorder-buffer depth (entries). Must be a power of two. Defaults to 64. + final int robDepth; + + /// Store-queue depth (entries), used when [loadStoreQueue] != none. Must be a + /// power of two. Defaults to 8. + final int storeQueueDepth; + + /// Load-queue depth (entries), used when [loadStoreQueue] == speculative. Must + /// be a power of two. Defaults to 8. + final int loadQueueDepth; + + final HarborL1CacheConfig? l1cache; final bool hasSupervisor; final bool hasUser; final RiverCoreType type; final IcsVersion? icsVersion; final int threads; - const RiverCore({ + /// Vector register width in bits (the V extension's VLEN). Only meaningful + /// when the V extension is present; 128 is the RVA23 minimum. + final int vlen; + + RiverCoreConfig({ this.vendorId = 0, - this.archId = 0, + this.archId = riverArchId, this.impId = 0, this.hartId = 0, this.resetVector = 0, @@ -146,85 +300,227 @@ class RiverCore { required this.interrupts, required this.mmu, this.microcodeMode = MicrocodeMode.none, - this.executionMode = ExecutionMode.in_order, + this.executionMode = ExecutionMode.inOrder, + this.issueWidth = IssueWidth.single, + IssueWidth? commitWidth, + this.writeBufferDepth = 0, + this.regfileReadLatency, + this.speculativeFetch = false, + this.prefetchFetch = false, + this.prefetchDepth = 2, + this.fetchOutstanding = 1, + this.branchPredictor = BranchPredictor.none, + this.loadStoreQueue = LoadStoreQueue.none, + this.robDepth = 64, + this.storeQueueDepth = 8, + this.loadQueueDepth = 8, this.l1cache, this.hasSupervisor = true, this.hasUser = true, required this.type, this.icsVersion, this.threads = 1, - }); - - const RiverCore._32({ - this.vendorId = 0, - this.archId = 0, - this.impId = 0, - this.hartId = 0, - this.resetVector = 0, - required this.clock, - required this.extensions, - required this.interrupts, - required this.mmu, - this.microcodeMode = MicrocodeMode.none, - this.executionMode = ExecutionMode.in_order, - this.l1cache, - this.hasSupervisor = false, - this.hasUser = false, - required this.type, - this.icsVersion, - this.threads = 1, - }) : mxlen = Mxlen.mxlen_32; - - const RiverCore._64({ - this.vendorId = 0, - this.archId = 0, - this.impId = 0, - this.hartId = 0, - this.resetVector = 0, - required this.clock, - required this.extensions, - required this.interrupts, - required this.mmu, - this.microcodeMode = MicrocodeMode.none, - this.executionMode = ExecutionMode.in_order, - this.l1cache, - this.hasSupervisor = false, - this.hasUser = false, - required this.type, - this.icsVersion, - this.threads = 1, - }) : mxlen = Mxlen.mxlen_64; - - String? get implementsName { - final hasI = extensions.any((e) => e.key == 'I'); - final hasE = extensions.any((e) => e.key == 'E'); - - if (!hasI && !hasE) { - return null; + this.vlen = 128, + }) : commitWidth = commitWidth ?? issueWidth { + // VLEN must be a power of two and at least 128 (the RVA23 minimum) so that + // configs always produce spec builds. + if (vlen < 128 || (vlen & (vlen - 1)) != 0) { + throw ArgumentError('vlen must be a power of two >= 128 (got $vlen).'); } - - final baseLetter = hasE ? 'E' : 'I'; - final base = 'RV${mxlen.size}$baseLetter'; - - final buf = StringBuffer(base); - - for (final ext in extensions) { - final key = ext.key; - if (key == null) continue; - if (key == baseLetter) continue; - buf.write(key); + // Dual-issue requires the OoO backend (only the ROB / issue queue are + // built 2-wide). An in-order dual-issue front-end is not supported. + if (issueWidth == IssueWidth.dual && + executionMode != ExecutionMode.outOfOrder) { + throw ArgumentError( + 'issueWidth=$issueWidth requires executionMode=outOfOrder ' + '(got executionMode=$executionMode).', + ); + } + // Dual-DISPATCH (two fetch/decode/rename lanes) needs the speculative + // front-end (lane coordination relies on self-sequencing fetch + redirect). + // Compressed instructions are supported: CompressedFetchBuffer aligns the + // two lanes from one stream window (lane 1 at lane 0 + size0, not fixed +4). + if (issueWidth == IssueWidth.dual && !speculativeFetch) { + throw ArgumentError('issueWidth=dual requires speculativeFetch=true.'); + } + // Branch prediction redirects the fetch stream speculatively, which only the + // speculative OoO front-end supports. + if (branchPredictor != BranchPredictor.none && !speculativeFetch) { + throw ArgumentError( + 'branchPredictor=$branchPredictor requires speculativeFetch=true.', + ); + } + // The load-store queue (buffering stores until commit, forwarding, replay) + // is built only on the OoO backend, and only the speculative front-end has + // out-of-order memory to manage, lockstep executes one memory op at a time, + // already in program order. + if (loadStoreQueue != LoadStoreQueue.none && + executionMode != ExecutionMode.outOfOrder) { + throw ArgumentError( + 'loadStoreQueue=$loadStoreQueue requires executionMode=outOfOrder ' + '(got executionMode=$executionMode).', + ); + } + if (loadStoreQueue != LoadStoreQueue.none && !speculativeFetch) { + throw ArgumentError( + 'loadStoreQueue=$loadStoreQueue requires speculativeFetch=true.', + ); + } + // The prefetch fetcher self-sequences (needs the speculative front-end) and + // currently supports only single-issue, fixed-width (non-compressed) fetch. + if (prefetchFetch && !speculativeFetch) { + throw ArgumentError('prefetchFetch=true requires speculativeFetch=true.'); + } + if (prefetchFetch && issueWidth == IssueWidth.dual) { + throw ArgumentError( + 'prefetchFetch=true does not yet support issueWidth=dual.', + ); + } + if (prefetchFetch && extensions.any((e) => e.name == 'C')) { + throw ArgumentError( + 'prefetchFetch=true does not yet support the compressed (C) extension.', + ); + } + if (prefetchDepth < 2 || (prefetchDepth & (prefetchDepth - 1)) != 0) { + throw ArgumentError( + 'prefetchDepth must be a power of two >= 2 (got $prefetchDepth).', + ); } + if (fetchOutstanding < 1) { + throw ArgumentError( + 'fetchOutstanding must be >= 1 (got $fetchOutstanding).', + ); + } + if (fetchOutstanding > 1 && !prefetchFetch) { + throw ArgumentError('fetchOutstanding > 1 requires prefetchFetch=true.'); + } + // The prefetch FIFO must hold every in-flight response plus one delivered + // entry, so it cannot be smaller than fetchOutstanding + 1. + if (fetchOutstanding > 1 && prefetchDepth < fetchOutstanding + 1) { + throw ArgumentError( + 'prefetchDepth ($prefetchDepth) must be >= fetchOutstanding + 1 ' + '(${fetchOutstanding + 1}) when fetchOutstanding > 1, so every ' + 'outstanding response can be buffered.', + ); + } + // Queue depths must be powers of two (the head/tail pointers wrap with a + // simple mask). + if (robDepth < 2 || (robDepth & (robDepth - 1)) != 0) { + throw ArgumentError( + 'robDepth must be a power of two >= 2 (got $robDepth).', + ); + } + if (storeQueueDepth < 2 || (storeQueueDepth & (storeQueueDepth - 1)) != 0) { + throw ArgumentError( + 'storeQueueDepth must be a power of two >= 2 (got $storeQueueDepth).', + ); + } + if (loadQueueDepth < 2 || (loadQueueDepth & (loadQueueDepth - 1)) != 0) { + throw ArgumentError( + 'loadQueueDepth must be a power of two >= 2 (got $loadQueueDepth).', + ); + } + // Dual-commit (a second register write port + the OoO commit stage's + // slot-1 path) is likewise only built for the OoO backend. + if (commitWidth == IssueWidth.dual && + executionMode != ExecutionMode.outOfOrder) { + throw ArgumentError( + 'commitWidth=$commitWidth requires executionMode=outOfOrder ' + '(got executionMode=$executionMode).', + ); + } + if (writeBufferDepth < 0) { + throw ArgumentError( + 'writeBufferDepth must be >= 0 (got $writeBufferDepth).', + ); + } + if (speculativeFetch && executionMode != ExecutionMode.outOfOrder) { + throw ArgumentError( + 'speculativeFetch requires executionMode=outOfOrder ' + '(got executionMode=$executionMode).', + ); + } + if (threads < 1) { + throw ArgumentError('threads must be >= 1 (got $threads).'); + } + // The Hypervisor extension virtualizes supervisor mode, so it cannot be + // present without supervisor support. + if (hasHypervisor && !hasSupervisor) { + throw ArgumentError('the H extension requires hasSupervisor=true.'); + } + } - return buf.toString(); + /// Instructions dispatched (renamed/allocated) per cycle. + int get dispatchLanes => issueWidth.lanes; + + /// Read-only value of the `rpipelinecap` vendor CSR (0x7C4): a feature- + /// discovery bitmap derived purely from this config, so software can probe + /// what the build contains before toggling [rpipelinectl]. Computed the same + /// way in the emulator and the HDL (both read this getter) so it stays in + /// parity. Bit layout: + /// [0] out-of-order [1] dual-issue [2] speculative fetch + /// [3] branch predictor present [4] load-store queue present + /// [5] store->load forwarding [6] speculative LSQ (v4 bypass) + /// [7] instruction cache [8] paging (MMU) present + int get rpipelineCap { + var v = 0; + if (executionMode == ExecutionMode.outOfOrder) v |= 1 << 0; + if (issueWidth == IssueWidth.dual) v |= 1 << 1; + if (speculativeFetch) v |= 1 << 2; + if (branchPredictor != BranchPredictor.none) v |= 1 << 3; + if (loadStoreQueue != LoadStoreQueue.none) v |= 1 << 4; + if (loadStoreQueue == LoadStoreQueue.forwarding || + loadStoreQueue == LoadStoreQueue.speculative) { + v |= 1 << 5; + } + if (loadStoreQueue == LoadStoreQueue.speculative) v |= 1 << 6; + if (l1cache != null) v |= 1 << 7; + if (mmu.hasPaging) v |= 1 << 8; + return v; } - Microcode get microcode => Microcode(Microcode.buildDecodeMap(extensions)); + /// Instructions committed (retired) per cycle; drives the number of register + /// write ports. + int get commitLanes => commitWidth.lanes; + + /// Whether the Vector (V) extension is configured. + bool get hasVector => extensions.any((e) => e.name == 'V'); + + /// Whether the Hypervisor (H) extension is configured. Derived from the + /// extension set so a config that omits [rvH] has zero hypervisor overhead. + /// H builds on supervisor mode (validated in the constructor). + bool get hasHypervisor => extensions.any((e) => e.name == 'H'); + + /// Whether the machine-level state-enable extension (Smstateen) is configured, + /// which provides the mstateen/sstateen/hstateen CSRs. + bool get hasStateen => extensions.any((e) => e.name == 'Smstateen'); + + /// Whether the core carries CSR hardware. Derived from the ISA: the CSR + /// file exists when Zicsr (or the privileged architecture, which implies + /// it) is in the extension set, gated by the core type's capability. A + /// tier without Zicsr (the nano) gets no CSR file at all, which is worth + /// roughly an eighth of its area. + bool get hasCsrs => + type.hasCsrs && + (extensions.contains(rvZicsr) || extensions.contains(rvPriv)); + + RiscVIsaConfig get isa => RiscVIsaConfig( + mxlen: mxlen, + extensions: extensions, + hasSupervisor: hasSupervisor, + hasUser: hasUser, + pagingModes: mmu.pagingModes, + ); @override String toString() => - 'RiverCore(vendorId: $vendorId, archId: $archId, hartId: $hartId,' - ' resetVector: $resetVector, clock: $clock, ${implementsName != null ? 'implements: $implementsName' : 'extensions: $extensions'}, interrupts: $interrupts,' - ' mmu: $mmu, microcodeMode: $microcodeMode, executionMode: $executionMode, l1Cache: $l1cache, type: $type, icsVersion: $icsVersion, threads: $threads)'; + 'RiverCoreConfig(vendorId: $vendorId, archId: $archId, hartId: $hartId,' + ' resetVector: $resetVector, clock: $clock, isa: ${isa.implementsString},' + ' interrupts: $interrupts, mmu: $mmu, microcodeMode: $microcodeMode,' + ' executionMode: $executionMode, issueWidth: $issueWidth,' + ' commitWidth: $commitWidth,' + ' l1Cache: $l1cache, type: $type,' + ' icsVersion: $icsVersion, threads: $threads)'; } class RiverPortMap { @@ -247,38 +543,83 @@ class RiverPortMap { 'RiverPortMap($name, pins: $pins, devices: $devices, isOutput: $isOutput)'; } -/// A River SoC -abstract class RiverSoC { - /// Devices on the SoC - List get devices; +class RiverDeviceField { + final String name; + final int width; + + const RiverDeviceField({required this.name, required this.width}); +} - /// Bus client ports on the interconnect - List get clients; +class RiverDeviceAccessor { + final String path; + final Map fields; + final Map _fieldOffsets; - /// All of the cores in the SoC - List get cores; + const RiverDeviceAccessor({ + required this.path, + required this.fields, + Map fieldOffsets = const {}, + }) : _fieldOffsets = fieldOffsets; - /// The interconnect fabric on the SoC - Interconnect get fabric; + int? fieldAddress(String name) => _fieldOffsets[name]; +} - /// The clocks for the SoC - List get clocks; +class RiverDevice { + final String name; + final String compatible; + final String module; + final BusAddressRange? range; + final List interrupts; + final int? clockFrequency; + final HarborClockConfig? clock; + final List ports; + final RiverDeviceAccessor? accessor; + + const RiverDevice({ + required this.name, + required this.compatible, + this.module = '', + this.range, + this.interrupts = const [], + this.clockFrequency, + this.clock, + this.ports = const [], + this.accessor, + }); - /// Physical pinout of the SoC - List get ports; + @override + String toString() => + 'RiverDevice(name: $name, compatible: $compatible, range: $range,' + ' interrupts: $interrupts)'; +} - const RiverSoC(); +class RiverSoCConfig { + final List devices; + final List cores; + final WishboneConfig busConfig; + final List clocks; + final List ports; + + const RiverSoCConfig({ + this.devices = const [], + this.cores = const [], + this.busConfig = const WishboneConfig( + addressWidth: 32, + dataWidth: 32, + selWidth: 4, + ), + this.clocks = const [], + this.ports = const [], + }); - RiverCore? getCore(int hartId) { + RiverCoreConfig? getCore(int hartId) { for (final core in cores) { - if (core.hartId == hartId) { - return core; - } + if (core.hartId == hartId) return core; } return null; } - Device? getDevice(String name) { + RiverDevice? getDevice(String name) { for (final dev in devices) { if (dev.name == name) return dev; } @@ -287,5 +628,6 @@ abstract class RiverSoC { @override String toString() => - 'RiverSoC(devices: $devices, clients: $clients, cores: $cores, fabric: $fabric, clocks: $clocks, ports: $ports)'; + 'RiverSoCConfig(devices: $devices, cores: $cores, clocks: $clocks,' + ' ports: $ports)'; } diff --git a/packages/river/pubspec.yaml b/packages/river/pubspec.yaml index d3bdc97..53e73a7 100644 --- a/packages/river/pubspec.yaml +++ b/packages/river/pubspec.yaml @@ -5,12 +5,11 @@ resolution: workspace # repository: https://github.com/my_org/my_repo environment: - sdk: ^3.9.3 + sdk: ^3.11.2 # Add regular dependencies here. dependencies: - riscv: ^1.0.0 - # path: ^1.9.0 + harbor: ^0.0.1 dev_dependencies: lints: ^6.0.0 diff --git a/packages/river/test/marchid_default_test.dart b/packages/river/test/marchid_default_test.dart new file mode 100644 index 0000000..bb09b37 --- /dev/null +++ b/packages/river/test/marchid_default_test.dart @@ -0,0 +1,13 @@ +import 'package:river/river.dart'; +import 'package:test/test.dart'; + +// Guards River's registered RISC-V architecture ID (marchid), per +// https://github.com/riscv/riscv-isa-manual/blob/main/marchid.md +// riverArchId is the default RiverCoreConfig.archId, so a change here would +// silently change every core's marchid. +void main() { + test( + 'River marchid (riverArchId) is the registry value 49', + () => expect(riverArchId, 49), + ); +} diff --git a/packages/river/test/river_test.dart b/packages/river/test/river_test.dart index 15c6dba..5ec5bdf 100644 --- a/packages/river/test/river_test.dart +++ b/packages/river/test/river_test.dart @@ -2,12 +2,250 @@ import 'package:river/river.dart'; import 'package:test/test.dart'; void main() { - group('Stream V1 - iCESugar', () { - const soc = StreamV1SoC.icesugar(); + group('RiverSoCConfig', () { + test('getDevice finds by name', () { + final config = RiverSoCConfig( + devices: [ + const RiverDevice( + name: 'flash', + compatible: 'river,flash', + range: BusAddressRange(0x20000000, 0x1000000), + ), + const RiverDevice( + name: 'sram', + compatible: 'river,sram', + range: BusAddressRange(0x80000000, 0x100000), + ), + ], + ); - test('Reset vector', () { - final flash = soc.getDevice('flash')!; - expect(soc.cores[0].resetVector, flash.range!.start); + expect(config.getDevice('flash'), isNotNull); + expect(config.getDevice('flash')!.range!.start, 0x20000000); + expect(config.getDevice('missing'), isNull); + }); + + test('getCore finds by hart ID', () { + final sysclk = HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ); + + final config = RiverSoCConfig( + cores: [ + RiverCoreConfigV1.nano( + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv32, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + interrupts: [], + clock: sysclk, + resetVector: 0x20000000, + ), + ], + ); + + expect(config.getCore(0), isNotNull); + expect(config.getCore(0)!.resetVector, 0x20000000); + expect(config.getCore(1), isNull); + }); + }); + + group('RiverCoreConfig validation', () { + final sysclk = HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ); + final mmu = HarborMmuConfig( + mxlen: RiscVMxlen.rv32, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ); + + test('defaults to in-order single-issue', () { + final c = RiverCoreConfigV1.nano(mmu: mmu, interrupts: [], clock: sysclk); + expect(c.executionMode, ExecutionMode.inOrder); + expect(c.issueWidth, IssueWidth.single); + expect(c.issueWidth.lanes, 1); + }); + + test('dual-issue with in-order throws ArgumentError', () { + expect( + () => RiverCoreConfig( + clock: sysclk, + mxlen: RiscVMxlen.rv32, + extensions: const [], + interrupts: const [], + mmu: mmu, + type: RiverCoreType.mcu, + executionMode: ExecutionMode.inOrder, + issueWidth: IssueWidth.dual, + ), + throwsArgumentError, + ); + }); + + test('dual-issue with out-of-order + speculative is accepted', () { + expect( + () => RiverCoreConfig( + clock: sysclk, + mxlen: RiscVMxlen.rv32, + extensions: const [], + interrupts: const [], + mmu: mmu, + type: RiverCoreType.mcu, + executionMode: ExecutionMode.outOfOrder, + speculativeFetch: true, + issueWidth: IssueWidth.dual, + ), + returnsNormally, + ); + }); + + test('dual-issue without speculative fetch throws ArgumentError', () { + expect( + () => RiverCoreConfig( + clock: sysclk, + mxlen: RiscVMxlen.rv32, + extensions: const [], + interrupts: const [], + mmu: mmu, + type: RiverCoreType.mcu, + executionMode: ExecutionMode.outOfOrder, + issueWidth: IssueWidth.dual, + ), + throwsArgumentError, + ); + }); + + test('threads < 1 throws ArgumentError', () { + expect( + () => RiverCoreConfig( + clock: sysclk, + mxlen: RiscVMxlen.rv32, + extensions: const [], + interrupts: const [], + mmu: mmu, + type: RiverCoreType.mcu, + threads: 0, + ), + throwsArgumentError, + ); + }); + }); + + group('RVA22 profile', () { + final sysclk = HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ); + final config = RiverCoreConfig( + mxlen: RiscVMxlen.rv64, + extensions: kRva22S64Extensions, + type: RiverCoreType.general, + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + interrupts: [], + clock: sysclk, + ); + final names = config.extensions.map((e) => e.name).toSet(); + + test('is RV64', () { + expect(config.mxlen, RiscVMxlen.rv64); + }); + + // RVA22U64 mandatory: RV64GC + counters/hint/bitmanip/cache-management. + const u64 = [ + 'M', + 'A', + 'F', + 'D', + 'C', + 'Zicsr', + 'Zifencei', + 'Zicntr', + 'Zihpm', + 'Zihintpause', + 'Zba', + 'Zbb', + 'Zbs', + 'Zicbom', + 'Zicbop', + 'Zicboz', + 'Zic64b', + 'Za64rs', + 'Ziccif', + 'Ziccrse', + 'Ziccamoa', + 'Zicclsm', + ]; + for (final ext in u64) { + test('U64 mandatory: $ext present', () { + expect(names, contains(ext)); + }); + } + + // RVA22S64 mandatory supervisor additions. + const s64 = ['Priv', 'Svbare', 'Svade', 'Svinval', 'Svnapot', 'Svpbmt']; + for (final ext in s64) { + test('S64 mandatory: $ext present', () { + expect(names, contains(ext)); + }); + } + }); + + group('RVA23 profile', () { + final config = RiverCoreConfig( + mxlen: RiscVMxlen.rv64, + extensions: kRva23S64Extensions, + type: RiverCoreType.general, + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + interrupts: [], + clock: HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ), + ); + final names = config.extensions.map((e) => e.name).toSet(); + + // RVA23 additions over RVA22 that Harbor expresses today (Zacas/Svadu/ + // state-enable are documented gaps, not yet in Harbor). + const added = [ + 'V', + 'Zicond', + 'Zimop', + 'Zcmop', + 'Zcb', + 'Zfa', + 'Zawrs', + 'Zihintntl', + 'Zkt', + 'Zfhmin', + 'Zvfhmin', + 'Zvbb', + 'Zvkt', + 'Sstc', + 'Sscofpmf', + ]; + for (final ext in added) { + test('RVA23 adds: $ext present', () { + expect(names, contains(ext)); + }); + } + + test('still includes the RVA22 base (e.g. Zba, Zicbom, Svnapot)', () { + expect(names, containsAll(['Zba', 'Zbb', 'Zbs', 'Zicbom', 'Svnapot'])); }); }); } diff --git a/packages/river_adl/analysis_options.yaml b/packages/river_adl/analysis_options.yaml index dee8927..f5d48c9 100644 --- a/packages/river_adl/analysis_options.yaml +++ b/packages/river_adl/analysis_options.yaml @@ -1,30 +1,2 @@ -# This file configures the static analysis results for your project (errors, -# warnings, and lints). -# -# This enables the 'recommended' set of lints from `package:lints`. -# This set helps identify many issues that may lead to problems when running -# or consuming Dart code, and enforces writing Dart using a single, idiomatic -# style and format. -# -# If you want a smaller set of lints you can change this to specify -# 'package:lints/core.yaml'. These are just the most critical lints -# (the recommended set includes the core lints). -# The core lints are also what is used by pub.dev for scoring packages. - -include: package:lints/recommended.yaml - -# Uncomment the following section to specify additional rules. - -# linter: -# rules: -# - camel_case_types - -# analyzer: -# exclude: -# - path/to/excluded/files/** - -# For more information about the core and recommended set of lints, see -# https://dart.dev/go/core-lints - -# For additional information about configuring this file, see -# https://dart.dev/guides/language/analysis-options +# Inherits the workspace production analysis baseline. +include: ../../analysis_options.yaml diff --git a/packages/river_adl/example/river_adl_example.dart b/packages/river_adl/example/river_adl_example.dart index d35fb2f..04d4e68 100644 --- a/packages/river_adl/example/river_adl_example.dart +++ b/packages/river_adl/example/river_adl_example.dart @@ -1,34 +1,25 @@ import 'dart:io'; -import 'package:riscv/riscv.dart'; +import 'package:harbor/harbor.dart'; +import 'package:river/river.dart'; import 'package:river_adl/river_adl.dart'; class MyModule extends Module { + @override + final isa = RiscVIsaConfig(mxlen: RiscVMxlen.rv32, extensions: [rv32i]); + DataField get c => output('c'); - //DataField get d => output('d'); MyModule(DataField a, DataField b) : super() { a = addInput('a', a); b = addInput('b', b); addOutput('c', type: a.type, source: DataLocation.register); - //addOutput('d', type: a.type, source: DataLocation.memory); c.bind(a + b); - //d.load(c); } } void main() async { - // Does: - // - // final a = 1; - // final b = 2; - // final c = a + b; - // - // Asm: - // addi x4, x0, 1 - // addi x5, x0, 2 - // add x6, x4, x5 final myModule = MyModule( DataField.from(1, name: 'a'), DataField.from(2, name: 'b'), @@ -40,6 +31,5 @@ void main() async { print(generatedAsm); final generatedBin = myModule.generateBinary(); - File('myProgram.bin').writeAsBytesSync(generatedBin); } diff --git a/packages/river_adl/lib/river_adl.dart b/packages/river_adl/lib/river_adl.dart index 94105bc..23b1497 100644 --- a/packages/river_adl/lib/river_adl.dart +++ b/packages/river_adl/lib/river_adl.dart @@ -1,4 +1,23 @@ library; +export 'package:bintools/bintools.dart' + show + ElfWriter, + ElfWriterClass, + Section, + SectionType, + SectionFlags, + Relocation, + RelocationType, + Symbol, + Linker, + LinkerScript, + LinkedBinary, + MemoryRegion; + +export 'src/control_flow.dart'; export 'src/data.dart'; +export 'src/instr.dart'; +export 'src/instruction_set.dart'; +export 'src/label.dart'; export 'src/module.dart'; diff --git a/packages/river_adl/lib/src/control_flow.dart b/packages/river_adl/lib/src/control_flow.dart new file mode 100644 index 0000000..de6d902 --- /dev/null +++ b/packages/river_adl/lib/src/control_flow.dart @@ -0,0 +1,68 @@ +import 'label.dart'; +import 'module.dart'; + +extension ControlFlow on Module { + void ifBlock({ + required void Function() condition, + required void Function() then, + void Function()? orElse, + }) { + final elseLabel = Label('_else_${instructions.length}'); + condition(); + + if (orElse != null) { + then(); + final end = Label('_endif_${instructions.length}'); + jal(end); + placeLabel(elseLabel); + orElse(); + placeLabel(end); + } else { + then(); + placeLabel(elseLabel); + } + } + + void whileLoop({ + required void Function() condition, + required void Function() body, + }) { + final top = Label('_while_${instructions.length}'); + final end = Label('_wend_${instructions.length}'); + + placeLabel(top); + condition(); + body(); + jal(top); + placeLabel(end); + } + + void doWhile({ + required void Function() body, + required void Function() condition, + }) { + final top = Label('_do_${instructions.length}'); + + placeLabel(top); + body(); + condition(); + } + + void forLoop({ + required void Function() init, + required void Function() condition, + required void Function() update, + required void Function() body, + }) { + init(); + final top = Label('_for_${instructions.length}'); + final end = Label('_forend_${instructions.length}'); + + placeLabel(top); + condition(); + body(); + update(); + jal(top); + placeLabel(end); + } +} diff --git a/packages/river_adl/lib/src/data.dart b/packages/river_adl/lib/src/data.dart index abac0ba..339cf5c 100644 --- a/packages/river_adl/lib/src/data.dart +++ b/packages/river_adl/lib/src/data.dart @@ -1,4 +1,4 @@ -import 'package:riscv/riscv.dart' hide Instruction; +import 'package:river/river.dart'; import 'instr.dart'; import 'module.dart'; @@ -17,7 +17,7 @@ enum DataType { final int width; final bool unsigned; - int get bytes => width ~/ 4; + int get bytes => width ~/ 8; } enum DataLocation { register, memory, immediate } @@ -43,6 +43,7 @@ class DataField { this.vreg, this.memAddress, }) : module = module ?? Module.current; + DataField.register( Register reg, { this.name, @@ -54,6 +55,7 @@ class DataField { assignedRegister = reg, memAddress = null, module = module ?? Module.current; + DataField.zero({this.name, Module? module, this.ssaId, this.vreg}) : type = DataType.i32, source = DataLocation.register, @@ -66,125 +68,63 @@ class DataField { DataLocation? source, Module? module, Instruction? producer, + Register? assignedRegister, int? ssaId, int? vreg, - }) => DataField( - type ?? this.type, - ssaId: ssaId ?? this.ssaId, - name: name ?? this.name, - source: source ?? this.source, - module: module ?? this.module, - producer: producer ?? this.producer, - vreg: vreg ?? this.vreg, - ); - - String? _subname(String suffix) => name != null ? '${name}_${suffix}' : null; - - bool _canFold(DataField other) => - source == DataLocation.immediate && - other.source == DataLocation.immediate && - producer != null && - other.producer != null && - producer?.imm != null && - other.producer?.imm != null; - - void bind(DataField value) { - producer = value.producer; - value.producer = value.producer!.assignOutput(this); - } - - void load(DataField other) { - final i = RInstruction( - RInstructionConfig.add(other), - this, - DataField.zero(module: module), + }) { + final f = DataField( + type ?? this.type, + ssaId: ssaId ?? this.ssaId, + name: name ?? this.name, + source: source ?? this.source, + module: module ?? this.module, + producer: producer ?? this.producer, + vreg: vreg ?? this.vreg, ); - - producer = i; - module!.addInstruction(i); - } - - DataField operator +(DataField other) { - final outName = _subname('add_out'); - if (_canFold(other)) { - final a = producer!.imm!; - final b = other.producer!.imm!; - return DataField.from(a + b, name: outName, module: module); - } else { - final out = module != null - ? module!.field(type, name: outName) - : DataField(type, name: outName); - final add = RInstruction(RInstructionConfig.add(this), out, other); - out.producer = add; - (module ?? other.module)!.addInstruction(add); - return out; - } - } - - DataField operator -(DataField other) { - final outName = _subname('sub_out'); - if (_canFold(other)) { - final a = producer!.imm!; - final b = other.producer!.imm!; - return DataField.from(a - b, name: outName, module: module); - } else { - final out = module != null - ? module!.field(type, name: outName) - : DataField(type, name: outName); - final sub = RInstruction(RInstructionConfig.sub(this), out, other); - out.producer = sub; - (module ?? other.module)!.addInstruction(sub); - return out; - } + f.assignedRegister = assignedRegister ?? this.assignedRegister; + return f; } - DataField operator |(DataField other) { - final outName = _subname('sub_out'); - if (_canFold(other)) { - final a = producer!.imm!; - final b = other.producer!.imm!; - return DataField.from(a | b, name: outName, module: module); - } else { - final out = module != null - ? module!.field(type, name: outName) - : DataField(type, name: outName); - final sub = RInstruction(RInstructionConfig.or(this), out, other); - out.producer = sub; - (module ?? other.module)!.addInstruction(sub); - return out; + void bind(DataField value) { + final oldInstr = value.producer!; + final newInstr = oldInstr.assignOutput(this); + producer = newInstr; + + if (module != null) { + final instrs = module!.instructions; + final idx = instrs.indexOf(oldInstr); + if (idx >= 0) { + instrs[idx] = newInstr; + } } } - DataField operator &(DataField other) { - final outName = _subname('sub_out'); - if (_canFold(other)) { - final a = producer!.imm!; - final b = other.producer!.imm!; - return DataField.from(a & b, name: outName, module: module); - } else { - final out = module != null - ? module!.field(type, name: outName) - : DataField(type, name: outName); - final sub = RInstruction(RInstructionConfig.and(this), out, other); - out.producer = sub; - (module ?? other.module)!.addInstruction(sub); - return out; - } - } - - @override - String toString() => - 'DataField(name: $name, type: $type, source: $source, module: $module)'; + DataField operator +(DataField other) => + (module ?? other.module)!.add(this, other); + DataField operator -(DataField other) => + (module ?? other.module)!.sub(this, other); + DataField operator |(DataField other) => + (module ?? other.module)!.or(this, other); + DataField operator &(DataField other) => + (module ?? other.module)!.and(this, other); + DataField operator ^(DataField other) => + (module ?? other.module)!.xor(this, other); static DataField from(int value, {String? name, Module? module}) { - final field = module != null - ? module.field(DataType.i32, name: name) - : DataField(DataType.i32, name: name); - field.producer = IInstruction( - IInstructionConfig.addi(value), - field, - DataField.zero(module: module), + final m = module ?? Module.current; + if (m != null) return m.li(value); + + final field = DataField( + DataType.i32, + name: name, + source: DataLocation.immediate, ); + field.pendingImm = value; return field; } + + int? pendingImm; + + @override + String toString() => 'DataField(name: $name, type: $type, source: $source)'; } diff --git a/packages/river_adl/lib/src/instr.dart b/packages/river_adl/lib/src/instr.dart index b6a8de3..9f3fc33 100644 --- a/packages/river_adl/lib/src/instr.dart +++ b/packages/river_adl/lib/src/instr.dart @@ -1,8 +1 @@ -import 'package:riscv/riscv.dart' hide Instruction; -import 'instr/base.dart'; -import 'data.dart'; -import 'module.dart'; - export 'instr/base.dart'; -export 'instr/i.dart'; -export 'instr/r.dart'; diff --git a/packages/river_adl/lib/src/instr/base.dart b/packages/river_adl/lib/src/instr/base.dart index 48913f9..429b04c 100644 --- a/packages/river_adl/lib/src/instr/base.dart +++ b/packages/river_adl/lib/src/instr/base.dart @@ -1,5 +1,7 @@ -import 'package:riscv/riscv.dart' hide Instruction; +import 'package:harbor/harbor.dart'; + import '../data.dart'; +import '../label.dart'; List encodeAsBytes(int word) => [ word & 0xFF, @@ -8,28 +10,179 @@ List encodeAsBytes(int word) => [ (word >> 24) & 0xFF, ]; -abstract class Instruction { - const Instruction(); +class Instruction { + final RiscVOperation op; + final DataField? rd; + final DataField? rs1; + final DataField? rs2; + final int? imm; + final Label? label; + final bool _hasSideEffects; + + const Instruction( + this.op, { + this.rd, + this.rs1, + this.rs2, + this.imm, + this.label, + bool hasSideEffects = false, + }) : _hasSideEffects = hasSideEffects; + + DataField? get output => rd; + + List get inputs => [if (rs1 != null) rs1!, if (rs2 != null) rs2!]; + + bool get hasSideEffects => + _hasSideEffects || op.format == sType || op.format == bType; + + Instruction copyWith({ + DataField? rd, + DataField? rs1, + DataField? rs2, + int? imm, + Label? label, + }) => Instruction( + op, + rd: rd ?? this.rd, + rs1: rs1 ?? this.rs1, + rs2: rs2 ?? this.rs2, + imm: imm ?? this.imm, + label: label ?? this.label, + hasSideEffects: _hasSideEffects, + ); + + Instruction assignOutput(DataField output) => copyWith(rd: output); + + Instruction assignInputs(List inputs) { + switch (inputs.length) { + case 0: + return this; + case 1: + return copyWith(rs1: inputs[0]); + default: + return copyWith(rs1: inputs[0], rs2: inputs[1]); + } + } + + int encode({int pc = 0}) { + final fmt = op.format; + final rdVal = rd?.assignedRegister?.value ?? 0; + final rs1Val = rs1?.assignedRegister?.value ?? 0; + final rs2Val = rs2?.assignedRegister?.value ?? 0; + final immVal = imm ?? 0; - int? get imm => null; + if (fmt == rType) { + final f7 = op.funct7 ?? 0; + final f3 = op.funct3 ?? 0; + // System instructions (mret, sret, ecall, etc.) encode funct7+rs2 + // as a fixed value passed via imm + final rs2Enc = (rd == null && rs1 == null && rs2 == null && imm != null) + ? (immVal & 0x1F) + : rs2Val; + return (f7 << 25) | + (rs2Enc << 20) | + (rs1Val << 15) | + (f3 << 12) | + (rdVal << 7) | + op.opcode; + } else if (fmt == iType) { + return ((immVal & 0xFFF) << 20) | + (rs1Val << 15) | + (op.funct3! << 12) | + (rdVal << 7) | + op.opcode; + } else if (fmt == sType) { + final immLo = immVal & 0x1F; + final immHi = (immVal >> 5) & 0x7F; + return (immHi << 25) | + (rs2Val << 20) | + (rs1Val << 15) | + (op.funct3! << 12) | + (immLo << 7) | + op.opcode; + } else if (fmt == bType) { + final raw = label != null ? (label!.offset - pc) : immVal; + final target = raw & 0x1FFF; + final b12 = (target >> 12) & 1; + final b11 = (target >> 11) & 1; + final b10_5 = (target >> 5) & 0x3F; + final b4_1 = (target >> 1) & 0xF; + return (b12 << 31) | + (b10_5 << 25) | + (rs2Val << 20) | + (rs1Val << 15) | + (op.funct3! << 12) | + (b4_1 << 8) | + (b11 << 7) | + op.opcode; + } else if (fmt == uType) { + return (immVal & 0xFFFFF000) | (rdVal << 7) | op.opcode; + } else if (fmt == jType) { + final raw = label != null ? (label!.offset - pc) : immVal; + final target = raw & 0x1FFFFF; + final b20 = (target >> 20) & 1; + final b19_12 = (target >> 12) & 0xFF; + final b11 = (target >> 11) & 1; + final b10_1 = (target >> 1) & 0x3FF; + return (b20 << 31) | + (b10_1 << 21) | + (b11 << 20) | + (b19_12 << 12) | + (rdVal << 7) | + op.opcode; + } - DataField? get output; - List get inputs; + throw UnsupportedError('Unknown format for ${op.mnemonic}'); + } - bool get hasSideEffects => false; + List toBinary({int pc = 0}) => encodeAsBytes(encode(pc: pc)); - Instruction assignOutput(DataField output); - Instruction assignInputs(List inputs); + String toAsm() { + final fmt = op.format; + final m = op.mnemonic; - String toAsm(); - InstructionType type(); + String reg(DataField? f) => f?.assignedRegister?.name ?? 'x0'; - List toBinary() { - final t = type(); - if (t is RType) return encodeAsBytes(t.encode()); - if (t is IType) return encodeAsBytes(t.encode()); - if (t is UType) return encodeAsBytes(t.encode()); + if (fmt == rType) { + if (rd == null && rs1 == null && rs2 == null) return m; + return '$m ${reg(rd)}, ${reg(rs1)}, ${reg(rs2)}'; + } else if (fmt == iType) { + return '$m ${reg(rd)}, ${reg(rs1)}, $imm'; + } else if (fmt == sType) { + return '$m ${reg(rs2)}, ${imm ?? 0}(${reg(rs1)})'; + } else if (fmt == bType) { + return '$m ${reg(rs1)}, ${reg(rs2)}, ${label?.name ?? imm}'; + } else if (fmt == uType) { + return '$m ${reg(rd)}, ${(imm ?? 0) >> 12}'; + } else if (fmt == jType) { + return '$m ${reg(rd)}, ${label?.name ?? imm}'; + } - throw 'Unknown instruction type for $t'; + return m; } + + @override + String toString() => toAsm(); +} + +class LabelInstruction extends Instruction { + LabelInstruction(Label label) + : super(_nop, label: label, hasSideEffects: true); + + @override + int encode({int pc = 0}) => 0; + + @override + List toBinary({int pc = 0}) => []; + + @override + String toAsm() => '${label!.name}:'; + + static final _nop = RiscVOperation( + mnemonic: '.label', + opcode: 0, + format: rType, + microcode: [], + ); } diff --git a/packages/river_adl/lib/src/instr/i.dart b/packages/river_adl/lib/src/instr/i.dart deleted file mode 100644 index 17b6929..0000000 --- a/packages/river_adl/lib/src/instr/i.dart +++ /dev/null @@ -1,76 +0,0 @@ -import 'package:riscv/riscv.dart' hide Instruction; -import 'base.dart'; -import '../data.dart'; -import '../module.dart'; - -class IInstructionConfig { - final String name; - final int opcode; - final int funct3; - final int imm; - - const IInstructionConfig(this.name, this.opcode, this.funct3, this.imm); - - const IInstructionConfig.addi(this.imm) - : name = 'addi', - opcode = 0x13, - funct3 = 0; - - const IInstructionConfig.xori(this.imm) - : name = 'xori', - opcode = 0x13, - funct3 = 0x4; - - const IInstructionConfig.ori(this.imm) - : name = 'ori', - opcode = 0x13, - funct3 = 0x6; - - const IInstructionConfig.andi(this.imm) - : name = 'andi', - opcode = 0x13, - funct3 = 0x7; -} - -class IInstruction extends Instruction { - final IInstructionConfig config; - final DataField rd; - final DataField rs1; - - const IInstruction(this.config, this.rd, this.rs1); - IInstruction.load(this.config, this.rd, {Module? module}) - : rs1 = DataField.zero(module: module); - - @override - int? get imm => config.imm; - - @override - DataField? get output => rd; - - @override - List get inputs => [rs1]; - - @override - Instruction assignOutput(DataField output) => - IInstruction(config, output, rs1); - - @override - Instruction assignInputs(List inputs) => - IInstruction(config, rd, inputs[0]); - - @override - String toAsm() => - '${config.name} ${rd.assignedRegister!.name}, ${rs1.assignedRegister!.name}, ${config.imm}'; - - @override - InstructionType type() => IType( - opcode: config.opcode, - funct3: config.funct3, - rd: rd.assignedRegister!.value, - rs1: rs1.assignedRegister!.value, - imm: config.imm, - ); - - @override - String toString() => '${config.name} $rd, $rs1, ${config.imm}'; -} diff --git a/packages/river_adl/lib/src/instr/r.dart b/packages/river_adl/lib/src/instr/r.dart deleted file mode 100644 index 76d01a8..0000000 --- a/packages/river_adl/lib/src/instr/r.dart +++ /dev/null @@ -1,94 +0,0 @@ -import 'package:riscv/riscv.dart' hide Instruction; -import 'base.dart'; -import '../data.dart'; -import '../module.dart'; - -class RInstructionConfig { - final String name; - final int opcode; - final int funct3; - final int funct7; - final DataField rs2; - - const RInstructionConfig( - this.name, - this.opcode, - this.funct3, - this.funct7, - this.rs2, - ); - - const RInstructionConfig.add(this.rs2) - : name = 'add', - opcode = 0x33, - funct3 = 0, - funct7 = 0; - - const RInstructionConfig.sub(this.rs2) - : name = 'sub', - opcode = 0x33, - funct3 = 0, - funct7 = 0x20; - - const RInstructionConfig.xor(this.rs2) - : name = 'xor', - opcode = 0x33, - funct3 = 0x4, - funct7 = 0x0; - - const RInstructionConfig.or(this.rs2) - : name = 'or', - opcode = 0x33, - funct3 = 0x6, - funct7 = 0x0; - - const RInstructionConfig.and(this.rs2) - : name = 'and', - opcode = 0x33, - funct3 = 0x7, - funct7 = 0x0; - - RInstructionConfig copyWith({DataField? rs2}) => - RInstructionConfig(name, opcode, funct3, funct7, rs2 ?? this.rs2); -} - -class RInstruction extends Instruction { - final RInstructionConfig config; - final DataField rd; - final DataField rs1; - - const RInstruction(this.config, this.rd, this.rs1); - RInstruction.load(this.config, this.rd, {Module? module}) - : rs1 = DataField.zero(module: module); - - @override - DataField? get output => rd; - - @override - List get inputs => [rs1, config.rs2]; - - @override - Instruction assignOutput(DataField output) => - RInstruction(config, output, rs1); - - @override - Instruction assignInputs(List inputs) => - RInstruction(config.copyWith(rs2: inputs[1]), rd, inputs[0]); - - @override - String toAsm() => - '${config.name} ${rd.assignedRegister!.name}, ${rs1.assignedRegister!.name}, ${config.rs2.assignedRegister!.name}'; - - @override - InstructionType type() => RType( - opcode: config.opcode, - funct3: config.funct3, - funct7: config.funct7, - rd: rd.assignedRegister!.value, - rs1: rs1.assignedRegister!.value, - rs2: config.rs2.assignedRegister!.value, - ); - - @override - String toString() => '${config.name} $rd, $rs1, ${config.rs2}'; -} diff --git a/packages/river_adl/lib/src/instr/ri.dart b/packages/river_adl/lib/src/instr/ri.dart deleted file mode 100644 index 05e904e..0000000 --- a/packages/river_adl/lib/src/instr/ri.dart +++ /dev/null @@ -1,108 +0,0 @@ -import 'package:riscv/riscv.dart' hide Instruction; -import 'base.dart'; -import 'i.dart'; -import 'r.dart'; -import '../data.dart'; -import '../module.dart'; - -class ROrIInstruction extends Instruction { - final IInstructionConfig? i; - final RInstructionConfig? r; - - final DataField rd; - final DataField rs1; - - const ROrIInstruction(RInstructionConfig r, this.rd, this.rs1) - : r = r, - i = null; - const ROrIInstruction.immediate(IInstructionConfig i, this.rd, this.rs1) - : i = i, - r = null; - - ROrIInstruction.load(RInstructionConfig r, this.rd, {Module? module}) - : r = r, - rs1 = DataField.zero(module: module), - i = null; - ROrIInstruction.loadImmediate(IInstructionConfig i, this.rd, {Module? module}) - : i = i, - rs1 = DataField.zero(module: module), - r = null; - - @override - DataField? get output => rd; - - @override - List get inputs => [rs1, if (r != null) r!.rs2]; - - @override - Instruction assignOutput(DataField output) { - if (i == null && r != null) { - return ROrIInstruction(r!, output, rs1); - } else if (i != null && r == null) { - return ROrIInstruction.immediate(i!, output, rs1); - } else { - throw 'Invalid encoding, rs2 and imm are both set.'; - } - } - - @override - Instruction assignInputs(List inputs) { - if (i == null && r != null) { - return ROrIInstruction(r!.copyWith(rs2: inputs[1]), rd, inputs[0]); - } else if (i != null && r == null) { - return ROrIInstruction.immediate(i!, rd, inputs[0]); - } else { - throw 'Invalid encoding, rs2 and imm are both set.'; - } - } - - @override - String toAsm() { - if (i == null && r != null) { - return '${r!.name} ${rd.assignedRegister!.name},' - ' ${rs1.assignedRegister!.name},' - ' ${r!.rs2.assignedRegister!.name}'; - } else if (i != null && r == null) { - return '${i!.name} ${rd.assignedRegister!.name},' - ' ${rs1.assignedRegister!.name},' - ' ${i!.imm}'; - } else { - throw 'Invalid encoding, rs2 and imm are both set.'; - } - } - - @override - InstructionType type() { - if (i == null && r != null) { - return RType( - opcode: r!.opcode, - funct3: r!.funct3, - funct7: r!.funct7, - rd: rd.assignedRegister!.value, - rs1: rs1.assignedRegister!.value, - rs2: r!.rs2.assignedRegister!.value, - ); - } else if (i != null && r == null) { - return IType( - opcode: i!.opcode, - funct3: i!.funct3, - rd: rd.assignedRegister!.value, - rs1: rs1.assignedRegister!.value, - imm: i!.imm, - ); - } else { - throw 'Invalid encoding, rs2 and imm are both set.'; - } - } - - @override - String toString() { - if (i == null && r != null) { - return '${r!.name} $rd, $rs1, ${r!.rs2}'; - } else if (i != null && r == null) { - return '${i!.name} $rd, $rs1, ${i!.imm}'; - } else { - throw 'Invalid encoding, rs2 and imm are both set.'; - } - } -} diff --git a/packages/river_adl/lib/src/instruction_set.dart b/packages/river_adl/lib/src/instruction_set.dart new file mode 100644 index 0000000..8bc784d --- /dev/null +++ b/packages/river_adl/lib/src/instruction_set.dart @@ -0,0 +1,361 @@ +import 'package:river/river.dart'; + +import 'data.dart'; +import 'instr/base.dart'; +import 'label.dart'; +import 'module.dart'; + +mixin InstructionSet { + RiscVIsaConfig get isa; + Module get currentModule; + + final Map _opCache = {}; + + RiscVOperation _require(String mnemonic) => + _opCache.putIfAbsent(mnemonic, () { + for (final op in isa.allOperations) { + if (op.mnemonic == mnemonic) return op; + } + throw UnsupportedError( + '"$mnemonic" not available in ISA ${isa.implementsString}', + ); + }); + + DataField get zero => DataField.zero(module: currentModule); + + DataField _snap(DataField f) { + if (f.producer != null && f.assignedRegister != null) { + return f.copyWith(ssaId: currentModule.nextSsaId()); + } + return f; + } + + DataField _emitR(String mnemonic, DataField rs1, DataField rs2) { + final op = _require(mnemonic); + final out = currentModule.field(rs1.type); + final instr = Instruction(op, rd: out, rs1: _snap(rs1), rs2: _snap(rs2)); + out.producer = instr; + currentModule.addInstruction(instr); + return out; + } + + DataField _emitI(String mnemonic, DataField rs1, int imm) { + final op = _require(mnemonic); + final out = currentModule.field(rs1.type); + final instr = Instruction(op, rd: out, rs1: _snap(rs1), imm: imm); + out.producer = instr; + currentModule.addInstruction(instr); + return out; + } + + void _emitS(String mnemonic, DataField base, DataField src, int offset) { + final op = _require(mnemonic); + final instr = Instruction( + op, + rs1: _snap(base), + rs2: _snap(src), + imm: offset, + ); + currentModule.addInstruction(instr); + } + + void _emitB(String mnemonic, DataField rs1, DataField rs2, Label target) { + final op = _require(mnemonic); + final instr = Instruction( + op, + rs1: _snap(rs1), + rs2: _snap(rs2), + label: target, + ); + currentModule.addInstruction(instr); + } + + DataField _emitU(String mnemonic, int imm) { + final op = _require(mnemonic); + final out = currentModule.field(DataType.i32); + final instr = Instruction(op, rd: out, imm: imm); + out.producer = instr; + currentModule.addInstruction(instr); + return out; + } + + DataField _emitJ(String mnemonic, Label target) { + final op = _require(mnemonic); + final out = currentModule.field(DataType.i32); + final instr = Instruction(op, rd: out, label: target, hasSideEffects: true); + out.producer = instr; + currentModule.addInstruction(instr); + return out; + } + + // ── RV32I ALU (R-type) ── + DataField add(DataField a, DataField b) => _emitR('add', a, b); + DataField sub(DataField a, DataField b) => _emitR('sub', a, b); + DataField sll(DataField a, DataField b) => _emitR('sll', a, b); + DataField slt(DataField a, DataField b) => _emitR('slt', a, b); + DataField sltu(DataField a, DataField b) => _emitR('sltu', a, b); + DataField xor(DataField a, DataField b) => _emitR('xor', a, b); + DataField srl(DataField a, DataField b) => _emitR('srl', a, b); + DataField sra(DataField a, DataField b) => _emitR('sra', a, b); + DataField or(DataField a, DataField b) => _emitR('or', a, b); + DataField and(DataField a, DataField b) => _emitR('and', a, b); + + // ── RV32I ALU (I-type) ── + DataField addi(DataField a, int imm) => _emitI('addi', a, imm); + DataField slti(DataField a, int imm) => _emitI('slti', a, imm); + DataField sltiu(DataField a, int imm) => _emitI('sltiu', a, imm); + DataField xori(DataField a, int imm) => _emitI('xori', a, imm); + DataField ori(DataField a, int imm) => _emitI('ori', a, imm); + DataField andi(DataField a, int imm) => _emitI('andi', a, imm); + DataField slli(DataField a, int imm) => _emitI('slli', a, imm); + DataField srli(DataField a, int imm) => _emitI('srli', a, imm); + DataField srai(DataField a, int imm) => _emitI('srai', a, imm); + + // ── Loads (I-type) ── + DataField lb(DataField base, {int offset = 0}) => _emitI('lb', base, offset); + DataField lh(DataField base, {int offset = 0}) => _emitI('lh', base, offset); + DataField lw(DataField base, {int offset = 0}) => _emitI('lw', base, offset); + DataField lbu(DataField base, {int offset = 0}) => + _emitI('lbu', base, offset); + DataField lhu(DataField base, {int offset = 0}) => + _emitI('lhu', base, offset); + + // ── Stores (S-type) ── + void sb(DataField base, DataField src, {int offset = 0}) => + _emitS('sb', base, src, offset); + void sh(DataField base, DataField src, {int offset = 0}) => + _emitS('sh', base, src, offset); + void sw(DataField base, DataField src, {int offset = 0}) => + _emitS('sw', base, src, offset); + void sd(DataField base, DataField src, {int offset = 0}) => + _emitS('sd', base, src, offset); + + // ── Branches (B-type) ── + void beq(DataField a, DataField b, Label target) => + _emitB('beq', a, b, target); + void bne(DataField a, DataField b, Label target) => + _emitB('bne', a, b, target); + void blt(DataField a, DataField b, Label target) => + _emitB('blt', a, b, target); + void bge(DataField a, DataField b, Label target) => + _emitB('bge', a, b, target); + void bltu(DataField a, DataField b, Label target) => + _emitB('bltu', a, b, target); + void bgeu(DataField a, DataField b, Label target) => + _emitB('bgeu', a, b, target); + + // ── Upper immediate (U-type) ── + DataField lui(int imm) => _emitU('lui', imm); + DataField auipc(int imm) => _emitU('auipc', imm); + + // ── Jumps (J-type) ── + DataField jal(Label target) => _emitJ('jal', target); + DataField jalr(DataField base, {int offset = 0}) { + final op = _require('jalr'); + final out = currentModule.field(base.type); + final instr = Instruction( + op, + rd: out, + rs1: _snap(base), + imm: offset, + hasSideEffects: true, + ); + out.producer = instr; + currentModule.addInstruction(instr); + return out; + } + + // ── CSR (I-type with CSR address as immediate) ── + DataField csrrw(int csr, DataField rs1) { + final op = _require('csrrw'); + final out = currentModule.field(rs1.type); + final instr = Instruction( + op, + rd: out, + rs1: _snap(rs1), + imm: csr, + hasSideEffects: true, + ); + out.producer = instr; + currentModule.addInstruction(instr); + return out; + } + + DataField csrrs(int csr, DataField rs1) { + final op = _require('csrrs'); + final out = currentModule.field(rs1.type); + final instr = Instruction( + op, + rd: out, + rs1: _snap(rs1), + imm: csr, + hasSideEffects: true, + ); + out.producer = instr; + currentModule.addInstruction(instr); + return out; + } + + DataField csrrc(int csr, DataField rs1) { + final op = _require('csrrc'); + final out = currentModule.field(rs1.type); + final instr = Instruction( + op, + rd: out, + rs1: _snap(rs1), + imm: csr, + hasSideEffects: true, + ); + out.producer = instr; + currentModule.addInstruction(instr); + return out; + } + + // ── M extension (R-type) ── + DataField mul(DataField a, DataField b) => _emitR('mul', a, b); + DataField mulh(DataField a, DataField b) => _emitR('mulh', a, b); + DataField div(DataField a, DataField b) => _emitR('div', a, b); + DataField divu(DataField a, DataField b) => _emitR('divu', a, b); + DataField rem(DataField a, DataField b) => _emitR('rem', a, b); + DataField remu(DataField a, DataField b) => _emitR('remu', a, b); + + // ── F extension (single-precision) ── + DataField flw(DataField base, {int offset = 0}) => + _emitI('flw', base, offset); + void fsw(DataField base, DataField src, {int offset = 0}) => + _emitS('fsw', base, src, offset); + DataField fadds(DataField a, DataField b) => _emitR('fadd.s', a, b); + DataField fsubs(DataField a, DataField b) => _emitR('fsub.s', a, b); + DataField fmuls(DataField a, DataField b) => _emitR('fmul.s', a, b); + DataField fdivs(DataField a, DataField b) => _emitR('fdiv.s', a, b); + DataField fsqrts(DataField a) { + final op = _require('fsqrt.s'); + final out = currentModule.field(DataType.i32); + final instr = Instruction(op, rd: out, rs1: a); + out.producer = instr; + currentModule.addInstruction(instr); + return out; + } + + DataField fcvtws(DataField a) { + final op = _require('fcvt.w.s'); + final out = currentModule.field(DataType.i32); + final instr = Instruction(op, rd: out, rs1: a); + out.producer = instr; + currentModule.addInstruction(instr); + return out; + } + + DataField fcvtsw(DataField a) { + final op = _require('fcvt.s.w'); + final out = currentModule.field(DataType.i32); + final instr = Instruction(op, rd: out, rs1: a); + out.producer = instr; + currentModule.addInstruction(instr); + return out; + } + + DataField feqs(DataField a, DataField b) => _emitR('feq.s', a, b); + DataField flts(DataField a, DataField b) => _emitR('flt.s', a, b); + DataField fles(DataField a, DataField b) => _emitR('fle.s', a, b); + + // ── D extension (double-precision) ── + DataField fld(DataField base, {int offset = 0}) => + _emitI('fld', base, offset); + void fsd(DataField base, DataField src, {int offset = 0}) => + _emitS('fsd', base, src, offset); + DataField faddd(DataField a, DataField b) => _emitR('fadd.d', a, b); + DataField fsubd(DataField a, DataField b) => _emitR('fsub.d', a, b); + DataField fmuld(DataField a, DataField b) => _emitR('fmul.d', a, b); + DataField fdivd(DataField a, DataField b) => _emitR('fdiv.d', a, b); + DataField fsqrtd(DataField a) { + final op = _require('fsqrt.d'); + final out = currentModule.field(DataType.i64); + final instr = Instruction(op, rd: out, rs1: a); + out.producer = instr; + currentModule.addInstruction(instr); + return out; + } + + DataField feqd(DataField a, DataField b) => _emitR('feq.d', a, b); + DataField fltd(DataField a, DataField b) => _emitR('flt.d', a, b); + DataField fled(DataField a, DataField b) => _emitR('fle.d', a, b); + + // ── Fence ── + void fence() { + final op = _require('fence'); + currentModule.addInstruction(Instruction(op, hasSideEffects: true)); + } + + // ── Labels ── + Label label(String name) { + final l = Label(name); + currentModule.addInstruction(LabelInstruction(l)); + return l; + } + + void placeLabel(Label l) { + currentModule.addInstruction(LabelInstruction(l)); + } + + // ── System ── + void ecall() { + final op = _require('ecall'); + currentModule.addInstruction(Instruction(op, imm: 0, hasSideEffects: true)); + } + + void ebreak() { + final op = _require('ebreak'); + currentModule.addInstruction(Instruction(op, imm: 1, hasSideEffects: true)); + } + + void mret() { + final op = _require('mret'); + currentModule.addInstruction( + Instruction(op, imm: 0x302, hasSideEffects: true), + ); + } + + void sret() { + final op = _require('sret'); + currentModule.addInstruction( + Instruction(op, imm: 0x102, hasSideEffects: true), + ); + } + + void wfi() { + final op = _require('wfi'); + currentModule.addInstruction( + Instruction(op, imm: 0x105, hasSideEffects: true), + ); + } + + // ── Pseudo-instructions ── + DataField li(int imm) { + if (imm >= -2048 && imm < 2048) return addi(zero, imm); + // addi sign-extends its low 12 bits, so when bit 11 is set the lui half must + // round up one page and addi subtracts back. Without the carry, immediates + // with low-12 >= 0x800 land 0x1000 low. + var lo = imm & 0xFFF; + if (lo >= 0x800) lo -= 0x1000; + final upper = lui((imm - lo) & 0xFFFFF000); + final value = addi(upper, lo); + // On RV64 `lui` sign-extends bit 31, so a 32-bit address >= 0x8000_0000 + // materializes as 0xFFFFFFFF_8.... Zero-extend the low 32 bits back; without + // this a load/store to 0x8000_0000 RAM drives 0xFFFFFFFF_80000000, which the + // decoder does not match (no ack, core wedges). + if (isa.mxlen == RiscVMxlen.rv64 && imm > 0x7FFFFFFF && imm <= 0xFFFFFFFF) { + return srli(slli(value, 32), 32); + } + return value; + } + + DataField mv(DataField src) => addi(src, 0); + void nop() { + addi(zero, 0); + } + + void ret() { + jalr(currentModule.register(Register.x1)); + } +} diff --git a/packages/river_adl/lib/src/label.dart b/packages/river_adl/lib/src/label.dart new file mode 100644 index 0000000..5d0fa4b --- /dev/null +++ b/packages/river_adl/lib/src/label.dart @@ -0,0 +1,20 @@ +class Label { + final String name; + int? _offset; + + Label(this.name); + + int get offset { + if (_offset == null) throw StateError('Label "$name" not yet resolved'); + return _offset!; + } + + bool get isResolved => _offset != null; + + void resolve(int offset) { + _offset = offset; + } + + @override + String toString() => '$name:'; +} diff --git a/packages/river_adl/lib/src/module.dart b/packages/river_adl/lib/src/module.dart index 9fc78a6..101374f 100644 --- a/packages/river_adl/lib/src/module.dart +++ b/packages/river_adl/lib/src/module.dart @@ -1,6 +1,10 @@ -import 'package:riscv/riscv.dart' show Register; +import 'package:harbor/harbor.dart'; +import 'package:river/river.dart' show Register; + import 'data.dart'; import 'instr.dart'; +import 'instruction_set.dart'; +import 'package:bintools/bintools.dart'; class _LiveInterval { int vreg; @@ -11,13 +15,11 @@ class _LiveInterval { } class _RegisterAllocator { - int nextRegIndex = 4; // start at x4 + int nextRegIndex = 4; final Map _vregToIndex = {}; final List _free = []; final Set _reserved = {0}; - _RegisterAllocator(); - void run( List instructions, Map intervals, @@ -32,18 +34,16 @@ class _RegisterAllocator { } } - int _allocIndexSkippingReserved() { + int allocIndexSkippingReserved() { while (_reserved.contains(nextRegIndex)) { nextRegIndex++; } return nextRegIndex++; } - int _allocIndex() { - if (_free.isNotEmpty) { - return _free.removeLast(); - } - return _allocIndexSkippingReserved(); + int allocIndex() { + if (_free.isNotEmpty) return _free.removeLast(); + return allocIndexSkippingReserved(); } for (final out in outputFields) { @@ -58,7 +58,7 @@ class _RegisterAllocator { continue; } - final idx = _allocIndexSkippingReserved(); + final idx = allocIndexSkippingReserved(); _vregToIndex[v] = idx; _reserved.add(idx); } @@ -72,7 +72,7 @@ class _RegisterAllocator { final active = <_LiveInterval>[]; - void _expireOld(int position) { + void expireOld(int position) { active.removeWhere((iv) { if (iv.end < position) { final idx = _vregToIndex[iv.vreg]; @@ -86,14 +86,14 @@ class _RegisterAllocator { } for (final iv in intervalList) { - _expireOld(iv.start); + expireOld(iv.start); if (_vregToIndex.containsKey(iv.vreg)) { active.add(iv); continue; } - final idx = _allocIndex(); + final idx = allocIndex(); _vregToIndex[iv.vreg] = idx; active.add(iv); } @@ -110,7 +110,6 @@ class _RegisterAllocator { void _recordPinned(DataField f) { if (f.vreg == null || f.assignedRegister == null) return; - final idx = f.assignedRegister!.value; _reserved.add(idx); _vregToIndex[f.vreg!] = idx; @@ -118,20 +117,28 @@ class _RegisterAllocator { void _assignField(DataField f) { if (f.assignedRegister != null) return; - final vreg = f.vreg; if (vreg == null) return; - - final idx = _vregToIndex[vreg]; - if (idx == null || idx >= Register.values.length) return; - + var idx = _vregToIndex[vreg]; + if (idx == null) { + // Vreg not mapped yet -- allocate on the fly + while (_reserved.contains(nextRegIndex)) { + nextRegIndex++; + } + idx = nextRegIndex++; + _vregToIndex[vreg] = idx; + } + if (idx >= Register.values.length) return; f.assignedRegister = Register.values[idx]; } } -abstract class Module { +abstract class Module with InstructionSet { static Module? current; + @override + Module get currentModule => this; + final Map inputs = {}; final Map outputs = {}; final List instructions = []; @@ -143,6 +150,8 @@ abstract class Module { current = this; } + int nextSsaId() => _nextSSA++; + DataField field(DataType type, {String? name}) => DataField(type, ssaId: _nextSSA++, name: name, module: this); @@ -150,16 +159,22 @@ abstract class Module { DataField output(String name) => outputs[name]!; DataField addInput(String name, DataField field) { - final input = field.copyWith(ssaId: _nextSSA++, name: name, module: this); + if (field.pendingImm != null) { + final resolved = li(field.pendingImm!); + inputs[name] = resolved; + return resolved; + } + + final inp = field.copyWith(ssaId: _nextSSA++, name: name, module: this); - if (input.producer != null) { - final inst = input.producer!.assignOutput(input); + if (inp.producer != null) { + final inst = inp.producer!.assignOutput(inp); instructions.add(inst); - input.producer = inst; + inp.producer = inst; } - inputs[name] = input; - return input; + inputs[name] = inp; + return inp; } DataField addOutput( @@ -185,16 +200,15 @@ abstract class Module { } DataField register(Register reg) { - if (outputs.containsKey(reg.abi)) { - return outputs[reg.abi]!; + if (!outputs.containsKey(reg.abi)) { + outputs[reg.abi] = DataField.register( + reg, + ssaId: _nextSSA++, + name: reg.abi, + module: this, + ); } - outputs[reg.abi] = DataField.register( - reg, - ssaId: _nextSSA++, - name: reg.abi, - module: this, - ); return outputs[reg.abi]!; } @@ -202,50 +216,77 @@ abstract class Module { String generateAssembly() { final asm = StringBuffer(); - for (final inst in _built) { asm.writeln(inst.toAsm()); } - return asm.toString(); } - List generateBinary() { + List generateBinary({int baseAddress = 0}) { final bytes = []; + var offset = 0; + for (final inst in _built) { + if (inst is LabelInstruction) continue; + bytes.addAll(inst.toBinary(pc: offset)); + offset += 4; + } + return bytes; + } + + Section emitToSection({String name = '.text', int baseAddress = 0}) { + final section = Section(name, type: SectionType.text); + var offset = 0; for (final inst in _built) { - bytes.addAll(inst.toBinary()); + if (inst is LabelInstruction) { + section.addSymbol(inst.label!.name); + continue; + } + + if (inst.label != null && !inst.label!.isResolved) { + section.addRelocation( + Relocation( + offset: section.size, + symbol: inst.label!.name, + type: inst.op.format == bType + ? RelocationType.branch + : RelocationType.jal, + ), + ); + } + + section.emitBytes(inst.toBinary(pc: offset)); + offset += 4; } - return bytes; + return section; + } + + void _resolveLabels() { + var offset = 0; + for (final inst in _built) { + if (inst is LabelInstruction) { + inst.label!.resolve(offset); + } else { + offset += 4; + } + } } void _clearState(List instrs) { _nextSSA = 0; - for (final instr in instrs) { if (instr.output != null) { final output = instr.output!; if (output.module == this) { output.ssaId = null; output.vreg = null; - - if (output.assignedRegister != null) { - final reg = output.assignedRegister!; - if (reg.value >= 4) output.assignedRegister = null; - } } } - for (final input in instr.inputs) { if (input.module == this) { input.ssaId = null; input.vreg = null; - - if (input.assignedRegister != null) { - final reg = input.assignedRegister!; - if (reg.value >= 4) input.assignedRegister = null; - } } } } @@ -256,60 +297,76 @@ abstract class Module { for (final instr in instrs) { for (final input in instr.inputs) { if (input.module == this) { - if (input.ssaId == null) { - input.ssaId = _nextSSA++; - } - - if (input.vreg == null) { - input.vreg = nextVreg++; - } + input.ssaId ??= _nextSSA++; + input.vreg ??= nextVreg++; } } - - if (instr.output != null) { - if (instr.output!.module == this) { - if (instr.output!.ssaId == null) { - instr.output!.ssaId = _nextSSA++; - } - - if (instr.output!.vreg == null) { - instr.output!.vreg = nextVreg++; - } - } + if (instr.output != null && instr.output!.module == this) { + instr.output!.ssaId ??= _nextSSA++; + instr.output!.vreg ??= nextVreg++; } } } List _topoSort(List instrs) { - final visited = {}; final sorted = []; - void visit(Instruction inst) { - if (visited.contains(inst)) return; - visited.add(inst); + // Split at labels, topo-sort each segment independently + final segments = >[]; + var current = []; + for (final inst in instrs) { + if (inst is LabelInstruction) { + segments.add(current); + segments.add([inst]); + current = []; + } else { + current.add(inst); + } + } + segments.add(current); - for (final input in inst.inputs) { - final prod = input.producer; - if (prod != null) { - visit(prod); + final visited = {}; + + for (final segment in segments) { + void visit(Instruction inst) { + if (visited.contains(inst)) return; + visited.add(inst); + for (final input in inst.inputs) { + if (input.producer != null) visit(input.producer!); } + sorted.add(inst); } - sorted.add(inst); + for (final inst in segment) { + visit(inst); + } } - for (final inst in instrs) visit(inst); - return sorted; } List _removeDeadCode(List instrs) { - final liveInstructions = {}; + final live = {}; final worklist = []; for (final out in outputs.values) { - if (out.producer != null) { - worklist.add(out); + if (out.producer != null) worklist.add(out); + } + + // Side-effect instructions are always live; seed their inputs too. A write to + // an explicitly pinned register (set via register(xN).bind(...)) is also + // seeded: pinning is intent to hold state across control flow the SSA + // dataflow does not model (loop back-edges, branch merges). Without it a + // pointer incremented at a loop bottom and consumed at the top (across the + // back-edge) has no forward producer-use and is wrongly eliminated. + for (final inst in instrs) { + final pinnedWrite = + inst.output?.assignedRegister != null && + inst.output?.assignedRegister != Register.x0; + if ((inst.hasSideEffects || pinnedWrite) && live.add(inst)) { + for (final input in inst.inputs) { + if (input.producer != null) worklist.add(input); + } } } @@ -317,18 +374,14 @@ abstract class Module { final field = worklist.removeLast(); final instr = field.producer; if (instr == null) continue; - if (liveInstructions.add(instr)) { + if (live.add(instr)) { for (final input in instr.inputs) { - if (input.producer != null) { - worklist.add(input); - } + if (input.producer != null) worklist.add(input); } } } - return instrs - .where((i) => liveInstructions.contains(i) || i.hasSideEffects) - .toList(); + return instrs.where((i) => live.contains(i)).toList(); } Map _computeLiveIntervals(List instrs) { @@ -336,13 +389,11 @@ abstract class Module { for (int i = 0; i < instrs.length; i++) { final inst = instrs[i]; - for (final input in inst.inputs) { if (input.vreg == null) continue; final v = input.vreg!; intervals.putIfAbsent(v, () => _LiveInterval(v, i, i)).end = i; } - if (inst.output != null && inst.output!.vreg != null) { final v = inst.output!.vreg!; intervals.putIfAbsent(v, () => _LiveInterval(v, i, i)).start = i; @@ -357,9 +408,7 @@ abstract class Module { v, () => _LiveInterval(v, lastIdx, lastIdx), ); - if (iv.end < lastIdx) { - iv.end = lastIdx; - } + if (iv.end < lastIdx) iv.end = lastIdx; } return intervals; @@ -370,10 +419,10 @@ abstract class Module { _built = _removeDeadCode(_built); _clearState(_built); _computeState(_built); + _resolveLabels(); final intervals = _computeLiveIntervals(_built); - - var regAlloc = _RegisterAllocator(); + final regAlloc = _RegisterAllocator(); regAlloc.run(_built, intervals, outputs.values); } } diff --git a/packages/river_adl/pubspec.yaml b/packages/river_adl/pubspec.yaml index 681db76..ddf895f 100644 --- a/packages/river_adl/pubspec.yaml +++ b/packages/river_adl/pubspec.yaml @@ -5,12 +5,13 @@ resolution: workspace # repository: https://github.com/my_org/my_repo environment: - sdk: ^3.9.3 + sdk: ^3.11.2 # Add regular dependencies here. dependencies: - riscv: ^1.0.0 - # path: ^1.9.0 + bintools: ^1.0.0 + harbor: ^0.0.1 + river: ^1.0.0 dev_dependencies: lints: ^6.0.0 diff --git a/packages/river_adl/test/river_adl_test.dart b/packages/river_adl/test/river_adl_test.dart index dc5a31e..dfd2405 100644 --- a/packages/river_adl/test/river_adl_test.dart +++ b/packages/river_adl/test/river_adl_test.dart @@ -1,34 +1,430 @@ -import 'package:riscv/riscv.dart'; +import 'package:harbor/harbor.dart'; +import 'package:river/river.dart'; import 'package:river_adl/river_adl.dart'; import 'package:test/test.dart'; -class MyModule extends Module { +class AddModule extends Module { + @override + final isa = RiscVIsaConfig(mxlen: RiscVMxlen.rv32, extensions: [rv32i]); + DataField get c => output('c'); - MyModule(DataField a, DataField b) : super() { + AddModule(DataField a, DataField b) : super() { a = addInput('a', a); b = addInput('b', b); - addOutput('c', type: a.type, source: DataLocation.register); - c.bind(a + b); } } void main() { - group('MyModule', () { - final myModule = MyModule( - DataField.from(1, name: 'a'), - DataField.from(2, name: 'b'), - ); + group('Basic ALU', () { + test('add generates correct assembly', () async { + final mod = AddModule(DataField.from(1), DataField.from(2)); + await mod.build(); + final asm = mod.generateAssembly(); + expect(asm, contains('addi')); + expect(asm, contains('add')); + expect(asm.split('\n').where((l) => l.isNotEmpty).length, 3); + }); + + test('add generates correct binary', () async { + final mod = AddModule(DataField.from(1), DataField.from(2)); + await mod.build(); + final binary = mod.generateBinary(); + expect(binary.length, 12); + }); + + test('sub via operator', () async { + final mod = _SubModule(); + await mod.build(); + expect(mod.generateAssembly(), contains('sub')); + }); + + test('bitwise operators', () async { + final mod = _BitwiseModule(); + await mod.build(); + final asm = mod.generateAssembly(); + expect(asm, contains('or')); + expect(asm, contains('and')); + expect(asm, contains('xor')); + }); + }); + + group('Immediate instructions', () { + test('addi', () async { + final mod = _AddiModule(); + await mod.build(); + expect(mod.generateAssembly(), contains('addi')); + }); + + test('li small value', () async { + final mod = _LiModule(42); + await mod.build(); + expect(mod.generateAssembly(), contains('addi')); + }); + + test('li large value uses lui+addi', () async { + final mod = _LiModule(0x12345); + await mod.build(); + final asm = mod.generateAssembly(); + expect(asm, contains('lui')); + expect(asm, contains('addi')); + }); + }); + + group('Control flow', () { + test('branch with label', () async { + final mod = _BranchModule(); + await mod.build(); + final asm = mod.generateAssembly(); + expect(asm, contains('beq')); + expect(asm, contains('end:')); + }); + + test('multiple branches', () async { + final mod = _MultiBranchModule(); + await mod.build(); + final asm = mod.generateAssembly(); + expect(asm, contains('bne')); + expect(asm, contains('blt')); + }); + }); + + group('Memory operations', () { + test('load word', () async { + final mod = _LoadModule(); + await mod.build(); + expect(mod.generateAssembly(), contains('lw')); + }); + + test('store word', () async { + final mod = _StoreModule(); + await mod.build(); + final asm = mod.generateAssembly(); + expect(asm, contains('sw')); + }); + }); + + group('ISA validation', () { + test('throws on missing M extension', () { + expect(() => _MulModule(), throwsA(isA())); + }); + + test('M extension works when present', () async { + final mod = _MulWithExtModule(); + await mod.build(); + expect(mod.generateAssembly(), contains('mul')); + }); + }); + + group('Section emission', () { + test('emitToSection produces correct section', () async { + final mod = AddModule(DataField.from(1), DataField.from(2)); + await mod.build(); + final section = mod.emitToSection(); + expect(section.name, '.text'); + expect(section.size, 12); + expect(section.type, SectionType.text); + }); + + test('labels become symbols in section', () async { + final mod = _BranchModule(); + await mod.build(); + final section = mod.emitToSection(); + expect(section.symbols.containsKey('end'), true); + }); + }); + + group('Linker integration', () { + test('link code and data sections', () async { + final code = AddModule(DataField.from(1), DataField.from(2)); + await code.build(); + final textSection = code.emitToSection(); + + final data = Section('.data', type: SectionType.data); + data.addSymbol('magic'); + data.emitWord(0xDEADBEEF); + + final linker = Linker(); + linker.addSection(textSection); + linker.addSection(data); + + final binary = linker.link( + script: LinkerScript( + entryPoint: 0x80000000, + memory: [ + MemoryRegion(name: 'rom', origin: 0x80000000, length: 0x1000), + ], + ), + ); + + expect(binary.entryPoint, 0x80000000); + expect(binary.symbolTable['magic'], 0x8000000C); + expect(binary.bytes.length, 16); + }); + }); + + group('Binary encoding', () { + test('addi encodes correctly', () async { + final mod = _AddiModule(); + await mod.build(); + final binary = mod.generateBinary(); + // addi x4, x0, 5 → 0x00500213 + // Check it's 4 bytes (one instruction: li 5 = addi x4, x0, 5) + // Plus the addi x5, x4, 10 + expect(binary.length, 8); + }); + + test('binary round-trips through emulator decode', () async { + final mod = AddModule(DataField.from(3), DataField.from(4)); + await mod.build(); + final binary = mod.generateBinary(); + expect(binary.length, 12); + // First instruction: addi rd, x0, 3 + final instr0 = + binary[0] | (binary[1] << 8) | (binary[2] << 16) | (binary[3] << 24); + expect(instr0 & 0x7F, 0x13); // OP-IMM opcode + }); + }); + + group('ELF output', () { + test('produces valid ELF from module', () async { + final mod = AddModule(DataField.from(1), DataField.from(2)); + await mod.build(); + + final section = mod.emitToSection(); + final writer = ElfWriter(entryPoint: 0x80000000); + writer.addSection(section, address: 0x80000000); + final elf = writer.write(); + + expect(elf[0], 0x7F); + expect(elf[1], 0x45); + expect(elf[2], 0x4C); + expect(elf[3], 0x46); + }); + }); + + group('Control flow', () { + test('loop with labels and branches', () async { + final mod = _LoopModule(); + await mod.build(); + final asm = mod.generateAssembly(); + expect(asm, contains('top:')); + expect(asm, contains('beq')); + expect(asm, contains('sw')); + expect(asm, contains('jal')); + expect(asm, contains('end:')); + }); + }); + + group('Pseudo-instructions', () { + test('mv generates addi', () async { + final mod = _MvModule(); + await mod.build(); + expect(mod.generateAssembly(), contains('addi')); + }); + + test('nop generates addi x0', () async { + final mod = _NopModule(); + await mod.build(); + expect(mod.generateAssembly(), contains('addi')); + }); + + test('li zero-extends a bit-31 address on RV64', () async { + // 0x8000_0000 must materialize as the positive address, not the + // lui-sign-extended 0xFFFFFFFF_80000000 (which the bus decoder misses + // and the core then wedges on). The fix appends slli/srli to zero-extend. + final mod = _LiAddrModule(RiscVMxlen.rv64, 0x80000000); + await mod.build(); + final asm = mod.generateAssembly(); + expect(asm, contains('slli')); + expect(asm, contains('srli')); + }); - setUp(myModule.build); + test('li does not zero-extend a sub-2GB address on RV64', () async { + // 0x1000_0000 has bit 31 clear, so lui does not sign-extend: no fixup. + final mod = _LiAddrModule(RiscVMxlen.rv64, 0x10000000); + await mod.build(); + final asm = mod.generateAssembly(); + expect(asm, isNot(contains('slli'))); + }); - test('Generated Assembly', () { - expect("""addi x4, x0, 1 -addi x5, x0, 2 -add x6, x5, x4 -""", myModule.generateAssembly()); + test('li does not over-extend on RV32', () async { + // RV32 has no upper half to corrupt, so no slli/srli fixup is emitted. + final mod = _LiAddrModule(RiscVMxlen.rv32, 0x80000000); + await mod.build(); + final asm = mod.generateAssembly(); + expect(asm, isNot(contains('slli'))); }); }); } + +class _LiAddrModule extends Module { + @override + final RiscVIsaConfig isa; + _LiAddrModule(RiscVMxlen mxlen, int imm) + : isa = RiscVIsaConfig( + mxlen: mxlen, + extensions: mxlen == RiscVMxlen.rv64 ? [rv64i, rv32i] : [rv32i], + ), + super() { + register(Register.x10).bind(li(imm)); + } +} + +class _SubModule extends Module { + @override + final isa = RiscVIsaConfig(mxlen: RiscVMxlen.rv32, extensions: [rv32i]); + _SubModule() : super() { + final a = addInput('a', DataField.from(10)); + final b = addInput('b', DataField.from(3)); + addOutput('c', type: DataType.i32, source: DataLocation.register); + output('c').bind(a - b); + } +} + +class _BitwiseModule extends Module { + @override + final isa = RiscVIsaConfig(mxlen: RiscVMxlen.rv32, extensions: [rv32i]); + _BitwiseModule() : super() { + final a = addInput('a', DataField.from(0xFF)); + final b = addInput('b', DataField.from(0x0F)); + addOutput('or_out', type: DataType.i32, source: DataLocation.register); + addOutput('and_out', type: DataType.i32, source: DataLocation.register); + addOutput('xor_out', type: DataType.i32, source: DataLocation.register); + output('or_out').bind(a | b); + output('and_out').bind(a & b); + output('xor_out').bind(a ^ b); + } +} + +class _AddiModule extends Module { + @override + final isa = RiscVIsaConfig(mxlen: RiscVMxlen.rv32, extensions: [rv32i]); + _AddiModule() : super() { + final a = addInput('a', DataField.from(5)); + addOutput('b', type: DataType.i32, source: DataLocation.register); + output('b').bind(addi(a, 10)); + } +} + +class _LiModule extends Module { + @override + final isa = RiscVIsaConfig(mxlen: RiscVMxlen.rv32, extensions: [rv32i]); + _LiModule(int value) : super() { + addOutput('v', type: DataType.i32, source: DataLocation.register); + output('v').bind(li(value)); + } +} + +class _BranchModule extends Module { + @override + final isa = RiscVIsaConfig(mxlen: RiscVMxlen.rv32, extensions: [rv32i]); + _BranchModule() : super() { + final a = addInput('a', DataField(DataType.i32)); + final b = addInput('b', DataField(DataType.i32)); + addOutput('result', type: DataType.i32, source: DataLocation.register); + final end = Label('end'); + beq(a, b, end); + final result = addi(a, 1); + placeLabel(end); + output('result').bind(result); + } +} + +class _MultiBranchModule extends Module { + @override + final isa = RiscVIsaConfig(mxlen: RiscVMxlen.rv32, extensions: [rv32i]); + _MultiBranchModule() : super() { + final a = addInput('a', DataField(DataType.i32)); + final b = addInput('b', DataField(DataType.i32)); + addOutput('result', type: DataType.i32, source: DataLocation.register); + final skip1 = Label('skip1'); + final skip2 = Label('skip2'); + bne(a, b, skip1); + blt(a, b, skip2); + placeLabel(skip1); + placeLabel(skip2); + output('result').bind(addi(a, 0)); + } +} + +class _LoadModule extends Module { + @override + final isa = RiscVIsaConfig(mxlen: RiscVMxlen.rv32, extensions: [rv32i]); + _LoadModule() : super() { + final base = addInput('base', DataField.from(0x1000)); + addOutput('value', type: DataType.i32, source: DataLocation.register); + output('value').bind(lw(base, offset: 4)); + } +} + +class _StoreModule extends Module { + @override + final isa = RiscVIsaConfig(mxlen: RiscVMxlen.rv32, extensions: [rv32i]); + _StoreModule() : super() { + final base = addInput('base', DataField.from(0x1000)); + final value = addInput('value', DataField.from(42)); + sw(base, value, offset: 8); + } +} + +class _MulModule extends Module { + @override + final isa = RiscVIsaConfig(mxlen: RiscVMxlen.rv32, extensions: [rv32i]); + _MulModule() : super() { + final a = addInput('a', DataField(DataType.i32)); + final b = addInput('b', DataField(DataType.i32)); + addOutput('c', type: DataType.i32, source: DataLocation.register); + output('c').bind(mul(a, b)); + } +} + +class _LoopModule extends Module { + @override + final isa = RiscVIsaConfig(mxlen: RiscVMxlen.rv32, extensions: [rv32i]); + _LoopModule() : super() { + final base = addInput('base', DataField.from(0x1000)); + final value = addInput('value', DataField.from(42)); + + final top = Label('top'); + final end = Label('end'); + placeLabel(top); + beq(value, zero, end); + sw(base, value, offset: 0); // side-effect: survives DCE + jal(top); + placeLabel(end); + } +} + +class _MvModule extends Module { + @override + final isa = RiscVIsaConfig(mxlen: RiscVMxlen.rv32, extensions: [rv32i]); + _MvModule() : super() { + final a = addInput('a', DataField.from(42)); + addOutput('b', type: DataType.i32, source: DataLocation.register); + output('b').bind(mv(a)); + } +} + +class _NopModule extends Module { + @override + final isa = RiscVIsaConfig(mxlen: RiscVMxlen.rv32, extensions: [rv32i]); + _NopModule() : super() { + nop(); + addOutput('x', type: DataType.i32, source: DataLocation.register); + output('x').bind(li(0)); + } +} + +class _MulWithExtModule extends Module { + @override + final isa = RiscVIsaConfig(mxlen: RiscVMxlen.rv32, extensions: [rv32i, rvM]); + _MulWithExtModule() : super() { + final a = addInput('a', DataField.from(6)); + final b = addInput('b', DataField.from(7)); + addOutput('c', type: DataType.i32, source: DataLocation.register); + output('c').bind(mul(a, b)); + } +} diff --git a/packages/river_emulator/analysis_options.yaml b/packages/river_emulator/analysis_options.yaml index dee8927..f5d48c9 100644 --- a/packages/river_emulator/analysis_options.yaml +++ b/packages/river_emulator/analysis_options.yaml @@ -1,30 +1,2 @@ -# This file configures the static analysis results for your project (errors, -# warnings, and lints). -# -# This enables the 'recommended' set of lints from `package:lints`. -# This set helps identify many issues that may lead to problems when running -# or consuming Dart code, and enforces writing Dart using a single, idiomatic -# style and format. -# -# If you want a smaller set of lints you can change this to specify -# 'package:lints/core.yaml'. These are just the most critical lints -# (the recommended set includes the core lints). -# The core lints are also what is used by pub.dev for scoring packages. - -include: package:lints/recommended.yaml - -# Uncomment the following section to specify additional rules. - -# linter: -# rules: -# - camel_case_types - -# analyzer: -# exclude: -# - path/to/excluded/files/** - -# For more information about the core and recommended set of lints, see -# https://dart.dev/go/core-lints - -# For additional information about configuring this file, see -# https://dart.dev/guides/language/analysis-options +# Inherits the workspace production analysis baseline. +include: ../../analysis_options.yaml diff --git a/packages/river_emulator/bin/river_emulator.dart b/packages/river_emulator/bin/river_emulator.dart index d326ee4..2475a93 100644 --- a/packages/river_emulator/bin/river_emulator.dart +++ b/packages/river_emulator/bin/river_emulator.dart @@ -1,5 +1,5 @@ -import 'dart:io' show Platform, File; -import 'dart:typed_data'; +import 'dart:async' show unawaited; +import 'dart:io' show Platform, File, stdout; import 'package:args/args.dart'; import 'package:bintools/bintools.dart'; @@ -7,216 +7,330 @@ import 'package:path/path.dart' as path; import 'package:river/river.dart'; import 'package:river_emulator/river_emulator.dart'; -Future _loadTextSegment( - CacheEmulator cache, - int addr, - Uint8List data, -) async { - var i = 0; - while (i < data.length) { - final firstHalfword = data[i] | (data[i + 1] << 8); - if ((firstHalfword & 0x3) != 0x3) { - await cache.write(addr + i, firstHalfword, 2); - i += 2; - } else { - final halfword = - firstHalfword | (data[i + 2] << 16) | (data[i + 3] << 24); - await cache.write(addr + i, halfword, 4); - i += 4; - } - } -} - -Future _loadDataSegment( - CacheEmulator cache, - int addr, - Uint8List data, -) async { - for (var i = 0; i < data.length; i++) { - await cache.write(addr + i, data[i], 1); - } -} - Future main(List arguments) async { - var parser = ArgParser(); - parser.addOption( - 'soc', - help: 'Sets the SoC to emulate', - allowed: RiverSoCChoice.values.map((v) => v.name).toList(), - ); - - parser.addMultiOption( - 'soc-option', - help: 'Adds an option when configuring the SoC', - splitCommas: false, - ); - - parser.addOption( - 'platform', - help: 'Sets the platform to emulate', - allowed: RiverPlatformChoice.values.map((v) => v.name).toList(), - ); - - parser.addMultiOption( - 'device-option', - help: 'Adds an option when configuring a device', - splitCommas: false, - ); - - parser.addOption( - 'maskrom-path', - help: 'Path to the binary to load into the maskrom', - ); - - parser.addFlag('help', help: 'Prints the usage'); + final parser = ArgParser() + ..addMultiOption( + 'core', + abbr: 'c', + help: 'Core model', + defaultsTo: ['rc1-mi'], + allowed: ['rc1-n', 'rc1-mi', 'rc1-s', 'rc1-m'], + ) + ..addMultiOption( + 'memory', + abbr: 'm', + help: 'Memory region (name:addr:size:type)', + ) + ..addMultiOption( + 'device', + abbr: 'd', + help: 'Peripheral device (name:type:addr[:compat])', + ) + ..addOption( + 'clock-freq', + help: 'System clock frequency (Hz)', + defaultsTo: '48000000', + ) + ..addMultiOption( + 'device-option', + help: 'Device option (device.key=value)', + splitCommas: false, + ) + ..addOption( + 'maskrom-path', + help: 'Path to the binary to load into the maskrom (L1 cache)', + ) + ..addOption( + 'firmware', + help: 'Path to an ELF to load into memory (e.g. OpenSBI fw_jump.elf)', + ) + ..addOption( + 'payload', + help: + 'Path to an ELF to load into memory after firmware (e.g. Linux kernel)', + ) + ..addOption( + 'max-cycles', + help: 'Stop after this many cycles (0 = run forever)', + defaultsTo: '0', + ) + ..addFlag( + 'remote-bitbang', + help: 'Expose core 0 over an OpenOCD remote_bitbang JTAG debug server', + ) + ..addOption( + 'remote-bitbang-port', + help: 'TCP port for the remote_bitbang debug server', + defaultsTo: '${RemoteBitbangServer.defaultPort}', + ) + ..addFlag( + 'start-halted', + help: + 'Start the hart halted (waiting for the debugger) instead of ' + 'free-running from reset. Use with --remote-bitbang so a debugger ' + 'or Heimdall can attach before the core runs.', + ) + ..addFlag('help', abbr: 'h', help: 'Prints usage'); final args = parser.parse(arguments); if (args.flag('help')) { - print('Usage: ${path.basename(Platform.script.toFilePath())}'); + print('Usage: ${path.basename(Platform.script.toFilePath())} [options]'); + print(''); + print('River SoC emulator'); print(''); print('Options:'); print(parser.usage); return; } - RiverPlatformChoice? platformChoice; - RiverSoCChoice? socChoice; - - if (args.option('platform') == null && args.option('soc') == null) { - print('Missing platform or soc option'); - return; - } else if (args.option('platform') != null && args.option('soc') == null) { - platformChoice = RiverPlatformChoice.getChoice(args.option('platform')!); + final clockFreq = int.parse(args.option('clock-freq')!); + final sysclk = HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(clockFreq), + ); - if (platformChoice == null) { - print('Invalid argument for platform option'); - return; + final coreModels = { + 'rc1-n': RiverCoreConfigV1.nano, + 'rc1-mi': RiverCoreConfigV1.micro, + 'rc1-s': RiverCoreConfigV1.small, + 'rc1-m': RiverCoreConfigV1.macro, + }; + + // Parse memory regions: name:addr:size:type + final memories = args.multiOption('memory').map((spec) { + final parts = spec.split(':'); + if (parts.length < 4) { + throw FormatException('Memory format: name:addr:size:type, got: $spec'); } + return RiverDevice( + name: parts[0], + compatible: 'river,${parts[3]}', + range: BusAddressRange(int.parse(parts[1]), _parseSize(parts[2])), + ); + }).toList(); + + // Parse devices: name:type:addr[:compat] + final devices = args.multiOption('device').map((spec) { + final parts = spec.split(':'); + if (parts.length < 3) { + throw FormatException( + 'Device format: name:type:addr[:compat], got: $spec', + ); + } + final type = parts[1]; + final defaultCompat = { + 'uart': 'ns16550a', + 'clint': 'riscv,clint0', + 'plic': 'riscv,plic0', + }; + final defaultSizes = {'clint': 0x10000, 'plic': 0x4000000, 'uart': 0x8}; + return RiverDevice( + name: parts[0], + compatible: parts.length > 3 + ? parts[3] + : (defaultCompat[type] ?? 'river,$type'), + range: BusAddressRange(int.parse(parts[2]), defaultSizes[type] ?? 0x1000), + ); + }).toList(); + + // Determine mxlen from first core + final firstCoreModel = args.multiOption('core').first; + final mxlen = (firstCoreModel == 'rc1-n' || firstCoreModel == 'rc1-mi') + ? RiscVMxlen.rv32 + : RiscVMxlen.rv64; + + final mmu = HarborMmuConfig( + mxlen: mxlen, + pagingModes: mxlen == RiscVMxlen.rv64 + ? const [RiscVPagingMode.bare, RiscVPagingMode.sv39] + : const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ); - socChoice = platformChoice!.soc; - } else if (args.option('platform') == null && args.option('soc') != null) { - socChoice = RiverSoCChoice.getChoice(args.option('soc')!); + final resetVector = memories.isNotEmpty ? memories.first.range!.start : 0; + + final cores = args.multiOption('core').map((coreModel) { + final factory = coreModels[coreModel]; + if (factory == null) throw ArgumentError('Unknown core model: $coreModel'); + return factory( + mmu: mmu, + interrupts: [], + clock: sysclk, + resetVector: resetVector, + ); + }).toList(); + + final socConfig = RiverSoCConfig( + devices: [...memories, ...devices], + cores: cores, + busConfig: WishboneConfig( + addressWidth: mxlen.size, + dataWidth: mxlen.size, + selWidth: mxlen.size ~/ 8, + ), + ); - if (socChoice == null) { - print('Invalid argument for soc option'); - return Future.value(); + // Parse device options: device.key=value + final deviceOptions = >{}; + for (final option in args.multiOption('device-option')) { + final dot = option.indexOf('.'); + if (dot < 0) { + throw FormatException( + 'Device option format: device.key=value, got: $option', + ); } - } else { - platformChoice = RiverPlatformChoice.getChoice(args.option('platform')!); - socChoice = RiverSoCChoice.getChoice(args.option('soc')!); - - if (platformChoice?.soc != socChoice) { - print( - "Platform's SoC and the value given for \"--soc\" do not align, unable to handle...", + final devName = option.substring(0, dot); + final rest = option.substring(dot + 1); + final eq = rest.indexOf('='); + if (eq < 0) { + throw FormatException( + 'Device option format: device.key=value, got: $option', ); - return Future.value(); } + deviceOptions.putIfAbsent(devName, () => {})[rest.substring(0, eq)] = rest + .substring(eq + 1); } - if (platformChoice == null) { - print('Platform is not set, unable to handle...'); - return; - } - - final platform = platformChoice ?? (throw 'Bad state, platform is not set'); - final soc = socChoice ?? (throw 'Bad state, soc is not set'); - - final socConfig = - soc.configure({ - ...Map.fromEntries( - args.multiOption('soc-option').map((entry) { - final i = entry.indexOf('='); - assert(i > 0); - return MapEntry(entry.substring(0, i), entry.substring(i + 1)); - }), - ), - 'platform': platform.name, - }) ?? - (throw 'Invalid platform configuration'); - final emulator = RiverEmulator( - soc: RiverSoCEmulator( - socConfig, - deviceOptions: Map.fromEntries( - args - .multiOption('device-option') - .map((option) { - final i = option.indexOf('.'); - assert(i > 0); - return option.substring(0, i); - }) - .map( - (key) => MapEntry( - key, - Map.fromEntries( - args - .multiOption('device-option') - .where((option) { - final i = option.indexOf('.'); - assert(i > 0); - return option.substring(0, i) == key; - }) - .map((option) { - final i = option.indexOf('.'); - assert(i > 0); - - final entry = option.substring(i + 1); - - final x = entry.indexOf('='); - assert(x > 0); - - return MapEntry( - entry.substring(0, x), - entry.substring(x + 1), - ); - }), - ), - ), - ), - ), - ), + soc: RiverSoC(socConfig, deviceOptions: deviceOptions), ); emulator.reset(); final maskromPath = args.option('maskrom-path'); - if (maskromPath != null && emulator.soc.cores[0].l1i != null) { - final resetVector = emulator.soc.cores[0].config.resetVector; - final l1i = emulator.soc.cores[0].l1i!; - final l1d = emulator.soc.cores[0].l1d; + if (maskromPath != null) { final maskrom = Elf.load(File(maskromPath).readAsBytesSync()); + await emulator.soc.loadMaskrom(maskrom); - final loadSegments = maskrom.programHeaders.where((ph) => ph.type == 1); - - for (final ph in loadSegments) { - final segBytes = maskrom.segmentData(ph); - final vaddr = ph.vAddr; - - if ((ph.flags & 0x1) != 0) { - await _loadTextSegment(l1i, vaddr, segBytes); - } else if (l1d != null && segBytes.isNotEmpty) { - await _loadDataSegment(l1d!, vaddr, segBytes); - } - } - - if (maskrom.header.entry != resetVector) { + final coreResetVector = emulator.soc.cores[0].config.resetVector; + if (maskrom.header.entry != coreResetVector) { print( - "WARNING: ELF entry is 0x${maskrom.header.entry.toRadixString(16)}, " - "but core reset vector is 0x${resetVector.toRadixString(16)}", + 'WARNING: ELF entry is 0x${maskrom.header.entry.toRadixString(16)}, ' + 'but core reset vector is 0x${coreResetVector.toRadixString(16)}', ); } - } else if (maskromPath == null && emulator.soc.cores[0].l1i != null) { + } else if (emulator.soc.cores[0].l1i != null) { print('Maskrom binary is required'); return; - } else if (maskromPath != null && emulator.soc.cores[0].l1i == null) { - print('Cannot load maskrom due to L1i not existing'); - return; + } + + final firmwarePath = args.option('firmware'); + if (firmwarePath != null) { + final fw = Elf.load(File(firmwarePath).readAsBytesSync()); + emulator.soc.loadElf(fw); + print( + 'Loaded firmware: ${fw.programHeaders.where((ph) => ph.type == 1).length} segments, ' + 'entry 0x${fw.header.entry.toRadixString(16)}', + ); + } + + final payloadPath = args.option('payload'); + if (payloadPath != null) { + final payload = Elf.load(File(payloadPath).readAsBytesSync()); + emulator.soc.loadElf(payload); + print( + 'Loaded payload: ${payload.programHeaders.where((ph) => ph.type == 1).length} segments, ' + 'entry 0x${payload.header.entry.toRadixString(16)}', + ); + } + + final maxCycles = int.parse(args.option('max-cycles')!); + + // Optional JTAG debug server: lets OpenOCD / Heimdall halt and inspect core 0 + // over the OpenOCD remote_bitbang protocol, the same path used for the HDL + // sim and silicon. + RiverDebugTarget? debug; + if (args.flag('remote-bitbang')) { + final port = int.parse(args.option('remote-bitbang-port')!); + debug = RiverDebugTarget(emulator.soc.cores[0]); + final server = RemoteBitbangServer( + SoftJtagDtm(SoftDebugModule(debug)), + port: port, + ); + await server.bind(); + unawaited(server.serve()); + // With --start-halted the hart waits for the debugger instead of + // free-running from the reset vector into a fault before the (slow) examine + // connects. This makes the emulator a stable DUT for Heimdall (load/run via + // JTAG), matching how a real debug target comes up with a pending halt. + if (args.flag('start-halted')) { + debug.requestHalt(); + debug.dpc = resetVector; + } + print('remote_bitbang debug server listening on port ${server.boundPort}'); } Map pcs = {}; - while (true) { - pcs = await emulator.soc.run(pcs); + var cycle = 0; + final dbgHartId = debug != null ? emulator.soc.cores[0].config.hartId : 0; + var prevHalted = debug?.halted ?? false; + // Instructions retired since we last handed control back to the event loop. + // soc.run's awaits all complete in-memory (no real I/O), so without an + // explicit yield the Dart scheduler keeps draining microtasks and never + // services the JTAG remote_bitbang socket. A loaded program that runs without + // faulting then starves the socket: the debugger's halt request sits unread + // and the rig wedges until the RPC times out. Pump the event loop every so + // often so an incoming halt is seen promptly while staying fast otherwise. + var sinceYield = 0; + const yieldEvery = 256; + while (maxCycles == 0 || cycle < maxCycles) { + final nowHalted = debug != null && debug.halted; + // On a halt/resume edge, sync dpc with the run loop's per-core PC: save the + // hart's PC into dpc when it stops, and resume from dpc (which the debugger + // may have rewritten, e.g. the fuzzer setting each program's entry). + if (debug != null && nowHalted != prevHalted) { + if (nowHalted) { + debug.dpc = pcs[dbgHartId] ?? resetVector; + } else { + pcs[dbgHartId] = debug.dpc; + } + prevHalted = nowHalted; + } + // While the debugger holds the hart halted, idle instead of retiring. + if (nowHalted) { + await Future.delayed(const Duration(milliseconds: 5)); + continue; + } + if (debug != null) { + // A debug target must not crash the process when the running program + // faults (e.g. a random fuzz program that double-faults with mtvec=0). + // Halt so the debugger / Heimdall observes the faulted state and can load + // the next program, the way real silicon stays alive under the debugger. + try { + pcs = await emulator.soc.run(pcs); + } catch (e) { + debug.requestHalt(); + print('hart faulted, halting for debugger: $e'); + } + // Yield to the event loop periodically so the JTAG socket is serviced + // even while a program runs straight-line without faulting; otherwise an + // incoming halt request is never read and the debug session wedges. + if (++sinceYield >= yieldEvery) { + sinceYield = 0; + await Future.delayed(Duration.zero); + } + } else { + pcs = await emulator.soc.run(pcs); + } + cycle++; + } + + // Let any in-flight UART transmits drain, then flush stdout so output is + // not lost when we exit. + await Future.delayed(const Duration(milliseconds: 50)); + await stdout.flush(); +} + +int _parseSize(String s) { + final upper = s.toUpperCase(); + if (upper.endsWith('M')) { + return int.parse(upper.substring(0, upper.length - 1)) * 1024 * 1024; + } + if (upper.endsWith('K')) { + return int.parse(upper.substring(0, upper.length - 1)) * 1024; } + return int.parse(s); } diff --git a/packages/river_emulator/lib/river_emulator.dart b/packages/river_emulator/lib/river_emulator.dart index 71317cd..e33ce23 100644 --- a/packages/river_emulator/lib/river_emulator.dart +++ b/packages/river_emulator/lib/river_emulator.dart @@ -3,9 +3,18 @@ library; export 'src/cache.dart'; export 'src/core.dart'; export 'src/csr.dart'; +export 'src/debug/debug_module.dart'; +export 'src/debug/jtag_dtm.dart'; +export 'src/debug/remote_bitbang.dart'; export 'src/dev.dart'; export 'src/devices.dart'; export 'src/int.dart'; export 'src/mmu.dart'; +export 'src/tlb.dart'; +export 'src/pipeline.dart'; +export 'src/plugins/cache_plugin.dart'; +export 'src/plugins/csr_plugin.dart'; +export 'src/plugins/mmu_plugin.dart'; +export 'src/plugins/trap_plugin.dart'; export 'src/river_emulator_base.dart'; export 'src/soc.dart'; diff --git a/packages/river_emulator/lib/src/cache.dart b/packages/river_emulator/lib/src/cache.dart index c3bdfe3..8e32f1c 100644 --- a/packages/river_emulator/lib/src/cache.dart +++ b/packages/river_emulator/lib/src/cache.dart @@ -3,42 +3,43 @@ import 'package:river/river.dart'; typedef CacheFill = Future> Function(int addr, int size); typedef CacheWriteback = Future Function(int addr, int value, int size); -class CacheLineEmulator { +class CacheLine { final List data; int tag; int lru; bool valid; + bool locked; - CacheLineEmulator({ + CacheLine({ required this.data, required this.tag, this.lru = 0, this.valid = true, + this.locked = false, }); @override String toString() => - 'CacheLineEmulator(tag: $tag, data: $data, lru: $lru, valid: $bool)'; + 'CacheLine(tag: $tag, lru: $lru, valid: $valid, locked: $locked)'; } -class CacheEmulator { - final Cache config; +class Cache { + final HarborCacheConfig config; final CacheFill fill; final CacheWriteback writeback; - final Map> _lines; + final Map> _lines; int get _sets => (config.size ~/ config.lineSize) ~/ config.ways; - CacheEmulator(Cache config, {required this.fill, required this.writeback}) - : this.config = config, - _lines = Map.fromEntries( + Cache(this.config, {required this.fill, required this.writeback}) + : _lines = Map.fromEntries( List.generate( (config.size ~/ config.lineSize) ~/ config.ways, (i) => MapEntry( i, List.generate( config.ways, - (_) => CacheLineEmulator( + (_) => CacheLine( tag: 0, data: List.filled(config.lineSize, 0), valid: false, @@ -48,13 +49,15 @@ class CacheEmulator { ), ); - int _setIndex(int addr) => (addr ~/ config.lineSize) % _sets; + int _unsigned(int addr) => addr & 0xFFFFFFFF; - int _tag(int addr) => addr ~/ config.lineSize ~/ _sets; + int _setIndex(int addr) => (_unsigned(addr) ~/ config.lineSize) % _sets; - int _offset(int addr) => addr % config.lineSize; + int _tag(int addr) => _unsigned(addr) ~/ config.lineSize ~/ _sets; - CacheLineEmulator? _findLine(int addr) { + int _offset(int addr) => _unsigned(addr) % config.lineSize; + + CacheLine? _findLine(int addr) { final set = _lines[_setIndex(addr)]!; final t = _tag(addr); @@ -67,12 +70,16 @@ class CacheEmulator { return null; } - CacheLineEmulator _allocateLine(int addr) { + CacheLine _allocateLine(int addr) { final set = _lines[_setIndex(addr)]!; final t = _tag(addr); - set.sort((a, b) => a.lru.compareTo(b.lru)); - final victim = set.last; + final candidates = set.where((l) => !l.locked).toList(); + if (candidates.isEmpty) { + throw StateError('All cache lines in set ${_setIndex(addr)} are locked'); + } + candidates.sort((a, b) => a.lru.compareTo(b.lru)); + final victim = candidates.last; victim.tag = t; victim.valid = true; @@ -81,7 +88,7 @@ class CacheEmulator { return victim; } - void _markUsed(CacheLineEmulator line) { + void _markUsed(CacheLine line) { final set = _lines.values.firstWhere((s) => s.contains(line)); for (final l in set) { l.lru++; @@ -90,15 +97,39 @@ class CacheEmulator { } void reset() { + for (final set in _lines.values) { + for (final line in set) { + if (!line.locked) { + line.valid = false; + } + line.lru = 0; + } + } + } + + void fullReset() { for (final set in _lines.values) { for (final line in set) { line.valid = false; + line.locked = false; line.lru = 0; } } } Future? read(int addr, int size) async { + // A read straddling a cache-line boundary (e.g. a 4-byte fetch split 2/2 + // across lines with RVC-aligned code) would index past this line's data. + // Split into per-byte reads so each resolves against the correct line. + if (_offset(addr) + size > config.lineSize) { + int value = 0; + for (int i = 0; i < size; i++) { + final byte = (await read(addr + i, 1)) ?? 0; + value |= (byte & 0xFF) << (8 * i); + } + return value; + } + final line = _findLine(addr); if (line != null) { _markUsed(line); @@ -138,7 +169,7 @@ class CacheEmulator { return; } - CacheLineEmulator? line = _findLine(addr); + CacheLine? line = _findLine(addr); if (line == null) { line = _allocateLine(addr); @@ -156,18 +187,54 @@ class CacheEmulator { _markUsed(line); - await writeback(addr, value, size); + if (!line.locked) { + await writeback(addr, value, size); + } } bool invalidate(int addr) { final line = _findLine(addr); - if (line != null) { + if (line != null && !line.locked) { line.valid = false; return true; } return false; } + CacheLine? findLockedLine(int addr) { + final line = _findLine(addr); + if (line != null && line.locked) return line; + return null; + } + + void lockRange(int addr, int size) { + addr = _unsigned(addr); + final end = addr + size; + for (var a = addr; a < end; a += config.lineSize) { + var line = _findLine(a); + if (line == null) { + line = _allocateLine(a); + line.data.fillRange(0, config.lineSize, 0); + } + line.locked = true; + } + } + + void unlockRange(int addr, int size) { + for (var a = addr; a < addr + size; a += config.lineSize) { + final line = _findLine(a); + if (line != null) line.locked = false; + } + } + + void unlockAll() { + for (final set in _lines.values) { + for (final line in set) { + line.locked = false; + } + } + } + @override - String toString() => 'CacheEmulator($config)'; + String toString() => 'Cache($config)'; } diff --git a/packages/river_emulator/lib/src/core.dart b/packages/river_emulator/lib/src/core.dart index a0edb70..f4da6d5 100644 --- a/packages/river_emulator/lib/src/core.dart +++ b/packages/river_emulator/lib/src/core.dart @@ -1,25 +1,94 @@ import 'dart:collection'; -import 'package:riscv/riscv.dart'; -import 'package:river/river.dart'; +import 'dart:math' as math; +import 'dart:typed_data'; +import 'package:river/river.dart' hide InterruptController; import 'cache.dart'; import 'csr.dart'; +import 'decoded_instruction.dart'; import 'dev.dart'; import 'mmu.dart'; import 'int.dart'; +import 'pipeline.dart'; +import 'plugins/csr_plugin.dart'; +import 'plugins/mmu_plugin.dart'; +import 'plugins/cache_plugin.dart'; +import 'plugins/trap_plugin.dart'; + +// IEEE-754 bit<->double conversions (little-endian), shared by scalar and +// vector FP. SEW selects half (16, Zvfh) / single (32) / double (64). +double fpBitsToDouble(int bits, int sewBits) { + if (sewBits == 16) return _halfBitsToDouble(bits & 0xFFFF); + final bd = ByteData(8); + if (sewBits >= 64) { + bd.setUint64(0, bits, Endian.little); + return bd.getFloat64(0, Endian.little); + } + bd.setUint32(0, bits & 0xFFFFFFFF, Endian.little); + return bd.getFloat32(0, Endian.little); +} + +int fpDoubleToBits(double v, int sewBits) { + final bd = ByteData(8); + if (sewBits == 16) { + bd.setFloat32(0, v, Endian.little); + return _f32BitsToHalf(bd.getUint32(0, Endian.little)); + } + if (sewBits >= 64) { + bd.setFloat64(0, v, Endian.little); + return bd.getUint64(0, Endian.little); + } + bd.setFloat32(0, v, Endian.little); + return bd.getUint32(0, Endian.little); +} + +// IEEE-754 half (Zvfh): 1 sign / 5 exp / 10 mantissa. half->double is exact. +double _halfBitsToDouble(int h) { + final sign = (h >> 15) & 1; + final e = (h >> 10) & 0x1F; + final mant = h & 0x3FF; + double v; + if (e == 0) { + v = mant * math.pow(2, -24).toDouble(); // subnormal + } else if (e == 0x1F) { + v = mant == 0 ? double.infinity : double.nan; + } else { + v = (1 + mant / 1024.0) * math.pow(2, e - 15).toDouble(); + } + return sign == 1 ? -v : v; +} + +// float32 bits -> half bits, round-to-nearest-even. +int _f32BitsToHalf(int f) { + final sign = (f >> 16) & 0x8000; + final e = (f >> 23) & 0xFF; + final mant = f & 0x7FFFFF; + if (e == 0xFF) return sign | 0x7C00 | (mant != 0 ? 0x200 : 0); // inf/NaN + final exp = e - 127 + 15; + if (exp >= 0x1F) return sign | 0x7C00; // overflow -> inf + if (exp <= 0) { + if (exp < -10) return sign; // underflow -> +/-0 + final m = mant | 0x800000; + final shift = 14 - exp; + var h = m >> shift; + final round = (m >> (shift - 1)) & 1; + final sticky = (m & ((1 << (shift - 1)) - 1)) != 0; + if (round == 1 && (sticky || (h & 1) == 1)) h++; + return sign | h; + } + final h = mant >> 13; + final round = (mant >> 12) & 1; + final sticky = (mant & 0xFFF) != 0; + var out = (exp << 10) | h; + if (round == 1 && (sticky || (h & 1) == 1)) out++; // carry into exp is ok + return sign | out; +} class AbortException extends TrapException { final String message; - const AbortException( - super.trap, - this.message, [ - super.tval = null, - super.stack = null, - ]); - const AbortException.illegalInstruction( - this.message, [ - StackTrace? stack = null, - ]) : super(Trap.illegal, null, stack); + const AbortException(super.trap, this.message, [super.tval, super.stack]); + const AbortException.illegalInstruction(this.message, [StackTrace? stack]) + : super(Trap.illegal, null, stack); @override String toString() => 'AbortException($trap, "$message", $tval, $stack)'; @@ -29,8 +98,8 @@ class TrapException implements Exception { final Trap trap; final StackTrace? stack; - const TrapException(this.trap, [this.tval = null, this.stack = null]); - const TrapException.illegalInstruction([this.stack = null]) + const TrapException(this.trap, [this.tval, this.stack]); + const TrapException.illegalInstruction([this.stack]) : trap = Trap.illegal, tval = null; @@ -48,101 +117,92 @@ class TrapException implements Exception { @override String toString() => - 'TrapException($trap, ${tval != null ? '0x' + tval!.toRadixString(16) : null}, $stack)'; + 'TrapException($trap, ${tval != null ? '0x${tval!.toRadixString(16)}' : null}, $stack)'; } -class RiverCoreEmulatorState { +class RiverCoreState { int pc; int? _rs1; int? _rs2; + int? _rs3; int? _rd; int? _imm; - InstructionType ir; + DecodedInstruction ir; - RiverCoreEmulatorState(this.pc, this.ir, this.sp) : alu = 0; + RiverCoreState(this.pc, this.ir, this.sp) : alu = 0; int alu; int sp; - int get rs1 => _rs1 ?? ir.toMap()['rs1'] ?? 0; - int get rs2 => _rs2 ?? ir.toMap()['rs2'] ?? 0; - int get rd => _rd ?? ir.toMap()['rd'] ?? 0; + int get rs1 => _rs1 ?? ir.rs1; + int get rs2 => _rs2 ?? ir.rs2; + int get rs3 => _rs3 ?? ir.rs3; + int get rd => _rd ?? ir.rd; int get imm => _imm ?? ir.imm; - int readSource(MicroOpSource source) { + int readSource(RiscVMicroOpSource source) { switch (source) { - case MicroOpSource.imm: + case RiscVMicroOpSource.imm: return imm; - case MicroOpSource.alu: + case RiscVMicroOpSource.alu: return alu; - case MicroOpSource.rs1: + case RiscVMicroOpSource.rs1: return rs1; - case MicroOpSource.rs2: + case RiscVMicroOpSource.rs2: return rs2; - case MicroOpSource.rd: + case RiscVMicroOpSource.rd: return rd; - case MicroOpSource.pc: + case RiscVMicroOpSource.pc: return pc; - default: - throw 'Invalid source $source'; } } - int readField(MicroOpField field, {bool register = true}) { + int readField(RiscVMicroOpField field, {bool register = true}) { switch (field) { - case MicroOpField.rd: - return register ? rd : (ir.toMap()['rd'] ?? 0); - case MicroOpField.rs1: - return register ? rs1 : (ir.toMap()['rs1'] ?? 0); - case MicroOpField.rs2: - return register ? rs2 : (ir.toMap()['rs2'] ?? 0); - case MicroOpField.imm: + case RiscVMicroOpField.rd: + return register ? rd : ir.rd; + case RiscVMicroOpField.rs1: + return register ? rs1 : ir.rs1; + case RiscVMicroOpField.rs2: + return register ? rs2 : ir.rs2; + case RiscVMicroOpField.rs3: + return register ? rs3 : ir.rs3; + case RiscVMicroOpField.imm: return register ? imm : ir.imm; - case MicroOpField.pc: + case RiscVMicroOpField.pc: return pc; - case MicroOpField.sp: - return sp; - default: - throw 'Invalid field $field'; } } - void clearField(MicroOpField field) { + void clearField(RiscVMicroOpField field) { switch (field) { - case MicroOpField.rd: + case RiscVMicroOpField.rd: _rd = null; - break; - case MicroOpField.rs1: + case RiscVMicroOpField.rs1: _rs1 = null; - break; - case MicroOpField.rs2: + case RiscVMicroOpField.rs2: _rs2 = null; - break; - case MicroOpField.imm: + case RiscVMicroOpField.rs3: + _rs3 = null; + case RiscVMicroOpField.imm: _imm = null; - break; default: throw 'Invalid field $field'; } } - void writeField(MicroOpField field, int value) { + void writeField(RiscVMicroOpField field, int value) { switch (field) { - case MicroOpField.rd: + case RiscVMicroOpField.rd: _rd = value; - break; - case MicroOpField.rs1: + case RiscVMicroOpField.rs1: _rs1 = value; - break; - case MicroOpField.rs2: + case RiscVMicroOpField.rs2: _rs2 = value; - break; - case MicroOpField.imm: + case RiscVMicroOpField.rs3: + _rs3 = value; + case RiscVMicroOpField.imm: _imm = value; - break; - case MicroOpField.sp: - sp = value; - break; default: throw 'Invalid field $field'; } @@ -150,283 +210,238 @@ class RiverCoreEmulatorState { @override String toString() => - 'RiverCoreEmulatorState($pc, $ir, rd: $rd, rs1: $rs1, rs2: $rs2, imm: $imm, alu: $alu, sp: $sp, pc: $pc)'; + 'RiverCoreState($pc, $ir, rd: $rd, rs1: $rs1, rs2: $rs2, imm: $imm, alu: $alu, sp: $sp, pc: $pc)'; } -class RiverCoreEmulator { - final RiverCore config; - - Map xregs; - CsrFile csrs; - List _reservationSet; - bool idle; - PrivilegeMode mode; +/// Couples [RiverCore] to an external debugger so an `ebreak` can enter Debug +/// Mode (halt) instead of trapping to mtvec. Set by [RiverDebugTarget] when a +/// debugger is attached, null when standalone. +abstract class DebugHook { + /// Whether an `ebreak` executed in [mode] should enter Debug Mode, i.e. the + /// matching dcsr.ebreakm/ebreaks/ebreaku bit is set. + bool ebreakEntersDebug(PrivilegeMode mode); + + /// Enter Debug Mode: halt the hart, latch [dpc] (the ebreak's address) and the + /// halt [cause] (1 = ebreak) into dcsr. + void enterDebug(int dpc, int cause); +} - List _interrupts; +class RiverCore implements CsrContext { + @override + final RiverCoreConfig config; - UnmodifiableListView get interrupts => - UnmodifiableListView(_interrupts); + /// Optional hook to an attached external debugger (see [DebugHook]). When set + /// and the relevant dcsr.ebreak* bit is armed, an `ebreak` halts into Debug + /// Mode rather than raising a breakpoint trap. + DebugHook? debugHook; - UnmodifiableListView get reservationSet => - UnmodifiableListView(_reservationSet); + final MmuPlugin _mmuPlugin; + final CsrPlugin _csrPlugin; + final CachePlugin _cachePlugin; + final TrapPlugin _trapPlugin; - final MmuEmulator mmu; - late final CacheEmulator? l1i; - late final CacheEmulator? l1d; + Map xregs; + Map fregs; + List _reservationSet; + bool idle; - RiverCoreEmulator( - this.config, { - Map memDevices = const {}, - }) : xregs = {}, - mmu = MmuEmulator(config.mmu, memDevices), - csrs = CsrFile( - config.mxlen, - hasSupervisor: config.hasSupervisor, - hasUser: config.hasUser, - ), - mode = PrivilegeMode.machine, - _reservationSet = [], - _interrupts = config.interrupts - .map((config) => InterruptControllerEmulator(config)) - .toList(), - idle = false { - l1i = config.l1cache?.i != null - ? CacheEmulator( - config.l1cache!.i!, - fill: (addr, size) async { - final mstatus = csrs.read(CsrAddress.mstatus.address, this); - final mxr = ((mstatus >> 19) & 1) != 0; - final sum = ((mstatus >> 18) & 1) != 0; - - final phys = await mmu.translate( - addr, - MemoryAccess.instr, - privilege: mode, - mxr: mxr, - sum: sum, - ); - - return await mmu.readBlock( - phys, - size, - pageTranslate: false, - privilege: mode, - mxr: mxr, - sum: sum, - ); - }, - writeback: (_, _, _) async {}, - ) - : null; - - l1d = config.l1cache?.d != null - ? CacheEmulator( - config.l1cache!.d!, - fill: (addr, size) async { - final phys = await translate(addr, MemoryAccess.read); - - final mstatus = csrs.read(CsrAddress.mstatus.address, this); - final mxr = ((mstatus >> 19) & 1) != 0; - final sum = ((mstatus >> 18) & 1) != 0; - - return await mmu.readBlock( - phys, - size, - pageTranslate: false, - privilege: mode, - mxr: mxr, - sum: sum, - ); - }, - writeback: (addr, value, size) async { - final phys = await translate(addr, MemoryAccess.write); - - final mstatus = csrs.read(CsrAddress.mstatus.address, this); - final mxr = ((mstatus >> 19) & 1) != 0; - final sum = ((mstatus >> 18) & 1) != 0; - - await mmu.write( - phys, - value, - size, - pageTranslate: true, - privilege: mode, - mxr: mxr, - sum: sum, - ); - }, - ) - : null; + // Vector (V) state, only present when the V extension is configured; a + // V-less core never allocates [vregs] and traps OP-V as illegal. 32 registers + // of VLEN bits (config.vlen), little-endian byte arrays, plus vl/vtype/vstart. + late final bool hasVector = config.extensions.any((e) => e.name == 'V'); + late final int _vlenBytes = config.vlen ~/ 8; + late final List> vregs = List.generate( + 32, + (_) => List.filled(_vlenBytes, 0), + ); + int vl = 0; + int vtype = 0; + int vstart = 0; + int vxsat = 0; // fixed-point saturation flag (vcsr bit 0) + int vxrm = 0; // fixed-point rounding mode (vcsr bits 2:1) + + /// Read element [idx] (sewBits wide) of vector register [vreg], little-endian. + /// Element indices beyond one register span the register group (LMUL>1): + /// element idx lives in physical register vreg + idx/elemsPerReg. + int vreadElem(int vreg, int idx, int sewBits) { + final bytes = sewBits ~/ 8; + final perReg = _vlenBytes ~/ bytes; + final r = (vreg + idx ~/ perReg) & 0x1F; + final off = (idx % perReg) * bytes; + var v = 0; + for (var b = 0; b < bytes; b++) { + v |= (vregs[r][off + b] & 0xFF) << (b * 8); + } + return v; } - void clearReservationSet() => _reservationSet.clear(); - - void reset() { - mode = PrivilegeMode.machine; - xregs = {}; - _reservationSet = []; - idle = false; - csrs.reset(); - mmu.reset(); - if (l1i != null) l1i!.reset(); - if (l1d != null) l1d!.reset(); + /// Write element [idx] (sewBits wide) of vector register [vreg]; spans the + /// register group for LMUL>1 (see [vreadElem]). + void vwriteElem(int vreg, int idx, int sewBits, int value) { + final bytes = sewBits ~/ 8; + final perReg = _vlenBytes ~/ bytes; + final r = (vreg + idx ~/ perReg) & 0x1F; + final off = (idx % perReg) * bytes; + for (var b = 0; b < bytes; b++) { + vregs[r][off + b] = (value >> (b * 8)) & 0xFF; + } } - InstructionType? decode(int instr) => config.microcode.decode(instr); + CsrFile get csrs => _csrPlugin.csrs; - Operation? findOperationByInstruction(InstructionType instr) { - for (final ext in config.extensions) { - for (final op in ext.operations) { - if (op.matches(instr)) { - return op; - } + @override + PrivilegeMode get mode => _csrPlugin.mode; + set mode(PrivilegeMode v) => _csrPlugin.mode = v; + + /// Virtualization bit (H extension): true while executing in VS/VU mode. + bool get virt => _csrPlugin.virt; + set virt(bool v) => _csrPlugin.virt = v; + + /// Smstateen access gating. Returns the trap to raise when the current mode is + /// denied access to a state-enable CSR (sstateen*/hstateen*) because the + /// controlling SE0 bit (bit 63) is clear in the higher-level *stateen CSR, or + /// null when the access is allowed. Only SE0 is implemented; it gates access to + /// the lower-level state-enable CSRs themselves. mstateen0.SE0 denial is an + /// illegal-instruction exception (from any mode below M); hstateen0.SE0 denial + /// of a VS-mode sstateen access is a virtual-instruction exception. + TrapException? _stateenDenied(int reg) { + if (!config.hasStateen) return null; + final isSstateen = reg >= 0x10C && reg <= 0x10F; + final isHstateen = reg >= 0x60C && reg <= 0x60F; + if (!isSstateen && !isHstateen) return null; + if (mode.id >= 3) return null; // M-mode is never gated. + final mse0 = (csrs.read(CsrAddress.mstateen0.address, this) >> 63) & 1; + if (mse0 == 0) { + return TrapException.illegalInstruction(StackTrace.current); + } + if (virt && isSstateen && config.hasHypervisor) { + final hse0 = (csrs.read(CsrAddress.hstateen0.address, this) >> 63) & 1; + if (hse0 == 0) { + return TrapException(Trap.virtualInstruction, 0, StackTrace.current); } } - return null; } - Future execute(int pc, InstructionType instr) async { - final op = findOperationByInstruction(instr)!; - var state = RiverCoreEmulatorState(pc, instr, xregs[Register.x2] ?? 0); - state = await _innerExecute(state, op); - xregs[Register.x2] = state.sp; - return state; - } + @override + Mmu get mmu => _mmuPlugin.mmu; - PrivilegeMode _selectTrapTargetMode(Trap trap) { - if (mode == PrivilegeMode.machine) { - return PrivilegeMode.machine; - } + Cache? get l1i => _cachePlugin.l1i; + Cache? get l1d => _cachePlugin.l1d; - if (!config.hasSupervisor) { - return PrivilegeMode.machine; - } + final List _interrupts; - final int code = switch (mode) { - PrivilegeMode.machine => trap.mcauseCode, - PrivilegeMode.supervisor => trap.scauseCode, - PrivilegeMode.user => trap.ucauseCode, - }; + UnmodifiableListView get interrupts => + UnmodifiableListView(_interrupts); - if (trap.interrupt) { - final mideleg = csrs.read(CsrAddress.mideleg.address, this); - final delegated = ((mideleg >> code) & 1) != 0; - return delegated ? PrivilegeMode.supervisor : PrivilegeMode.machine; - } else { - final medeleg = csrs.read(CsrAddress.medeleg.address, this); - final delegated = ((medeleg >> code) & 1) != 0; - return delegated ? PrivilegeMode.supervisor : PrivilegeMode.machine; - } - } + UnmodifiableListView get reservationSet => + UnmodifiableListView(_reservationSet); - int _encodeCause( - Trap trap, - PrivilegeMode oldMode, - PrivilegeMode targetMode, - int xlen, - ) { - final code = switch (oldMode) { - PrivilegeMode.machine => trap.mcauseCode, - PrivilegeMode.supervisor => trap.scauseCode, - PrivilegeMode.user => trap.ucauseCode, + RiverCore( + this.config, { + Map memDevices = const {}, + }) : _mmuPlugin = MmuPlugin(config.mmu, memDevices), + _csrPlugin = CsrPlugin(config), + _cachePlugin = CachePlugin(config), + _trapPlugin = TrapPlugin(), + xregs = {}, + fregs = {}, + _reservationSet = [], + _interrupts = config.interrupts + .map((config) => InterruptController(config)) + .toList(), + idle = false, + pipeline = EmulatorPipeline() { + // Wire plugins together (sync, bypassing PluginHost elaboration) + _mmuPlugin.mmu = Mmu(config.mmu, memDevices); + _csrPlugin.bind(_mmuPlugin.mmu); + _cachePlugin.bind(_mmuPlugin, _csrPlugin); + _trapPlugin.csr = _csrPlugin; + + // Cache control CSR handler + csrs.onWrite = (address, value, context) { + if (address == CsrAddress.rcachectl.address) { + final addr = csrs.read(CsrAddress.rcacheaddr.address, this); + final size = csrs.read(CsrAddress.rcachesize.address, this); + if (value == 1 && l1d != null) { + l1d!.lockRange(addr, size); + } else if (value == 0 && l1d != null) { + l1d!.unlockRange(addr, size); + } + } }; - final interruptBit = trap.interrupt ? (1 << (xlen - 1)) : 0; - return interruptBit | code; - } - - int trap(int pc, TrapException e) { - final oldMode = this.mode; - final targetMode = _selectTrapTargetMode(e.trap); - final xlen = config.mxlen.size; - - final causeValue = _encodeCause(e.trap, oldMode, targetMode, xlen); - - late final CsrAddress causeCsr; - late final CsrAddress epcCsr; - late final CsrAddress tvalCsr; - late final CsrAddress tvecCsr; - - switch (targetMode) { - case PrivilegeMode.machine: - causeCsr = CsrAddress.mcause; - epcCsr = CsrAddress.mepc; - tvalCsr = CsrAddress.mtval; - tvecCsr = CsrAddress.mtvec; - break; - case PrivilegeMode.supervisor: - causeCsr = CsrAddress.scause; - epcCsr = CsrAddress.sepc; - tvalCsr = CsrAddress.stval; - tvecCsr = CsrAddress.stvec; - break; - case PrivilegeMode.user: - causeCsr = CsrAddress.ucause; - epcCsr = CsrAddress.uepc; - tvalCsr = CsrAddress.utval; - tvecCsr = CsrAddress.utvec; - break; - } - - var mstatus = csrs.read(CsrAddress.mstatus.address, this); - - switch (targetMode) { - case PrivilegeMode.machine: - final mpp = oldMode.id; - mstatus = (mstatus & ~(0x3 << 11)) | (mpp << 11); - - final mie = (mstatus >> 3) & 1; - mstatus = (mstatus & ~(1 << 7)) | (mie << 7); - mstatus &= ~(1 << 3); - break; - - case PrivilegeMode.supervisor: - final spp = (oldMode == PrivilegeMode.user) ? 0 : 1; - mstatus = (mstatus & ~(1 << 8)) | (spp << 8); - - final sie = (mstatus >> 1) & 1; - mstatus = (mstatus & ~(1 << 5)) | (sie << 5); - mstatus &= ~(1 << 1); - break; - - case PrivilegeMode.user: - final uie = mstatus & 1; - mstatus = (mstatus & ~(1 << 4)) | (uie << 4); - mstatus &= ~1; - break; + // Vector CSRs read/write the live vector-unit state (not plain registers). + // vl/vtype/vlenb are read-only; vstart/vxsat/vxrm/vcsr are writable. + if (hasVector) { + final f = csrs.csrs; + f[CsrAddress.vstart.address] = CallbackCsr( + CsrAddress.vstart.address, + () => vstart, + (v) => vstart = v & (config.vlen - 1), + ); + f[CsrAddress.vxsat.address] = CallbackCsr( + CsrAddress.vxsat.address, + () => vxsat, + (v) => vxsat = v & 0x1, + ); + f[CsrAddress.vxrm.address] = CallbackCsr( + CsrAddress.vxrm.address, + () => vxrm, + (v) => vxrm = v & 0x3, + ); + f[CsrAddress.vcsr.address] = CallbackCsr( + CsrAddress.vcsr.address, + () => (vxrm << 1) | vxsat, + (v) { + vxsat = v & 0x1; + vxrm = (v >> 1) & 0x3; + }, + ); + f[CsrAddress.vl.address] = CallbackCsr(CsrAddress.vl.address, () => vl); + f[CsrAddress.vtype.address] = CallbackCsr( + CsrAddress.vtype.address, + () => vtype, + ); + f[CsrAddress.vlenb.address] = CallbackCsr( + CsrAddress.vlenb.address, + () => _vlenBytes, + ); } - csrs.write(causeCsr.address, causeValue, this); - csrs.write(epcCsr.address, pc, this); - csrs.write(tvalCsr.address, e.tval ?? 0, this); - csrs.write(CsrAddress.mstatus.address, mstatus, this); - - this.mode = targetMode; - final tvec = csrs.read(tvecCsr.address, this); - - if (tvec == 0) - throw AbortException.illegalInstruction( - 'Double fault due to $tvecCsr being invalid ($tvec): $e', - e.stack, - ); + // Register pipeline stage handlers + pipeline.at(EmulatorStage.interrupt, _handleInterrupt); + pipeline.at(EmulatorStage.fetch, _handleFetch); + pipeline.at(EmulatorStage.decode, _handleDecode); + pipeline.at(EmulatorStage.execute, _handleExecute); + } - final base = tvec & ~0x3; - final mode = tvec & 0x3; + final EmulatorPipeline pipeline; - if (mode == 1 && e.trap.interrupt) { - final code = switch (this.mode) { - PrivilegeMode.machine => e.trap.mcauseCode, - PrivilegeMode.supervisor => e.trap.scauseCode, - PrivilegeMode.user => e.trap.ucauseCode, - }; + void clearReservationSet() => _reservationSet.clear(); - return base + 4 * code; - } else { - return base; + void reset() { + xregs = {}; + fregs = {}; + _reservationSet = []; + idle = false; + if (hasVector) { + vl = 0; + vtype = 0; + vstart = 0; + vxsat = 0; + vxrm = 0; + for (final v in vregs) { + v.fillRange(0, v.length, 0); + } } + _csrPlugin.reset(); + _mmuPlugin.reset(); + _cachePlugin.reset(); } + int trap(int pc, TrapException e) => _trapPlugin.trap(pc, e, config); + PrivilegeMode _effectiveMemPrivilege() { final mstatus = csrs.read(CsrAddress.mstatus.address, this); @@ -449,6 +464,7 @@ class RiverCoreEmulator { } Future translate(int addr, MemoryAccess access) async { + addr = addr.toUnsigned(config.mxlen.size); final eff = _effectiveMemPrivilege(); int mstatus = csrs.read(CsrAddress.mstatus.address, this); @@ -501,6 +517,14 @@ class RiverCoreEmulator { Future read(int addr, int width) async { final phys = await translate(addr, MemoryAccess.read); + // Locked cache lines act as RAM + if (l1d != null) { + final line = l1d!.findLockedLine(phys); + if (line != null) { + return (await l1d!.read(phys, width))!; + } + } + final mstatus = csrs.read(CsrAddress.mstatus.address, this); final mxr = ((mstatus >> 19) & 1) != 0; final sum = ((mstatus >> 18) & 1) != 0; @@ -546,6 +570,15 @@ class RiverCoreEmulator { _reservationSet.clear(); + // Locked cache lines act as RAM -- skip MMU write + if (l1d != null) { + final line = l1d!.findLockedLine(phys); + if (line != null) { + await l1d!.write(phys, value, width); + return; + } + } + final mstatus = csrs.read(CsrAddress.mstatus.address, this); final mxr = ((mstatus >> 19) & 1) != 0; final sum = ((mstatus >> 18) & 1) != 0; @@ -577,249 +610,368 @@ class RiverCoreEmulator { } } - Future _innerExecute( - RiverCoreEmulatorState state, - Operation op, + Future _innerExecute( + RiverCoreState state, + RiscVOperation op, ) async { - if (!op.allowedLevels.contains(mode)) { - state.pc = trap( - state.pc, - TrapException.illegalInstruction(StackTrace.current), - ); - return state; + // Check privilege level + if (op.privilegeLevel != null) { + if (mode.id < op.privilegeLevel!) { + state.pc = trap( + state.pc, + TrapException.illegalInstruction(StackTrace.current), + ); + return state; + } } final hasAtomics = config.extensions.any((e) => e.name == 'A'); for (final mop in op.microcode) { - if (mop is WriteRegisterMicroOp) { + if (mop is RiscVWriteRegister) { final value = state.readSource(mop.source) + mop.valueOffset; - final reg = Register.values[mop.offset + state.readField(mop.field)]; + final reg = Register.values[state.readField(mop.dest, register: false)]; if (reg == Register.x0) { continue; } xregs[reg] = value; - } else if (mop is ReadRegisterMicroOp) { - final reg = Register.values[mop.offset + state.readField(mop.source)]; - final value = (xregs[reg] ?? 0) + mop.valueOffset; + // sp (x2) is mirrored in state.sp, which _handleExecute writes back + // after the microcode runs; keep it in sync or the write is reverted. + if (reg == Register.x2) state.sp = value; + } else if (mop is RiscVReadRegister) { + final reg = Register + .values[mop.offset + state.readField(mop.source, register: false)]; + final value = xregs[reg] ?? 0; state.writeField(mop.source, value); - } else if (mop is AluMicroOp) { + } else if (mop is RiscVAlu) { final a = state.readField(mop.a); final b = state.readField(mop.b); - switch (mop.alu) { - case MicroOpAluFunct.add: + switch (mop.funct) { + case RiscVAluFunct.add: state.alu = a + b; - break; - case MicroOpAluFunct.sub: + case RiscVAluFunct.sub: state.alu = a - b; - break; - case MicroOpAluFunct.mul: + case RiscVAluFunct.mul: state.alu = a * b; - break; - case MicroOpAluFunct.and: + case RiscVAluFunct.and_: state.alu = a & b; - break; - case MicroOpAluFunct.or: + case RiscVAluFunct.or_: state.alu = a | b; - break; - case MicroOpAluFunct.xor: + case RiscVAluFunct.xor_: state.alu = a ^ b; - break; - case MicroOpAluFunct.sll: - state.alu = a << b; - break; - case MicroOpAluFunct.srl: - case MicroOpAluFunct.sra: - state.alu = a >> b; - break; - case MicroOpAluFunct.slt: - state.alu = a <= b ? 1 : 0; - break; - case MicroOpAluFunct.sltu: + case RiscVAluFunct.sll: + // Shift amount masked to log2(xlen) bits (RISC-V). + state.alu = a << (b & (config.mxlen.size - 1)); + case RiscVAluFunct.srl: + // Logical right shift (was arithmetic `>>`, which sign-extends). + state.alu = + a.toUnsigned(config.mxlen.size) >>> + (b & (config.mxlen.size - 1)); + case RiscVAluFunct.sra: + // Arithmetic right shift on the sign-extended operand. state.alu = - a.toUnsigned(config.mxlen.size) <= - b.toUnsigned(config.mxlen.size) + a.toSigned(config.mxlen.size) >> (b & (config.mxlen.size - 1)); + case RiscVAluFunct.slt: + // Signed strict less-than (was `<=`, which is wrong when a == b). + state.alu = + a.toSigned(config.mxlen.size) < b.toSigned(config.mxlen.size) ? 1 : 0; - break; - case MicroOpAluFunct.masked: - state.alu = a & ~b; - break; - case MicroOpAluFunct.mulh: - { - final xlen = config.mxlen.size; - final aS = a.toSigned(xlen); - final bS = b.toSigned(xlen); - final wide = BigInt.from(aS) * BigInt.from(bS); - final high = wide >> xlen; - state.alu = (high & ((BigInt.one << xlen) - BigInt.one)).toInt(); - break; - } - case MicroOpAluFunct.mulhsu: - { - final xlen = config.mxlen.size; - final aS = a.toSigned(xlen); - final bU = b.toUnsigned(xlen); - final wide = BigInt.from(aS) * BigInt.from(bU); - final high = wide >> xlen; - state.alu = (high & ((BigInt.one << xlen) - BigInt.one)).toInt(); - break; - } - case MicroOpAluFunct.mulhu: - { - final xlen = config.mxlen.size; - final aU = a.toUnsigned(xlen); - final bU = b.toUnsigned(xlen); - final wide = BigInt.from(aU) * BigInt.from(bU); - final high = wide >> xlen; - state.alu = (high & ((BigInt.one << xlen) - BigInt.one)).toInt(); - break; - } - case MicroOpAluFunct.div: - { - final xlen = config.mxlen.size; - final dividend = a.toSigned(xlen); - final divisor = b.toSigned(xlen); - - if (divisor == 0) { - state.alu = -1; + case RiscVAluFunct.sltu: + // Unsigned strict less-than. toUnsigned(64) is a no-op on Dart's + // 64-bit-signed int, so at xlen=64 flip the top bit to map unsigned + // order onto signed order. + state.alu = + (config.mxlen.size < 64 + ? a.toUnsigned(config.mxlen.size) < + b.toUnsigned(config.mxlen.size) + : (a ^ 0x8000000000000000) < (b ^ 0x8000000000000000)) + ? 1 + : 0; + case RiscVAluFunct.mulh: + final xlen = config.mxlen.size; + final aS = a.toSigned(xlen); + final bS = b.toSigned(xlen); + final wide = BigInt.from(aS) * BigInt.from(bS); + final high = wide >> xlen; + state.alu = (high & ((BigInt.one << xlen) - BigInt.one)) + .toSigned(64) + .toInt(); + case RiscVAluFunct.mulhsu: + final xlen = config.mxlen.size; + // b is unsigned: unsign at BigInt width (Dart toUnsigned(64) no-ops). + final wide = + BigInt.from(a.toSigned(xlen)) * BigInt.from(b).toUnsigned(xlen); + final high = wide >> xlen; + state.alu = (high & ((BigInt.one << xlen) - BigInt.one)) + .toSigned(64) + .toInt(); + case RiscVAluFunct.mulhu: + final xlen = config.mxlen.size; + final wide = + BigInt.from(a).toUnsigned(xlen) * + BigInt.from(b).toUnsigned(xlen); + final high = wide >> xlen; + state.alu = (high & ((BigInt.one << xlen) - BigInt.one)) + .toSigned(64) + .toInt(); + case RiscVAluFunct.div: + final xlen = config.mxlen.size; + final dividend = a.toSigned(xlen); + final divisor = b.toSigned(xlen); + if (divisor == 0) { + state.alu = -1; + } else { + final intMin = 1 << (xlen - 1); + if (dividend == intMin && divisor == -1) { + state.alu = intMin; } else { - final intMin = 1 << (xlen - 1); - if (dividend == intMin && divisor == -1) { - state.alu = intMin; - } else { - state.alu = (dividend ~/ divisor); - } + state.alu = (dividend ~/ divisor); } - break; } - case MicroOpAluFunct.divu: - { - final xlen = config.mxlen.size; - - final mask = (BigInt.one << xlen) - BigInt.one; - - final dividend = BigInt.from(a) & mask; - final divisor = BigInt.from(b) & mask; - - if (divisor == BigInt.zero) { - state.alu = mask.toInt(); + case RiscVAluFunct.divu: + final xlen = config.mxlen.size; + final mask = (BigInt.one << xlen) - BigInt.one; + final dividend = BigInt.from(a) & mask; + final divisor = BigInt.from(b) & mask; + if (divisor == BigInt.zero) { + // all-ones; toSigned avoids BigInt.toInt() clamping at >= 2^63. + state.alu = mask.toSigned(64).toInt(); + } else { + final q = dividend ~/ divisor; + state.alu = (q & mask).toSigned(64).toInt(); + } + case RiscVAluFunct.rem: + final xlen = config.mxlen.size; + final dividend = a.toSigned(xlen); + final divisor = b.toSigned(xlen); + if (divisor == 0) { + state.alu = dividend; + } else { + final intMin = 1 << (xlen - 1); + if (dividend == intMin && divisor == -1) { + state.alu = 0; } else { final q = dividend ~/ divisor; - state.alu = (q & mask).toInt(); + final r = dividend - q * divisor; + state.alu = r; } - break; } - case MicroOpAluFunct.rem: - { - final xlen = config.mxlen.size; - final dividend = a.toSigned(xlen); - final divisor = b.toSigned(xlen); - - if (divisor == 0) { - state.alu = dividend; - } else { - final intMin = 1 << (xlen - 1); - if (dividend == intMin && divisor == -1) { - state.alu = 0; - } else { - final q = dividend ~/ divisor; - final r = dividend - q * divisor; - state.alu = r; - } - } - break; + case RiscVAluFunct.remu: + final xlen = config.mxlen.size; + // toUnsigned(64) is a no-op on Dart ints; unsign at BigInt width. + final mask = (BigInt.one << xlen) - BigInt.one; + final dividend = BigInt.from(a) & mask; + final divisor = BigInt.from(b) & mask; + state.alu = (divisor == BigInt.zero ? dividend : dividend % divisor) + .toSigned(xlen) + .toInt(); + case RiscVAluFunct.addw: + state.alu = ((a + b) & 0xFFFFFFFF).toSigned(32); + case RiscVAluFunct.subw: + state.alu = ((a - b) & 0xFFFFFFFF).toSigned(32); + case RiscVAluFunct.sllw: + state.alu = ((a << (b & 0x1F)) & 0xFFFFFFFF).toSigned(32); + case RiscVAluFunct.srlw: + state.alu = (a.toUnsigned(32) >> (b & 0x1F)).toSigned(32); + case RiscVAluFunct.sraw: + state.alu = (a.toSigned(32) >> (b & 0x1F)); + case RiscVAluFunct.mulw: + final prod = (a.toSigned(32) * b.toSigned(32)) & 0xFFFFFFFF; + state.alu = prod.toSigned(32); + case RiscVAluFunct.divw: + final dividend = a.toSigned(32); + final divisor = b.toSigned(32); + if (divisor == 0) { + state.alu = -1; + } else if (dividend == -0x80000000 && divisor == -1) { + state.alu = -0x80000000; + } else { + state.alu = (dividend ~/ divisor).toSigned(32); + } + case RiscVAluFunct.divuw: + final dividend = a.toUnsigned(32); + final divisor = b.toUnsigned(32); + // W ops sign-extend the 32-bit result to 64 (even unsigned ones). + if (divisor == 0) { + state.alu = 0xFFFFFFFF.toSigned(32); // all-ones -> -1 + } else { + state.alu = (dividend ~/ divisor).toSigned(32); } - case MicroOpAluFunct.remu: + case RiscVAluFunct.remw: + final dividend = a.toSigned(32); + final divisor = b.toSigned(32); + if (divisor == 0) { + state.alu = dividend.toSigned(32); + } else if (dividend == -0x80000000 && divisor == -1) { + state.alu = 0; + } else { + final q = dividend ~/ divisor; + state.alu = (dividend - q * divisor).toSigned(32); + } + case RiscVAluFunct.remuw: + final dividend = a.toUnsigned(32); + final divisor = b.toUnsigned(32); + // 32-bit result sign-extended to 64. + state.alu = (divisor == 0 ? dividend : dividend % divisor).toSigned( + 32, + ); + // Zbb / Zba / Zbs bit manipulation + case RiscVAluFunct.andn: + state.alu = a & ~b; + case RiscVAluFunct.orn: + state.alu = a | ~b; + case RiscVAluFunct.xnor: + state.alu = ~(a ^ b); + case RiscVAluFunct.minOp: + state.alu = + a.toSigned(config.mxlen.size) <= b.toSigned(config.mxlen.size) + ? a + : b; + case RiscVAluFunct.maxOp: + state.alu = + a.toSigned(config.mxlen.size) >= b.toSigned(config.mxlen.size) + ? a + : b; + case RiscVAluFunct.minuOp: + state.alu = + BigInt.from(a).toUnsigned(config.mxlen.size) <= + BigInt.from(b).toUnsigned(config.mxlen.size) + ? a + : b; + case RiscVAluFunct.maxuOp: + state.alu = + BigInt.from(a).toUnsigned(config.mxlen.size) >= + BigInt.from(b).toUnsigned(config.mxlen.size) + ? a + : b; + case RiscVAluFunct.rol: + case RiscVAluFunct.ror: { - final xlen = config.mxlen.size; - final dividend = a.toUnsigned(xlen); - final divisor = b.toUnsigned(xlen); - - if (divisor == 0) { - state.alu = dividend; - } else { - state.alu = (dividend % divisor); - } - break; + final x = config.mxlen.size; + final sh = b & (x - 1); + final u = BigInt.from(a).toUnsigned(x); + final mask = (BigInt.one << x) - BigInt.one; + final r = mop.funct == RiscVAluFunct.ror + ? ((u >> sh) | (u << (x - sh))) & mask + : ((u << sh) | (u >> (x - sh))) & mask; + state.alu = r.toSigned(x).toInt(); } - case MicroOpAluFunct.mulw: + case RiscVAluFunct.rolw: + case RiscVAluFunct.rorw: { - final prod = (a.toSigned(32) * b.toSigned(32)) & 0xFFFFFFFF; - state.alu = prod.toSigned(32); - break; + final sh = b & 31; + final u = BigInt.from(a).toUnsigned(32); + final mask = (BigInt.one << 32) - BigInt.one; + final r = mop.funct == RiscVAluFunct.rorw + ? ((u >> sh) | (u << (32 - sh))) & mask + : ((u << sh) | (u >> (32 - sh))) & mask; + state.alu = r.toInt().toSigned(32); } - case MicroOpAluFunct.divw: + case RiscVAluFunct.clz: + state.alu = + config.mxlen.size - + BigInt.from(a).toUnsigned(config.mxlen.size).bitLength; + case RiscVAluFunct.clzw: + state.alu = 32 - BigInt.from(a).toUnsigned(32).bitLength; + case RiscVAluFunct.ctz: + case RiscVAluFunct.ctzw: { - final dividend = a.toSigned(32); - final divisor = b.toSigned(32); - - if (divisor == 0) { - state.alu = -1; - } else if (dividend == -0x80000000 && divisor == -1) { - state.alu = -0x80000000; - } else { - state.alu = (dividend ~/ divisor).toSigned(32); - } - break; + final x = mop.funct == RiscVAluFunct.ctzw + ? 32 + : config.mxlen.size; + final u = BigInt.from(a).toUnsigned(x); + state.alu = u == BigInt.zero ? x : (u & (-u)).bitLength - 1; } - case MicroOpAluFunct.divuw: + case RiscVAluFunct.cpop: + case RiscVAluFunct.cpopw: { - final dividend = a.toUnsigned(32); - final divisor = b.toUnsigned(32); - - if (divisor == 0) { - state.alu = 0xFFFFFFFF; - } else { - final q = dividend ~/ divisor; - state.alu = q.toUnsigned(32); + final x = mop.funct == RiscVAluFunct.cpopw + ? 32 + : config.mxlen.size; + var v = BigInt.from(a).toUnsigned(x); + var c = 0; + while (v > BigInt.zero) { + if ((v & BigInt.one) == BigInt.one) c++; + v >>= 1; } - break; + state.alu = c; } - case MicroOpAluFunct.remw: + case RiscVAluFunct.sextb: + state.alu = (a & 0xFF).toSigned(8); + case RiscVAluFunct.sexth: + state.alu = (a & 0xFFFF).toSigned(16); + case RiscVAluFunct.zexth: + state.alu = a & 0xFFFF; + case RiscVAluFunct.rev8: { - final dividend = a.toSigned(32); - final divisor = b.toSigned(32); - - if (divisor == 0) { - state.alu = dividend.toSigned(32); - } else if (dividend == -0x80000000 && divisor == -1) { - state.alu = 0; - } else { - final q = dividend ~/ divisor; - state.alu = (dividend - q * divisor).toSigned(32); + final x = config.mxlen.size; + var r = 0; + for (var i = 0; i < x ~/ 8; i++) { + r |= ((a >> (i * 8)) & 0xFF) << ((x ~/ 8 - 1 - i) * 8); } - break; + state.alu = r; } - case MicroOpAluFunct.remuw: + case RiscVAluFunct.orcb: { - final dividend = a.toUnsigned(32); - final divisor = b.toUnsigned(32); - - if (divisor == 0) { - state.alu = dividend; - } else { - final r = dividend % divisor; - state.alu = r.toUnsigned(32); + final x = config.mxlen.size; + var r = 0; + for (var i = 0; i < x ~/ 8; i++) { + if (((a >> (i * 8)) & 0xFF) != 0) r |= 0xFF << (i * 8); } - break; + state.alu = r; } - default: - throw 'Invalid ALU function ${mop.alu}'; + case RiscVAluFunct.sh1add: + state.alu = (a << 1) + b; + case RiscVAluFunct.sh2add: + state.alu = (a << 2) + b; + case RiscVAluFunct.sh3add: + state.alu = (a << 3) + b; + case RiscVAluFunct.adduw: + state.alu = (a & 0xFFFFFFFF) + b; + case RiscVAluFunct.sh1adduw: + state.alu = ((a & 0xFFFFFFFF) << 1) + b; + case RiscVAluFunct.sh2adduw: + state.alu = ((a & 0xFFFFFFFF) << 2) + b; + case RiscVAluFunct.sh3adduw: + state.alu = ((a & 0xFFFFFFFF) << 3) + b; + case RiscVAluFunct.bset: + state.alu = a | (1 << (b & (config.mxlen.size - 1))); + case RiscVAluFunct.bclr: + state.alu = a & ~(1 << (b & (config.mxlen.size - 1))); + case RiscVAluFunct.binv: + state.alu = a ^ (1 << (b & (config.mxlen.size - 1))); + case RiscVAluFunct.bext: + state.alu = (a >> (b & (config.mxlen.size - 1))) & 1; + // Zicond + case RiscVAluFunct.czeroEqz: + state.alu = b == 0 ? 0 : a; + case RiscVAluFunct.czeroNez: + state.alu = b != 0 ? 0 : a; + // Zcb unary helpers + case RiscVAluFunct.zextb: + state.alu = a & 0xFF; + case RiscVAluFunct.zextw: + state.alu = a & 0xFFFFFFFF; + case RiscVAluFunct.notOp: + state.alu = ~a; } - } else if (mop is UpdatePCMicroOp) { + } else if (mop is RiscVUpdatePc) { int value = mop.offset; if (mop.offsetField != null) value = state.readField(mop.offsetField!); - if (mop.offsetSource != null) + if (mop.offsetSource != null) { value = state.readSource(mop.offsetSource!); + } if (mop.align) value &= ~1; state.pc = (mop.absolute ? 0 : state.pc) + value; - } else if (mop is MemLoadMicroOp) { + } else if (mop is RiscVMemLoad) { final base = state.readField(mop.base); - final addr = base + state.imm; + final addr = (base + state.imm).toUnsigned(config.mxlen.size); + final sizeBytes = mop.size.bytes; + final sizeBits = sizeBytes * 8; - if (mop.size.bytes > 1 && (addr & (mop.size.bytes - 1)) != 0) { + if (sizeBytes > 1 && (addr & (sizeBytes - 1)) != 0) { state.pc = trap( state.pc, TrapException(Trap.misalignedLoad, addr, StackTrace.current), @@ -828,23 +980,25 @@ class RiverCoreEmulator { } try { - final loaded = await read(addr, mop.size.bytes); + final loaded = await read(addr, sizeBytes); final finalValue = mop.unsigned - ? loaded.toUnsigned(mop.size.bits) - : loaded.toSigned(mop.size.bits); + ? loaded.toUnsigned(sizeBits) + : loaded.toSigned(sizeBits); state.writeField(mop.dest, finalValue); } on TrapException catch (e) { state.pc = trap(state.pc, e); return state; } - } else if (mop is MemStoreMicroOp) { + } else if (mop is RiscVMemStore) { final base = state.readField(mop.base); final value = state.readField(mop.src); - final addr = base + state.imm; + final addr = (base + state.imm).toUnsigned(config.mxlen.size); + final sizeBytes = mop.size.bytes; + final sizeBits = sizeBytes * 8; - if (mop.size.bytes > 1 && (addr & (mop.size.bytes - 1)) != 0) { + if (sizeBytes > 1 && (addr & (sizeBytes - 1)) != 0) { state.pc = trap( state.pc, TrapException(Trap.misalignedStore, addr, StackTrace.current), @@ -853,58 +1007,90 @@ class RiverCoreEmulator { } try { - await write(addr, value.toUnsigned(mop.size.bits), mop.size.bytes); + await write(addr, value.toUnsigned(sizeBits), sizeBytes); } on TrapException catch (e) { state.pc = trap(state.pc, e); return state; } - } else if (mop is TrapMicroOp) { - state.pc = trap( - state.pc, - TrapException(switch (mode) { - PrivilegeMode.machine => mop.kindMachine, - PrivilegeMode.supervisor => mop.kindSupervisor ?? mop.kindMachine, - PrivilegeMode.user => mop.kindUser ?? mop.kindMachine, - }), + } else if (mop is RiscVTrapOp) { + var trapKind = Trap.values.firstWhere( + (t) => t.causeCode == mop.causeCode && t.interrupt == mop.isInterrupt, + orElse: () => Trap.illegal, ); + // ecall: microcode hardcodes cause 8 (ecallU); real cause depends on + // originating mode: U/VU=8, HS=9, VS=10 (H), M=11. + if (mop.causeCode == 8 && !mop.isInterrupt) { + trapKind = switch (mode) { + PrivilegeMode.machine => Trap.ecallM, + PrivilegeMode.supervisor => virt ? Trap.ecallVS : Trap.ecallS, + _ => Trap.ecallU, + }; + } + // External-debug ebreak: when a debugger has armed dcsr.ebreak* for the + // current mode, an ebreak halts into Debug Mode instead of trapping to + // mtvec (which on a bare debug target can be the program itself). + if (trapKind == Trap.breakpoint && + debugHook != null && + debugHook!.ebreakEntersDebug(mode)) { + debugHook!.enterDebug(state.pc, 1); + return state; // pc stays at the ebreak; the run loop sees the halt + } + state.pc = trap(state.pc, TrapException(trapKind)); return state; - } else if (mop is BranchIfMicroOp) { + } else if (mop is RiscVBranch) { final target = state.readSource(mop.target); final value = mop.offsetField != null ? state.readField(mop.offsetField!) : mop.offset; + // Unsigned conditions cannot come from the sign of the signed rs1-rs2 + // difference (`target`), so compare the operands as unsigned, same width + // handling as SLTU above (flip the top bit at xlen=64). + final xlen = config.mxlen.size; + final lhs = state.readField(RiscVMicroOpField.rs1); + final rhs = state.readField(RiscVMicroOpField.rs2); + final ltu = xlen < 64 + ? lhs.toUnsigned(xlen) < rhs.toUnsigned(xlen) + : (lhs ^ 0x8000000000000000) < (rhs ^ 0x8000000000000000); + final condition = switch (mop.condition) { - MicroOpCondition.eq => target == 0, - MicroOpCondition.ne => target != 0, - MicroOpCondition.lt => target < 0, - MicroOpCondition.gt => target > 0, - MicroOpCondition.ge => target >= 0, - MicroOpCondition.le => target <= 0, + RiscVBranchCondition.eq => target == 0, + RiscVBranchCondition.ne => target != 0, + RiscVBranchCondition.lt => target < 0, + RiscVBranchCondition.ge => target >= 0, + RiscVBranchCondition.ltu => ltu, + RiscVBranchCondition.geu => !ltu, }; if (condition) { state.pc += value; return state; } - } else if (mop is WriteLinkRegisterMicroOp) { + } else if (mop is RiscVWriteLinkRegister) { final value = state.pc + mop.pcOffset; - - Register reg = Register.x0; - if (mop.link.reg != null) { - reg = mop.link.reg!; - } else if (mop.link.source != null) { - reg = Register.values[state.readSource(mop.link.source!)]; - } - + final rdIndex = state.readField(mop.dest, register: false); + final reg = Register.values[rdIndex]; if (reg != Register.x0) { xregs[reg] = value; } - } else if (mop is ReadCsrMicroOp && config.type.hasCsrs) { - final reg = state.readField(mop.source); + } else if (mop is RiscVReadCsr && config.hasCsrs) { + // CSR address is the unsigned 12-bit field; the imm latch is + // sign-extended, so mask it (else CSRs >= 0x800 like cycle/mcycle miss). + var reg = state.readField(mop.source) & 0xFFF; + + // H VS-mode (virt=1): a VS access to an HS-only hypervisor CSR (0x6xx) + // raises a virtual-instruction exception, ahead of the privilege check. + if (config.hasHypervisor && virt && (reg & 0xF00) == 0x600) { + state.pc = trap( + state.pc, + TrapException(Trap.virtualInstruction, 0, StackTrace.current), + ); + return state; + } - if (mode == PrivilegeMode.user) { + final csrPriv = (reg >> 8) & 0x3; + if (mode.id < csrPriv) { state.pc = trap( state.pc, TrapException.illegalInstruction(StackTrace.current), @@ -912,6 +1098,24 @@ class RiverCoreEmulator { return state; } + // Smstateen: deny access to a state-enable CSR when SE0 is clear above. + final stTrap = _stateenDenied(reg); + if (stTrap != null) { + state.pc = trap(state.pc, stTrap); + return state; + } + + // H VS-mode: supervisor CSRs (0x1xx) redirect to their VS shadow + // (+0x100, e.g. sstatus->vsstatus, satp->vsatp). Done after the priv + // check so the original (S, priv 1) address is what's privilege-checked. + // State-enable CSRs (sstateen*) have no VS shadow, so exclude them. + if (config.hasHypervisor && + virt && + (reg & 0xF00) == 0x100 && + !(reg >= 0x10C && reg <= 0x10F)) { + reg += 0x100; + } + try { final value = csrs.read(reg, this); state.writeField(mop.source, value); @@ -919,11 +1123,21 @@ class RiverCoreEmulator { state.pc = trap(state.pc, e); return state; } - } else if (mop is WriteCsrMicroOp && config.type.hasCsrs) { + } else if (mop is RiscVWriteCsr && config.hasCsrs) { final value = state.readSource(mop.source); - final reg = state.readField(mop.field); + var reg = state.readField(mop.dest) & 0xFFF; + + // H VS-mode: virtual-instruction on a VS access to an HS hypervisor CSR. + if (config.hasHypervisor && virt && (reg & 0xF00) == 0x600) { + state.pc = trap( + state.pc, + TrapException(Trap.virtualInstruction, 0, StackTrace.current), + ); + return state; + } - if (mode == PrivilegeMode.user) { + final csrPriv = (reg >> 8) & 0x3; + if (mode.id < csrPriv) { state.pc = trap( state.pc, TrapException.illegalInstruction(StackTrace.current), @@ -931,17 +1145,48 @@ class RiverCoreEmulator { return state; } + // Smstateen: deny access to a state-enable CSR when SE0 is clear above. + final stTrap = _stateenDenied(reg); + if (stTrap != null) { + state.pc = trap(state.pc, stTrap); + return state; + } + + // H VS-mode: supervisor CSRs redirect to their VS shadow (+0x100); + // state-enable CSRs have no VS shadow, so exclude them. + if (config.hasHypervisor && + virt && + (reg & 0xF00) == 0x100 && + !(reg >= 0x10C && reg <= 0x10F)) { + reg += 0x100; + } + try { - csrs.write(reg, value, this); + // CSRRS/CSRRC with rs1=x0 (e.g. rdcycle/rdtime/rdinstret) and + // CSRRSI/CSRRCI with uimm=0 compute an unchanged value and must not + // write the CSR. Skipping no-op writes lets them read read-only + // counters without faulting, while real writes to RO CSRs still trap. + final unchanged = + csrs.csrs.containsKey(reg) && csrs.read(reg, this) == value; + if (!unchanged) csrs.write(reg, value, this); } on TrapException catch (e) { state.pc = trap(state.pc, e); return state; } - } else if (mop is ReturnMicroOp) { + } else if (mop is RiscVReturnOp) { + final returnMode = PrivilegeMode.find(mop.privilegeLevel); + if (returnMode == null) { + state.pc = trap( + state.pc, + TrapException.illegalInstruction(StackTrace.current), + ); + return state; + } + var mstatus = csrs.read(CsrAddress.mstatus.address, this); try { - switch (mop.mode) { + switch (returnMode) { case PrivilegeMode.machine: { final mpp = (mstatus >> 11) & 0x3; @@ -961,6 +1206,12 @@ class RiverCoreEmulator { csrs.write(CsrAddress.mstatus.address, mstatus, this); mode = newMode; + // MRET enters virtualized mode when MPV is set (never for M). + if (config.hasHypervisor) { + virt = + newMode != PrivilegeMode.machine && + ((mstatus >> 39) & 1) == 1; + } state.pc = csrs.read(CsrAddress.mepc.address, this); break; @@ -980,6 +1231,18 @@ class RiverCoreEmulator { csrs.write(CsrAddress.mstatus.address, mstatus, this); mode = newMode; + // An SRET from HS-mode enters the guest when hstatus.SPV is set; + // SPV is then cleared. (A guest-mode SRET is left to the normal + // supervisor path here.) + if (config.hasHypervisor && !virt) { + final hstatus = csrs.read(CsrAddress.hstatus.address, this); + virt = ((hstatus >> 7) & 1) == 1; // SPV + csrs.write( + CsrAddress.hstatus.address, + hstatus & ~(1 << 7), + this, + ); + } state.pc = csrs.read(CsrAddress.sepc.address, this); break; @@ -1003,7 +1266,7 @@ class RiverCoreEmulator { state.pc = trap(state.pc, e); return state; } - } else if (mop is InterruptHoldMicroOp) { + } else if (mop is RiscVInterruptHold) { final mstatus = csrs.read(CsrAddress.mstatus.address, this); final mie = (mstatus >> 3) & 1; if (mie == 0) continue; @@ -1012,18 +1275,15 @@ class RiverCoreEmulator { if (pending != null) return state; idle = true; - } else if (mop is ModifyLatchMicroOp) { - if (mop.replace) { - final value = state.readSource(mop.source); - state.writeField(mop.field, value); - } else { - state.clearField(mop.field); - } - } else if (mop is LoadReservedMicroOp) { + } else if (mop is RiscVWaitForInterrupt) { + idle = true; + } else if (mop is RiscVLoadReserved) { final base = state.readField(mop.base); final addr = base + state.imm; + final sizeBytes = mop.size.bytes; + final sizeBits = sizeBytes * 8; - if (mop.size.bytes > 1 && (addr & (mop.size.bytes - 1)) != 0) { + if (sizeBytes > 1 && (addr & (sizeBytes - 1)) != 0) { state.pc = trap( state.pc, TrapException(Trap.misalignedLoad, addr, StackTrace.current), @@ -1032,9 +1292,9 @@ class RiverCoreEmulator { } try { - final loaded = await read(addr, config.mxlen.width); + final loaded = await read(addr, config.mxlen.bytes); - final value = loaded.toSigned(mop.size.bits); + final value = loaded.toSigned(sizeBits); final rd = Register.values[state.readField(mop.dest)]; xregs[rd] = value; @@ -1047,11 +1307,12 @@ class RiverCoreEmulator { state.pc = trap(state.pc, e); return state; } - } else if (mop is StoreConditionalMicroOp && hasAtomics) { + } else if (mop is RiscVStoreConditional && hasAtomics) { final base = state.readField(mop.base); final addr = base + state.imm; + final sizeBytes = mop.size.bytes; - if (mop.size.bytes > 1 && (addr & (mop.size.bytes - 1)) != 0) { + if (sizeBytes > 1 && (addr & (sizeBytes - 1)) != 0) { state.pc = trap( state.pc, TrapException(Trap.misalignedStore, addr, StackTrace.current), @@ -1076,8 +1337,8 @@ class RiverCoreEmulator { await mmu.write( phys, - srcValue.toUnsigned(mop.size.bits), - mop.size.bytes, + srcValue.toUnsigned(sizeBytes * 8), + sizeBytes, pageTranslate: false, sum: sum, mxr: mxr, @@ -1099,11 +1360,13 @@ class RiverCoreEmulator { state.pc = trap(state.pc, e); return state; } - } else if (mop is AtomicMemoryMicroOp && hasAtomics) { + } else if (mop is RiscVAtomicMemory && hasAtomics) { final base = state.readField(mop.base); final addr = base + state.imm; + final sizeBytes = mop.size.bytes; + final sizeBits = sizeBytes * 8; - if (mop.size.bytes > 1 && (addr & (mop.size.bytes - 1)) != 0) { + if (sizeBytes > 1 && (addr & (sizeBytes - 1)) != 0) { state.pc = trap( state.pc, TrapException(Trap.misalignedLoad, addr, StackTrace.current), @@ -1122,13 +1385,13 @@ class RiverCoreEmulator { final loaded = await mmu.read( phys, - config.mxlen.width, + config.mxlen.bytes, pageTranslate: false, sum: sum, mxr: mxr, ); - final mask = (mop.size.bits == 64) ? -1 : ((1 << mop.size.bits) - 1); + final mask = (sizeBits == 64) ? -1 : ((1 << sizeBits) - 1); final oldVal = loaded & mask; final srcVal = srcRaw & mask; @@ -1136,51 +1399,47 @@ class RiverCoreEmulator { int newVal; int sx(int v) { - return v.toSigned(mop.size.bits); + return v.toSigned(sizeBits); } - switch (mop.afunct) { - case MicroOpAtomicFunct.add: + switch (mop.funct) { + case RiscVAtomicFunct.add: newVal = (sx(oldVal) + sx(srcVal)) & mask; - break; - case MicroOpAtomicFunct.swap: + case RiscVAtomicFunct.swap: newVal = srcVal; - break; - case MicroOpAtomicFunct.xor: + case RiscVAtomicFunct.xor_: newVal = (oldVal ^ srcVal) & mask; - break; - case MicroOpAtomicFunct.and: + case RiscVAtomicFunct.and_: newVal = (oldVal & srcVal) & mask; - break; - case MicroOpAtomicFunct.or: + case RiscVAtomicFunct.or_: newVal = (oldVal | srcVal) & mask; - break; - case MicroOpAtomicFunct.min: + case RiscVAtomicFunct.min: newVal = sx(srcVal) < sx(oldVal) ? srcVal : oldVal; - break; - case MicroOpAtomicFunct.max: + case RiscVAtomicFunct.max: newVal = sx(srcVal) > sx(oldVal) ? srcVal : oldVal; - break; - case MicroOpAtomicFunct.minu: - newVal = - srcVal.toUnsigned(mop.size.bits) < - oldVal.toUnsigned(mop.size.bits) + case RiscVAtomicFunct.minu: + newVal = srcVal.toUnsigned(sizeBits) < oldVal.toUnsigned(sizeBits) ? srcVal : oldVal; - break; - case MicroOpAtomicFunct.maxu: - newVal = - srcVal.toUnsigned(mop.size.bits) > - oldVal.toUnsigned(mop.size.bits) + case RiscVAtomicFunct.maxu: + newVal = srcVal.toUnsigned(sizeBits) > oldVal.toUnsigned(sizeBits) ? srcVal : oldVal; - break; + case RiscVAtomicFunct.cas: + // Zacas amocas: store rs2 (srcVal) only if mem == rd's current + // value. readField(dest) gives the register index, so read the + // compare value out of xregs; rd then receives the loaded value. + final cmpIdx = state.readField(mop.dest); + final cmpReg = Register.values[cmpIdx]; + final cmp = + (cmpReg == Register.x0 ? 0 : (xregs[cmpReg] ?? 0)) & mask; + newVal = (oldVal == cmp) ? srcVal : oldVal; } await mmu.write( phys, newVal, - config.mxlen.width, + config.mxlen.bytes, pageTranslate: false, sum: sum, mxr: mxr, @@ -1190,73 +1449,1061 @@ class RiverCoreEmulator { final rdReg = Register.values[rdIndex]; if (rdReg != Register.x0) { final xlen = config.mxlen.size; - final oldXlen = oldVal.toSigned(mop.size.bits).toSigned(xlen); + final oldXlen = oldVal.toSigned(sizeBits).toSigned(xlen); xregs[rdReg] = oldXlen; } } on TrapException catch (e) { state.pc = trap(state.pc, e); return state; } - } else if (mop is ValidateFieldMicroOp) { - final value = state.readField(mop.field); - bool valid = true; + } else if (mop is RiscVTlbFenceOp) { + final rs1Val = state.readField(RiscVMicroOpField.rs1, register: false); + final rs2Val = state.readField(RiscVMicroOpField.rs2, register: false); + final vaddr = rs1Val != 0 ? xregs[Register.values[rs1Val]] : null; + final asid = rs2Val != 0 ? xregs[Register.values[rs2Val]] : null; + mmu.flushTlb(asid: asid, vaddr: vaddr); + } else if (mop is RiscVTlbInvalidateOp) { + mmu.flushTlb(); + } else if (mop is RiscVCopyField) { + state.writeField(mop.dest, state.readField(mop.src)); + } else if (mop is RiscVSetField) { + state.writeField(mop.dest, state.readSource(mop.src)); + } else if (mop is RiscVFpuOp) { + final aVal = state.readField(mop.a); + final bVal = mop.b != null ? state.readField(mop.b!) : 0; + final cVal = mop.c != null ? state.readField(mop.c!) : 0; + + double toF32(int bits) { + final bd = ByteData(4); + bd.setUint32(0, bits & 0xFFFFFFFF, Endian.little); + return bd.getFloat32(0, Endian.little); + } - switch (mop.condition) { - case MicroOpCondition.eq: - valid = value == mop.value; - break; - case MicroOpCondition.ne: - valid = value != mop.value; - break; - case MicroOpCondition.lt: - valid = value < mop.value; - break; - case MicroOpCondition.gt: - valid = value > mop.value; - break; - case MicroOpCondition.ge: - valid = value >= mop.value; - break; - case MicroOpCondition.le: - valid = value <= mop.value; - break; - default: - throw 'Invalid condition: ${mop.condition}'; + double toF64(int bits) { + final bd = ByteData(8); + bd.setUint64(0, bits, Endian.little); + return bd.getFloat64(0, Endian.little); } - if (!valid) { - state.pc = trap( - state.pc, - TrapException.illegalInstruction(StackTrace.current), - ); + int fromF32(double v) { + final bd = ByteData(4); + bd.setFloat32(0, v, Endian.little); + return bd.getUint32(0, Endian.little); + } + + int fromF64(double v) { + final bd = ByteData(8); + bd.setFloat64(0, v, Endian.little); + return bd.getUint64(0, Endian.little); + } + + // fcvt int<->fp width/sign is carried in the rs2 field (NOT a register): + // bit1 = 64-bit (L) vs 32-bit (W), bit0 = unsigned vs signed. funct7 + // (captured in the op enum's precision) picks f32 vs f64. The HDL reads + // rs2 the same way, so fcvt.{w,wu,l,lu}.{s,d} stay in lockstep. + final cvtRs2 = state.readField(RiscVMicroOpField.rs2, register: false); + final cvtWide = (cvtRs2 & 2) != 0; + final cvtUns = (cvtRs2 & 1) != 0; + // Rounding mode from the instruction's funct3 (rm). 0=RNE, 1=RTZ, 2=RDN, + // 3=RUP, 4=RMM, 7=DYN. The frm CSR is not modelled, so DYN falls back to + // RNE (its reset value); the HDL does the same, keeping parity. + final cvtRmRaw = (state.ir.raw >> 12) & 0x7; + final cvtRm = cvtRmRaw == 7 ? 0 : cvtRmRaw; + // Round a float to an integer-valued double per rm (used before fp->int). + double roundRm(double f) { + if (f.isNaN || f.isInfinite) return f; + final t = f.truncateToDouble(); + final frac = f - t; + if (frac == 0.0) return f; + switch (cvtRm) { + case 1: // RTZ + return t; + case 2: // RDN (toward -inf) + return f.floorToDouble(); + case 3: // RUP (toward +inf) + return f.ceilToDouble(); + case 4: // RMM (nearest, ties away from zero) == Dart round() + return f.roundToDouble(); + default: // RNE (nearest, ties to even) + final af = frac.abs(); + final step = f.isNegative ? -1.0 : 1.0; + if (af < 0.5) return t; + if (af > 0.5) return t + step; + // exact tie: round to the even neighbour + return (t % 2.0 == 0.0) ? t : t + step; + } + } + + // fp -> int with RISC-V rounding (per rm) then saturation: NaN -> max + // (unsigned: all-ones), out-of-range saturates to the destination min/max. + // 32-bit results are sign-extended to XLEN (even unsigned). + int fpToInt(double fRaw) { + final f = roundRm(fRaw); + if (cvtWide) { + if (cvtUns) { + if (f.isNaN || f >= 18446744073709551616.0) return -1; + if (f <= 0.0) return 0; + return BigInt.from(f).toSigned(64).toInt(); + } + if (f.isNaN || f >= 9223372036854775808.0) { + return 0x7FFFFFFFFFFFFFFF; + } + if (f < -9223372036854775808.0) return -0x8000000000000000; + return f.toInt(); + } + if (cvtUns) { + int u; + if (f.isNaN || f >= 4294967296.0) { + u = 0xFFFFFFFF; + } else if (f <= 0.0) { + u = 0; + } else { + u = f.toInt(); + } + return u.toSigned(32); + } + int s; + if (f.isNaN || f >= 2147483648.0) { + s = 0x7FFFFFFF; + } else if (f < -2147483648.0) { + s = -2147483648; + } else { + s = f.toInt(); + } + return s.toSigned(32); + } + + // int -> fp: interpret the source register per width+sign from rs2. + double intToFpVal(int raw) { + if (cvtWide) { + if (cvtUns) { + return raw >= 0 + ? raw.toDouble() + : BigInt.from(raw).toUnsigned(64).toDouble(); + } + return raw.toDouble(); + } + final lo = raw & 0xFFFFFFFF; + return cvtUns ? lo.toDouble() : lo.toSigned(32).toDouble(); + } + + double a, b, c; + if (mop.doublePrecision) { + a = toF64(aVal); + b = toF64(bVal); + c = toF64(cVal); + } else { + a = toF32(aVal); + b = toF32(bVal); + c = toF32(cVal); + } + + int result; + switch (mop.funct) { + case RiscVFpuFunct.fadd: + result = mop.doublePrecision ? fromF64(a + b) : fromF32(a + b); + // Fused multiply-add: rd = +-(a*b) +- c. The product a*b is a Dart + // f64, so it is computed at higher precision before the add (as the + // fused op intends); fromF32 rounds the final result to single. + case RiscVFpuFunct.fmadd: + result = mop.doublePrecision + ? fromF64(a * b + c) + : fromF32(a * b + c); + case RiscVFpuFunct.fmsub: + result = mop.doublePrecision + ? fromF64(a * b - c) + : fromF32(a * b - c); + case RiscVFpuFunct.fnmsub: + result = mop.doublePrecision + ? fromF64(-(a * b) + c) + : fromF32(-(a * b) + c); + case RiscVFpuFunct.fnmadd: + result = mop.doublePrecision + ? fromF64(-(a * b) - c) + : fromF32(-(a * b) - c); + case RiscVFpuFunct.fsub: + result = mop.doublePrecision ? fromF64(a - b) : fromF32(a - b); + case RiscVFpuFunct.fmul: + result = mop.doublePrecision ? fromF64(a * b) : fromF32(a * b); + case RiscVFpuFunct.fdiv: + result = mop.doublePrecision ? fromF64(a / b) : fromF32(a / b); + case RiscVFpuFunct.fsqrt: + result = mop.doublePrecision + ? fromF64(math.sqrt(a)) + : fromF32(math.sqrt(a)); + case RiscVFpuFunct.feq: + result = a == b ? 1 : 0; + case RiscVFpuFunct.flt: + result = a < b ? 1 : 0; + case RiscVFpuFunct.fle: + result = a <= b ? 1 : 0; + // f32/f64 -> int (width+sign from rs2). fcvtWS/fcvtLS both name the + // f32->int family; the actual width/sign comes from rs2 via fpToInt. + case RiscVFpuFunct.fcvtWS || RiscVFpuFunct.fcvtLS: + result = fpToInt(toF32(aVal)); + case RiscVFpuFunct.fcvtWD || RiscVFpuFunct.fcvtLD: + result = fpToInt(toF64(aVal)); + // int -> f32/f64 (width+sign from rs2). + case RiscVFpuFunct.fcvtSW || RiscVFpuFunct.fcvtSL: + result = fromF32(intToFpVal(aVal)); + case RiscVFpuFunct.fcvtDW || RiscVFpuFunct.fcvtDL: + result = fromF64(intToFpVal(aVal)); + case RiscVFpuFunct.fcvtSD: + result = fromF32(toF64(aVal)); + case RiscVFpuFunct.fcvtDS: + result = fromF64(toF32(aVal)); + case RiscVFpuFunct.fmv: + result = aVal; + case RiscVFpuFunct.fclass: + final v = mop.doublePrecision ? toF64(aVal) : toF32(aVal); + if (v.isNaN) { + result = (aVal >> (mop.doublePrecision ? 51 : 22)) & 1 == 1 + ? 0x200 + : 0x100; + } else if (v.isInfinite) { + result = v.isNegative ? 0x1 : 0x80; + } else if (v == 0.0) { + result = aVal == 0 ? 0x10 : 0x8; + } else { + final isDenorm = mop.doublePrecision + ? (aVal >> 52) & 0x7FF == 0 + : (aVal >> 23) & 0xFF == 0; + if (v.isNegative) { + result = isDenorm ? 0x4 : 0x2; + } else { + result = isDenorm ? 0x20 : 0x40; + } + } + case RiscVFpuFunct.fsgnj: + final signB = mop.doublePrecision + ? (bVal >> 63) & 1 + : (bVal >> 31) & 1; + final mask = mop.doublePrecision ? (1 << 63) - 1 : (1 << 31) - 1; + result = (aVal & mask) | (signB << (mop.doublePrecision ? 63 : 31)); + case RiscVFpuFunct.fsgnjn: + final signB = mop.doublePrecision + ? (bVal >> 63) & 1 + : (bVal >> 31) & 1; + final mask = mop.doublePrecision ? (1 << 63) - 1 : (1 << 31) - 1; + result = + (aVal & mask) | + ((1 - signB) << (mop.doublePrecision ? 63 : 31)); + case RiscVFpuFunct.fsgnjx: + final signA = mop.doublePrecision + ? (aVal >> 63) & 1 + : (aVal >> 31) & 1; + final signB = mop.doublePrecision + ? (bVal >> 63) & 1 + : (bVal >> 31) & 1; + final mask = mop.doublePrecision ? (1 << 63) - 1 : (1 << 31) - 1; + result = + (aVal & mask) | + ((signA ^ signB) << (mop.doublePrecision ? 63 : 31)); + case RiscVFpuFunct.fmin: + result = mop.doublePrecision + ? fromF64(a < b ? a : b) + : fromF32(a < b ? a : b); + case RiscVFpuFunct.fmax: + result = mop.doublePrecision + ? fromF64(a > b ? a : b) + : fromF32(a > b ? a : b); + } + + state.writeField(mop.dest, result); + } else if (mop is RiscVFenceOp) { + l1i?.reset(); + l1d?.reset(); + } else if (mop is RiscVHypervisorFenceOp) { + // HFENCE.VVMA / HFENCE.GVMA: with a single shared TLB model, flush all. + mmu.flushTlb(); + } else if (mop is RiscVHypervisorMemOp) { + // HLV/HSV: access guest memory using two-stage (VS + G) translation. + final vsatp = csrs.read(CsrAddress.vsatp.address, this); + final hgatp = csrs.read(CsrAddress.hgatp.address, this); + final gva = state.readField(mop.base); + final bytes = mop.size.bytes; + try { + if (mop.isStore) { + final hpa = await mmu.translateGuest( + gva, + MemoryAccess.write, + vsatpVal: vsatp, + hgatpVal: hgatp, + ); + await mmu.write( + hpa, + state.readField(mop.dest), + bytes, + pageTranslate: false, + ); + } else { + final hpa = await mmu.translateGuest( + gva, + MemoryAccess.read, + vsatpVal: vsatp, + hgatpVal: hgatp, + ); + var value = await mmu.read(hpa, bytes, pageTranslate: false); + if (!mop.unsigned && bytes < 8) value = value.toSigned(bytes * 8); + // The HLV microcode has no trailing RiscVWriteRegister, so commit the + // loaded value to the register file here (mirroring that handler). + final reg = + Register.values[state.readField(mop.dest, register: false)]; + if (reg != Register.x0) { + xregs[reg] = value; + if (reg == Register.x2) state.sp = value; + } + } + } on TrapException catch (e) { + // A two-stage fault (regular VS-stage cause, or a guest cause from the + // G-stage) traps like any other memory access. + state.pc = trap(state.pc, e); return state; } - } else if (mop is SetFieldMicroOp) { - state.writeField(mop.field, mop.value); - } else if (mop is TlbFenceMicroOp) { - // TODO: once MMU has a TLB - } else if (mop is TlbInvalidateMicroOp) { - // TODO: once MMU has a TLB - } else if (mop is FenceMicroOp) { - // Do nothing - } else { - throw 'Invalid micro-op $mop'; } } return state; } + /// Special-cased execution of the V (vector) extension. Returns the next PC + /// when [instr] is a vector op, else null so [cycle] uses the normal path. + /// Emulator-first: handles OP-V / vector load-store opcodes directly against + /// [vregs] + vl/vtype, bypassing the (stub) rv_v microcode. + Future executeVector(int pc, int instr) async { + if (!hasVector) return null; + final opcode = instr & 0x7F; + final funct3 = (instr >> 12) & 0x7; + const opV = 0x57, vLoad = 0x07, vStore = 0x27; + bool vWidth(int f) => f == 0 || f == 5 || f == 6 || f == 7; + int reg(int field) => xregs[Register.values[field]] ?? 0; + const widthSew = {0: 8, 5: 16, 6: 32, 7: 64}; + + if (opcode == opV && funct3 == 7) { + // vset{i}vl{i}: configure vtype/vl. vl = min(AVL, VLMAX). + final rd = (instr >> 7) & 0x1F; + final rs1 = (instr >> 15) & 0x1F; + final int newVtype; + int avl; // -1 = "use VLMAX" (rs1=x0, rd!=x0) + if (((instr >> 30) & 0x3) == 0x3) { + newVtype = (instr >> 20) & 0x3FF; // vsetivli: vtype=zimm[9:0] + avl = rs1; // uimm5 in the rs1 field + } else if (((instr >> 31) & 1) == 1) { + newVtype = reg((instr >> 20) & 0x1F); // vsetvl: vtype from rs2 + avl = rs1 != 0 ? reg(rs1) : (rd != 0 ? -1 : vl); + } else { + newVtype = (instr >> 20) & 0x7FF; // vsetvli: vtype=zimm[10:0] + avl = rs1 != 0 ? reg(rs1) : (rd != 0 ? -1 : vl); + } + final sew = 8 << ((newVtype >> 3) & 0x7); + final lmulField = newVtype & 0x7; + final vlmax = lmulField <= 3 + ? (config.vlen * (1 << lmulField)) ~/ sew + : (config.vlen ~/ sew) >> (8 - lmulField); + vtype = newVtype; + vstart = 0; + vl = avl < 0 ? vlmax : (avl < vlmax ? avl : vlmax); + if (rd != 0) xregs[Register.values[rd]] = vl; + return pc + 4; + } + + if (opcode == opV && + (funct3 == 2 || funct3 == 6) && + ((instr >> 26) & 0x3F) == 0x10) { + // funct6=0x10: scalar<->vector moves and mask popcount/first. + final vd = (instr >> 7) & 0x1F; + final f1 = (instr >> 15) & 0x1F; // sub-op (OPMVV) / rs1 (OPMVX) + final vs2 = (instr >> 20) & 0x1F; + final sew = 8 << ((vtype >> 3) & 0x7); + if (funct3 == 6) { + // vmv.s.x: v[vd][0] = x[rs1]; element 0 only. + vwriteElem(vd, 0, sew, reg(f1)); + vstart = 0; + return pc + 4; + } + final rd = vd; // OPMVV: bits[11:7] is the int dest + if (f1 == 0x00) { + // vmv.x.s: x[rd] = sign-extended v[vs2][0] + final e = vreadElem(vs2, 0, sew); + final v = sew >= 64 ? e : e.toSigned(sew); + if (rd != 0) xregs[Register.values[rd]] = v; + } else if (f1 == 0x10) { + // vcpop.m: count set mask bits over vl + var cnt = 0; + for (var i = vstart; i < vl; i++) { + if (((vregs[vs2][i >> 3] >> (i & 7)) & 1) == 1) cnt++; + } + if (rd != 0) xregs[Register.values[rd]] = cnt; + } else if (f1 == 0x11) { + // vfirst.m: index of first set mask bit, or -1 + var idx = -1; + for (var i = vstart; i < vl; i++) { + if (((vregs[vs2][i >> 3] >> (i & 7)) & 1) == 1) { + idx = i; + break; + } + } + if (rd != 0) xregs[Register.values[rd]] = idx; + } + vstart = 0; + return pc + 4; + } + + if (opcode == opV && + funct3 == 2 && + ((instr >> 26) & 0x3F) >= 0x18 && + ((instr >> 26) & 0x3F) <= 0x1F) { + // Mask logical ops (.mm): per-element bit of v[vd] = v[vs2] op v[vs1]. + // Always unmasked, operate over vl bits. + final funct6 = (instr >> 26) & 0x3F; + final vd = (instr >> 7) & 0x1F; + final vs1 = (instr >> 15) & 0x1F; + final vs2 = (instr >> 20) & 0x1F; + for (var i = vstart; i < vl; i++) { + final a = (vregs[vs2][i >> 3] >> (i & 7)) & 1; + final b = (vregs[vs1][i >> 3] >> (i & 7)) & 1; + final r = switch (funct6) { + 0x18 => a & (~b & 1), // vmandn + 0x19 => a & b, // vmand + 0x1A => a | b, // vmor + 0x1B => a ^ b, // vmxor + 0x1C => a | (~b & 1), // vmorn + 0x1D => (~(a & b)) & 1, // vmnand + 0x1E => (~(a | b)) & 1, // vmnor + _ => (~(a ^ b)) & 1, // 0x1F vmxnor + }; + if (r == 1) { + vregs[vd][i >> 3] |= (1 << (i & 7)); + } else { + vregs[vd][i >> 3] &= ~(1 << (i & 7)); + } + } + vstart = 0; + return pc + 4; + } + + if (opcode == opV && + (funct3 == 0 || funct3 == 3 || funct3 == 4) && + ((instr >> 26) & 0x3F) == 0x0C) { + // vrgather: vd[i] = (idx < VLMAX) ? vs2[idx] : 0. idx from vs1[i] (.vv) / + // x[rs1] (.vx) / uimm5 (.vi). + final vm = (instr >> 25) & 0x1; + final vd = (instr >> 7) & 0x1F; + final f1 = (instr >> 15) & 0x1F; + final vs2 = (instr >> 20) & 0x1F; + final sew = 8 << ((vtype >> 3) & 0x7); + final mask = sew >= 64 ? -1 : ((1 << sew) - 1); + final vlmax = config.vlen ~/ sew; + final scalarIdx = funct3 == 4 ? reg(f1) : f1; // .vx reg / .vi uimm5 + bool active(int i) => vm == 1 || ((vregs[0][i >> 3] >> (i & 7)) & 1) == 1; + for (var i = vstart; i < vl; i++) { + if (!active(i)) continue; + final idx = funct3 == 0 ? vreadElem(f1, i, sew) : scalarIdx; + final v = (idx >= 0 && idx < vlmax) ? vreadElem(vs2, idx, sew) : 0; + vwriteElem(vd, i, sew, v & mask); + } + vstart = 0; + return pc + 4; + } + + if (opcode == opV && funct3 == 2 && ((instr >> 26) & 0x3F) == 0x17) { + // vcompress.vm: pack vs2 elements selected by mask v[vs1] into vd from 0. + final vd = (instr >> 7) & 0x1F; + final vs1 = (instr >> 15) & 0x1F; // mask source + final vs2 = (instr >> 20) & 0x1F; + final sew = 8 << ((vtype >> 3) & 0x7); + final mask = sew >= 64 ? -1 : ((1 << sew) - 1); + var dst = 0; + for (var i = vstart; i < vl; i++) { + if (((vregs[vs1][i >> 3] >> (i & 7)) & 1) == 1) { + vwriteElem(vd, dst, sew, vreadElem(vs2, i, sew) & mask); + dst++; + } + } + vstart = 0; + return pc + 4; + } + + if (opcode == opV && + funct3 == 6 && + (((instr >> 26) & 0x3F) == 0x0E || ((instr >> 26) & 0x3F) == 0x0F)) { + // vslide1up (0x0E) / vslide1down (0x0F): shift by one, inserting x[rs1]. + final vm = (instr >> 25) & 0x1; + final vd = (instr >> 7) & 0x1F; + final f1 = (instr >> 15) & 0x1F; // rs1 (scalar inserted) + final vs2 = (instr >> 20) & 0x1F; + final sew = 8 << ((vtype >> 3) & 0x7); + final mask = sew >= 64 ? -1 : ((1 << sew) - 1); + final up = ((instr >> 26) & 0x3F) == 0x0E; + bool active(int i) => vm == 1 || ((vregs[0][i >> 3] >> (i & 7)) & 1) == 1; + for (var i = vstart; i < vl; i++) { + if (!active(i)) continue; + final int v; + if (up) { + v = i == 0 ? reg(f1) : vreadElem(vs2, i - 1, sew); + } else { + v = i == vl - 1 ? reg(f1) : vreadElem(vs2, i + 1, sew); + } + vwriteElem(vd, i, sew, v & mask); + } + vstart = 0; + return pc + 4; + } + + if (opcode == opV && + (funct3 == 3 || funct3 == 4) && + (((instr >> 26) & 0x3F) == 0x0E || ((instr >> 26) & 0x3F) == 0x0F)) { + // vslideup (0x0E) / vslidedown (0x0F): shift elements by an offset + // (x[rs1] for .vx, uimm5 for .vi). + final funct6 = (instr >> 26) & 0x3F; + final vm = (instr >> 25) & 0x1; + final vd = (instr >> 7) & 0x1F; + final f1 = (instr >> 15) & 0x1F; + final vs2 = (instr >> 20) & 0x1F; + final sew = 8 << ((vtype >> 3) & 0x7); + final mask = sew >= 64 ? -1 : ((1 << sew) - 1); + final vlmax = config.vlen ~/ sew; + final offset = funct3 == 4 ? reg(f1) : f1; // .vx reg, .vi uimm5 + final up = funct6 == 0x0E; + bool active(int i) => vm == 1 || ((vregs[0][i >> 3] >> (i & 7)) & 1) == 1; + for (var i = vstart; i < vl; i++) { + if (!active(i)) continue; + if (up) { + if (i < offset) continue; // vd[0..offset-1] undisturbed + vwriteElem(vd, i, sew, vreadElem(vs2, i - offset, sew) & mask); + } else { + final src = i + offset; + final v = src < vlmax + ? vreadElem(vs2, src, sew) + : 0; // past VLMAX => 0 + vwriteElem(vd, i, sew, v & mask); + } + } + vstart = 0; + return pc + 4; + } + + if (opcode == opV && + funct3 == 1 && + ((instr >> 26) & 0x3F) == 0x12 && + ((instr >> 15) & 0x1F) >= 0x08) { + // Widening / narrowing converts (VFUNARY0, funct6=0x12, vs1>=0x08): + // vs1 0x08-0x0F widen SEW->2*SEW, 0x10-0x17 narrow 2*SEW->SEW. The low 3 + // bits of vs1 select the kind: xu.f float->uint (0/6=rtz), x.f float->int + // (1/7=rtz), f.xu uint->float (2), f.x int->float (3), f.f float->float + // (4; 5=rod narrow). (Same-width vfcvt + vfclass are in the OPFV block + // below; SEW=16/Zvfh deferred.) + final vm = (instr >> 25) & 0x1; + final vd = (instr >> 7) & 0x1F; + final vs1sel = (instr >> 15) & 0x1F; + final vs2 = (instr >> 20) & 0x1F; + final sew = 8 << ((vtype >> 3) & 0x7); + final narrow = vs1sel >= 0x10; + final srcSew = narrow ? sew * 2 : sew; + final dstSew = narrow ? sew : sew * 2; + final dmask = dstSew >= 64 ? -1 : ((1 << dstSew) - 1); + // float->int saturation bounds at the destination width (RISC-V fcvt: + // NaN/overflow saturate; truncate toward zero). + final dsmax = dstSew >= 64 ? 0x7FFFFFFFFFFFFFFF : (1 << (dstSew - 1)) - 1; + final dsmin = dstSew >= 64 ? (1 << 63) : -(1 << (dstSew - 1)); + // Double base (2.0): 2^63/2^64 overflow a signed int, so an int base + // would wrap negative and break the saturation comparisons. + final dp2 = math.pow(2.0, dstSew).toDouble(); // 2^dstSew + final dp2m1 = math.pow(2.0, dstSew - 1).toDouble(); // 2^(dstSew-1) + double srcUToDouble(int bits) => srcSew >= 64 + ? (bits >= 0 + ? bits.toDouble() + : bits.toDouble() + math.pow(2.0, srcSew).toDouble()) + : (bits & ((1 << srcSew) - 1)).toDouble(); + final kind = vs1sel & 0x7; // low 3 bits select the conversion kind + bool active(int i) => vm == 1 || ((vregs[0][i >> 3] >> (i & 7)) & 1) == 1; + for (var i = vstart; i < vl; i++) { + if (!active(i)) continue; + final aBits = vreadElem(vs2, i, srcSew); + // Float reinterpretation of the source (used by the float->* kinds; a + // harmless no-op double for the int-source f.x/f.xu kinds). + final a = fpBitsToDouble(aBits, srcSew); + final r = switch (kind) { + // f.f float->float (widen 0x0C / narrow 0x14; 0x15 rod ~ f.f) + 0x4 || 0x5 => fpDoubleToBits(a, dstSew) & dmask, + // xu.f float->unsigned int (0x6 = rtz) + 0x0 || 0x6 => + a.isNaN ? dmask : (a <= 0 ? 0 : (a >= dp2 ? dmask : a.toInt())), + // x.f float->signed int (0x7 = rtz) + 0x1 || 0x7 => + (a.isNaN + ? dsmax + : (a >= dp2m1 ? dsmax : (a < -dp2m1 ? dsmin : a.toInt()))) & + dmask, + // f.xu unsigned int->float + 0x2 => fpDoubleToBits(srcUToDouble(aBits), dstSew) & dmask, + // f.x signed int->float + 0x3 => + fpDoubleToBits(aBits.toSigned(srcSew).toDouble(), dstSew) & dmask, + _ => aBits & dmask, + }; + vwriteElem(vd, i, dstSew, r); + } + vstart = 0; + return pc + 4; + } + + if (opcode == opV && + (funct3 == 1 || funct3 == 5) && + ((instr >> 26) & 0x3F) >= 0x30 && + ((instr >> 26) & 0x3F) <= 0x3F) { + // FP widening (.vv/.vf): result is 2*SEW float. vfwadd/vfwsub/vfwmul. + final funct6 = (instr >> 26) & 0x3F; + final vm = (instr >> 25) & 0x1; + final vd = (instr >> 7) & 0x1F; + final f1 = (instr >> 15) & 0x1F; + final vs2 = (instr >> 20) & 0x1F; + final sew = 8 << ((vtype >> 3) & 0x7); + final wsew = sew * 2; + final isVf = funct3 == 5; + final scalar = isVf + ? fpBitsToDouble(reg(f1) & (sew >= 64 ? -1 : ((1 << sew) - 1)), sew) + : 0.0; + bool active(int i) => vm == 1 || ((vregs[0][i >> 3] >> (i & 7)) & 1) == 1; + for (var i = vstart; i < vl; i++) { + if (!active(i)) continue; + final a = fpBitsToDouble(vreadElem(vs2, i, sew), sew); + final b = isVf ? scalar : fpBitsToDouble(vreadElem(f1, i, sew), sew); + final double r = switch (funct6) { + 0x30 => a + b, // vfwadd + 0x32 => a - b, // vfwsub + 0x38 => a * b, // vfwmul + _ => a, + }; + vwriteElem(vd, i, wsew, fpDoubleToBits(r, wsew)); + } + vstart = 0; + return pc + 4; + } + + if (opcode == opV && (funct3 == 1 || funct3 == 5)) { + // Vector floating-point: OPFVV (.vv, funct3==1) and OPFVF (.vf, + // funct3==5; second operand is the FP scalar in x[rs1], the emulator + // uses a unified regfile). SEW selects float(32)/double(64). Includes + // same-width vfcvt (funct6 0x12) and vfclass (0x13). (SEW=16/Zvfh + // deferred.) + final funct6 = (instr >> 26) & 0x3F; + final vm = (instr >> 25) & 0x1; + final vd = (instr >> 7) & 0x1F; + final vs1 = (instr >> 15) & 0x1F; // vs1 (.vv) / rs1 scalar (.vf) + final vs2 = (instr >> 20) & 0x1F; + final sew = 8 << ((vtype >> 3) & 0x7); + final mask = sew >= 64 ? -1 : ((1 << sew) - 1); + final signMask = 1 << (sew - 1); + final isVf = funct3 == 5; + final scalarBits = isVf ? (reg(vs1) & mask) : 0; + // float<->int conversion bounds (RISC-V fcvt: NaN/overflow saturate). + final smax = sew >= 64 ? 0x7FFFFFFFFFFFFFFF : (1 << (sew - 1)) - 1; + final smin = sew >= 64 ? (1 << 63) : -(1 << (sew - 1)); + // Double base (2.0): 2^64 overflows a signed int at SEW=64. + final p2 = math.pow(2.0, sew).toDouble(); // 2^SEW + final p2m1 = math.pow(2.0, sew - 1).toDouble(); // 2^(SEW-1) + double uToDouble(int bits) => sew >= 64 + ? (bits >= 0 ? bits.toDouble() : bits.toDouble() + p2) + : (bits & mask).toDouble(); + // vfclass: 10-bit classification (bit0 -inf … bit9 qNaN). + int classify(double v, int bits) { + final sign = (bits & signMask) != 0; + if (v.isNaN) { + final quiet = sew >= 64 ? (1 << 51) : (1 << 22); + return (bits & quiet) != 0 ? (1 << 9) : (1 << 8); + } + if (v.isInfinite) return sign ? 1 : (1 << 7); + if (v == 0.0) return sign ? (1 << 3) : (1 << 4); + final expMask = sew >= 64 ? (0x7FF << 52) : (0xFF << 23); + if ((bits & expMask) == 0) + return sign ? (1 << 2) : (1 << 5); // subnormal + return sign ? (1 << 1) : (1 << 6); // normal + } + + bool active(int i) => vm == 1 || ((vregs[0][i >> 3] >> (i & 7)) & 1) == 1; + // Compares write a bit-per-element mask to v[vd] (NaN => false except + // vmfne; Dart's comparisons already match that ordering). vmfgt/vmfge are + // .vf-only. + final isCompare = + funct6 == 0x18 || // vmfeq + funct6 == 0x19 || // vmfle + funct6 == 0x1B || // vmflt + funct6 == 0x1C || // vmfne + funct6 == 0x1D || // vmfgt (.vf) + funct6 == 0x1F; // vmfge (.vf) + // Reductions (.vs): vd[0] = reduce(vs1[0], all active vs2 elements). + final isReduce = + funct6 == 0x01 || // vfredusum + funct6 == 0x03 || // vfredosum + funct6 == 0x05 || // vfredmin + funct6 == 0x07; // vfredmax + if (isReduce) { + var acc = fpBitsToDouble(vreadElem(vs1, 0, sew), sew); + for (var i = vstart; i < vl; i++) { + if (!active(i)) continue; + final e = fpBitsToDouble(vreadElem(vs2, i, sew), sew); + acc = switch (funct6) { + 0x01 || 0x03 => acc + e, + 0x05 => acc < e ? acc : e, + _ => acc > e ? acc : e, // 0x07 + }; + } + vwriteElem(vd, 0, sew, fpDoubleToBits(acc, sew) & mask); + vstart = 0; + return pc + 4; + } + for (var i = vstart; i < vl; i++) { + if (!active(i)) continue; + final aBits = vreadElem(vs2, i, sew); + final bBits = isVf ? scalarBits : vreadElem(vs1, i, sew); + final a = fpBitsToDouble(aBits, sew); + final b = fpBitsToDouble(bBits, sew); + if (isCompare) { + final cmp = switch (funct6) { + 0x18 => a == b, + 0x19 => a <= b, + 0x1B => a < b, + 0x1D => a > b, // vmfgt (.vf) + 0x1F => a >= b, // vmfge (.vf) + _ => a != b, // 0x1C vmfne + }; + if (cmp) { + vregs[vd][i >> 3] |= (1 << (i & 7)); + } else { + vregs[vd][i >> 3] &= ~(1 << (i & 7)); + } + continue; + } + // vd element, used as the third operand by the fused multiply-adds. + final d = fpBitsToDouble(vreadElem(vd, i, sew), sew); + final int r; + switch (funct6) { + case 0x00: // vfadd + r = fpDoubleToBits(a + b, sew); + case 0x02: // vfsub + r = fpDoubleToBits(a - b, sew); + case 0x24: // vfmul + r = fpDoubleToBits(a * b, sew); + case 0x20: // vfdiv + r = fpDoubleToBits(a / b, sew); + case 0x04: // vfmin + r = fpDoubleToBits(a < b ? a : b, sew); + case 0x06: // vfmax + r = fpDoubleToBits(a > b ? a : b, sew); + case 0x08: // vfsgnj: sign of b, magnitude of a + r = (aBits & ~signMask) | (bBits & signMask); + case 0x09: // vfsgnjn: ~sign of b + r = (aBits & ~signMask) | ((~bBits) & signMask); + case 0x0A: // vfsgnjx: sign a^b + r = aBits ^ (bBits & signMask); + case 0x12: // vfunary0 = vfcvt; vs1 selects direction + r = switch (vs1) { + 0x02 => fpDoubleToBits( + uToDouble(aBits), + sew, + ), // f.xu: uint->float + 0x03 => fpDoubleToBits( + aBits.toSigned(sew).toDouble(), + sew, + ), // f.x: int->float + 0x00 || 0x06 => + a + .isNaN // xu.f: float->uint (rtz, saturate) + ? mask + : (a <= 0 ? 0 : (a >= p2 ? mask : a.toInt())), + 0x01 || 0x07 => + a + .isNaN // x.f: float->int (rtz, saturate) + ? smax + : (a >= p2m1 ? smax : (a < -p2m1 ? smin : a.toInt())), + _ => aBits, + }; + case 0x13: // vfunary1: vs1=0 vfsqrt, vs1=0x10 vfclass + r = vs1 == 0x00 + ? fpDoubleToBits(math.sqrt(a), sew) + : (vs1 == 0x10 ? classify(a, aBits) : aBits); + // Fused multiply-add family (a=vs2, b=vs1, d=vd). The *macc forms use + // vd as the addend; the *madd forms use vd as a multiplicand. + case 0x2C: // vfmacc: vd = a*b + vd + r = fpDoubleToBits(a * b + d, sew); + case 0x2D: // vfnmacc: vd = -(a*b) - vd + r = fpDoubleToBits(-(a * b) - d, sew); + case 0x2E: // vfmsac: vd = a*b - vd + r = fpDoubleToBits(a * b - d, sew); + case 0x2F: // vfnmsac: vd = -(a*b) + vd + r = fpDoubleToBits(-(a * b) + d, sew); + case 0x28: // vfmadd: vd = b*vd + a + r = fpDoubleToBits(b * d + a, sew); + case 0x29: // vfnmadd: vd = -(b*vd) - a + r = fpDoubleToBits(-(b * d) - a, sew); + case 0x2A: // vfmsub: vd = b*vd - a + r = fpDoubleToBits(b * d - a, sew); + case 0x2B: // vfnmsub: vd = -(b*vd) + a + r = fpDoubleToBits(-(b * d) + a, sew); + default: + r = aBits; + } + vwriteElem(vd, i, sew, r & mask); + } + vstart = 0; + return pc + 4; + } + + if (opcode == opV && + (funct3 == 0 || funct3 == 3 || funct3 == 4) && + (((instr >> 26) & 0x3F) == 0x2C || ((instr >> 26) & 0x3F) == 0x2D)) { + // Narrowing shift-right: vd[SEW] = (vs2[2*SEW] >> shamt). vnsrl (0x2C, + // logical) / vnsra (0x2D, arithmetic). shamt from vs1[SEW]/x[rs1]/uimm5. + final funct6 = (instr >> 26) & 0x3F; + final vm = (instr >> 25) & 0x1; + final vd = (instr >> 7) & 0x1F; + final f1 = (instr >> 15) & 0x1F; + final vs2 = (instr >> 20) & 0x1F; + final sew = 8 << ((vtype >> 3) & 0x7); + final wsew = sew * 2; + final mask = sew >= 64 ? -1 : ((1 << sew) - 1); + final scalar = funct3 == 4 ? reg(f1) : f1; // .wx reg / .wi uimm5 + bool active(int i) => vm == 1 || ((vregs[0][i >> 3] >> (i & 7)) & 1) == 1; + for (var i = vstart; i < vl; i++) { + if (!active(i)) continue; + final wide = vreadElem(vs2, i, wsew); + final sh = (funct3 == 0 ? vreadElem(f1, i, sew) : scalar) & (wsew - 1); + final r = funct6 == 0x2C + ? wide >>> + sh // vnsrl (logical) + : wide.toSigned(wsew) >> sh; // vnsra (arithmetic) + vwriteElem(vd, i, sew, r & mask); + } + vstart = 0; + return pc + 4; + } + + if (opcode == opV && funct3 == 2 && ((instr >> 26) & 0x3F) == 0x12) { + // vxunary0: vzext/vsext by factor 2/4/8 (vs1 selects). Source element is + // SEW/factor wide, result is SEW. + final vm = (instr >> 25) & 0x1; + final vd = (instr >> 7) & 0x1F; + final f1 = (instr >> 15) & 0x1F; + final vs2 = (instr >> 20) & 0x1F; + final sew = 8 << ((vtype >> 3) & 0x7); + final mask = sew >= 64 ? -1 : ((1 << sew) - 1); + final factor = f1 >= 0x06 ? 2 : (f1 >= 0x04 ? 4 : 8); + final signed = (f1 & 1) == 1; // odd vs1 => sext, even => zext + final ssew = sew ~/ factor; + final smask = ssew >= 64 ? -1 : ((1 << ssew) - 1); + bool active(int i) => vm == 1 || ((vregs[0][i >> 3] >> (i & 7)) & 1) == 1; + for (var i = vstart; i < vl; i++) { + if (!active(i)) continue; + final src = vreadElem(vs2, i, ssew); + final r = signed ? src.toSigned(ssew) : (src & smask); + vwriteElem(vd, i, sew, r & mask); + } + vstart = 0; + return pc + 4; + } + + if (opcode == opV && + (funct3 == 2 || funct3 == 6) && + ((instr >> 26) & 0x3F) >= 0x30 && + ((instr >> 26) & 0x3F) <= 0x3F) { + // Widening integer arithmetic: result is 2*SEW (spans the vd group, which + // the LMUL-aware element accessors handle). Valid for SEW<=32 (a 2*SEW=128 + // result for SEW=64 would need BigInt; truncated here). + final funct6 = (instr >> 26) & 0x3F; + final vm = (instr >> 25) & 0x1; + final vd = (instr >> 7) & 0x1F; + final f1 = (instr >> 15) & 0x1F; + final vs2 = (instr >> 20) & 0x1F; + final sew = 8 << ((vtype >> 3) & 0x7); + final wsew = sew * 2; + final wmask = wsew >= 64 ? -1 : ((1 << wsew) - 1); + final smask = sew >= 64 ? -1 : ((1 << sew) - 1); + int sx(int x) => x.toSigned(sew); // sign-extend from SEW + int zx(int x) => x & smask; // zero-extend from SEW + final scalar = funct3 == 6 ? reg(f1) : 0; + bool active(int i) => vm == 1 || ((vregs[0][i >> 3] >> (i & 7)) & 1) == 1; + for (var i = vstart; i < vl; i++) { + if (!active(i)) continue; + final aRaw = vreadElem(vs2, i, sew); + final bRaw = funct3 == 6 ? scalar : vreadElem(f1, i, sew); + final r = switch (funct6) { + 0x30 => zx(aRaw) + zx(bRaw), // vwaddu + 0x31 => sx(aRaw) + sx(bRaw), // vwadd + 0x32 => zx(aRaw) - zx(bRaw), // vwsubu + 0x33 => sx(aRaw) - sx(bRaw), // vwsub + 0x38 => zx(aRaw) * zx(bRaw), // vwmulu + 0x3A => sx(aRaw) * zx(bRaw), // vwmulsu + 0x3B => sx(aRaw) * sx(bRaw), // vwmul + _ => sx(aRaw), + }; + vwriteElem(vd, i, wsew, r & wmask); + } + vstart = 0; + return pc + 4; + } + + if (opcode == opV) { + // Integer / multiply vector arithmetic. funct6 = bits[31:26]; funct3 + // selects operand source & category: + // 0=OPIVV 3=OPIVI 4=OPIVX (integer), 2=OPMVV 6=OPMVX (mul/div/misc). + final funct6 = (instr >> 26) & 0x3F; + final vm = (instr >> 25) & 0x1; // 0 => element-masked by v0 + final vd = (instr >> 7) & 0x1F; + final f1 = (instr >> 15) & 0x1F; // vs1 (vv) / rs1 (vx) / simm5 (vi) + final vs2 = (instr >> 20) & 0x1F; + final sew = 8 << ((vtype >> 3) & 0x7); + final mask = sew >= 64 ? -1 : ((1 << sew) - 1); + final minInt = 1 << 63; + + int us(int x) => x & mask; // unsigned within SEW + int ss(int x) => x.toSigned(sew); // signed within SEW + bool ltu(int x, int y) => + sew < 64 ? us(x) < us(y) : (x ^ minInt) < (y ^ minInt); + BigInt big(int x, {required bool signed}) => signed + ? BigInt.from(ss(x)) + : BigInt.from(us(x)) & ((BigInt.one << sew) - BigInt.one); + bool active(int i) => vm == 1 || ((vregs[0][i >> 3] >> (i & 7)) & 1) == 1; + + final isMul = funct3 == 2 || funct3 == 6; // OPMVV / OPMVX + final isMerge = !isMul && funct6 == 0x17; // vmerge / vmv.v.* + // .vx/OPMVX scalar from rs1; .vi simm5; .vv/OPMVV take vs1 elements. + final scalar = (funct3 == 4 || funct3 == 6) ? reg(f1) : f1.toSigned(5); + + for (var i = vstart; i < vl; i++) { + // vmerge writes every element (selecting source by mask); ordinary + // masked ops leave inactive elements undisturbed. + if (!isMerge && !active(i)) continue; + final a = vreadElem(vs2, i, sew); + final b = (funct3 == 0 || funct3 == 2) + ? vreadElem(f1, i, sew) // .vv / OPMVV: vs1 element + : scalar; + final int r; + if (isMerge) { + r = active(i) ? b : a; // vm==1 => vmv.v (always b) + } else if (isMul) { + r = switch (funct6) { + 0x25 => a * b, // vmul (low bits) + 0x24 => + (big(a, signed: false) * big(b, signed: false) >> sew) + .toInt(), // vmulhu + 0x27 => + (big(a, signed: true) * big(b, signed: true) >> sew) + .toInt(), // vmulh + 0x26 => + (big(a, signed: true) * big(b, signed: false) >> sew) + .toInt(), // vmulhsu + 0x20 => us(b) == 0 ? -1 : us(a) ~/ us(b), // vdivu (/0 => all-ones) + 0x21 => ss(b) == 0 ? -1 : ss(a) ~/ ss(b), // vdiv + 0x22 => us(b) == 0 ? a : us(a) % us(b), // vremu (/0 => dividend) + 0x23 => ss(b) == 0 ? a : ss(a).remainder(ss(b)), // vrem + 0x14 => i, // vid.v (element index) + _ => a, + }; + } else { + final sh = b & (sew - 1); + r = switch (funct6) { + 0x00 => a + b, // vadd + 0x02 => a - b, // vsub + 0x03 => b - a, // vrsub (.vx/.vi) + 0x04 => ltu(a, b) ? a : b, // vminu + 0x05 => ss(a) < ss(b) ? a : b, // vmin + 0x06 => ltu(a, b) ? b : a, // vmaxu + 0x07 => ss(a) < ss(b) ? b : a, // vmax + 0x09 => a & b, // vand + 0x0A => a | b, // vor + 0x0B => a ^ b, // vxor + 0x25 => a << sh, // vsll + 0x28 => us(a) >> sh, // vsrl (logical) + 0x29 => ss(a) >> sh, // vsra (arithmetic) + _ => a, + }; + } + vwriteElem(vd, i, sew, r & mask); + } + vstart = 0; + return pc + 4; + } + + // Unit-stride load/store only (mop bits[27:26] == 0). vm bit[25]: 0 masks + // by v0, skipping inactive elements (undisturbed/unmodified memory). + bool vActive(int vm, int i) => + vm == 1 || ((vregs[0][i >> 3] >> (i & 7)) & 1) == 1; + + // Unit-stride (mop==0) and strided (mop==2) loads. For strided the byte + // stride is x[rs2]; for unit-stride it is the element size. + if (opcode == vLoad && + vWidth(funct3) && + (((instr >> 26) & 0x3) == 0 || ((instr >> 26) & 0x3) == 2)) { + final mop = (instr >> 26) & 0x3; + final vm = (instr >> 25) & 0x1; + final vd = (instr >> 7) & 0x1F; + final base = reg((instr >> 15) & 0x1F); + final sew = widthSew[funct3]!; + final bytes = sew ~/ 8; + final stride = mop == 2 ? reg((instr >> 20) & 0x1F) : bytes; + for (var i = vstart; i < vl; i++) { + if (!vActive(vm, i)) continue; + vwriteElem(vd, i, sew, await mmu.read(base + i * stride, bytes)); + } + vstart = 0; + return pc + 4; + } + + if (opcode == vStore && + vWidth(funct3) && + (((instr >> 26) & 0x3) == 0 || ((instr >> 26) & 0x3) == 2)) { + final mop = (instr >> 26) & 0x3; + final vm = (instr >> 25) & 0x1; + final vs3 = (instr >> 7) & 0x1F; + final base = reg((instr >> 15) & 0x1F); + final sew = widthSew[funct3]!; + final bytes = sew ~/ 8; + final stride = mop == 2 ? reg((instr >> 20) & 0x1F) : bytes; + for (var i = vstart; i < vl; i++) { + if (!vActive(vm, i)) continue; + await mmu.write(base + i * stride, vreadElem(vs3, i, sew), bytes); + } + vstart = 0; + return pc + 4; + } + + return null; + } + Future cycle(int pc, int instr) async { - final op = config.microcode.lookup(instr); - if (op != null) { - final ir = op.decode(instr); - if (ir != null) { - var state = RiverCoreEmulatorState(pc, ir, xregs[Register.x2] ?? 0); - state = await _innerExecute(state, op); - xregs[Register.x2] = state.sp; - return state.pc; + // Only the V opcodes take the (async) vector path. Gate it so the common + // path doesn't gain an early await, some callers don't await cycle() and + // rely on it completing synchronously up to the first real suspension. + final op7 = instr & 0x7F; + if (hasVector && (op7 == 0x57 || op7 == 0x07 || op7 == 0x27)) { + final vec = await executeVector(pc, instr); + if (vec != null) return vec; + } + + RiscVOperation? op; + if ((instr & 0x3) != 0x3) { + final opcode = instr & 0x3; + final funct3 = (instr >> 13) & 0x7; + for (final ext in config.extensions) { + op = ext.findOperation( + opcode, + funct3: funct3, + instruction: instr, + mxlen: config.mxlen, + ); + if (op != null) break; } + } else { + op = config.isa.findOperation(instr); + } + + if (op != null) { + final ir = DecodedInstruction.decode(instr, op); + var state = RiverCoreState(pc, ir, xregs[Register.x2] ?? 0); + state = await _innerExecute(state, op); + xregs[Register.x2] = state.sp; + return state.pc; } return trap(pc, TrapException.illegalInstruction(StackTrace.current)); @@ -1264,7 +2511,6 @@ class RiverCoreEmulator { int? _nextPendingIrq() { int? bestIrq; - InterruptControllerEmulator? bestCtl; for (final ctl in _interrupts) { final irq = ctl.nextPending(); @@ -1272,7 +2518,6 @@ class RiverCoreEmulator { if (bestIrq == null || irq < bestIrq) { bestIrq = irq; - bestCtl = ctl; } } @@ -1285,36 +2530,86 @@ class RiverCoreEmulator { } final mideleg = csrs.read(CsrAddress.mideleg.address, this); - final delegated = ((mideleg >> Trap.machineExternal.mcauseCode) & 1) != 0; + final delegated = ((mideleg >> Trap.machineExternal.causeCode) & 1) != 0; return delegated ? Trap.supervisorExternal : Trap.machineExternal; } - Future runPipeline(int pc) async { - if (idle) return pc; + Future _handleInterrupt(PipelineContext ctx) async { + if (idle) { + ctx.halted = true; + return; + } final irq = _nextPendingIrq(); if (irq != null) { final mie = csrs.read(CsrAddress.mie.address, this); final mstatus = csrs.read(CsrAddress.mstatus.address, this); - final mieMeie = ((mie >> Trap.machineExternal.mcauseCode) & 1) != 0; + final mieMeie = ((mie >> Trap.machineExternal.causeCode) & 1) != 0; final mstatusMie = ((mstatus >> 3) & 1) != 0; if (mieMeie && mstatusMie) { final trapTarget = _selectExternalInterruptTrap(); - return trap(pc, TrapException(trapTarget)); + ctx.pc = trap(ctx.pc, TrapException(trapTarget)); + ctx.halted = true; + } + } + } + + Future _handleFetch(PipelineContext ctx) async { + ctx.instruction = await fetch(ctx.pc); + } + + Future _handleDecode(PipelineContext ctx) async { + final instr = ctx.instruction!; + + if ((instr & 0x3) != 0x3) { + final opcode = instr & 0x3; + final funct3 = (instr >> 13) & 0x7; + for (final ext in config.extensions) { + ctx.op = ext.findOperation( + opcode, + funct3: funct3, + instruction: instr, + mxlen: config.mxlen, + ); + if (ctx.op != null) break; } + } else { + ctx.op = config.isa.findOperation(instr); } + if (ctx.op != null) { + final ir = DecodedInstruction.decode(instr, ctx.op!); + ctx.state = RiverCoreState(ctx.pc, ir, xregs[Register.x2] ?? 0); + } + } + + Future _handleExecute(PipelineContext ctx) async { + if (ctx.op == null) { + ctx.pc = trap( + ctx.pc, + TrapException.illegalInstruction(StackTrace.current), + ); + return; + } + + final state = await _innerExecute(ctx.state!, ctx.op!); + xregs[Register.x2] = state.sp; + ctx.pc = state.pc; + } + + Future runPipeline(int pc) async { + final ctx = PipelineContext(pc); try { - int instr = await fetch(pc); - return await cycle(pc, instr); - } on TrapException catch (e, stack) { - return trap(pc, e); + await pipeline.run(ctx); + } on TrapException catch (e) { + ctx.pc = trap(ctx.pc, e); } + return ctx.pc; } @override String toString() => - 'RiverCoreEmulator(xregs: $xregs, mmu: $mmu, csrs: ${csrs.toStringWithCore(this)}, mode: $mode, interrupts: $interrupts)'; + 'RiverCore(xregs: $xregs, mmu: $mmu, csrs: ${csrs.toStringWithCore(this)}, mode: $mode, interrupts: $interrupts)'; } diff --git a/packages/river_emulator/lib/src/csr.dart b/packages/river_emulator/lib/src/csr.dart index 09ff4b2..09256d4 100644 --- a/packages/river_emulator/lib/src/csr.dart +++ b/packages/river_emulator/lib/src/csr.dart @@ -1,13 +1,20 @@ -import 'package:riscv/riscv.dart'; +import 'package:river/river.dart'; import 'core.dart'; +import 'mmu.dart'; + +abstract class CsrContext { + RiverCoreConfig get config; + PrivilegeMode get mode; + Mmu get mmu; +} abstract class Csr { final int address; const Csr(this.address); - int read(RiverCoreEmulator core); - void write(RiverCoreEmulator core, int value); + int read(CsrContext context); + void write(CsrContext context, int value); } class SimpleCsr extends Csr { @@ -16,10 +23,10 @@ class SimpleCsr extends Csr { SimpleCsr(super.address); @override - int read(RiverCoreEmulator core) => value; + int read(CsrContext context) => value; @override - void write(RiverCoreEmulator core, int newValue) { + void write(CsrContext context, int newValue) { value = newValue; } } @@ -30,10 +37,10 @@ class ReadOnlyCsr extends Csr { const ReadOnlyCsr(super.address, this.value); @override - int read(RiverCoreEmulator core) => value; + int read(CsrContext context) => value; @override - void write(RiverCoreEmulator _core, int _value) { + void write(CsrContext context, int value) { throw TrapException.illegalInstruction(); } } @@ -45,10 +52,10 @@ class MaskedCsr extends Csr { MaskedCsr(super.address, this.writableMask); @override - int read(RiverCoreEmulator core) => value; + int read(CsrContext context) => value; @override - void write(RiverCoreEmulator core, int newValue) { + void write(CsrContext context, int newValue) { value = (value & ~writableMask) | (newValue & writableMask); } } @@ -61,24 +68,47 @@ class LinkCsr extends Csr { const LinkCsr(super.address, this.target, {this.mask, this.writable = true}); @override - int read(RiverCoreEmulator core) { - final value = target.read(core); + int read(CsrContext context) { + final value = target.read(context); return mask != null ? (value & mask!) : value; } @override - void write(RiverCoreEmulator core, int newValue) { + void write(CsrContext context, int newValue) { if (!writable) { throw TrapException.illegalInstruction(); } if (mask != null) { final masked = newValue & mask!; - final preserved = target.read(core) & ~mask!; - target.write(core, preserved | masked); + final preserved = target.read(context) & ~mask!; + target.write(context, preserved | masked); } else { - target.write(core, newValue); + target.write(context, newValue); + } + } +} + +/// A CSR whose value is backed by live state elsewhere in the core (e.g. the +/// vector unit's vl/vtype, which are not a plain register in the CSR file). +/// [readValue] returns the current value; [writeValue] applies a write, or is +/// null for a read-only CSR (writes raise illegal-instruction). +class CallbackCsr extends Csr { + final int Function() readValue; + final void Function(int value)? writeValue; + + const CallbackCsr(super.address, this.readValue, [this.writeValue]); + + @override + int read(CsrContext context) => readValue(); + + @override + void write(CsrContext context, int value) { + final w = writeValue; + if (w == null) { + throw TrapException.illegalInstruction(); } + w(value); } } @@ -86,21 +116,23 @@ class IdCsr extends Csr { const IdCsr(super.address); @override - int read(RiverCoreEmulator core) => switch (CsrAddress.find(address)) { - CsrAddress.mvendorid => core.config.vendorId, - CsrAddress.marchid => core.config.archId, - CsrAddress.mimpid => core.config.impId, - CsrAddress.mhartid => core.config.hartId, + int read(CsrContext context) => switch (CsrAddress.find(address)) { + CsrAddress.mvendorid => context.config.vendorId, + CsrAddress.marchid => context.config.archId, + CsrAddress.mimpid => context.config.impId, + CsrAddress.mhartid => context.config.hartId, CsrAddress.misa => - core.config.extensions.map((ext) => ext.mask).fold(0, (t, i) => t | i) | - core.config.mxlen.misa | - ((core.config.hasSupervisor ? 1 : 0) << 18) | - ((core.config.hasUser ? 1 : 0) << 20), + context.config.extensions + .map((ext) => ext.mask) + .fold(0, (t, i) => t | i) | + context.config.mxlen.misa | + ((context.config.hasSupervisor ? 1 : 0) << 18) | + ((context.config.hasUser ? 1 : 0) << 20), _ => throw TrapException.illegalInstruction(), }; @override - void write(RiverCoreEmulator _core, int _value) { + void write(CsrContext context, int value) { throw TrapException.illegalInstruction(); } @@ -114,15 +146,27 @@ class IdCsr extends Csr { } class CsrFile { - final Mxlen mxlen; + final RiscVMxlen mxlen; final Map csrs = {}; - CsrFile(this.mxlen, {bool hasSupervisor = false, bool hasUser = false}) { - for (final csr in IdCsr.registers) csrs[csr.address] = IdCsr(csr.address); + CsrFile( + this.mxlen, { + bool hasSupervisor = false, + bool hasUser = false, + bool hasHypervisor = false, + bool hasStateen = false, + int rpipelineCap = 0, + }) { + for (final csr in IdCsr.registers) { + csrs[csr.address] = IdCsr(csr.address); + } + + final fullMask = mxlen == RiscVMxlen.rv64 ? -1 : 0xFFFFFFFF; + final tvecMask = mxlen == RiscVMxlen.rv64 ? -4 : 0xFFFFFFFC; csrs[CsrAddress.mstatus.address] = MaskedCsr( CsrAddress.mstatus.address, - 0xFFFFFFFF, + fullMask, ); csrs[CsrAddress.mie.address] = SimpleCsr(CsrAddress.mie.address); @@ -130,7 +174,7 @@ class CsrFile { csrs[CsrAddress.mtvec.address] = MaskedCsr( CsrAddress.mtvec.address, - 0xFFFFFFFC, + tvecMask, ); csrs[CsrAddress.mscratch.address] = SimpleCsr(CsrAddress.mscratch.address); csrs[CsrAddress.mepc.address] = SimpleCsr(CsrAddress.mepc.address); @@ -139,22 +183,140 @@ class CsrFile { csrs[CsrAddress.satp.address] = MaskedCsr( CsrAddress.satp.address, - 0xFFFFFFFF, + fullMask, + ); + + csrs[CsrAddress.mcounteren.address] = SimpleCsr( + CsrAddress.mcounteren.address, ); csrs[CsrAddress.mideleg.address] = SimpleCsr(CsrAddress.mideleg.address); csrs[CsrAddress.medeleg.address] = SimpleCsr(CsrAddress.medeleg.address); + csrs[CsrAddress.mcycle.address] = SimpleCsr(CsrAddress.mcycle.address); + csrs[CsrAddress.minstret.address] = SimpleCsr(CsrAddress.minstret.address); + + // River custom cache control CSRs + csrs[CsrAddress.rcachectl.address] = SimpleCsr( + CsrAddress.rcachectl.address, + ); + csrs[CsrAddress.rcacheaddr.address] = SimpleCsr( + CsrAddress.rcacheaddr.address, + ); + csrs[CsrAddress.rcachesize.address] = SimpleCsr( + CsrAddress.rcachesize.address, + ); + // Pipeline/speculation control. WARL: only bits [3:0] are writable + // (SSBD/BPD/SERIALIZE/DTLBFC). The emulator is an in-order architectural + // model with no speculation, so these bits have no behavioural effect here; + // they exist so software reads back what it wrote and stays in parity with + // the HDL, where the bits gate real micro-architecture. + csrs[CsrAddress.rpipelinectl.address] = MaskedCsr( + CsrAddress.rpipelinectl.address, + 0xF, + ); + // Read-only pipeline feature-discovery bitmap (writes trap, RO address). + csrs[CsrAddress.rpipelinecap.address] = ReadOnlyCsr( + CsrAddress.rpipelinecap.address, + rpipelineCap, + ); + + _initCounters(); + if (hasSupervisor) _initSupervisor(); if (hasUser) _initUser(); + if (hasHypervisor) _initHypervisor(); + if (hasStateen) _initStateen(hasSupervisor, hasHypervisor); + } + + /// State-enable CSRs (Smstateen/Ssstateen). Only SE0 (bit 63), which gates + /// access to the lower-level state-enable CSRs, is implemented; the other + /// architecturally-defined bits (envcfg/AIA/IMSIC/CSRIND/scontext/custom) gate + /// features River does not implement, so they are WARL-0. The actual access + /// denial is enforced in the CSR read/write path (see RiverCore). + void _initStateen(bool hasSupervisor, bool hasHypervisor) { + const se0 = 1 << 63; // bit 63 = SE0 + csrs[CsrAddress.mstateen0.address] = MaskedCsr( + CsrAddress.mstateen0.address, + se0, + ); + for (final a in [ + CsrAddress.mstateen1, + CsrAddress.mstateen2, + CsrAddress.mstateen3, + ]) { + csrs[a.address] = MaskedCsr(a.address, 0); + } + if (hasSupervisor) { + // No U-accessible state-enabled features in River, so sstateen* read 0. + for (final a in [ + CsrAddress.sstateen0, + CsrAddress.sstateen1, + CsrAddress.sstateen2, + CsrAddress.sstateen3, + ]) { + csrs[a.address] = MaskedCsr(a.address, 0); + } + } + if (hasHypervisor) { + csrs[CsrAddress.hstateen0.address] = MaskedCsr( + CsrAddress.hstateen0.address, + se0, + ); + for (final a in [ + CsrAddress.hstateen1, + CsrAddress.hstateen2, + CsrAddress.hstateen3, + ]) { + csrs[a.address] = MaskedCsr(a.address, 0); + } + } + } + + /// Hypervisor (H) CSRs plus the virtual-supervisor (VS-mode) shadow CSRs. + /// Only registered when the H extension is configured. + void _initHypervisor() { + const writable = [ + CsrAddress.hstatus, + CsrAddress.hedeleg, + CsrAddress.hideleg, + CsrAddress.hie, + CsrAddress.hcounteren, + CsrAddress.hgeie, + CsrAddress.htval, + CsrAddress.hip, + CsrAddress.hvip, + CsrAddress.htinst, + CsrAddress.henvcfg, + CsrAddress.htimedelta, + CsrAddress.hgatp, + CsrAddress.vsstatus, + CsrAddress.vsie, + CsrAddress.vstvec, + CsrAddress.vsscratch, + CsrAddress.vsepc, + CsrAddress.vscause, + CsrAddress.vstval, + CsrAddress.vsip, + CsrAddress.vsatp, + ]; + for (final addr in writable) { + csrs[addr.address] = SimpleCsr(addr.address); + } + // hgeip (guest external interrupt pending) is read-only. + csrs[CsrAddress.hgeip.address] = ReadOnlyCsr(CsrAddress.hgeip.address, 0); } void _initSupervisor() { final mstatus = csrs[CsrAddress.mstatus.address]!; final mie = csrs[CsrAddress.mie.address]!; final mip = csrs[CsrAddress.mip.address]!; + final fullMask = mxlen == RiscVMxlen.rv64 ? -1 : 0xFFFFFFFF; + final tvecMask = mxlen == RiscVMxlen.rv64 ? -4 : 0xFFFFFFFC; - const sstatusMask = 0x800DE133; + final sstatusMask = mxlen == RiscVMxlen.rv64 + ? 0x80000003000DE133 + : 0x800DE133; csrs[CsrAddress.sstatus.address] = LinkCsr( CsrAddress.sstatus.address, mstatus, @@ -177,21 +339,27 @@ class CsrFile { csrs[CsrAddress.stvec.address] = MaskedCsr( CsrAddress.stvec.address, - 0xFFFFFFFC, + tvecMask, ); csrs[CsrAddress.sscratch.address] = SimpleCsr(CsrAddress.sscratch.address); csrs[CsrAddress.sepc.address] = SimpleCsr(CsrAddress.sepc.address); csrs[CsrAddress.scause.address] = SimpleCsr(CsrAddress.scause.address); csrs[CsrAddress.stval.address] = SimpleCsr(CsrAddress.stval.address); + csrs[CsrAddress.scounteren.address] = SimpleCsr( + CsrAddress.scounteren.address, + ); + csrs[CsrAddress.satp.address] = MaskedCsr( CsrAddress.satp.address, - 0xFFFFFFFF, + fullMask, ); } void _initUser() { final mstatus = csrs[CsrAddress.mstatus.address]!; + final tvecMask = mxlen == RiscVMxlen.rv64 ? -4 : 0xFFFFFFFC; + const ustatusMask = 0x11; csrs[CsrAddress.ustatus.address] = LinkCsr( CsrAddress.ustatus.address, @@ -202,7 +370,7 @@ class CsrFile { csrs[CsrAddress.utvec.address] = MaskedCsr( CsrAddress.utvec.address, - 0xFFFFFFFC, + tvecMask, ); csrs[CsrAddress.uscratch.address] = SimpleCsr(CsrAddress.uscratch.address); @@ -226,12 +394,38 @@ class CsrFile { ); } + void _initCounters() { + final mcycle = csrs[CsrAddress.mcycle.address]!; + final minstret = csrs[CsrAddress.minstret.address]!; + + csrs[CsrAddress.cycle.address] = LinkCsr( + CsrAddress.cycle.address, + mcycle, + mask: -1, + writable: false, + ); + csrs[CsrAddress.instret.address] = LinkCsr( + CsrAddress.instret.address, + minstret, + mask: -1, + writable: false, + ); + // time has no separate mtime here; mirror the cycle counter. + csrs[CsrAddress.time.address] = LinkCsr( + CsrAddress.time.address, + mcycle, + mask: -1, + writable: false, + ); + } + void reset() { for (final csr in csrs.values) { - if (csr is SimpleCsr) + if (csr is SimpleCsr) { csr.value = 0; - else if (csr is MaskedCsr) + } else if (csr is MaskedCsr) { csr.value = 0; + } } } @@ -242,24 +436,36 @@ class CsrFile { return csrs[address]!; } - int read(int address, RiverCoreEmulator core) { - return this[address].read(core); + int read(int address, CsrContext context) { + return this[address].read(context); } - void write(int address, int value, RiverCoreEmulator core) { - this[address].write(core, value); + void write(int address, int value, CsrContext context) { + this[address].write(context, value); if (address == CsrAddress.satp.address) { final modeId = (value >> mxlen.satpModeShift) & mxlen.satpModeMask; final ppn = value & mxlen.satpPpnMask; - core.mmu.configure(modeId, ppn); + context.mmu.configure(modeId, ppn); } + + onWrite?.call(address, value, context); } - void increment() {} + void Function(int address, int value, CsrContext context)? onWrite; + + void increment() { + final mcycle = csrs[CsrAddress.mcycle.address]; + if (mcycle is SimpleCsr) mcycle.value++; + } + + void retireInstruction() { + final minstret = csrs[CsrAddress.minstret.address]; + if (minstret is SimpleCsr) minstret.value++; + } - String toStringWithCore(RiverCoreEmulator core) => - 'CsrFile(${Map.fromEntries(csrs.entries.map((entry) => MapEntry(CsrAddress.find(entry.key), entry.value.read(core))))})'; + String toStringWithCore(CsrContext context) => + 'CsrFile(${Map.fromEntries(csrs.entries.map((entry) => MapEntry(CsrAddress.find(entry.key), entry.value.read(context))))})'; @override String toString() => 'CsrFile()'; diff --git a/packages/river_emulator/lib/src/csr_address.dart b/packages/river_emulator/lib/src/csr_address.dart new file mode 100644 index 0000000..120c927 --- /dev/null +++ b/packages/river_emulator/lib/src/csr_address.dart @@ -0,0 +1,76 @@ +/// CSR address constants for the RISC-V emulator. +/// +/// Maps standard RISC-V CSR names to their addresses. +enum CsrAddress { + // Machine Information + mvendorid(0xF11), + marchid(0xF12), + mimpid(0xF13), + mhartid(0xF14), + mconfigptr(0xF15), + + // Machine Trap Setup + mstatus(0x300), + misa(0x301), + medeleg(0x302), + mideleg(0x303), + mie(0x304), + mtvec(0x305), + mcounteren(0x306), + mstatush(0x310), + + // Machine Trap Handling + mscratch(0x340), + mepc(0x341), + mcause(0x342), + mtval(0x343), + mip(0x344), + + // Machine Counter/Timer + mcycle(0xB00), + minstret(0xB02), + + // Supervisor Trap Setup + sstatus(0x100), + sie(0x104), + stvec(0x105), + scounteren(0x106), + + // Supervisor Trap Handling + sscratch(0x140), + sepc(0x141), + scause(0x142), + stval(0x143), + sip(0x144), + + // Supervisor Address Translation + satp(0x180), + + // User Trap Setup + ustatus(0x000), + uie(0x004), + utvec(0x005), + + // User Trap Handling + uscratch(0x040), + uepc(0x041), + ucause(0x042), + utval(0x043), + uip(0x044), + + // User Counter/Timer (read-only) + cycle(0xC00), + time(0xC01), + instret(0xC02); + + final int address; + + const CsrAddress(this.address); + + static CsrAddress? find(int address) { + for (final csr in CsrAddress.values) { + if (csr.address == address) return csr; + } + return null; + } +} diff --git a/packages/river_emulator/lib/src/debug/debug_module.dart b/packages/river_emulator/lib/src/debug/debug_module.dart new file mode 100644 index 0000000..c3db11d --- /dev/null +++ b/packages/river_emulator/lib/src/debug/debug_module.dart @@ -0,0 +1,252 @@ +/// A software RISC-V Debug Module (DM) for the emulator, reachable over the +/// OpenOCD `remote_bitbang` protocol (see [RemoteBitbangServer]). It lets an +/// external debugger / Heimdall halt the core and inspect registers and memory +/// exactly as it would real silicon. +/// +/// This follows the RISC-V External Debug Support spec (version 0.13.2, +/// reported in `dmstatus.version`). DMI addresses use the standard map +/// (dmstatus=0x11, dmcontrol=0x10, data0=0x04, command=0x17, sbcs=0x38). +/// Note this intentionally differs from Harbor's HDL `HarborDebugModule`, +/// which mis-maps dmstatus to 0x04. +library; + +/// What the Debug Module needs from the core it debugs. The emulator's +/// `RiverCore` is adapted to this by `RiverDebugTarget`. +abstract class DebugTarget { + /// Whether the hart is currently halted (in debug mode). + bool get halted; + + /// Request the hart enter/leave debug mode. The emulator's run loop honours + /// [halted]; while halted the core does not retire instructions. + void requestHalt(); + void requestResume(); + + int readGpr(int index); + void writeGpr(int index, int value); + + int readCsr(int address); + void writeCsr(int address, int value); + + /// Read/write [size] bytes (1/2/4/8) of physical memory. + Future readMem(int address, int size); + Future writeMem(int address, int value, int size); +} + +/// The DMI operation field (dmi register bits [1:0]). +enum DmiOp { nop, read, write } + +/// DMI operation status returned in the capture (bits [1:0]). +class DmiStatus { + static const success = 0; + static const failed = 2; + static const busy = 3; +} + +/// The software Debug Module: a DMI (Debug Module Interface) register file +/// backed by a [DebugTarget]. [dmiRead]/[dmiWrite] are the only entry points; +/// the DTM drives them from JTAG scans. +class SoftDebugModule { + final DebugTarget target; + + // Abstract-command data registers (data0/data1) hold the 64-bit operand. + int _data0 = 0; + int _data1 = 0; + + // Abstract command status: cmderr (bits 10:8). + int _cmderr = 0; + + // System-bus access registers. _sbdata is sbdata0 (low 32 bits); _sbdata1 is + // sbdata1 (high 32) used for 64-bit (sbaccess=3) accesses. + int _sbcs = _sbcsDefault; + int _sbaddress = 0; + int _sbdata = 0; + int _sbdata1 = 0; + + // dmcontrol latched bits we care about. + bool _dmactive = false; + + SoftDebugModule(this.target); + + // sbcs defaults: sbversion=1, 32-bit access selected, 8/16/32/64 supported, + // sbasize=32. + static const int _sbcsDefault = + (1 << 29) | // sbversion = 1 + (2 << 17) | // sbaccess = 2 (32-bit) + (32 << 5) | // sbasize = 32 + (1 << 0) | // sbaccess8 + (1 << 1) | // sbaccess16 + (1 << 2) | // sbaccess32 + (1 << 3); // sbaccess64 + + /// Read a DMI register (RISC-V Debug Spec addresses). Some reads (sbdata0 + /// with sbreadondata) have side effects, hence the Future. + Future dmiRead(int address) async { + switch (address) { + case 0x11: // dmstatus + return _dmstatusValue(); + case 0x10: // dmcontrol (haltreq/resumereq read back 0) + return _dmactive ? 0x1 : 0x0; + case 0x16: // abstractcs: datacount=2, cmderr[10:8], busy=0, progbuf=0 + return 0x2 | (_cmderr << 8); + case 0x04: // data0 + return _data0 & 0xFFFFFFFF; + case 0x05: // data1 + return _data1 & 0xFFFFFFFF; + case 0x38: // sbcs + return _sbcs; + case 0x39: // sbaddress0 + return _sbaddress & 0xFFFFFFFF; + case 0x3c: // sbdata0 + final v = _sbdata & 0xFFFFFFFF; + if ((_sbcs >> 15) & 1 == 1) await _sbAccess(read: true); // sbreadondata + return v; + case 0x3d: // sbdata1 (high 32 bits of a 64-bit system-bus access) + return _sbdata1 & 0xFFFFFFFF; + default: + return 0; + } + } + + /// Write a DMI register, possibly triggering an action (halt, abstract + /// command, system-bus access). + Future dmiWrite(int address, int value) async { + switch (address) { + case 0x10: // dmcontrol + final dmactive = (value & 0x1) == 1; + // dmactive is the DM's reset signal: while it is low the whole module + // takes its reset values (Debug Spec 0.13.2). A debugger reconnecting + // for the next fuzz iteration toggles it low to clear sticky state from + // the prior session. Without honouring it, a leftover sbcs.sberror or + // cmderr from iteration N makes iteration N+1's system-bus memory write + // report "unsupported size" and fall back to a failing abstract access. + if (!dmactive) _resetDmState(); + _dmactive = dmactive; + if ((value >> 31) & 1 == 1) target.requestHalt(); // haltreq + if ((value >> 30) & 1 == 1) target.requestResume(); // resumereq + case 0x04: // data0 + _data0 = value & 0xFFFFFFFF; + case 0x05: // data1 + _data1 = value & 0xFFFFFFFF; + case 0x17: // command + await _runCommand(value); + case 0x38: // sbcs + // Only the control fields are writable. The capability fields + // (sbversion[31:29], sbasize[11:5], sbaccessN[4:0]) are read-only: if a + // debugger's write is allowed to clear them, a later reconnect reads + // sbcs back, sees no supported access size, and abandons the system bus + // (the "unsupported size" memory-write failure). sberror[14:12] and + // sbbusyerror[22] are write-1-clear. + const sbcsRoMask = 0xE0000FFF; + const sbcsRwMask = + 0x001F8000; // sbreadonaddr|sbaccess|sbautoinc|sbreadondata + const sbcsW1cMask = (1 << 22) | (0x7 << 12); + final sbcsKeptW1c = _sbcs & sbcsW1cMask & ~value; + _sbcs = + (_sbcsDefault & sbcsRoMask) | (value & sbcsRwMask) | sbcsKeptW1c; + case 0x39: // sbaddress0 + _sbaddress = value & 0xFFFFFFFF; + if ((_sbcs >> 20) & 1 == 1) await _sbAccess(read: true); // sbreadonaddr + case 0x3d: // sbdata1: high 32 bits, staged before the sbdata0 write + _sbdata1 = value & 0xFFFFFFFF; + case 0x3c: // sbdata0 + _sbdata = value & 0xFFFFFFFF; + await _sbAccess(read: false); + } + } + + /// Reset the Debug Module's register state to its defaults. Triggered by + /// dmcontrol.dmactive=0 (the spec's DM reset) so each debugger session starts + /// clean even though this module object outlives a single connection. + void _resetDmState() { + _cmderr = 0; + _data0 = 0; + _data1 = 0; + _sbcs = _sbcsDefault; + _sbaddress = 0; + _sbdata = 0; + _sbdata1 = 0; + } + + int _dmstatusValue() { + final halted = target.halted; + return 2 | // version = 2 (0.13.2) + (1 << 7) | // authenticated + (halted ? (1 << 9) | (1 << 8) : 0) | // all/anyhalted + (halted ? 0 : (1 << 11) | (1 << 10)) | // all/anyrunning + (1 << 17) | + (1 << 16); // all/anyresumeack + } + + /// Execute an abstract command (cmdtype in bits [31:24]). Only "access + /// register" (0) is supported; memory uses the system bus instead. + Future _runCommand(int command) async { + _cmderr = 0; + final cmdtype = (command >> 24) & 0xFF; + if (cmdtype != 0) { + _cmderr = 2; // not supported -> debugger falls back to system bus + return; + } + final aarsize = (command >> 20) & 0x7; + final transfer = (command >> 17) & 1; + final write = (command >> 16) & 1; + final regno = command & 0xFFFF; + final is64 = aarsize == 3; + if (transfer == 0) return; + + try { + if (write == 1) { + final v = is64 ? (_data0 & 0xFFFFFFFF) | (_data1 << 32) : _data0; + _writeReg(regno, v); + } else { + final v = _readReg(regno); + _data0 = v & 0xFFFFFFFF; + _data1 = is64 ? (v >> 32) & 0xFFFFFFFF : 0; + } + } catch (_) { + _cmderr = 3; // exception + } + } + + int _readReg(int regno) { + if (regno >= 0x1000 && regno <= 0x101F) + return target.readGpr(regno - 0x1000); + if (regno <= 0x0FFF) return target.readCsr(regno); + throw StateError('unsupported regno 0x${regno.toRadixString(16)}'); + } + + void _writeReg(int regno, int value) { + if (regno >= 0x1000 && regno <= 0x101F) { + target.writeGpr(regno - 0x1000, value); + } else if (regno <= 0x0FFF) { + target.writeCsr(regno, value); + } else { + throw StateError('unsupported regno 0x${regno.toRadixString(16)}'); + } + } + + /// Perform one system-bus access at [_sbaddress], honouring sbaccess size and + /// autoincrement. + Future _sbAccess({required bool read}) async { + final size = + 1 << ((_sbcs >> 17) & 0x7); // sbaccess: 0->1B,1->2B,2->4B,3->8B + try { + if (read) { + final v = await target.readMem(_sbaddress, size); + _sbdata = v & 0xFFFFFFFF; + _sbdata1 = size > 4 ? (v >> 32) & 0xFFFFFFFF : 0; + } else { + // A 64-bit access spans sbdata1 (high) + sbdata0 (low); the debugger + // writes sbdata1 first, then sbdata0 (which triggers this). Without + // combining them a 64-bit write stores only the low word and zeroes the + // high 4 bytes, corrupting every other word of a downloaded image. + final v = size > 4 + ? (_sbdata & 0xFFFFFFFF) | (_sbdata1 << 32) + : _sbdata; + await target.writeMem(_sbaddress, v, size); + } + if ((_sbcs >> 16) & 1 == 1) _sbaddress += size; // sbautoincrement + } catch (_) { + _sbcs |= (2 << 12); // sberror = 2 (alignment/bus) + } + } +} diff --git a/packages/river_emulator/lib/src/debug/jtag_dtm.dart b/packages/river_emulator/lib/src/debug/jtag_dtm.dart new file mode 100644 index 0000000..9dead3d --- /dev/null +++ b/packages/river_emulator/lib/src/debug/jtag_dtm.dart @@ -0,0 +1,163 @@ +import 'debug_module.dart'; + +/// IEEE 1149.1 TAP states. +enum TapState { + testLogicReset, + runTestIdle, + selectDr, + captureDr, + shiftDr, + exit1Dr, + pauseDr, + exit2Dr, + updateDr, + selectIr, + captureIr, + shiftIr, + exit1Ir, + pauseIr, + exit2Ir, + updateIr, +} + +/// A software JTAG TAP + Debug Transport Module. It runs the standard TAP +/// finite state machine, shifts the IR and the per-instruction DRs (LSB-first), +/// and bridges the DMI access instruction to a [SoftDebugModule]. +/// +/// Instructions (IR width 5, RISC-V convention): IDCODE=0x01, DTMCS=0x10, +/// DMI=0x11, BYPASS=0x1F. The DMI data register is `abits + 34` = 41 bits: +/// `{address[6:0], data[31:0], op[1:0]}`. +class SoftJtagDtm { + final SoftDebugModule dm; + final int idcode; + final int irWidth; + + static const int abits = 7; + static const int dmiWidth = abits + 34; // 41 + + TapState _state = TapState.testLogicReset; + int _ir = 0x01; // IDCODE is the reset default (IEEE 1149.1) + int _irShift = 0; + int _dr = 0; + int _drLen = 1; + + // Latched result of the previous DMI transaction (captured on the next scan). + int _dmiData = 0; + int _dmiAddr = 0; + int _dmiStatus = DmiStatus.success; + + SoftJtagDtm(this.dm, {this.idcode = 0x10000001, this.irWidth = 5}); + + /// The current TDO value (0/1) presented to the host. Combinational: it is + /// the shift register's current LSB so a host that samples TDO while TCK is + /// low (the OpenOCD remote_bitbang convention) reads the bit that the next + /// rising edge will shift out. Latching it inside [clock] instead presents it + /// one clock late (IDCODE comes back as `idcode << 1`). + int get tdo { + if (_state == TapState.shiftIr) return _irShift & 1; + if (_state == TapState.shiftDr) return _dr & 1; + return 0; + } + + TapState get state => _state; + + void reset() { + _state = TapState.testLogicReset; + _ir = 0x01; + } + + /// Advance one TCK rising edge with the given TMS and TDI pin levels. + Future clock(int tms, int tdi) async { + // While shifting, shift TDI in at the MSB. TDO is presented combinationally + // by the [tdo] getter (the current LSB), read by the host before this edge. + if (_state == TapState.shiftIr) { + _irShift = (_irShift >> 1) | ((tdi & 1) << (irWidth - 1)); + } else if (_state == TapState.shiftDr) { + _dr = (_dr >> 1) | ((tdi & 1) << (_drLen - 1)); + } + + final next = _nextState(_state, tms & 1); + switch (next) { + case TapState.testLogicReset: + _ir = 0x01; + case TapState.captureIr: + _irShift = 0x01; // low two bits read back as 01 per spec + case TapState.updateIr: + _ir = _irShift & ((1 << irWidth) - 1); + case TapState.captureDr: + _loadDr(); + case TapState.updateDr: + await _updateDr(); + default: + break; + } + _state = next; + } + + void _loadDr() { + switch (_ir) { + case 0x01: // IDCODE + _dr = idcode & 0xFFFFFFFF; + _drLen = 32; + case 0x10: // DTMCS + _dr = _dtmcs(); + _drLen = 32; + case 0x11: // DMI: present the previous transaction's result. + _dr = + (_dmiAddr << 34) | + ((_dmiData & 0xFFFFFFFF) << 2) | + (_dmiStatus & 0x3); + _drLen = dmiWidth; + default: // BYPASS + _dr = 0; + _drLen = 1; + } + } + + int _dtmcs() => + 1 | // version = 1 (debug 0.13) + (abits << 4) | // abits = 7 + (_dmiStatus << 10) | // dmistat + (1 << 12); // idle hint + + Future _updateDr() async { + if (_ir == 0x10) { + // DTMCS write: dmireset (bit16) / dmihardreset (bit17) clear sticky state. + if (((_dr >> 16) & 1) == 1 || ((_dr >> 17) & 1) == 1) { + _dmiStatus = DmiStatus.success; + } + } else if (_ir == 0x11) { + final op = _dr & 0x3; + final data = (_dr >> 2) & 0xFFFFFFFF; + _dmiAddr = (_dr >> 34) & ((1 << abits) - 1); + if (op == DmiOp.read.index) { + _dmiData = await dm.dmiRead(_dmiAddr); + _dmiStatus = DmiStatus.success; + } else if (op == DmiOp.write.index) { + await dm.dmiWrite(_dmiAddr, data); + _dmiStatus = DmiStatus.success; + } + } + } + + TapState _nextState(TapState s, int tms) => switch (s) { + TapState.testLogicReset => + tms == 1 ? TapState.testLogicReset : TapState.runTestIdle, + TapState.runTestIdle => tms == 1 ? TapState.selectDr : TapState.runTestIdle, + TapState.selectDr => tms == 1 ? TapState.selectIr : TapState.captureDr, + TapState.captureDr => tms == 1 ? TapState.exit1Dr : TapState.shiftDr, + TapState.shiftDr => tms == 1 ? TapState.exit1Dr : TapState.shiftDr, + TapState.exit1Dr => tms == 1 ? TapState.updateDr : TapState.pauseDr, + TapState.pauseDr => tms == 1 ? TapState.exit2Dr : TapState.pauseDr, + TapState.exit2Dr => tms == 1 ? TapState.updateDr : TapState.shiftDr, + TapState.updateDr => tms == 1 ? TapState.selectDr : TapState.runTestIdle, + TapState.selectIr => + tms == 1 ? TapState.testLogicReset : TapState.captureIr, + TapState.captureIr => tms == 1 ? TapState.exit1Ir : TapState.shiftIr, + TapState.shiftIr => tms == 1 ? TapState.exit1Ir : TapState.shiftIr, + TapState.exit1Ir => tms == 1 ? TapState.updateIr : TapState.pauseIr, + TapState.pauseIr => tms == 1 ? TapState.exit2Ir : TapState.pauseIr, + TapState.exit2Ir => tms == 1 ? TapState.updateIr : TapState.shiftIr, + TapState.updateIr => tms == 1 ? TapState.selectDr : TapState.runTestIdle, + }; +} diff --git a/packages/river_emulator/lib/src/debug/remote_bitbang.dart b/packages/river_emulator/lib/src/debug/remote_bitbang.dart new file mode 100644 index 0000000..9994eb8 --- /dev/null +++ b/packages/river_emulator/lib/src/debug/remote_bitbang.dart @@ -0,0 +1,229 @@ +import 'dart:async'; +import 'dart:io'; + +import 'package:river/river.dart'; + +import '../core.dart'; +import 'debug_module.dart'; +import 'jtag_dtm.dart'; + +/// Adapts a [RiverCore] to the [DebugTarget] interface so the software Debug +/// Module can halt it and inspect its registers and memory. +class RiverDebugTarget implements DebugTarget, DebugHook { + final RiverCore core; + bool _halted = false; + + /// Debug PC. The run loop saves the hart's PC here when it halts and resumes + /// from here, so a debugger that writes dpc (regno 0x7b1) redirects execution + /// (the fuzzer sets it to each program's entry before resuming). These are + /// Debug-Mode CSRs the normal CSR file does not hold. + int dpc = 0; + + /// dcsr (0x7b0): debugver=4 (0.13.2), prv=3 (machine), cause set on halt. + /// OpenOCD reads this during resume_prep (the "priv register") and writes the + /// ebreak/step bits, so it must be a real readable/writable register. + int _dcsr = 0x40000003; + + RiverDebugTarget(this.core) { + // Let the core enter Debug Mode on an armed ebreak instead of trapping. + core.debugHook = this; + } + + @override + bool get halted => _halted; + + @override + bool ebreakEntersDebug(PrivilegeMode mode) { + final bit = switch (mode) { + PrivilegeMode.machine => 15, // dcsr.ebreakm + PrivilegeMode.supervisor => 13, // dcsr.ebreaks + PrivilegeMode.user => 12, // dcsr.ebreaku + }; + return ((_dcsr >> bit) & 1) == 1; + } + + @override + void enterDebug(int dpcValue, int cause) { + dpc = dpcValue; + _halted = true; + // Latch the halt cause (8:6) and force debugver; keep ebreak*/step config. + _dcsr = (_dcsr & 0xFFFFFE3F) | ((cause & 0x7) << 6) | 0x40000000; + } + + @override + void requestHalt() { + _halted = true; + // Halt cause = 3 (haltreq); keep the other dcsr bits, force debugver. + _dcsr = (_dcsr & 0xFFFFFE3F) | (3 << 6) | 0x40000000; + } + + @override + void requestResume() => _halted = false; + + @override + int readGpr(int index) => core.xregs[Register.values[index]] ?? 0; + + @override + void writeGpr(int index, int value) { + if (index != 0) core.xregs[Register.values[index]] = value; + } + + @override + int readCsr(int address) { + if (address == 0x7b1) return dpc; // dpc + if (address == 0x7b0) return _dcsr; // dcsr + return core.csrs.read(address, core); + } + + @override + void writeCsr(int address, int value) { + if (address == 0x7b1) { + dpc = value; + return; + } + if (address == 0x7b0) { + // debugver (31:28) is read-only (=4) and cause (8:6) is hardware-set; + // force the former and preserve the latter on every write. + _dcsr = (value & 0x0FFFFE3F) | 0x40000000 | (_dcsr & 0x000001C0); + return; + } + core.csrs.write(address, value, core); + } + + @override + Future readMem(int address, int size) => + core.mmu.read(address, size, pageTranslate: false); + + @override + Future writeMem(int address, int value, int size) => + core.mmu.write(address, value, size, pageTranslate: false); +} + +/// An OpenOCD `remote_bitbang` protocol server. It speaks the same wire +/// protocol as a JTAG adapter, driving a software [SoftJtagDtm] (TAP + DTM) which +/// in turn reaches a [SoftDebugModule]. This lets OpenOCD, and therefore +/// Heimdall, connect to the emulator exactly as it would to silicon or the +/// HDL simulation, so the same verification flow validates all three. +/// +/// OpenOCD config: +/// ``` +/// adapter driver remote_bitbang +/// remote_bitbang host localhost +/// remote_bitbang port 44853 +/// ``` +/// +/// Protocol bytes: `0`-`7` set {TCK,TMS,TDI}; `R` read TDO ('0'/'1'); `Q` quit; +/// `r`/`s`/`t`/`u` are (t)rst/(s)rst reset combos; `B`/`b` blink (ignored). +class RemoteBitbangServer { + final SoftJtagDtm dtm; + final int port; + + ServerSocket? _server; + Socket? _client; + bool _running = false; + int _prevTck = 0; + + static const defaultPort = 44853; + + RemoteBitbangServer(this.dtm, {this.port = defaultPort}); + + /// The actual bound port (useful when constructed with `port: 0`). + int? get boundPort => _server?.port; + + /// Bind the listening socket. Call before [serve] so [boundPort] is known. + Future bind() async { + _server = await ServerSocket.bind(InternetAddress.loopbackIPv4, port); + _running = true; + } + + /// Bind (if needed) and serve until [stop]. Typically started with + /// `unawaited`. + Future start() async { + if (_server == null) await bind(); + await serve(); + } + + /// Accept and handle clients until [stop]. Requires [bind] first. + Future serve() async { + await for (final client in _server!) { + if (!_running) break; + _client = client; + client.setOption(SocketOption.tcpNoDelay, true); + // A write that races with the peer (OpenOCD) disconnecting surfaces its + // error asynchronously on the socket's done future, not at the add() call + // site. With no handler it becomes an unhandled async error that tears + // down the whole isolate, so a debugger reconnecting between fuzz + // iterations crashes the emulator. Absorb it here so the server just + // moves on to the next connection. + unawaited(client.done.catchError((Object _) => client)); + try { + await _handle(client); + } catch (_) { + // Drop the connection on any protocol/IO error; keep serving. + } + try { + await client.close(); + } catch (_) { + // Already gone; nothing to clean up. + } + _client = null; + } + } + + Future stop() async { + _running = false; + await _client?.close(); + await _server?.close(); + _server = null; + _client = null; + } + + Future _handle(Socket client) async { + await for (final data in client) { + if (!_running) break; + for (final byte in data) { + if (byte >= 0x30 && byte <= 0x37) { + // '0'-'7': {TCK,TMS,TDI}. Clock the TAP on a TCK rising edge. + final v = byte - 0x30; + final tck = (v >> 2) & 1; + final tms = (v >> 1) & 1; + final tdi = v & 1; + if (tck == 1 && _prevTck == 0) await dtm.clock(tms, tdi); + _prevTck = tck; + } else if (byte == 0x52) { + // 'R': read TDO. Guard the write: if the peer has already gone the + // add() can fail, and we drop this connection so serve() accepts the + // next one instead of letting the error escape. + try { + client.add([dtm.tdo == 1 ? 0x31 : 0x30]); + } catch (_) { + return; + } + } else if (byte == 0x74 || byte == 0x75) { + // 't'/'u': TRST asserted -> reset the TAP. + dtm.reset(); + } else if (byte == 0x51) { + // 'Q': quit + await client.close(); + return; + } + // 'r','s','B','b' and others: no-op. + } + } + } +} + +/// Build and start a remote-bitbang debug server for [core] on [port]. +/// Returns the server (already listening in the background). +Future startRiverDebugServer( + RiverCore core, { + int port = RemoteBitbangServer.defaultPort, + int idcode = 0x10000001, +}) async { + final dm = SoftDebugModule(RiverDebugTarget(core)); + final dtm = SoftJtagDtm(dm, idcode: idcode); + final server = RemoteBitbangServer(dtm, port: port); + await server.bind(); // so boundPort is available immediately + unawaited(server.serve()); + return server; +} diff --git a/packages/river_emulator/lib/src/decoded_instruction.dart b/packages/river_emulator/lib/src/decoded_instruction.dart new file mode 100644 index 0000000..81d143d --- /dev/null +++ b/packages/river_emulator/lib/src/decoded_instruction.dart @@ -0,0 +1,163 @@ +import 'package:harbor/harbor.dart'; + +/// A decoded RISC-V instruction with extracted fields. +/// +/// Provides rd, rs1, rs2, and immediate values extracted from +/// the raw instruction bits based on the operation's format. +class DecodedInstruction { + final int raw; + final int rd; + final int rs1; + final int rs2; + // Third source register (R4-type fused multiply-add only); 0 otherwise. + final int rs3; + final int imm; + + const DecodedInstruction({ + required this.raw, + this.rd = 0, + this.rs1 = 0, + this.rs2 = 0, + this.rs3 = 0, + this.imm = 0, + }); + + Map toMap() => { + 'rd': rd, + 'rs1': rs1, + 'rs2': rs2, + 'rs3': rs3, + 'imm': imm, + }; + + /// Decode a 32-bit instruction using the operation's format. + factory DecodedInstruction.from32(int raw, RiscVOperation op) { + final fields = op.format.decode(raw); + final rd = fields['rd'] ?? 0; + final rs1 = fields['rs1'] ?? 0; + final rs2 = fields['rs2'] ?? 0; + final rs3 = fields['rs3'] ?? 0; + final imm = _extractImm32(raw, fields); + return DecodedInstruction( + raw: raw, + rd: rd, + rs1: rs1, + rs2: rs2, + rs3: rs3, + imm: imm, + ); + } + + /// Decode a compressed (16-bit) instruction. + factory DecodedInstruction.fromCompressed(int raw, RiscVOperation op) { + final fields = op.format.decode(raw); + + // Compressed formats use different field names + int rd = fields['rd'] ?? fields['rd_rs1'] ?? 0; + int rs1 = fields['rs1'] ?? fields['rd_rs1'] ?? 0; + int rs2 = fields['rs2'] ?? 0; + + // Handle prime registers (3-bit, maps to x8-x15) + if (fields.containsKey('rd_prime')) rd = (fields['rd_prime']! & 0x7) + 8; + if (fields.containsKey('rs1_prime')) rs1 = (fields['rs1_prime']! & 0x7) + 8; + if (fields.containsKey('rs2_prime')) rs2 = (fields['rs2_prime']! & 0x7) + 8; + if (fields.containsKey('rd_rs1_prime')) { + rd = (fields['rd_rs1_prime']! & 0x7) + 8; + rs1 = rd; + } + + // Implicit registers (x1 link for c.jal/c.jalr; x2/sp base for the + // stack-pointer-relative ops) override the encoded fields. + if (op.fixedRd != null) rd = op.fixedRd!; + if (op.fixedRs1 != null) rs1 = op.fixedRs1!; + if (op.fixedRs2 != null) rs2 = op.fixedRs2!; + + // Compressed immediates are per-instruction bit-scrambles (op.immKind), + // descrambled by the shared Harbor RVC engine. Register-only ops have no + // immKind; a few legacy formats expose contiguous imm fields. + final int imm; + if (op.immKind != null) { + imm = decodeRvcImm(op.immKind!, raw); + } else if (fields.containsKey('imm_hi')) { + imm = (fields['imm_hi']! << 5) | (fields['imm_lo'] ?? 0); + } else { + imm = fields['imm'] ?? fields['imm_lo'] ?? 0; + } + + return DecodedInstruction(raw: raw, rd: rd, rs1: rs1, rs2: rs2, imm: imm); + } + + /// Auto-detect instruction width and decode. + factory DecodedInstruction.decode(int raw, RiscVOperation op) { + if ((raw & 0x3) != 0x3) { + return DecodedInstruction.fromCompressed(raw & 0xFFFF, op); + } + return DecodedInstruction.from32(raw, op); + } + + static int _extractImm32(int raw, Map fields) { + final opcode = raw & 0x7F; + return switch (opcode) { + // U-type: LUI, AUIPC + 0x37 || 0x17 => (raw & 0xFFFFF000).toSigned(32), + // J-type: JAL + 0x6F => _jImm(raw), + // B-type: branches + 0x63 => _bImm(raw), + // S-type: stores + 0x23 || 0x27 => _sImm(raw), + // R-type: no immediate (OP, OP-32, AMO) + 0x33 || 0x3B || 0x2F => 0, + // I-type: everything else with immediate + _ => (raw >> 20).toSigned(12), + }; + } + + static int _sImm(int raw) { + final hi = (raw >> 25) & 0x7F; + final lo = (raw >> 7) & 0x1F; + return ((hi << 5) | lo).toSigned(12); + } + + static int _bImm(int raw) { + final b12 = (raw >> 31) & 1; + final b11 = (raw >> 7) & 1; + final b10_5 = (raw >> 25) & 0x3F; + final b4_1 = (raw >> 8) & 0xF; + return ((b12 << 12) | (b11 << 11) | (b10_5 << 5) | (b4_1 << 1)).toSigned( + 13, + ); + } + + static int _jImm(int raw) { + final b20 = (raw >> 31) & 1; + final b19_12 = (raw >> 12) & 0xFF; + final b11 = (raw >> 20) & 1; + final b10_1 = (raw >> 21) & 0x3FF; + return ((b20 << 20) | (b19_12 << 12) | (b11 << 11) | (b10_1 << 1)).toSigned( + 21, + ); + } + + @override + String toString() => + 'DecodedInstruction(0x${raw.toRadixString(16)}, rd: $rd, rs1: $rs1, rs2: $rs2, imm: $imm)'; +} + +/// Extension to add helper methods for paging mode lookup. +extension RiscVPagingModeExt on RiscVPagingMode { + /// PPN field shift within PTE at the given level. + int ppnShift(int level) => 10 + ppnBits.take(level).fold(0, (a, b) => a + b); + + /// PPN field shift within physical address at the given level. + int ppnPhysShift(int level) => + 12 + ppnBits.take(level).fold(0, (a, b) => a + b); +} + +/// Find a paging mode by its satp MODE field value. +RiscVPagingMode? pagingModeFromId(int id) { + for (final mode in RiscVPagingMode.values) { + if (mode.id == id) return mode; + } + return null; +} diff --git a/packages/river_emulator/lib/src/dev.dart b/packages/river_emulator/lib/src/dev.dart index 28de67b..b00d1fa 100644 --- a/packages/river_emulator/lib/src/dev.dart +++ b/packages/river_emulator/lib/src/dev.dart @@ -1,145 +1,46 @@ -import 'package:riscv/riscv.dart'; import 'package:river/river.dart'; import 'core.dart'; import 'soc.dart'; -typedef DeviceEmulatorFactory = - DeviceEmulator Function(Device, Map, RiverSoCEmulator); +typedef DeviceFactory = + Device Function(RiverDevice, Map, RiverSoC); -class DeviceEmulator { - final Device config; +enum DeviceAccessorType { memory, io, mixed } - const DeviceEmulator(this.config); +class Device { + final RiverDevice config; + + const Device(this.config); void reset() {} void increment() {} Map interrupts(int hart) => {}; - DeviceAccessorEmulator? get memAccessor { - if (config.accessor != null && config.mmap != null) - return DeviceFieldAccessorEmulator(this); - return null; - } + DeviceAccessor? get memAccessor => null; - MapEntry? get mem { - if (memAccessor == null || config.mmap == null) return null; - return MapEntry(config.mmap!, memAccessor!); + MapEntry? get mem { + if (memAccessor == null || config.range == null) return null; + return MapEntry(config.range!, memAccessor!); } @override - String toString() => 'DeviceEmulator(config: $config)'; + String toString() => 'Device(config: $config)'; } -class DeviceAccessorEmulator { - final DeviceAccessor config; +class DeviceAccessor { + final DeviceAccessorType type; - const DeviceAccessorEmulator(this.config); + const DeviceAccessor({this.type = DeviceAccessorType.memory}); - Future read(int addr, int _width) { + Future read(int addr, int width) { throw TrapException(Trap.loadAccess, addr, StackTrace.current); } - Future write(int addr, int _value, int _width) { + Future write(int addr, int value, int width) { throw TrapException(Trap.storeAccess, addr, StackTrace.current); } @override - String toString() => '$runtimeType(config: $config)'; -} - -class DeviceFieldAccessorEmulator - extends DeviceAccessorEmulator { - final T device; - - DeviceFieldAccessorEmulator(this.device) : super(device.config.accessor!); - - Future readPath(String name) { - throw TrapException( - Trap.loadAccess, - config.fieldAddress(name)!, - StackTrace.current, - ); - } - - Future writePath(String name, int _value) { - throw TrapException( - Trap.storeAccess, - config.fieldAddress(name)!, - StackTrace.current, - ); - } - - Future read(int addr, int width) async { - final fields = config.getFields(addr, width); - - if (fields.isEmpty) { - throw TrapException(Trap.loadAccess, addr, StackTrace.current); - } - - final end = addr + width; - - int result = 0; - int offset = 0; - for (final field in fields) { - final fieldStart = config.fieldAddress(field.name)!; - final fieldEnd = fieldStart + field.width; - - offset = fieldEnd; - - if (fieldEnd <= addr || fieldStart >= end) continue; - - final overlapStart = addr > fieldStart ? addr : fieldStart; - final overlapEnd = end < fieldEnd ? end : fieldEnd; - final overlapBytes = overlapEnd - overlapStart; - - final sliceOffset = overlapStart - fieldStart; - - final fieldValue = await readPath(field.name); - - final slice = - (fieldValue >> (sliceOffset * 8)) & ((1 << (overlapBytes * 8)) - 1); - - final shift = (overlapStart - addr) * 8; - - result |= (slice << shift); - } - - return result; - } - - Future write(int addr, int value, int width) async { - final fields = config.getFields(addr, width); - - if (fields.isEmpty) { - throw TrapException(Trap.storeAccess, addr, StackTrace.current); - } - - final end = addr + width; - - int offset = 0; - for (final field in fields) { - final fieldStart = config.fieldAddress(field.name)!; - final fieldEnd = fieldStart + field.width; - - offset = fieldEnd; - - if (fieldEnd <= addr || fieldStart >= end) continue; - - final overlapStart = addr > fieldStart ? addr : fieldStart; - final overlapEnd = end < fieldEnd ? end : fieldEnd; - final overlapBytes = overlapEnd - overlapStart; - - final sliceOffset = overlapStart - fieldStart; - - final valueOffset = overlapStart - addr; - - final slice = - (value >> (valueOffset * 8)) & ((1 << (overlapBytes * 8)) - 1); - - final result = slice << (sliceOffset * 8); - - await writePath(field.name, slice); - } - } + String toString() => '$runtimeType(type: $type)'; } diff --git a/packages/river_emulator/lib/src/devices.dart b/packages/river_emulator/lib/src/devices.dart index f722acf..cd24308 100644 --- a/packages/river_emulator/lib/src/devices.dart +++ b/packages/river_emulator/lib/src/devices.dart @@ -13,11 +13,11 @@ export 'devices/plic.dart'; export 'devices/sram.dart'; export 'devices/uart.dart'; -const Map kDeviceEmulatorFactory = { - 'riscv,clint': RiscVClintEmulator.create, - 'river,dram': DramEmulator.create, - 'riscv,plic': RiscVPlicEmulator.create, - 'river,flash': FlashEmulator.create, - 'river,sram': SramEmulator.create, - 'river,uart': UartEmulator.create, +const Map kDeviceFactory = { + 'riscv,clint0': Clint.create, + 'river,dram': Dram.create, + 'riscv,plic0': Plic.create, + 'river,flash': Flash.create, + 'river,sram': Sram.create, + 'ns16550a': Uart.create, }; diff --git a/packages/river_emulator/lib/src/devices/clint.dart b/packages/river_emulator/lib/src/devices/clint.dart index ab5555b..0baf0ca 100644 --- a/packages/river_emulator/lib/src/devices/clint.dart +++ b/packages/river_emulator/lib/src/devices/clint.dart @@ -1,30 +1,23 @@ import 'dart:async'; -import 'dart:math'; import 'package:river/river.dart'; import '../dev.dart'; import '../soc.dart'; -class RiscVClintEmulator extends DeviceEmulator { +class Clint extends Device { int msip = 0; - int _mtimecmp = 0; + int mtimecmp = 0; int _mtimeBase = 0; final Stopwatch _stopwatch = Stopwatch(); - RiscVClintEmulator(super.config) { + Clint(super.config) { _stopwatch.start(); } - int get mtimecmp => _mtimecmp; - - set mtimecmp(int value) { - _mtimecmp = value; - } - int get mtime { - final hz = config.clock?.baseFreqHz ?? 0; + final hz = config.clockFrequency ?? 0; if (hz <= 0) { return _mtimeBase + _stopwatch.elapsedMicroseconds; } @@ -46,14 +39,14 @@ class RiscVClintEmulator extends DeviceEmulator { bool get timerInterruptPending => mtimecmp != 0 && mtime >= mtimecmp; @override - Map interrupts(int hartId) { + Map interrupts(int hart) { return {0: softwareInterruptPending, 1: timerInterruptPending}; } @override void reset() { msip = 0; - _mtimecmp = 0; + mtimecmp = 0; _mtimeBase = 0; _stopwatch ..reset() @@ -61,46 +54,53 @@ class RiscVClintEmulator extends DeviceEmulator { } @override - DeviceAccessorEmulator? get memAccessor => RiscVClintAccessorEmulator(this); + DeviceAccessor? get memAccessor => ClintAccessor(this); - static DeviceEmulator create( - Device config, + static Device create( + RiverDevice config, Map options, - RiverSoCEmulator _soc, + RiverSoC soc, ) { - return RiscVClintEmulator(config); + return Clint(config); } } -class RiscVClintAccessorEmulator - extends DeviceFieldAccessorEmulator { - RiscVClintAccessorEmulator(super.device); +class ClintAccessor extends DeviceAccessor { + final Clint device; + + ClintAccessor(this.device) : super(type: DeviceAccessorType.io); @override - Future readPath(String name) async { - switch (name) { - case 'msip': - return device.msip & 0xFFFFFFFF; - case 'mtimecmp': - return device.mtimecmp; - case 'mtime': - return device.mtime; + Future read(int addr, int width) async { + // CLINT register map: + // 0x0000: msip (4 bytes) + // 0x4000: mtimecmp (8 bytes) + // 0xBFF8: mtime (8 bytes) + if (addr >= 0x0000 && addr < 0x0004) { + return device.msip & 0xFFFFFFFF; + } else if (addr >= 0x4000 && addr < 0x4008) { + final offset = addr - 0x4000; + return (device.mtimecmp >> (offset * 8)) & ((1 << (width * 8)) - 1); + } else if (addr >= 0xBFF8 && addr < 0xC000) { + final offset = addr - 0xBFF8; + return (device.mtime >> (offset * 8)) & ((1 << (width * 8)) - 1); } return 0; } @override - Future writePath(String name, int value) async { - switch (name) { - case 'msip': - device.msip = value & 0x1; - break; - case 'mtimecmp': - device.mtimecmp = value; - break; - case 'mtime': - device.mtime = value; - break; + Future write(int addr, int value, int width) async { + if (addr >= 0x0000 && addr < 0x0004) { + device.msip = value & 0x1; + } else if (addr >= 0x4000 && addr < 0x4008) { + final offset = addr - 0x4000; + final mask = ((1 << (width * 8)) - 1) << (offset * 8); + device.mtimecmp = + (device.mtimecmp & ~mask) | ((value << (offset * 8)) & mask); + } else if (addr >= 0xBFF8 && addr < 0xC000) { + final offset = addr - 0xBFF8; + final mask = ((1 << (width * 8)) - 1) << (offset * 8); + device.mtime = (device.mtime & ~mask) | ((value << (offset * 8)) & mask); } } } diff --git a/packages/river_emulator/lib/src/devices/dram.dart b/packages/river_emulator/lib/src/devices/dram.dart index 17c9554..7faf366 100644 --- a/packages/river_emulator/lib/src/devices/dram.dart +++ b/packages/river_emulator/lib/src/devices/dram.dart @@ -4,55 +4,174 @@ import 'package:river/river.dart'; import '../dev.dart'; import '../soc.dart'; -class DramEmulator extends DeviceEmulator { - DramEmulator(super.config); +/// DRAM model with an optional CPU-driven read-training control window, mirroring +/// the HDL [HarborDdrController] trainable path. When [trainable], an MMIO +/// register window sits just above the array (offsets `>= [arraySize]`). The +/// array is unusable until the read tap is walked into the valid eye: +/// 0x00 RDTAP_TARGET (RW, 7b) tap the controller walks to +/// 0x08 CTL (W) [0] SET (walk to target), [1] LOAD (reload 0) +/// 0x10 RDSLACK (RW) runtime read-window slack +/// 0x18 STATUS (RO) [0] busy (always 0, instant walk), [8:1] tap +/// Array reads are correct only while `currentTap` is in [[eyeLo], [eyeHi]]; +/// outside the eye a read returns a deterministically wrong value so a training +/// sweep can find it. Writes always land (read training, not write training). +class Dram extends Device { + /// Size of the training control-register window above the array (matches the + /// HDL [HarborDdrController.trainCtrlSize]). + static const int trainCtrlSize = 0x1000; + + // Register indices within the control window (8-byte strided for 64-bit-bus + // lane alignment, matching the HDL). + static const int _regRdTap = 0; + static const int _regCtl = 1; + static const int _regRdSlack = 2; + static const int _regStatus = 3; + static const int _regMpr = 4; // MPRCTL (0x20): bit0 = MPR mode + + /// The fixed multi-purpose-register pattern a DDR3 part returns in MPR mode + /// (what a read-training read sees instead of array data). Matches Weir's + /// FSBL (src/fsbl/ddr.zig MPR_PATTERN). + static const int _mprPattern = 0xFFFF0000; + + final bool trainable; + final int arraySize; + final int eyeLo; + final int eyeHi; + + List data; + + int currentTap = 0; + int targetTap = 0; + int rdSlack = 1; + + /// MPR (multi-purpose register) read-training mode. A trainable part boots in + /// MPR mode so a sweep that has not written real data yet reads the fixed + /// training pattern; the first real array WRITE drops it (the controller is + /// now serving array data). Software can also toggle it via MPRCTL. + bool mprMode; + + Dram(super.config, {this.trainable = false, this.eyeLo = 8, this.eyeHi = 40}) + : arraySize = trainable + ? config.range!.size - trainCtrlSize + : config.range!.size, + data = List.filled( + trainable ? config.range!.size - trainCtrlSize : config.range!.size, + 0, + ), + mprMode = trainable; + + /// True when the read tap sits inside the valid eye, so array reads are + /// reliable. Untrainable DRAM is always reliable. + bool get trained => + !trainable || (currentTap >= eyeLo && currentTap <= eyeHi); @override - void reset() {} + void reset() { + data.fillRange(0, data.length, 0); + currentTap = 0; + targetTap = 0; + rdSlack = 1; + mprMode = trainable; + } @override - DeviceAccessorEmulator? get memAccessor => DramAccessorEmulator(this); + DeviceAccessor? get memAccessor => DramAccessor(this); - static DeviceEmulator create( - Device config, + static Device create( + RiverDevice config, Map options, - RiverSoCEmulator _soc, + RiverSoC soc, ) { - return DramEmulator(config); + final trainable = options.containsKey('train'); + return Dram( + config, + trainable: trainable, + eyeLo: int.tryParse(options['eye-lo'] ?? '') ?? 8, + eyeHi: int.tryParse(options['eye-hi'] ?? '') ?? 40, + ); } } -class DramAccessorEmulator extends DeviceFieldAccessorEmulator { - DramAccessorEmulator(super.device); +class DramAccessor extends DeviceAccessor { + final Dram dram; - @override - Future readPath(String name) async { - return 0; - } + DramAccessor(this.dram); - @override - Future writePath(String name, int value) async {} + bool _isCtrl(int addr) => dram.trainable && addr >= dram.arraySize; + + int _widthMask(int width) => + width >= 8 ? -1 : (1 << (8 * width)) - 1; // -1 == all 64 bits set @override Future read(int addr, int width) async { - final fields = config.getFields(addr, width); - - if (fields.isNotEmpty) { - return super.read(addr, width); + if (_isCtrl(addr)) { + final reg = (addr - dram.arraySize) >> 3; + switch (reg) { + case Dram._regRdTap: + return dram.targetTap; + case Dram._regRdSlack: + return dram.rdSlack; + case Dram._regStatus: + // [0] busy (instant walk -> always 0), [8:1] current tap. + return dram.currentTap << 1; + case Dram._regMpr: + return dram.mprMode ? 1 : 0; + default: + return 0; + } } - // TODO: we're reading from one of the memory banks - return 0; + // Array read. In MPR (read-training) mode the part returns its fixed MPR + // pattern instead of array data; otherwise it returns what was stored. + int value; + if (dram.mprMode) { + value = width >= 8 + ? (Dram._mprPattern << 32) | Dram._mprPattern + : Dram._mprPattern & _widthMask(width); + } else { + if (addr + width > dram.data.length) return 0; + value = 0; + for (int i = 0; i < width; i++) { + value |= (dram.data[addr + i] & 0xFF) << (8 * i); + } + } + // Outside the read eye the captured data is garbage: corrupt it + // deterministically so a training sweep can tell a bad tap from a good one. + if (!dram.trained) value = (~value) & _widthMask(width); + return value; } @override Future write(int addr, int value, int width) async { - final fields = config.getFields(addr, width); - - if (fields.isNotEmpty) { - return super.write(addr, value, width); + if (_isCtrl(addr)) { + final reg = (addr - dram.arraySize) >> 3; + switch (reg) { + case Dram._regRdTap: + dram.targetTap = value & 0x7F; + break; + case Dram._regCtl: + if (value & 0x1 != 0) dram.currentTap = dram.targetTap; // SET (walk) + if (value & 0x2 != 0) dram.currentTap = 0; // LOAD (reload) + break; + case Dram._regRdSlack: + dram.rdSlack = value & 0x7; + break; + case Dram._regMpr: + dram.mprMode = value & 0x1 != 0; + break; + // STATUS is read-only. + } + return; } - // TODO: we're writing to one of the memory banks + // The first real array write takes the part out of MPR/training mode (it is + // now serving array data). Writes always land (read training does not + // corrupt the write path). + dram.mprMode = false; + if (addr + width > dram.data.length) return; + for (int i = 0; i < width; i++) { + final byte = (value >> (8 * i)) & 0xFF; + dram.data[addr + i] = byte; + } } } diff --git a/packages/river_emulator/lib/src/devices/flash.dart b/packages/river_emulator/lib/src/devices/flash.dart index 065321a..f9ebada 100644 --- a/packages/river_emulator/lib/src/devices/flash.dart +++ b/packages/river_emulator/lib/src/devices/flash.dart @@ -1,30 +1,28 @@ import 'dart:io'; -import 'dart:convert'; -import 'package:riscv/riscv.dart'; import 'package:river/river.dart'; import '../core.dart'; import '../dev.dart'; import '../soc.dart'; -class FlashEmulator extends DeviceEmulator { +class Flash extends Device { final List data; bool enabled; - FlashEmulator(super.config, this.data) : enabled = true; + Flash(super.config, this.data) : enabled = true; @override - DeviceAccessorEmulator? get memAccessor => FlashAccessorEmulator(this); + DeviceAccessor? get memAccessor => FlashAccessor(this); @override - String toString() => 'FlashEmulator(config: $config)'; + String toString() => 'Flash(config: $config)'; - static DeviceEmulator create( - Device config, + static Device create( + RiverDevice config, Map options, - RiverSoCEmulator _soc, + RiverSoC soc, ) { - var data = List.filled(config.mmap!.size, 0); + var data = List.filled(config.range!.size, 0); if (options.containsKey('file')) { data = File(options['file']!).readAsBytesSync(); @@ -37,18 +35,18 @@ class FlashEmulator extends DeviceEmulator { .toList(); } - if (data.length < config.mmap!.size) { - data = [...data, ...List.filled(config.mmap!.size - data.length, 0)]; + if (data.length < config.range!.size) { + data = [...data, ...List.filled(config.range!.size - data.length, 0)]; } - return FlashEmulator(config, data); + return Flash(config, data); } } -class FlashAccessorEmulator extends DeviceAccessorEmulator { - final FlashEmulator rom; +class FlashAccessor extends DeviceAccessor { + final Flash rom; - FlashAccessorEmulator(this.rom) : super(rom.config.accessor!); + FlashAccessor(this.rom); @override Future read(int addr, int width) { diff --git a/packages/river_emulator/lib/src/devices/plic.dart b/packages/river_emulator/lib/src/devices/plic.dart index 3263268..fa96865 100644 --- a/packages/river_emulator/lib/src/devices/plic.dart +++ b/packages/river_emulator/lib/src/devices/plic.dart @@ -4,7 +4,7 @@ import 'package:river/river.dart'; import '../dev.dart'; import '../soc.dart'; -class RiscVPlicEmulator extends DeviceEmulator { +class Plic extends Device { final int numSources; final List _priority; final Map _enable = {}; @@ -12,7 +12,7 @@ class RiscVPlicEmulator extends DeviceEmulator { int _pending = 0; - RiscVPlicEmulator(super.config, {this.numSources = 32}) + Plic(super.config, {this.numSources = 32}) : _priority = List.filled(33, 1); void setPriority(int i, int value) { @@ -54,8 +54,8 @@ class RiscVPlicEmulator extends DeviceEmulator { } @override - Map interrupts(int hartId) { - final best = _findBest(hartId); + Map interrupts(int hart) { + final best = _findBest(hart); return {0: best != 0}; } @@ -72,83 +72,82 @@ class RiscVPlicEmulator extends DeviceEmulator { @override void reset() { - for (int i = 0; i < _priority.length; i++) _priority[i] = 1; + for (int i = 0; i < _priority.length; i++) { + _priority[i] = 1; + } _pending = 0; _enable.clear(); _threshold.clear(); } @override - DeviceAccessorEmulator? get memAccessor => RiscVPlicAccessorEmulator(this); + DeviceAccessor? get memAccessor => PlicAccessor(this); - static DeviceEmulator create( - Device config, + static Device create( + RiverDevice config, Map options, - RiverSoCEmulator _soc, + RiverSoC soc, ) { final sources = int.tryParse(options['sources'] ?? '') ?? 32; - return RiscVPlicEmulator(config, numSources: sources); + return Plic(config, numSources: sources); } } -class RiscVPlicAccessorEmulator - extends DeviceFieldAccessorEmulator { - RiscVPlicAccessorEmulator(super.device); +class PlicAccessor extends DeviceAccessor { + final Plic device; - int _parseHart(String name) { - final match = RegExp(r'cpu(\d+)').firstMatch(name); - if (match == null) return 0; - return int.parse(match.group(1)!); - } + PlicAccessor(this.device) : super(type: DeviceAccessorType.io); @override - Future readPath(String name) async { - if (name == 'priority') return device._priority[1]; - if (name == 'pending') return device._pending; - - if (name.startsWith('enable_cpu')) { - final hart = _parseHart(name); + Future read(int addr, int width) async { + // PLIC register map: + // 0x000000-0x000FFF: source priorities (4 bytes each) + // 0x001000-0x00107F: pending bits + // 0x002000-0x0020FF: enable bits for context 0 + // 0x200000: threshold for context 0 + // 0x200004: claim/complete for context 0 + if (addr >= 0x000000 && addr < 0x001000) { + final source = addr ~/ 4; + if (source > 0 && source <= device.numSources) { + return device._priority[source]; + } + } else if (addr >= 0x001000 && addr < 0x001080) { + return device._pending; + } else if (addr >= 0x002000 && addr < 0x002100) { + final hart = (addr - 0x002000) ~/ 0x80; return device._enable[hart] ?? 0; + } else if (addr >= 0x200000 && addr < 0x400000) { + final context = (addr - 0x200000) ~/ 0x1000; + final offset = (addr - 0x200000) % 0x1000; + if (offset == 0) { + return device._threshold[context] ?? 0; + } else if (offset == 4) { + return device.claim(context); + } } - - if (name.startsWith('threshold_cpu')) { - final hart = _parseHart(name); - return device._threshold[hart] ?? 0; - } - - if (name.startsWith('claim_cpu')) { - final hart = _parseHart(name); - return device.claim(hart); - } - return 0; } @override - Future writePath(String name, int value) async { + Future write(int addr, int value, int width) async { value &= 0xFFFFFFFF; - if (name == 'priority') { - device._priority[1] = value & 0x7; - return; - } - - if (name.startsWith('enable_cpu')) { - final hart = _parseHart(name); + if (addr >= 0x000000 && addr < 0x001000) { + final source = addr ~/ 4; + if (source > 0 && source <= device.numSources) { + device._priority[source] = value & 0x7; + } + } else if (addr >= 0x002000 && addr < 0x002100) { + final hart = (addr - 0x002000) ~/ 0x80; device._enable[hart] = value; - return; - } - - if (name.startsWith('threshold_cpu')) { - final hart = _parseHart(name); - device._threshold[hart] = value & 0x7; - return; - } - - if (name.startsWith('claim_cpu')) { - final hart = _parseHart(name); - device.complete(hart, value); - return; + } else if (addr >= 0x200000 && addr < 0x400000) { + final context = (addr - 0x200000) ~/ 0x1000; + final offset = (addr - 0x200000) % 0x1000; + if (offset == 0) { + device._threshold[context] = value & 0x7; + } else if (offset == 4) { + device.complete(context, value); + } } } } diff --git a/packages/river_emulator/lib/src/devices/sram.dart b/packages/river_emulator/lib/src/devices/sram.dart index 804ba84..d5cf052 100644 --- a/packages/river_emulator/lib/src/devices/sram.dart +++ b/packages/river_emulator/lib/src/devices/sram.dart @@ -1,13 +1,11 @@ -import 'package:riscv/riscv.dart'; import 'package:river/river.dart'; -import '../core.dart'; import '../dev.dart'; import '../soc.dart'; -class SramEmulator extends DeviceEmulator { +class Sram extends Device { List data; - SramEmulator(super.config) : data = List.filled(config.mmap!.size, 0); + Sram(super.config) : data = List.filled(config.range!.size, 0); @override void reset() { @@ -15,22 +13,22 @@ class SramEmulator extends DeviceEmulator { } @override - DeviceAccessorEmulator? get memAccessor => SramAccessorEmulator(this); + DeviceAccessor? get memAccessor => SramAccessor(this); @override - String toString() => 'SramEmulator(config: $config)'; + String toString() => 'Sram(config: $config)'; - static DeviceEmulator create( - Device config, - Map _options, - RiverSoCEmulator _soc, - ) => SramEmulator(config); + static Device create( + RiverDevice config, + Map options, + RiverSoC soc, + ) => Sram(config); } -class SramAccessorEmulator extends DeviceAccessorEmulator { - final SramEmulator sram; +class SramAccessor extends DeviceAccessor { + final Sram sram; - SramAccessorEmulator(this.sram) : super(sram.config.accessor!); + SramAccessor(this.sram); @override Future read(int addr, int width) { @@ -46,7 +44,6 @@ class SramAccessorEmulator extends DeviceAccessorEmulator { Future write(int addr, int value, int width) async { for (int i = 0; i < width; i++) { final byte = (value >> (8 * i)) & 0xFF; - sram.data[addr + i] = byte; } } diff --git a/packages/river_emulator/lib/src/devices/uart.dart b/packages/river_emulator/lib/src/devices/uart.dart index 4b5b0da..af88deb 100644 --- a/packages/river_emulator/lib/src/devices/uart.dart +++ b/packages/river_emulator/lib/src/devices/uart.dart @@ -4,14 +4,13 @@ import 'package:river/river.dart'; import '../dev.dart'; import '../soc.dart'; -class UartEmulator extends DeviceEmulator { +class Uart extends Device { final Stream> input; final StreamSink> output; final List _rxFifo = []; final List _txFifo = []; - - late final StreamSubscription _inputSubscription; + bool _txPending = false; int dll = 0; int dlm = 0; @@ -24,8 +23,8 @@ class UartEmulator extends DeviceEmulator { int scr = 0; int fcr = 0; - UartEmulator(super.config, {required this.input, required this.output}) { - _inputSubscription = input.listen((data) { + Uart(super.config, {required this.input, required this.output}) { + input.listen((data) { _rxFifo.addAll(data); _updateLineStatus(); _updateIIR(); @@ -38,7 +37,7 @@ class UartEmulator extends DeviceEmulator { int get baud { if (divisor == 0) return 0; - return config.clock!.baseFreqHz ~/ divisor; + return (config.clockFrequency ?? 0) ~/ divisor; } void _updateLineStatus() { @@ -51,8 +50,10 @@ class UartEmulator extends DeviceEmulator { } Future flush() async { - while (_txFifo.isNotEmpty) await Future.delayed(Duration.zero); - await Future.delayed(Duration.zero); + while (_txFifo.isNotEmpty) { + await Future.delayed(Duration.zero); + } + await Future.delayed(Duration.zero); } void _updateIIR() { @@ -75,8 +76,6 @@ class UartEmulator extends DeviceEmulator { } bool _lineStatusInterrupt() { - // Typically parity/framing/overrun/break errors - // For now: no errors return false; } @@ -100,32 +99,31 @@ class UartEmulator extends DeviceEmulator { _txFifo.add(value & 0xFF); _updateLineStatus(); _updateIIR(); - - if (_txFifo.isNotEmpty) { - _scheduleNextTx(); - } + _scheduleNextTx(); } void _scheduleNextTx() { - if (_txFifo.isEmpty) return; - - final byte = _txFifo.first; + // Only one drain may be in flight; otherwise multiple timers race and + // capture a stale head, dropping/duplicating bytes. + if (_txPending || _txFifo.isEmpty) return; + _txPending = true; Future.delayed(txDelay(), () { + _txPending = false; + if (_txFifo.isEmpty) return; + + final byte = _txFifo.removeAt(0); output.add([byte]); - _txFifo.removeAt(0); _updateLineStatus(); _updateIIR(); - if (_txFifo.isNotEmpty) { - _scheduleNextTx(); - } + _scheduleNextTx(); }); } @override - Map interrupts(int hartId) { + Map interrupts(int hart) { final pending = (iir & 0x01) == 0; return {0: pending}; } @@ -148,12 +146,12 @@ class UartEmulator extends DeviceEmulator { } @override - DeviceAccessorEmulator? get memAccessor => UartAccessorEmulator(this); + DeviceAccessor? get memAccessor => UartAccessor(this); - static DeviceEmulator create( - Device config, + static Device create( + RiverDevice config, Map options, - RiverSoCEmulator _soc, + RiverSoC soc, ) { Stream>? input; StreamSink>? output; @@ -188,74 +186,73 @@ class UartEmulator extends DeviceEmulator { input = stdin; } - return UartEmulator(config, input: input!, output: output ?? stdout); + return Uart(config, input: input, output: output ?? stdout); } } -class UartAccessorEmulator extends DeviceFieldAccessorEmulator { - UartAccessorEmulator(super.device); +class UartAccessor extends DeviceAccessor { + final Uart device; + + UartAccessor(this.device) : super(type: DeviceAccessorType.io); @override - Future readPath(String name) async { - switch (name) { - case 'rbr_thr_dll': - await Future.delayed(Duration.zero); + Future read(int addr, int width) async { + // NS16550A register map (1 byte each) + switch (addr) { + case 0: // RBR/DLL + await Future.delayed(Duration.zero); return device.dlab ? device.dll : device._readRBR(); - case 'ier_dlm': + case 1: // IER/DLM return device.dlab ? device.dlm : device.ier; - case 'iir_fcr': + case 2: // IIR return device.iir | (device.fcr & 0xC0); - case 'lcr': + case 3: // LCR return device.lcr; - case 'mcr': + case 4: // MCR return device.mcr; - case 'lsr': - await Future.delayed(Duration.zero); + case 5: // LSR + await Future.delayed(Duration.zero); return device.lsr; - case 'msr': + case 6: // MSR return device.msr; - case 'scr': + case 7: // SCR return device.scr; + default: + return 0; } - - return 0; } @override - Future writePath(String name, int value) async { + Future write(int addr, int value, int width) async { value &= 0xFF; - switch (name) { - case 'rbr_thr_dll': - if (device.dlab) + switch (addr) { + case 0: // THR/DLL + if (device.dlab) { device.dll = value; - else + } else { device._writeTHR(value); - break; - case 'ier_dlm': - if (device.dlab) + } + case 1: // IER/DLM + if (device.dlab) { device.dlm = value; - else + } else { device.ier = value; + } device._updateIIR(); - break; - case 'iir_fcr': + case 2: // FCR device.fcr = value; if ((value & 0x02) != 0) device._rxFifo.clear(); if ((value & 0x04) != 0) device._txFifo.clear(); device._updateLineStatus(); device._updateIIR(); - break; - case 'lcr': + case 3: // LCR device.lcr = value; device._updateLineStatus(); - break; - case 'mcr': + case 4: // MCR device.mcr = value; - break; - case 'scr': + case 7: // SCR device.scr = value; - break; } } } diff --git a/packages/river_emulator/lib/src/int.dart b/packages/river_emulator/lib/src/int.dart index dfddca4..5a4052f 100644 --- a/packages/river_emulator/lib/src/int.dart +++ b/packages/river_emulator/lib/src/int.dart @@ -1,7 +1,7 @@ -import 'package:river/river.dart'; +import 'package:river/river.dart' as river; -class InterruptControllerEmulator { - final InterruptController config; +class InterruptController { + final river.InterruptController config; final Map _pending = {}; final Map _priority = {}; @@ -10,7 +10,7 @@ class InterruptControllerEmulator { final Map _targetByIrq = {}; final Map _sourceByIrq = {}; - InterruptControllerEmulator(this.config) { + InterruptController(this.config) { for (final line in config.lines) { final irq = line.irq; _pending[irq] = false; @@ -179,6 +179,5 @@ class InterruptControllerEmulator { } @override - String toString() => - 'InterruptControllerEmulator(config: $config, pending: $irqs)'; + String toString() => 'InterruptController(config: $config, pending: $irqs)'; } diff --git a/packages/river_emulator/lib/src/mmu.dart b/packages/river_emulator/lib/src/mmu.dart index 4d71d84..7cd3304 100644 --- a/packages/river_emulator/lib/src/mmu.dart +++ b/packages/river_emulator/lib/src/mmu.dart @@ -1,21 +1,40 @@ -import 'package:riscv/riscv.dart'; import 'package:river/river.dart'; -import 'core.dart'; +import 'core.dart' show TrapException; +import 'decoded_instruction.dart'; import 'dev.dart'; +import 'tlb.dart'; + +enum MemoryAccess { instr, read, write } const kPageSize = 4096; -class MmuEmulator { - final Mmu config; - final Map devices; - PagingMode mode; +Trap _pageFault(MemoryAccess access) => switch (access) { + MemoryAccess.instr => Trap.instructionPageFault, + MemoryAccess.read => Trap.loadPageFault, + MemoryAccess.write => Trap.storePageFault, +}; + +/// Guest (second/G-stage) page-fault cause, used when a two-stage walk faults in +/// the hgatp G-stage rather than the VS-stage. Cf. instruction/load/storePageFault. +Trap _guestPageFault(MemoryAccess access) => switch (access) { + MemoryAccess.instr => Trap.instructionGuestPageFault, + MemoryAccess.read => Trap.loadGuestPageFault, + MemoryAccess.write => Trap.storeGuestPageFault, +}; + +class Mmu { + final HarborMmuConfig config; + final Map devices; + RiscVPagingMode mode; bool _pagingEnabled; int _pageTable; + final Tlb tlb; - MmuEmulator(this.config, this.devices) + Mmu(this.config, this.devices, {int tlbEntries = 32}) : _pagingEnabled = false, _pageTable = 0, - mode = PagingMode.bare; + mode = RiscVPagingMode.bare, + tlb = Tlb(entries: tlbEntries); bool get pagingEnabled => config.hasPaging && _pagingEnabled; @@ -39,7 +58,7 @@ class MmuEmulator { void configure(int modeId, int ppn) { final pmode = - PagingMode.fromId(modeId) ?? + pagingModeFromId(modeId) ?? (throw TrapException.illegalInstruction(StackTrace.current)); if (!pmode.isSupported(config.mxlen)) { @@ -48,13 +67,18 @@ class MmuEmulator { mode = pmode; pageTable = ppn * kPageSize; - pagingEnabled = mode != PagingMode.bare; + pagingEnabled = mode != RiscVPagingMode.bare; } void reset() { - mode = PagingMode.bare; + mode = RiscVPagingMode.bare; _pagingEnabled = false; _pageTable = 0; + tlb.reset(); + } + + void flushTlb({int? asid, int? vaddr}) { + tlb.flush(asid: asid, vaddr: vaddr, mode: mode); } Future translate( @@ -64,11 +88,39 @@ class MmuEmulator { bool sum = false, bool mxr = false, }) async { - if (!pagingEnabled || mode == PagingMode.bare) return addr; + if (!pagingEnabled || mode == RiscVPagingMode.bare) return addr; + + sum = sum && config.hasSupervisorUserMemory; + mxr = mxr && config.hasMakeExecutableReadable; + + // TLB lookup + final tlbResult = tlb.lookup(addr, access, mode); + if (tlbResult.hit) { + final entry = tlbResult.entry!; + bool allowed = false; + switch (access) { + case MemoryAccess.read: + allowed = entry.read || (mxr && entry.execute); + case MemoryAccess.write: + allowed = entry.write; + case MemoryAccess.instr: + allowed = entry.execute; + } + if (privilege == PrivilegeMode.user && !entry.user) allowed = false; + if (privilege == PrivilegeMode.supervisor && + entry.user && + !sum && + access != MemoryAccess.instr) { + allowed = false; + } - sum = sum && config.hasSum; - mxr = mxr && config.hasMxr; + if (!allowed) { + throw TrapException(_pageFault(access), addr); + } + return tlbResult.physAddr; + } + // TLB miss - full page table walk final levels = mode.levels; final vpnBits = mode.vpnBits; final vpnMask = (1 << vpnBits) - 1; @@ -102,8 +154,8 @@ class MmuEmulator { while (true) { final pte = await read( - a + vpn[i] * config.mxlen.width, - config.mxlen.width, + a + vpn[i] * config.mxlen.bytes, + config.mxlen.bytes, pageTranslate: false, privilege: privilege, ); @@ -115,29 +167,17 @@ class MmuEmulator { final u = (pte >> 4) & 1; if (v == 0 || (r == 0 && w == 1)) { - throw TrapException( - access == MemoryAccess.read ? Trap.loadAccess : Trap.storeAccess, - addr, - StackTrace.current, - ); + throw TrapException(_pageFault(access), addr, StackTrace.current); } if (privilege == PrivilegeMode.user && u == 0) { - throw TrapException( - access == MemoryAccess.read ? Trap.loadAccess : Trap.storeAccess, - addr, - StackTrace.current, - ); + throw TrapException(_pageFault(access), addr, StackTrace.current); } if (privilege == PrivilegeMode.supervisor && u == 1) { final isExec = access == MemoryAccess.instr; if (!sum && !isExec) { - throw TrapException( - access == MemoryAccess.read ? Trap.loadAccess : Trap.storeAccess, - addr, - StackTrace.current, - ); + throw TrapException(_pageFault(access), addr, StackTrace.current); } } @@ -157,22 +197,48 @@ class MmuEmulator { } if (!allowed) { - throw TrapException( - access == MemoryAccess.read ? Trap.loadAccess : Trap.storeAccess, - addr, + throw TrapException(_pageFault(access), addr); + } + + // Set Accessed bit, and Dirty bit on writes + final aSet = (pte >> 6) & 1; + final dSet = (pte >> 7) & 1; + final needA = aSet == 0; + final needD = access == MemoryAccess.write && dSet == 0; + if (needA || needD) { + var newPte = pte | (1 << 6); + if (needD) newPte |= (1 << 7); + await write( + a + vpn[i] * config.mxlen.bytes, + newPte, + config.mxlen.bytes, + pageTranslate: false, + privilege: privilege, ); } - return buildPhys(pte, i); + final physAddr = buildPhys(pte, i); + + final g = (pte >> 5) & 1; + tlb.insert( + addr, + physAddr, + i, + mode, + read: r == 1, + write: w == 1, + execute: x == 1, + user: u == 1, + global: g == 1, + ); + + return physAddr; } i -= 1; if (i < 0) { - throw TrapException( - access == MemoryAccess.read ? Trap.loadAccess : Trap.storeAccess, - addr, - ); + throw TrapException(_pageFault(access), addr); } final nextPpn = (pte >> 10); @@ -180,6 +246,139 @@ class MmuEmulator { } } + /// Two-stage (Hypervisor) translation: a guest virtual address [gva] is + /// translated through the VS-stage page tables ([vsatpVal]) and then the + /// G-stage page tables ([hgatpVal]) to a host physical address. Used by the + /// HLV/HSV instructions. A `bare` stage is the identity for that stage. + /// + /// The G-stage uses the "x4" page-table layout: the root index is widened by + /// two bits (a 16 KiB root table) and every leaf must be user-accessible. + Future translateGuest( + int gva, + MemoryAccess access, { + required int vsatpVal, + required int hgatpVal, + }) async { + final modeShift = config.mxlen.satpModeShift; + final modeMask = config.mxlen.satpModeMask; + final ppnMask = config.mxlen.satpPpnMask; + + final vsMode = + pagingModeFromId((vsatpVal >> modeShift) & modeMask) ?? + RiscVPagingMode.bare; + final gMode = + pagingModeFromId((hgatpVal >> modeShift) & modeMask) ?? + RiscVPagingMode.bare; + final gBase = (hgatpVal & ppnMask) * kPageSize; + + // G-stage translator: guest physical -> host physical (identity if bare). + Future gtrans(int gpa, MemoryAccess acc) async => + gMode == RiscVPagingMode.bare + ? gpa + : _walkStage(gBase, gMode, gpa, acc, gStage: true); + + if (vsMode == RiscVPagingMode.bare) { + return gtrans(gva, access); // GPA == GVA + } + final vsBase = (vsatpVal & ppnMask) * kPageSize; + return _walkStage(vsBase, vsMode, gva, access, gtrans: gtrans); + } + + /// One page-table walk for [translateGuest]. When [gtrans] is non-null this + /// is the VS-stage: each guest-physical PTE/table address (including the + /// root) is mapped through it before the host read. [gStage] selects the + /// G-stage "x4" widening of the root index and the user-page requirement. + Future _walkStage( + int rootBase, + RiscVPagingMode mode, + int va, + MemoryAccess access, { + Future Function(int gpa, MemoryAccess acc)? gtrans, + bool gStage = false, + }) async { + final size = config.mxlen.bytes; + final levels = mode.levels; + final vpnBits = mode.vpnBits; + + Future readPte(int gpa) async { + final host = gtrans != null ? await gtrans(gpa, MemoryAccess.read) : gpa; + return read(host, size, pageTranslate: false); + } + + int vpnIndex(int i) { + final extra = (gStage && i == levels - 1) ? 2 : 0; + final width = vpnBits + extra; + return (va >> (12 + vpnBits * i)) & ((1 << width) - 1); + } + + int buildPhys(int pte, int level) { + var phys = va & 0xfff; + for (var i = 0; i < mode.ppnBits.length; i++) { + final extra = (gStage && i == mode.ppnBits.length - 1) ? 2 : 0; + final mask = (1 << (mode.ppnBits[i] + extra)) - 1; + final value = i < level + ? (va >> (12 + mode.vpnBits * i)) & mask + : (pte >> mode.ppnShift(i)) & mask; + phys |= value << mode.ppnPhysShift(i); + } + return phys; + } + + var a = rootBase; + var i = levels - 1; + while (true) { + final pte = await readPte(a + vpnIndex(i) * size); + final v = pte & 1; + final r = (pte >> 1) & 1; + final w = (pte >> 2) & 1; + final x = (pte >> 3) & 1; + final u = (pte >> 4) & 1; + + if (v == 0 || (r == 0 && w == 1)) { + throw TrapException( + gStage ? _guestPageFault(access) : _pageFault(access), + va, + StackTrace.current, + ); + } + + if (r == 1 || x == 1) { + // Every G-stage *leaf* page must be user-accessible (non-leaf PTEs + // carry no meaningful U bit). + if (gStage && u == 0) { + throw TrapException( + gStage ? _guestPageFault(access) : _pageFault(access), + va, + StackTrace.current, + ); + } + final allowed = switch (access) { + MemoryAccess.read => r == 1, + MemoryAccess.write => w == 1, + MemoryAccess.instr => x == 1, + }; + if (!allowed) { + throw TrapException( + gStage ? _guestPageFault(access) : _pageFault(access), + va, + StackTrace.current, + ); + } + return buildPhys(pte, i); + } + + i -= 1; + if (i < 0) { + throw TrapException( + gStage ? _guestPageFault(access) : _pageFault(access), + va, + StackTrace.current, + ); + } + a = (pte >> 10) * kPageSize; // next table (guest-physical in VS-stage) + } + } + Future canCache( int addr, { PrivilegeMode privilege = PrivilegeMode.machine, @@ -196,26 +395,13 @@ class MmuEmulator { ); if (entry != null) { - if (entry.value.config.type == DeviceAccessorType.mixed) { - final laddr = addr - entry.key.start; - if (entry.value.config.ioRange != null) { - if (laddr >= entry.value.config.ioRange!.start && - laddr <= entry.value.config.ioRange!.end) - return false; - } - if (entry.value.config.memoryRange != null) { - if (laddr >= entry.value.config.memoryRange!.start && - laddr <= entry.value.config.memoryRange!.end) - return true; - } - } - return entry.value.config.type == DeviceAccessorType.memory; + return entry.value.type == DeviceAccessorType.memory; } return false; } - Future?> getDevice( + Future?> getDevice( int addr, { PrivilegeMode privilege = PrivilegeMode.machine, bool pageTranslate = true, @@ -328,5 +514,5 @@ class MmuEmulator { @override String toString() => - 'MmuEmulator(config: $config, devices: $devices, pagingEnabled: $pagingEnabled, pageTable: $pageTable)'; + 'Mmu(config: $config, devices: $devices, pagingEnabled: $pagingEnabled, pageTable: $pageTable)'; } diff --git a/packages/river_emulator/lib/src/pipeline.dart b/packages/river_emulator/lib/src/pipeline.dart new file mode 100644 index 0000000..9c16c6d --- /dev/null +++ b/packages/river_emulator/lib/src/pipeline.dart @@ -0,0 +1,60 @@ +import 'package:harbor/harbor.dart' hide PrivilegeMode; +import 'package:river/river.dart'; + +import 'core.dart'; + +enum EmulatorStage { interrupt, fetch, decode, execute, trap } + +typedef StageHandler = Future Function(PipelineContext ctx); + +class PipelineContext { + int pc; + int? instruction; + RiscVOperation? op; + RiverCoreState? state; + bool halted = false; + + PipelineContext(this.pc); +} + +class EmulatorPipeline { + final List _order; + final Map> _handlers = {}; + + EmulatorPipeline({List? order}) + : _order = order ?? EmulatorStage.values; + + void at(EmulatorStage stage, StageHandler handler) { + _handlers.putIfAbsent(stage, () => []).add(handler); + } + + Future run(PipelineContext ctx) async { + for (final stage in _order) { + if (ctx.halted) break; + final handlers = _handlers[stage]; + if (handlers == null) continue; + for (final handler in handlers) { + if (ctx.halted) break; + await handler(ctx); + } + } + return ctx.pc; + } +} + +abstract class EmulatorPipelinePlugin extends FiberPlugin { + EmulatorStage get stage; + + Future handle(PipelineContext ctx); + + @override + void init() { + during.build(() async { + final elem = host.database.get(kPipelineKey); + final pipeline = (elem as HarborValueElement).value; + pipeline.at(stage, handle); + }); + } +} + +const kPipelineKey = HarborDatabaseKey('emulator.pipeline'); diff --git a/packages/river_emulator/lib/src/plugins/cache_plugin.dart b/packages/river_emulator/lib/src/plugins/cache_plugin.dart new file mode 100644 index 0000000..1e20b79 --- /dev/null +++ b/packages/river_emulator/lib/src/plugins/cache_plugin.dart @@ -0,0 +1,61 @@ +import 'package:river/river.dart'; + +import '../cache.dart'; +import 'csr_plugin.dart'; +import 'mmu_plugin.dart'; + +class CachePlugin extends FiberPlugin { + final RiverCoreConfig config; + + Cache? l1i; + Cache? l1d; + + @override + String get name => 'cache'; + + @override + Set get dependencies => {MmuPlugin, CsrPlugin}; + + CachePlugin(this.config); + + void bind(MmuPlugin mmuPlugin, CsrPlugin csrPlugin) { + final mmu = mmuPlugin.mmu; + + l1i = config.l1cache?.i != null + ? Cache( + config.l1cache!.i!, + fill: (addr, size) async { + return await mmu.readBlock(addr, size, pageTranslate: false); + }, + writeback: (_, _, _) async {}, + ) + : null; + + l1d = config.l1cache?.d != null + ? Cache( + config.l1cache!.d, + fill: (addr, size) async { + return await mmu.readBlock(addr, size, pageTranslate: false); + }, + writeback: (addr, value, size) async { + await mmu.write(addr, value, size, pageTranslate: false); + }, + ) + : null; + } + + void reset() { + l1i?.reset(); + l1d?.reset(); + } + + @override + void init() { + during.build(() async { + bind(host.apply(), host.apply()); + }); + } + + @override + Map toJson() => {'name': name}; +} diff --git a/packages/river_emulator/lib/src/plugins/csr_plugin.dart b/packages/river_emulator/lib/src/plugins/csr_plugin.dart new file mode 100644 index 0000000..693c2b0 --- /dev/null +++ b/packages/river_emulator/lib/src/plugins/csr_plugin.dart @@ -0,0 +1,64 @@ +import 'package:river/river.dart'; + +import '../csr.dart'; +import '../mmu.dart'; +import 'mmu_plugin.dart'; + +class CsrPlugin extends FiberPlugin implements CsrContext { + @override + final RiverCoreConfig config; + + late final CsrFile csrs; + + @override + PrivilegeMode mode = PrivilegeMode.machine; + + /// Virtualization bit (H extension). When true the effective mode is the + /// virtualized form (VS/VU) of [mode]. Always false on a core without H. + bool virt = false; + + late final Mmu _mmu; + + @override + Mmu get mmu => _mmu; + + @override + String get name => 'csr'; + + CsrPlugin(this.config); + + void bind(Mmu mmu) { + _mmu = mmu; + csrs = CsrFile( + config.mxlen, + hasSupervisor: config.hasSupervisor, + hasUser: config.hasUser, + hasHypervisor: config.hasHypervisor, + hasStateen: config.hasStateen, + rpipelineCap: config.rpipelineCap, + ); + } + + int read(int address) => csrs.read(address, this); + + void write(int address, int value) => csrs.write(address, value, this); + + void reset() { + mode = PrivilegeMode.machine; + virt = false; + csrs.reset(); + } + + void increment() => csrs.increment(); + + @override + void init() { + during.setup(() async { + final mmuPlugin = host.apply(); + bind(mmuPlugin.mmu); + }); + } + + @override + Map toJson() => {'name': name}; +} diff --git a/packages/river_emulator/lib/src/plugins/mmu_plugin.dart b/packages/river_emulator/lib/src/plugins/mmu_plugin.dart new file mode 100644 index 0000000..3364fb2 --- /dev/null +++ b/packages/river_emulator/lib/src/plugins/mmu_plugin.dart @@ -0,0 +1,29 @@ +import 'package:harbor/harbor.dart' hide PrivilegeMode; +import 'package:river/river.dart'; + +import '../dev.dart'; +import '../mmu.dart'; + +class MmuPlugin extends FiberPlugin { + final HarborMmuConfig mmuConfig; + final Map memDevices; + + late final Mmu mmu; + + @override + String get name => 'mmu'; + + MmuPlugin(this.mmuConfig, this.memDevices); + + void reset() => mmu.reset(); + + @override + void init() { + during.setup(() async { + mmu = Mmu(mmuConfig, memDevices); + }); + } + + @override + Map toJson() => {'name': name}; +} diff --git a/packages/river_emulator/lib/src/plugins/trap_plugin.dart b/packages/river_emulator/lib/src/plugins/trap_plugin.dart new file mode 100644 index 0000000..0d76d5b --- /dev/null +++ b/packages/river_emulator/lib/src/plugins/trap_plugin.dart @@ -0,0 +1,157 @@ +import 'package:river/river.dart'; + +import '../core.dart'; +import 'csr_plugin.dart'; + +class TrapPlugin extends FiberPlugin { + late CsrPlugin csr; + + @override + String get name => 'trap'; + + @override + Set get dependencies => {CsrPlugin}; + + int encodeCause(Trap trap, int xlen) { + final interruptBit = trap.interrupt ? (1 << (xlen - 1)) : 0; + return interruptBit | trap.causeCode; + } + + PrivilegeMode selectTrapTargetMode(Trap trap, RiverCoreConfig config) { + if (csr.mode == PrivilegeMode.machine) return PrivilegeMode.machine; + if (!config.hasSupervisor) return PrivilegeMode.machine; + + if (trap.interrupt) { + final mideleg = csr.read(CsrAddress.mideleg.address); + return ((mideleg >> trap.causeCode) & 1) != 0 + ? PrivilegeMode.supervisor + : PrivilegeMode.machine; + } else { + final medeleg = csr.read(CsrAddress.medeleg.address); + return ((medeleg >> trap.causeCode) & 1) != 0 + ? PrivilegeMode.supervisor + : PrivilegeMode.machine; + } + } + + /// H: whether hedeleg (exceptions) / hideleg (interrupts) further delegate a + /// medeleg-delegated trap from HS down to VS-mode. + bool _hDelegates(Trap trap) { + final reg = trap.interrupt + ? csr.read(CsrAddress.hideleg.address) + : csr.read(CsrAddress.hedeleg.address); + return ((reg >> trap.causeCode) & 1) != 0; + } + + int trap(int pc, TrapException e, RiverCoreConfig config) { + final oldMode = csr.mode; + final oldVirt = csr.virt; + final targetMode = selectTrapTargetMode(e.trap, config); + final xlen = config.mxlen.size; + final causeValue = encodeCause(e.trap, xlen); + + // H: a trap taken in VS-mode (virt=1) that medeleg delegates to S AND + // hedeleg/hideleg further delegates stays virtualized -> VS-mode: it uses the + // vs* trap CSRs, vectors through vstvec, pushes vsstatus, and keeps virt=1. + // Otherwise the trap de-virtualizes (HS or M) and clears virt. + final toVS = + config.hasHypervisor && + oldVirt && + targetMode == PrivilegeMode.supervisor && + _hDelegates(e.trap); + + late final CsrAddress causeCsr, epcCsr, tvalCsr, tvecCsr; + + if (toVS) { + causeCsr = CsrAddress.vscause; + epcCsr = CsrAddress.vsepc; + tvalCsr = CsrAddress.vstval; + tvecCsr = CsrAddress.vstvec; + } else { + switch (targetMode) { + case PrivilegeMode.machine: + causeCsr = CsrAddress.mcause; + epcCsr = CsrAddress.mepc; + tvalCsr = CsrAddress.mtval; + tvecCsr = CsrAddress.mtvec; + case PrivilegeMode.supervisor: + causeCsr = CsrAddress.scause; + epcCsr = CsrAddress.sepc; + tvalCsr = CsrAddress.stval; + tvecCsr = CsrAddress.stvec; + case PrivilegeMode.user: + causeCsr = CsrAddress.ucause; + epcCsr = CsrAddress.uepc; + tvalCsr = CsrAddress.utval; + tvecCsr = CsrAddress.utvec; + } + } + + if (toVS) { + // Push the VS status stack (vsstatus.SPP/SPIE/SIE): SPP=0 from VU, 1 from VS. + var vsstatus = csr.read(CsrAddress.vsstatus.address); + final spp = (oldMode == PrivilegeMode.user) ? 0 : 1; + vsstatus = (vsstatus & ~(1 << 8)) | (spp << 8); + final sie = (vsstatus >> 1) & 1; + vsstatus = (vsstatus & ~(1 << 5)) | (sie << 5); + vsstatus &= ~(1 << 1); + csr.write(CsrAddress.vsstatus.address, vsstatus); + } else { + var mstatus = csr.read(CsrAddress.mstatus.address); + switch (targetMode) { + case PrivilegeMode.machine: + final mpp = oldMode.id; + mstatus = (mstatus & ~(0x3 << 11)) | (mpp << 11); + final mie = (mstatus >> 3) & 1; + mstatus = (mstatus & ~(1 << 7)) | (mie << 7); + mstatus &= ~(1 << 3); + case PrivilegeMode.supervisor: + final spp = (oldMode == PrivilegeMode.user) ? 0 : 1; + mstatus = (mstatus & ~(1 << 8)) | (spp << 8); + final sie = (mstatus >> 1) & 1; + mstatus = (mstatus & ~(1 << 5)) | (sie << 5); + mstatus &= ~(1 << 1); + case PrivilegeMode.user: + final uie = mstatus & 1; + mstatus = (mstatus & ~(1 << 4)) | (uie << 4); + mstatus &= ~1; + } + csr.write(CsrAddress.mstatus.address, mstatus); + } + + csr.write(causeCsr.address, causeValue); + csr.write(epcCsr.address, pc); + csr.write(tvalCsr.address, e.tval ?? 0); + + // VS-mode keeps virt=1; HS/M traps de-virtualize. + csr.mode = toVS ? PrivilegeMode.supervisor : targetMode; + if (config.hasHypervisor) csr.virt = toVS; + final tvec = csr.read(tvecCsr.address); + + if (tvec == 0) { + throw AbortException.illegalInstruction( + 'Double fault due to $tvecCsr being invalid ($tvec): $e', + e.stack, + ); + } + + final base = tvec & ~0x3; + final vecMode = tvec & 0x3; + + if (vecMode == 1 && e.trap.interrupt) { + return base + 4 * e.trap.causeCode; + } else { + return base; + } + } + + @override + void init() { + during.setup(() async { + csr = host.apply(); + }); + } + + @override + Map toJson() => {'name': name}; +} diff --git a/packages/river_emulator/lib/src/river_emulator_base.dart b/packages/river_emulator/lib/src/river_emulator_base.dart index a84fd14..61c4f91 100644 --- a/packages/river_emulator/lib/src/river_emulator_base.dart +++ b/packages/river_emulator/lib/src/river_emulator_base.dart @@ -1,8 +1,7 @@ -import 'package:river/river.dart'; import 'soc.dart'; class RiverEmulator { - RiverSoCEmulator soc; + RiverSoC soc; RiverEmulator({required this.soc}); diff --git a/packages/river_emulator/lib/src/soc.dart b/packages/river_emulator/lib/src/soc.dart index d43374e..f150547 100644 --- a/packages/river_emulator/lib/src/soc.dart +++ b/packages/river_emulator/lib/src/soc.dart @@ -1,25 +1,26 @@ import 'dart:collection'; +import 'package:bintools/bintools.dart'; import 'package:river/river.dart'; import 'core.dart'; import 'dev.dart'; import 'devices.dart'; +const _emptyConfig = RiverSoCConfig(); + /// Emulator of the SoC -class RiverSoCEmulator { - List _cores; - List _devices; +class RiverSoC { + List _cores; + List _devices; - final RiverSoC config; + final RiverSoCConfig config; - UnmodifiableListView get cores => - UnmodifiableListView(_cores); - UnmodifiableListView get devices => - UnmodifiableListView(_devices); + UnmodifiableListView get cores => UnmodifiableListView(_cores); + UnmodifiableListView get devices => UnmodifiableListView(_devices); - RiverSoCEmulator( + RiverSoC( this.config, { Map> deviceOptions = const {}, - Map deviceFactory = kDeviceEmulatorFactory, + Map deviceFactory = kDeviceFactory, }) : _cores = const [], _devices = const [] { _devices = config.devices.map((dev) { @@ -31,18 +32,25 @@ class RiverSoCEmulator { ); } - return DeviceEmulator(dev); + return Device(dev); }).toList(); final memDevices = Map.fromEntries( _devices.map((dev) => dev.mem).nonNulls.toList(), ); _cores = config.cores - .map((core) => RiverCoreEmulator(core, memDevices: memDevices)) + .map((core) => RiverCore(core, memDevices: memDevices)) .toList(); } - DeviceEmulator? getDevice(String name) { + RiverSoC.fromDevicesAndCores({ + required List cores, + required List devices, + }) : config = _emptyConfig, + _cores = cores, + _devices = devices; + + Device? getDevice(String name) { for (final dev in devices) { if (dev.config.name == name) return dev; } @@ -50,13 +58,21 @@ class RiverSoCEmulator { } void reset() { - for (final core in _cores) core.reset(); - for (final dev in _devices) dev.reset(); + for (final core in _cores) { + core.reset(); + } + for (final dev in _devices) { + dev.reset(); + } } void increment() { - for (final dev in _devices) dev.increment(); - for (final core in _cores) core.csrs.increment(); + for (final dev in _devices) { + dev.increment(); + } + for (final core in _cores) { + core.csrs.increment(); + } } void interrupts() { @@ -68,8 +84,10 @@ class RiverSoCEmulator { final id = entry.key; final value = entry.value; - if (dev.config.interrupts.length < id) { - throw 'Unmapped interrupt #$id for $dev'; + if (id >= dev.config.interrupts.length) { + // Device emits an interrupt with no configured routing (e.g. a + // CLI-defined SoC without an interrupt map); nothing to deliver. + continue; } final irq = dev.config.interrupts[id]; @@ -83,10 +101,11 @@ class RiverSoCEmulator { if (line.target != '/cpu${core.config.hartId}') continue; - if (value) + if (value) { ctrl.raise(line.source, line.irq); - else + } else { ctrl.lower(line.source, line.irq); + } } } } @@ -111,6 +130,108 @@ class RiverSoCEmulator { return pcs; } + List? _deviceData(Device dev) { + if (dev is Sram) return dev.data; + if (dev is Dram) return dev.data; + if (dev is Flash) return dev.data; + return null; + } + + void loadBytes(int addr, List bytes) { + for (final dev in _devices) { + if (dev.config.range == null) continue; + final range = dev.config.range!; + final data = _deviceData(dev); + if (data == null) continue; + + if (addr >= range.start && addr < range.end) { + final offset = addr - range.start; + for (var i = 0; i < bytes.length && offset + i < data.length; i++) { + data[offset + i] = bytes[i]; + } + return; + } + } + } + + void loadElf(Elf elf) { + for (final ph in elf.programHeaders) { + if (ph.type != 1) continue; + if (ph.fileSize == 0 && ph.memSize == 0) continue; + + final paddr = ph.pAddr; + final segData = elf.segmentData(ph); + + for (final dev in _devices) { + if (dev.config.range == null) continue; + final range = dev.config.range!; + final devData = _deviceData(dev); + if (devData == null) continue; + + if (paddr >= range.start && paddr < range.end) { + final offset = paddr - range.start; + for ( + var i = 0; + i < segData.length && offset + i < devData.length; + i++ + ) { + devData[offset + i] = segData[i]; + } + if (ph.memSize > ph.fileSize) { + final bssStart = offset + ph.fileSize; + final bssEnd = offset + ph.memSize; + for (var i = bssStart; i < bssEnd && i < devData.length; i++) { + devData[i] = 0; + } + } + break; + } + } + } + } + + Future loadMaskrom(Elf elf, {int? hartId}) async { + final core = hartId != null + ? _cores.firstWhere((c) => c.config.hartId == hartId) + : _cores.first; + + final l1i = core.l1i; + final l1d = core.l1d; + + if (l1i == null) { + throw StateError('Cannot load maskrom: core has no L1I cache'); + } + + for (final ph in elf.programHeaders) { + if (ph.type != 1) continue; + final data = elf.segmentData(ph); + if (data.isEmpty) continue; + + final addr = ph.vAddr; + + if ((ph.flags & 0x1) != 0) { + // Executable: load as instructions into L1I + var i = 0; + while (i < data.length) { + final hw = data[i] | (data[i + 1] << 8); + if ((hw & 0x3) != 0x3) { + await l1i.write(addr + i, hw, 2); + i += 2; + } else { + final word = hw | (data[i + 2] << 16) | (data[i + 3] << 24); + await l1i.write(addr + i, word, 4); + i += 4; + } + } + } else if (l1d != null) { + // Data: load into L1D + for (var i = 0; i < data.length; i++) { + await l1d.write(addr + i, data[i], 1); + } + } + } + } + @override - String toString() => 'RiverSoCEmulator(cores: $cores, devices: $devices)'; + String toString() => 'RiverSoC(cores: $cores, devices: $devices)'; } diff --git a/packages/river_emulator/lib/src/tlb.dart b/packages/river_emulator/lib/src/tlb.dart new file mode 100644 index 0000000..9233b6f --- /dev/null +++ b/packages/river_emulator/lib/src/tlb.dart @@ -0,0 +1,155 @@ +import 'package:river/river.dart'; +import 'mmu.dart'; + +class TlbEntry { + final int vpn; + final int ppn; + final int level; + final int asid; + final bool valid; + final bool read; + final bool write; + final bool execute; + final bool user; + final bool global; + int lastAccess; + + TlbEntry({ + required this.vpn, + required this.ppn, + required this.level, + this.asid = 0, + this.valid = true, + this.read = false, + this.write = false, + this.execute = false, + this.user = false, + this.global = false, + this.lastAccess = 0, + }); +} + +class TlbLookupResult { + final int physAddr; + final bool hit; + final TlbEntry? entry; + + const TlbLookupResult.hit(this.physAddr, this.entry) : hit = true; + const TlbLookupResult.miss() : physAddr = 0, hit = false, entry = null; +} + +class Tlb { + final int entries; + final List _table; + int _accessCounter = 0; + int _hits = 0; + int _misses = 0; + + int get hits => _hits; + int get misses => _misses; + + Tlb({this.entries = 32}) : _table = List.filled(entries, null); + + TlbLookupResult lookup( + int vaddr, + MemoryAccess access, + RiscVPagingMode mode, { + int asid = 0, + }) { + _accessCounter++; + + final vpnBits = mode.vpnBits; + + for (var i = 0; i < _table.length; i++) { + final entry = _table[i]; + if (entry == null || !entry.valid) continue; + if (!entry.global && entry.asid != asid) continue; + + final pageBits = 12 + vpnBits * entry.level; + final entryVpn = vaddr >> pageBits; + if (entryVpn != entry.vpn) continue; + + final offset = vaddr & ((1 << pageBits) - 1); + final physAddr = (entry.ppn << pageBits) | offset; + + entry.lastAccess = _accessCounter; + _hits++; + return TlbLookupResult.hit(physAddr, entry); + } + + _misses++; + return const TlbLookupResult.miss(); + } + + void insert( + int vaddr, + int paddr, + int level, + RiscVPagingMode mode, { + int asid = 0, + bool read = false, + bool write = false, + bool execute = false, + bool user = false, + bool global = false, + }) { + final vpnBits = mode.vpnBits; + final pageBits = 12 + vpnBits * level; + final vpn = vaddr >> pageBits; + final ppn = paddr >> pageBits; + + int victimIdx = 0; + int oldestAccess = _accessCounter + 1; + + for (var i = 0; i < _table.length; i++) { + if (_table[i] == null || !_table[i]!.valid) { + victimIdx = i; + break; + } + if (_table[i]!.lastAccess < oldestAccess) { + oldestAccess = _table[i]!.lastAccess; + victimIdx = i; + } + } + + _table[victimIdx] = TlbEntry( + vpn: vpn, + ppn: ppn, + level: level, + asid: asid, + read: read, + write: write, + execute: execute, + user: user, + global: global, + lastAccess: _accessCounter, + ); + } + + void flush({int? asid, int? vaddr, RiscVPagingMode? mode}) { + for (var i = 0; i < _table.length; i++) { + final entry = _table[i]; + if (entry == null) continue; + + if (asid != null && !entry.global && entry.asid != asid) continue; + + if (vaddr != null && mode != null) { + final vpnBits = mode.vpnBits; + final pageBits = 12 + vpnBits * entry.level; + final entryVpn = vaddr >> pageBits; + if (entryVpn != entry.vpn) continue; + } + + _table[i] = null; + } + } + + void reset() { + for (var i = 0; i < _table.length; i++) { + _table[i] = null; + } + _hits = 0; + _misses = 0; + _accessCounter = 0; + } +} diff --git a/packages/river_emulator/pubspec.yaml b/packages/river_emulator/pubspec.yaml index 9404cd6..4c17251 100644 --- a/packages/river_emulator/pubspec.yaml +++ b/packages/river_emulator/pubspec.yaml @@ -5,14 +5,14 @@ resolution: workspace # repository: https://github.com/my_org/my_repo environment: - sdk: ^3.9.3 + sdk: ^3.11.2 # Add regular dependencies here. dependencies: args: ^2.7.0 bintools: ^1.0.0 + harbor: ^0.0.1 path: ^1.9.1 - riscv: ^1.0.0 river: ^1.0.0 dev_dependencies: diff --git a/packages/river_emulator/test/constants.dart b/packages/river_emulator/test/constants.dart index 2ca272e..9e385ca 100644 --- a/packages/river_emulator/test/constants.dart +++ b/packages/river_emulator/test/constants.dart @@ -1,33 +1,73 @@ -import 'package:riscv/riscv.dart'; import 'package:river/river.dart'; import 'package:test/test.dart'; -const kCpuConfigs = { - 'RC1.n': const RiverCoreV1.nano( - mmu: Mmu(mxlen: Mxlen.mxlen_32, blocks: []), +final kCpuConfigs = { + 'RC1.n': RiverCoreConfigV1.nano( + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv32, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), interrupts: [], - clock: ClockConfig(name: 'test', baseFreqHz: 10000), + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), ), - 'RC1.mi': const RiverCoreV1.micro( - mmu: Mmu(mxlen: Mxlen.mxlen_32, blocks: []), + 'RC1.mi': RiverCoreConfigV1.micro( + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv32, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), interrupts: [], - clock: ClockConfig(name: 'test', baseFreqHz: 10000), + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), ), - 'RC1.s': const RiverCoreV1.small( - mmu: Mmu(mxlen: Mxlen.mxlen_64, blocks: []), + 'RC1.ma': RiverCoreConfigV1.macro( + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + hasSupervisorUserMemory: true, + hasMakeExecutableReadable: true, + ), interrupts: [], - clock: ClockConfig(name: 'test', baseFreqHz: 10000), + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + ), + 'RC1.s': RiverCoreConfigV1.small( + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + hasSupervisorUserMemory: true, + hasMakeExecutableReadable: true, + ), + interrupts: [], + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), ), }; void cpuTests( String name, - dynamic Function(RiverCore) body, { - bool Function(RiverCore)? condition, + dynamic Function(RiverCoreConfig) body, { + bool Function(RiverCoreConfig)? condition, }) { for (final entry in kCpuConfigs.entries) { if (condition != null) { - if (!condition!(entry.value)) continue; + if (!condition(entry.value)) continue; } group('${entry.key} - $name', () => body(entry.value)); } diff --git a/packages/river_emulator/test/core/extensions/a_test.dart b/packages/river_emulator/test/core/extensions/a_test.dart index b7cf986..27e160a 100644 --- a/packages/river_emulator/test/core/extensions/a_test.dart +++ b/packages/river_emulator/test/core/extensions/a_test.dart @@ -1,53 +1,57 @@ -import 'package:riscv/riscv.dart'; import 'package:river/river.dart'; import 'package:river_emulator/river_emulator.dart'; import 'package:test/test.dart'; import '../../constants.dart'; +// AMO instruction builder: funct7[31:25] | rs2[24:20] | rs1[19:15] | funct3[14:12] | rd[11:7] | opcode[6:0] +int _amo(int funct7, int rs2, int rs1, int funct3, int rd) => + (funct7 << 25) | + (rs2 << 20) | + (rs1 << 15) | + (funct3 << 12) | + (rd << 7) | + 0x2F; + void main() { cpuTests('A extension', (config) { - late SramEmulator sram; - late RiverCoreEmulator core; + late Sram sram; + late RiverCore core; late int pc; setUp(() { - sram = SramEmulator( - Device.simple( + sram = Sram( + RiverDevice( name: 'sram', compatible: 'river,sram', range: BusAddressRange(0, 0xFFFF), - fields: const {0: DeviceField('data', 4)}, - clock: config.clock, + clockFrequency: (config.clock.rate as HarborFixedClockRate).frequency, ), ); - core = RiverCoreEmulator( - config, - memDevices: Map.fromEntries([sram.mem!]), - ); + core = RiverCore(config, memDevices: Map.fromEntries([sram.mem!])); pc = config.resetVector; }); Future writeWord(int addr, int value) => - core.mmu.write(addr, value, MicroOpMemSize.word.bytes); + core.mmu.write(addr, value, 4); - Future readWord(int addr) => - core.mmu.read(addr, MicroOpMemSize.word.bytes); + Future readWord(int addr) => core.mmu.read(addr, 4); Future writeDword(int addr, int value) => - core.mmu.write(addr, value, MicroOpMemSize.dword.bytes); + core.mmu.write(addr, value, 8); - Future readDword(int addr) => - core.mmu.read(addr, MicroOpMemSize.dword.bytes); + Future readDword(int addr) => core.mmu.read(addr, 8); + + // funct7 = funct5<<2: lr=0x08, sc=0x0C, amoswap=0x04, amoadd=0x00 + // funct3: word=0x2, dword=0x3 test('lr.w loads a word and reserves the address', () async { await writeWord(0x1000, 0x1234); - await writeWord(0x1234, 10); core.xregs[Register.x5] = 0x1000; - final lrw = 0x1002A0AF; + final lrw = _amo(0x08, 0, 5, 2, 1); // lr.w x1, (x5) await core.cycle(pc, lrw); expect(core.xregs[Register.x1], 0x1234); @@ -59,10 +63,10 @@ void main() { core.xregs[Register.x5] = 0x1000; core.xregs[Register.x6] = 0x2222; - final lrw = 0x1002A0AF; + final lrw = _amo(0x08, 0, 5, 2, 1); // lr.w x1, (x5) await core.cycle(pc, lrw); - final scw = 0x1862A12F; + final scw = _amo(0x0C, 6, 5, 2, 2); // sc.w x2, x6, (x5) await core.cycle(pc, scw); expect(await readWord(0x1000), 0x2222); @@ -74,12 +78,12 @@ void main() { core.xregs[Register.x5] = 0x1000; core.xregs[Register.x6] = 0x2222; - final lrw = 0x1002A0AF; + final lrw = _amo(0x08, 0, 5, 2, 1); // lr.w x1, (x5) await core.cycle(pc, lrw); core.clearReservationSet(); - final scw = 0x1862A1AF; + final scw = _amo(0x0C, 6, 5, 2, 3); // sc.w x3, x6, (x5) await core.cycle(pc, scw); expect(await readWord(0x1000), 0x1111); @@ -91,7 +95,7 @@ void main() { core.xregs[Register.x5] = 0x1000; core.xregs[Register.x6] = 0x5555; - final amoswap = 0x0862A1AF; + final amoswap = _amo(0x04, 6, 5, 2, 3); // amoswap.w x3, x6, (x5) await core.cycle(pc, amoswap); expect(core.xregs[Register.x3], 0xAAAA); @@ -99,24 +103,23 @@ void main() { }); test('amoadd.w adds correctly', () async { - writeWord(0x1000, 10); + await writeWord(0x1000, 10); core.xregs[Register.x5] = 0x1000; core.xregs[Register.x6] = 3; - final amoadd = 0x0062A1AF; + final amoadd = _amo(0x00, 6, 5, 2, 3); // amoadd.w x3, x6, (x5) await core.cycle(pc, amoadd); expect(core.xregs[Register.x3], 10); expect(await readWord(0x1000), 13); }); - if (config.mxlen == Mxlen.mxlen_64) { + if (config.mxlen == RiscVMxlen.rv64) { test('lr.d loads a doubleword and reserves address', () async { await writeDword(0x2000, 0x1122334455667788); core.xregs[Register.x5] = 0x2000; - final lrd = 0x1002B0AF; - + final lrd = _amo(0x08, 0, 5, 3, 1); // lr.d x1, (x5) await core.cycle(pc, lrd); expect(core.xregs[Register.x1], 0x1122334455667788); @@ -124,14 +127,14 @@ void main() { }); test('sc.d succeeds when reservation matches', () async { - writeDword(0x2000, 0x1111); + await writeDword(0x2000, 0x1111); core.xregs[Register.x5] = 0x2000; core.xregs[Register.x6] = 0x2222333344445555; - final lrd = 0x1002B0AF; + final lrd = _amo(0x08, 0, 5, 3, 1); // lr.d x1, (x5) await core.cycle(pc, lrd); - final scd = 0x1862B12F; + final scd = _amo(0x0C, 6, 5, 3, 2); // sc.d x2, x6, (x5) await core.cycle(pc, scd); expect(await readDword(0x2000), 0x2222333344445555); @@ -143,12 +146,12 @@ void main() { core.xregs[Register.x5] = 0x2000; core.xregs[Register.x6] = 0x1111; - final lrd = 0x1002B0AF; + final lrd = _amo(0x08, 0, 5, 3, 1); // lr.d x1, (x5) await core.cycle(pc, lrd); core.clearReservationSet(); - final scd = 0x1862B1AF; + final scd = _amo(0x0C, 6, 5, 3, 3); // sc.d x3, x6, (x5) await core.cycle(pc, scd); expect(await readDword(0x2000), 0x9999); diff --git a/packages/river_emulator/test/core/extensions/c_test.dart b/packages/river_emulator/test/core/extensions/c_test.dart index e5114e3..4aaa21f 100644 --- a/packages/river_emulator/test/core/extensions/c_test.dart +++ b/packages/river_emulator/test/core/extensions/c_test.dart @@ -1,4 +1,3 @@ -import 'package:riscv/riscv.dart'; import 'package:river/river.dart'; import 'package:river_emulator/river_emulator.dart'; import 'package:test/test.dart'; @@ -9,39 +8,29 @@ void main() { cpuTests( 'C extension', (config) { - late SramEmulator sram; - late RiverCoreEmulator core; + late Sram sram; + late RiverCore core; late int pc; setUp(() { - sram = SramEmulator( - Device.simple( + sram = Sram( + RiverDevice( name: 'sram', compatible: 'river,sram', range: BusAddressRange(0, 0xFFFF), - fields: const {0: DeviceField('data', 4)}, - clock: config.clock, + clockFrequency: + (config.clock.rate as HarborFixedClockRate).frequency, ), ); - core = RiverCoreEmulator( - config, - memDevices: Map.fromEntries([sram.mem!]), - ); + core = RiverCore(config, memDevices: Map.fromEntries([sram.mem!])); pc = config.resetVector; }); Future writeWord(int addr, int value) => - core.mmu.write(addr, value, MicroOpMemSize.word.bytes); - - Future readWord(int addr) => - core.mmu.read(addr, MicroOpMemSize.word.bytes); - - Future writeDword(int addr, int value) => - core.mmu.write(addr, value, MicroOpMemSize.dword.bytes); + core.mmu.write(addr, value, 4); - Future readDword(int addr) => - core.mmu.read(addr, MicroOpMemSize.dword.bytes); + Future readWord(int addr) => core.mmu.read(addr, 4); test('c.addi4spn expands to addi rd, x2, nzuimm', () async { core.xregs[Register.x2] = 0x1000; diff --git a/packages/river_emulator/test/core/extensions/d_test.dart b/packages/river_emulator/test/core/extensions/d_test.dart new file mode 100644 index 0000000..caca521 --- /dev/null +++ b/packages/river_emulator/test/core/extensions/d_test.dart @@ -0,0 +1,228 @@ +import 'dart:typed_data'; + +import 'package:river/river.dart'; +import 'package:river_emulator/river_emulator.dart'; +import 'package:test/test.dart'; + +import '../../constants.dart'; + +int _fR(int funct7, int rs2, int rs1, int rm, int rd) => + (funct7 << 25) | (rs2 << 20) | (rs1 << 15) | (rm << 12) | (rd << 7) | 0x53; + +int _fLoad(int imm, int rs1, int funct3, int rd) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (funct3 << 12) | (rd << 7) | 0x07; + +int _fStore(int imm, int rs2, int rs1, int funct3) => + (((imm >> 5) & 0x7F) << 25) | + (rs2 << 20) | + (rs1 << 15) | + (funct3 << 12) | + ((imm & 0x1F) << 7) | + 0x27; + +int f64bits(double v) { + final bd = ByteData(8); + bd.setFloat64(0, v, Endian.little); + return bd.getUint64(0, Endian.little); +} + +double f64val(int bits) { + final bd = ByteData(8); + bd.setUint64(0, bits, Endian.little); + return bd.getFloat64(0, Endian.little); +} + +void writeDword(Sram sram, int addr, int value) { + for (int i = 0; i < 8; i++) { + sram.data[addr + i] = (value >> (i * 8)) & 0xFF; + } +} + +int readDword(Sram sram, int addr) { + int v = 0; + for (int i = 0; i < 8; i++) { + v |= sram.data[addr + i] << (i * 8); + } + return v; +} + +void main() { + cpuTests('D extension', (config) { + late Sram sram; + late RiverCore core; + late int pc; + + setUp(() { + sram = Sram( + RiverDevice( + name: 'sram', + compatible: 'river,sram', + range: BusAddressRange(0, 0xFFFF), + clockFrequency: (config.clock.rate as HarborFixedClockRate).frequency, + ), + ); + + core = RiverCore(config, memDevices: Map.fromEntries([sram.mem!])); + pc = config.resetVector; + }); + + test('fadd.d adds two doubles', () async { + core.xregs[Register.x5] = f64bits(3.0); + core.xregs[Register.x6] = f64bits(4.5); + + // fadd.d f7, f5, f6 (funct7=0x01) + final fadd = _fR(0x01, 6, 5, 0, 7); + pc = await core.cycle(pc, fadd); + + expect(f64val(core.xregs[Register.x7]!), closeTo(7.5, 1e-12)); + }); + + test('fsub.d subtracts two doubles', () async { + core.xregs[Register.x5] = f64bits(10.0); + core.xregs[Register.x6] = f64bits(3.5); + + // fsub.d f7, f5, f6 (funct7=0x05) + final fsub = _fR(0x05, 6, 5, 0, 7); + pc = await core.cycle(pc, fsub); + + expect(f64val(core.xregs[Register.x7]!), closeTo(6.5, 1e-12)); + }); + + test('fmul.d multiplies two doubles', () async { + core.xregs[Register.x5] = f64bits(3.0); + core.xregs[Register.x6] = f64bits(2.5); + + // fmul.d f7, f5, f6 (funct7=0x09) + final fmul = _fR(0x09, 6, 5, 0, 7); + pc = await core.cycle(pc, fmul); + + expect(f64val(core.xregs[Register.x7]!), closeTo(7.5, 1e-12)); + }); + + test('fdiv.d divides two doubles', () async { + core.xregs[Register.x5] = f64bits(10.0); + core.xregs[Register.x6] = f64bits(4.0); + + // fdiv.d f7, f5, f6 (funct7=0x0D) + final fdiv = _fR(0x0D, 6, 5, 0, 7); + pc = await core.cycle(pc, fdiv); + + expect(f64val(core.xregs[Register.x7]!), closeTo(2.5, 1e-12)); + }); + + test('fsqrt.d computes square root', () async { + core.xregs[Register.x5] = f64bits(9.0); + + // fsqrt.d f7, f5 (funct7=0x2D, rs2=0) + final fsqrt = _fR(0x2D, 0, 5, 0, 7); + pc = await core.cycle(pc, fsqrt); + + expect(f64val(core.xregs[Register.x7]!), closeTo(3.0, 1e-12)); + }); + + test('feq.d returns 1 when equal', () async { + core.xregs[Register.x5] = f64bits(2.5); + core.xregs[Register.x6] = f64bits(2.5); + + // feq.d x7, f5, f6 (funct7=0x51, funct3=0x2) + final feq = _fR(0x51, 6, 5, 2, 7); + pc = await core.cycle(pc, feq); + + expect(core.xregs[Register.x7], 1); + }); + + test('feq.d returns 0 when not equal', () async { + core.xregs[Register.x5] = f64bits(2.5); + core.xregs[Register.x6] = f64bits(3.0); + + final feq = _fR(0x51, 6, 5, 2, 7); + pc = await core.cycle(pc, feq); + + expect(core.xregs[Register.x7], 0); + }); + + test('flt.d returns 1 when less than', () async { + core.xregs[Register.x5] = f64bits(2.0); + core.xregs[Register.x6] = f64bits(3.0); + + // flt.d x7, f5, f6 (funct7=0x51, funct3=0x1) + final flt = _fR(0x51, 6, 5, 1, 7); + pc = await core.cycle(pc, flt); + + expect(core.xregs[Register.x7], 1); + }); + + test('fle.d returns 1 when less or equal', () async { + core.xregs[Register.x5] = f64bits(3.0); + core.xregs[Register.x6] = f64bits(3.0); + + // fle.d x7, f5, f6 (funct7=0x51, funct3=0x0) + final fle = _fR(0x51, 6, 5, 0, 7); + pc = await core.cycle(pc, fle); + + expect(core.xregs[Register.x7], 1); + }); + + test('fcvt.w.d converts double to signed int', () async { + core.xregs[Register.x5] = f64bits(42.7); + + // fcvt.w.d x7, f5 (funct7=0x61, rs2=0, rm=1 RTZ -> truncate) + final fcvtwd = _fR(0x61, 0, 5, 1, 7); + pc = await core.cycle(pc, fcvtwd); + + expect(core.xregs[Register.x7]! & 0xFFFFFFFF, 42); + }); + + test('fcvt.d.w converts signed int to double', () async { + core.xregs[Register.x5] = 42; + + // fcvt.d.w f7, x5 (funct7=0x69, rs2=0) + final fcvtdw = _fR(0x69, 0, 5, 0, 7); + pc = await core.cycle(pc, fcvtdw); + + expect(f64val(core.xregs[Register.x7]!), closeTo(42.0, 1e-12)); + }); + + test('fld loads double from memory', () async { + core.xregs[Register.x10] = 0x100; + writeDword(sram, 0x100, f64bits(1.5)); + + // fld f7, 0(x10) (funct3=0x3) + final fld = _fLoad(0, 10, 0x3, 7); + pc = await core.cycle(pc, fld); + + expect(f64val(core.xregs[Register.x7]!), closeTo(1.5, 1e-12)); + }); + + test('fsd stores double to memory', () async { + core.xregs[Register.x10] = 0x200; + core.xregs[Register.x7] = f64bits(3.14159); + + // fsd f7, 0(x10) (funct3=0x3) + final fsd = _fStore(0, 7, 10, 0x3); + pc = await core.cycle(pc, fsd); + + expect(f64val(readDword(sram, 0x200)), closeTo(3.14159, 1e-5)); + }); + + test('fadd.d with negative numbers', () async { + core.xregs[Register.x5] = f64bits(-100.5); + core.xregs[Register.x6] = f64bits(50.25); + + final fadd = _fR(0x01, 6, 5, 0, 7); + pc = await core.cycle(pc, fadd); + + expect(f64val(core.xregs[Register.x7]!), closeTo(-50.25, 1e-12)); + }); + + test('fdiv.d precision', () async { + core.xregs[Register.x5] = f64bits(1.0); + core.xregs[Register.x6] = f64bits(3.0); + + final fdiv = _fR(0x0D, 6, 5, 0, 7); + pc = await core.cycle(pc, fdiv); + + expect(f64val(core.xregs[Register.x7]!), closeTo(1.0 / 3.0, 1e-15)); + }); + }, condition: (config) => config.extensions.any((e) => e.name == 'D')); +} diff --git a/packages/river_emulator/test/core/extensions/f_test.dart b/packages/river_emulator/test/core/extensions/f_test.dart new file mode 100644 index 0000000..f5d4b91 --- /dev/null +++ b/packages/river_emulator/test/core/extensions/f_test.dart @@ -0,0 +1,376 @@ +import 'dart:typed_data'; + +import 'package:river/river.dart'; +import 'package:river_emulator/river_emulator.dart'; +import 'package:test/test.dart'; + +import '../../constants.dart'; + +// R-type FP: funct7[31:25] | rs2[24:20] | rs1[19:15] | rm[14:12] | rd[11:7] | opcode[6:0] +int _fR(int funct7, int rs2, int rs1, int rm, int rd) => + (funct7 << 25) | (rs2 << 20) | (rs1 << 15) | (rm << 12) | (rd << 7) | 0x53; + +// R4-type FMA: rs3[31:27] | fmt[26:25] | rs2[24:20] | rs1[19:15] | rm | rd | op. +int _fR4(int opcode, int rs3, int rs2, int rs1, int rd, {int fmt = 0}) => + (rs3 << 27) | (fmt << 25) | (rs2 << 20) | (rs1 << 15) | (rd << 7) | opcode; + +// I-type FP load: imm[31:20] | rs1[19:15] | funct3[14:12] | rd[11:7] | opcode[6:0] +int _fLoad(int imm, int rs1, int funct3, int rd) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (funct3 << 12) | (rd << 7) | 0x07; + +// S-type FP store: imm[11:5][31:25] | rs2[24:20] | rs1[19:15] | funct3[14:12] | imm[4:0][11:7] | opcode[6:0] +int _fStore(int imm, int rs2, int rs1, int funct3) => + (((imm >> 5) & 0x7F) << 25) | + (rs2 << 20) | + (rs1 << 15) | + (funct3 << 12) | + ((imm & 0x1F) << 7) | + 0x27; + +int f32bits(double v) { + final bd = ByteData(4); + bd.setFloat32(0, v, Endian.little); + return bd.getUint32(0, Endian.little); +} + +double f32val(int bits) { + final bd = ByteData(4); + bd.setUint32(0, bits & 0xFFFFFFFF, Endian.little); + return bd.getFloat32(0, Endian.little); +} + +void writeWord(Sram sram, int addr, int value) { + for (int i = 0; i < 4; i++) { + sram.data[addr + i] = (value >> (i * 8)) & 0xFF; + } +} + +int readWord(Sram sram, int addr) { + int v = 0; + for (int i = 0; i < 4; i++) { + v |= sram.data[addr + i] << (i * 8); + } + return v; +} + +void main() { + cpuTests('F extension', (config) { + late Sram sram; + late RiverCore core; + late int pc; + + setUp(() { + sram = Sram( + RiverDevice( + name: 'sram', + compatible: 'river,sram', + range: BusAddressRange(0, 0xFFFF), + clockFrequency: (config.clock.rate as HarborFixedClockRate).frequency, + ), + ); + + core = RiverCore(config, memDevices: Map.fromEntries([sram.mem!])); + pc = config.resetVector; + }); + + test('fadd.s adds two floats', () async { + core.xregs[Register.x5] = f32bits(3.0); + core.xregs[Register.x6] = f32bits(4.5); + + // fadd.s f7, f5, f6 (funct7=0x00) + final fadd = _fR(0x00, 6, 5, 0, 7); + pc = await core.cycle(pc, fadd); + + expect(f32val(core.xregs[Register.x7]!), closeTo(7.5, 1e-6)); + }); + + test('fsub.s subtracts two floats', () async { + core.xregs[Register.x5] = f32bits(10.0); + core.xregs[Register.x6] = f32bits(3.5); + + // fsub.s f7, f5, f6 (funct7=0x04) + final fsub = _fR(0x04, 6, 5, 0, 7); + pc = await core.cycle(pc, fsub); + + expect(f32val(core.xregs[Register.x7]!), closeTo(6.5, 1e-6)); + }); + + test('fmul.s multiplies two floats', () async { + core.xregs[Register.x5] = f32bits(3.0); + core.xregs[Register.x6] = f32bits(2.5); + + // fmul.s f7, f5, f6 (funct7=0x08) + final fmul = _fR(0x08, 6, 5, 0, 7); + pc = await core.cycle(pc, fmul); + + expect(f32val(core.xregs[Register.x7]!), closeTo(7.5, 1e-6)); + }); + + test('fdiv.s divides two floats', () async { + core.xregs[Register.x5] = f32bits(10.0); + core.xregs[Register.x6] = f32bits(4.0); + + // fdiv.s f7, f5, f6 (funct7=0x0C) + final fdiv = _fR(0x0C, 6, 5, 0, 7); + pc = await core.cycle(pc, fdiv); + + expect(f32val(core.xregs[Register.x7]!), closeTo(2.5, 1e-6)); + }); + + test('fsqrt.s computes square root', () async { + core.xregs[Register.x5] = f32bits(9.0); + + // fsqrt.s f7, f5 (funct7=0x2C, rs2=0) + final fsqrt = _fR(0x2C, 0, 5, 0, 7); + pc = await core.cycle(pc, fsqrt); + + expect(f32val(core.xregs[Register.x7]!), closeTo(3.0, 1e-6)); + }); + + test('feq.s returns 1 when equal', () async { + core.xregs[Register.x5] = f32bits(2.5); + core.xregs[Register.x6] = f32bits(2.5); + + // feq.s x7, f5, f6 (funct7=0x50, funct3=0x2) + final feq = _fR(0x50, 6, 5, 2, 7); + pc = await core.cycle(pc, feq); + + expect(core.xregs[Register.x7], 1); + }); + + test('feq.s returns 0 when not equal', () async { + core.xregs[Register.x5] = f32bits(2.5); + core.xregs[Register.x6] = f32bits(3.0); + + final feq = _fR(0x50, 6, 5, 2, 7); + pc = await core.cycle(pc, feq); + + expect(core.xregs[Register.x7], 0); + }); + + test('flt.s returns 1 when less than', () async { + core.xregs[Register.x5] = f32bits(2.0); + core.xregs[Register.x6] = f32bits(3.0); + + // flt.s x7, f5, f6 (funct7=0x50, funct3=0x1) + final flt = _fR(0x50, 6, 5, 1, 7); + pc = await core.cycle(pc, flt); + + expect(core.xregs[Register.x7], 1); + }); + + test('flt.s returns 0 when not less than', () async { + core.xregs[Register.x5] = f32bits(5.0); + core.xregs[Register.x6] = f32bits(3.0); + + final flt = _fR(0x50, 6, 5, 1, 7); + pc = await core.cycle(pc, flt); + + expect(core.xregs[Register.x7], 0); + }); + + test('fle.s returns 1 when less or equal', () async { + core.xregs[Register.x5] = f32bits(3.0); + core.xregs[Register.x6] = f32bits(3.0); + + // fle.s x7, f5, f6 (funct7=0x50, funct3=0x0) + final fle = _fR(0x50, 6, 5, 0, 7); + pc = await core.cycle(pc, fle); + + expect(core.xregs[Register.x7], 1); + }); + + test('fcvt.w.s converts float to signed int', () async { + core.xregs[Register.x5] = f32bits(42.7); + + // fcvt.w.s x7, f5 (funct7=0x60, rs2=0, rm=1 RTZ -> truncate) + final fcvtws = _fR(0x60, 0, 5, 1, 7); + pc = await core.cycle(pc, fcvtws); + + expect(core.xregs[Register.x7], 42); + }); + + test('fcvt.w.s converts negative float to signed int', () async { + core.xregs[Register.x5] = f32bits(-7.9); + + final fcvtws = _fR(0x60, 0, 5, 1, 7); // rm=1 RTZ -> truncate + pc = await core.cycle(pc, fcvtws); + + expect(core.xregs[Register.x7]! & 0xFFFFFFFF, (-7 & 0xFFFFFFFF)); + }); + + test('fcvt.s.w converts signed int to float', () async { + core.xregs[Register.x5] = 42; + + // fcvt.s.w f7, x5 (funct7=0x68, rs2=0) + final fcvtsw = _fR(0x68, 0, 5, 0, 7); + pc = await core.cycle(pc, fcvtsw); + + expect(f32val(core.xregs[Register.x7]!), closeTo(42.0, 1e-6)); + }); + + // fcvt variants select int width+sign from the rs2 field (1=wu, 2=l, 3=lu), + // not the mnemonic. These distinguish the rs2-driven paths from the rs2=0 + // signed-word default. + test('fcvt.wu.s: negative float saturates to 0 (unsigned)', () async { + core.xregs[Register.x5] = f32bits(-7.9); + pc = await core.cycle(pc, _fR(0x60, 1, 5, 0, 7)); // rs2=1 -> wu + expect(core.xregs[Register.x7], 0); + }); + + test('fcvt.wu.s: value above int32 max (unsigned 32)', () async { + core.xregs[Register.x5] = f32bits(3221225472.0); // 0xC0000000 + pc = await core.cycle(pc, _fR(0x60, 1, 5, 0, 7)); + expect(core.xregs[Register.x7]! & 0xFFFFFFFF, 0xC0000000); + }); + + test('fcvt.w.s: 2^31 saturates to int32 max', () async { + core.xregs[Register.x5] = f32bits(2147483648.0); + pc = await core.cycle(pc, _fR(0x60, 0, 5, 0, 7)); // rs2=0 -> w + expect(core.xregs[Register.x7]! & 0xFFFFFFFF, 0x7FFFFFFF); + }); + + test('fcvt.l.s: 2^31 converts to signed 64 (no W saturation)', () async { + core.xregs[Register.x5] = f32bits(2147483648.0); + pc = await core.cycle(pc, _fR(0x60, 2, 5, 0, 7)); // rs2=2 -> l + expect(core.xregs[Register.x7], 2147483648); + }); + + test('fcvt.s.wu: 0xFFFFFFFF is +4.29e9, not -1.0', () async { + core.xregs[Register.x5] = 0xFFFFFFFF; + pc = await core.cycle(pc, _fR(0x68, 1, 5, 0, 7)); // rs2=1 -> s.wu + expect(f32val(core.xregs[Register.x7]!), closeTo(4294967295.0, 256.0)); + }); + + test('fcvt.s.lu: max u64 converts as unsigned (not -1)', () async { + core.xregs[Register.x5] = -1; // 0xFFFFFFFFFFFFFFFF + pc = await core.cycle(pc, _fR(0x68, 3, 5, 0, 7)); // rs2=3 -> s.lu + expect( + f32val(core.xregs[Register.x7]!), + closeTo(1.8446744073709552e19, 1e13), + ); + }); + + // Fused multiply-add: rd = +-(rs1*rs2) +- rs3. a=2, b=3, c=4. + test('fmadd.s = a*b + c', () async { + core.xregs[Register.x5] = f32bits(2.0); + core.xregs[Register.x6] = f32bits(3.0); + core.xregs[Register.x7] = f32bits(4.0); + pc = await core.cycle(pc, _fR4(0x43, 7, 6, 5, 8)); // fmadd.s x8 + expect(f32val(core.xregs[Register.x8]!), closeTo(10.0, 1e-6)); + }); + + test('fmsub.s = a*b - c', () async { + core.xregs[Register.x5] = f32bits(2.0); + core.xregs[Register.x6] = f32bits(3.0); + core.xregs[Register.x7] = f32bits(4.0); + pc = await core.cycle(pc, _fR4(0x47, 7, 6, 5, 8)); // fmsub.s x8 + expect(f32val(core.xregs[Register.x8]!), closeTo(2.0, 1e-6)); + }); + + test('fnmsub.s = -(a*b) + c', () async { + core.xregs[Register.x5] = f32bits(2.0); + core.xregs[Register.x6] = f32bits(3.0); + core.xregs[Register.x7] = f32bits(4.0); + pc = await core.cycle(pc, _fR4(0x4B, 7, 6, 5, 8)); // fnmsub.s x8 + expect(f32val(core.xregs[Register.x8]!), closeTo(-2.0, 1e-6)); + }); + + test('fnmadd.s = -(a*b) - c', () async { + core.xregs[Register.x5] = f32bits(2.0); + core.xregs[Register.x6] = f32bits(3.0); + core.xregs[Register.x7] = f32bits(4.0); + pc = await core.cycle(pc, _fR4(0x4F, 7, 6, 5, 8)); // fnmadd.s x8 + expect(f32val(core.xregs[Register.x8]!), closeTo(-10.0, 1e-6)); + }); + + // fcvt.w.s rounding modes (rm = funct3): 0=RNE,1=RTZ,2=RDN,3=RUP,4=RMM. + // 2.5 distinguishes them (RNE->2 ties-even, RUP/RMM->3, RTZ/RDN->2). + for (final (rm, want) in const [(0, 2), (1, 2), (2, 2), (3, 3), (4, 3)]) { + test('fcvt.w.s 2.5 rm=$rm -> $want', () async { + core.xregs[Register.x5] = f32bits(2.5); + pc = await core.cycle(pc, _fR(0x60, 0, 5, rm, 6)); + expect(core.xregs[Register.x6]! & 0xFFFFFFFF, want); + }); + } + + test('fcvt.w.s 3.5 RNE -> 4 (ties to even)', () async { + core.xregs[Register.x5] = f32bits(3.5); + pc = await core.cycle(pc, _fR(0x60, 0, 5, 0, 6)); // RNE + expect(core.xregs[Register.x6]! & 0xFFFFFFFF, 4); + }); + + test('fcvt.w.s -2.5 RDN -> -3, RUP -> -2', () async { + core.xregs[Register.x5] = f32bits(-2.5); + pc = await core.cycle(pc, _fR(0x60, 0, 5, 2, 6)); // RDN + expect(core.xregs[Register.x6]! & 0xFFFFFFFF, (-3) & 0xFFFFFFFF); + core.xregs[Register.x5] = f32bits(-2.5); + pc = await core.cycle(pc, _fR(0x60, 0, 5, 3, 7)); // RUP + expect(core.xregs[Register.x7]! & 0xFFFFFFFF, (-2) & 0xFFFFFFFF); + }); + + test('flw loads float from memory', () async { + core.xregs[Register.x10] = 0x100; + writeWord(sram, 0x100, f32bits(1.5)); + + // flw f7, 0(x10) (funct3=0x2) + final flw = _fLoad(0, 10, 0x2, 7); + pc = await core.cycle(pc, flw); + + expect(f32val(core.xregs[Register.x7]!), closeTo(1.5, 1e-6)); + }); + + test('flw loads float with offset', () async { + core.xregs[Register.x10] = 0x100; + writeWord(sram, 0x108, f32bits(99.5)); + + // flw f7, 8(x10) + final flw = _fLoad(8, 10, 0x2, 7); + pc = await core.cycle(pc, flw); + + expect(f32val(core.xregs[Register.x7]!), closeTo(99.5, 1e-6)); + }); + + test('fsw stores float to memory', () async { + core.xregs[Register.x10] = 0x200; + core.xregs[Register.x7] = f32bits(3.14); + + // fsw f7, 0(x10) (funct3=0x2) + final fsw = _fStore(0, 7, 10, 0x2); + pc = await core.cycle(pc, fsw); + + expect(f32val(readWord(sram, 0x200)), closeTo(3.14, 0.01)); + }); + + test('fsw stores float with offset', () async { + core.xregs[Register.x10] = 0x200; + core.xregs[Register.x7] = f32bits(2.718); + + // fsw f7, 4(x10) + final fsw = _fStore(4, 7, 10, 0x2); + pc = await core.cycle(pc, fsw); + + expect(f32val(readWord(sram, 0x204)), closeTo(2.718, 0.01)); + }); + + test('fadd.s with negative numbers', () async { + core.xregs[Register.x5] = f32bits(-3.0); + core.xregs[Register.x6] = f32bits(1.5); + + final fadd = _fR(0x00, 6, 5, 0, 7); + pc = await core.cycle(pc, fadd); + + expect(f32val(core.xregs[Register.x7]!), closeTo(-1.5, 1e-6)); + }); + + test('fmul.s with zero', () async { + core.xregs[Register.x5] = f32bits(123.456); + core.xregs[Register.x6] = f32bits(0.0); + + final fmul = _fR(0x08, 6, 5, 0, 7); + pc = await core.cycle(pc, fmul); + + expect(f32val(core.xregs[Register.x7]!), 0.0); + }); + }, condition: (config) => config.extensions.any((e) => e.name == 'F')); +} diff --git a/packages/river_emulator/test/core/extensions/m_test.dart b/packages/river_emulator/test/core/extensions/m_test.dart index cda4892..0829d96 100644 --- a/packages/river_emulator/test/core/extensions/m_test.dart +++ b/packages/river_emulator/test/core/extensions/m_test.dart @@ -1,4 +1,3 @@ -import 'package:riscv/riscv.dart'; import 'package:river/river.dart'; import 'package:river_emulator/river_emulator.dart'; import 'package:test/test.dart'; @@ -7,25 +6,21 @@ import '../../constants.dart'; void main() { cpuTests('M extension', (config) { - late SramEmulator sram; - late RiverCoreEmulator core; + late Sram sram; + late RiverCore core; late int pc; setUp(() { - sram = SramEmulator( - Device.simple( + sram = Sram( + RiverDevice( name: 'sram', compatible: 'river,sram', range: BusAddressRange(0, 0xFFFF), - fields: const {0: DeviceField('data', 4)}, - clock: config.clock, + clockFrequency: (config.clock.rate as HarborFixedClockRate).frequency, ), ); - core = RiverCoreEmulator( - config, - memDevices: Map.fromEntries([sram.mem!]), - ); + core = RiverCore(config, memDevices: Map.fromEntries([sram.mem!])); pc = config.resetVector; }); @@ -106,9 +101,12 @@ void main() { final divu = 0x025353b3; await core.cycle(pc, divu); + // All-ones in the emulator's Dart-int convention: toSigned(64) maps the + // 64-bit all-ones to -1 and leaves the 32-bit value (4294967295) positive. + // (Plain .toInt() would clamp the 64-bit value to maxInt - that was a bug.) expect( core.xregs[Register.x7], - ((BigInt.one << config.mxlen.size) - BigInt.one).toInt(), + ((BigInt.one << config.mxlen.size) - BigInt.one).toSigned(64).toInt(), ); }); @@ -122,7 +120,7 @@ void main() { expect(core.xregs[Register.x7], -42); }); - if (config.mxlen == Mxlen.mxlen_64) { + if (config.mxlen == RiscVMxlen.rv64) { test('mulw uses 32-bit product and sign-extends to XLEN', () async { core.xregs[Register.x5] = 2; core.xregs[Register.x6] = 0x00000000FFFFFFFF; diff --git a/packages/river_emulator/test/core/extensions/rva22_smode_test.dart b/packages/river_emulator/test/core/extensions/rva22_smode_test.dart new file mode 100644 index 0000000..5bd2878 --- /dev/null +++ b/packages/river_emulator/test/core/extensions/rva22_smode_test.dart @@ -0,0 +1,184 @@ +import 'package:river/river.dart'; +import 'package:river_emulator/river_emulator.dart'; +import 'package:test/test.dart'; + +/// RVA22S64 supervisor verification: Sv39 paging (3-level walk) and the +/// Svnapot NAPOT page-attribute bit. See project_rva22 in memory. +void main() { + group('RVA22 S-mode Sv39', () { + late Sram sram; + late Mmu mmu; + + // Page tables live inside SRAM; map virtual pages identity to a physical + // address that is also within SRAM so reads/writes resolve. + const l2Base = 0x10000; + const l1Base = 0x11000; + const l0Base = 0x12000; + + setUp(() { + sram = Sram( + RiverDevice( + name: 'sram', + compatible: 'river,sram', + range: BusAddressRange(0, 0xFFFFFF), + clockFrequency: 10000, + ), + ); + mmu = Mmu( + HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + hasSupervisorUserMemory: true, + hasMakeExecutableReadable: true, + ), + Map.fromEntries([sram.mem!]), + ); + mmu.configure(8, l2Base >> 12); // Sv39 + }); + + void writeDword(int addr, int value) { + for (var i = 0; i < 8; i++) { + sram.data[addr + i] = (value >> (i * 8)) & 0xFF; + } + } + + // Identity-map the 4 KiB page containing [vaddr]. napot sets PTE bit 63. + void mapPage( + int vaddr, { + bool r = true, + bool w = true, + bool x = true, + bool u = false, + bool napot = false, + }) { + final vpn2 = (vaddr >> 30) & 0x1FF; + final vpn1 = (vaddr >> 21) & 0x1FF; + final vpn0 = (vaddr >> 12) & 0x1FF; + final physPage = vaddr >> 12; + writeDword(l2Base + vpn2 * 8, ((l1Base >> 12) << 10) | 0x1); // non-leaf + writeDword(l1Base + vpn1 * 8, ((l0Base >> 12) << 10) | 0x1); // non-leaf + var flags = 0x1; + if (r) flags |= 0x2; + if (w) flags |= 0x4; + if (x) flags |= 0x8; + if (u) flags |= 0x10; + var pte = (physPage << 10) | flags; + if (napot) pte |= 1 << 63; + writeDword(l0Base + vpn0 * 8, pte); + } + + test('translates a leaf page (3-level walk)', () async { + mapPage(0x20000); + final phys = await mmu.translate( + 0x20000, + MemoryAccess.read, + privilege: PrivilegeMode.supervisor, + ); + expect(phys, 0x20000); + }); + + test('load page fault for unmapped address', () async { + expect( + () => mmu.translate( + 0x40000, + MemoryAccess.read, + privilege: PrivilegeMode.supervisor, + ), + throwsA(isA()), + ); + }); + + test('store page fault for read-only page', () async { + mapPage(0x20000, w: false); + expect( + () => mmu.translate( + 0x20000, + MemoryAccess.write, + privilege: PrivilegeMode.supervisor, + ), + throwsA(isA()), + ); + }); + + test('Svnapot: PTE with N bit still translates', () async { + mapPage(0x20000, napot: true); + final phys = await mmu.translate( + 0x20000, + MemoryAccess.read, + privilege: PrivilegeMode.supervisor, + ); + expect(phys, 0x20000); + }); + }); + + group('RVA22 S-mode privilege', () { + late Sram sram; + late RiverCore core; + final config = RiverCoreConfig( + mxlen: RiscVMxlen.rv64, + extensions: kRva22S64Extensions, + type: RiverCoreType.general, + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + hasSupervisorUserMemory: true, + hasMakeExecutableReadable: true, + ), + interrupts: [], + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + ); + + setUp(() { + sram = Sram( + RiverDevice( + name: 'sram', + compatible: 'river,sram', + range: BusAddressRange(0, 0xFFFF), + clockFrequency: 10000, + ), + ); + core = RiverCore(config, memDevices: Map.fromEntries([sram.mem!])); + core.reset(); + }); + + test('SRET returns to supervisor via sepc', () async { + core.csrs.write(CsrAddress.stvec.address, 0x80000000, core); + core.csrs.write(CsrAddress.sepc.address, 0x300, core); + var sstatus = core.csrs.read(CsrAddress.sstatus.address, core); + sstatus |= 1 << 8; // SPP = supervisor + core.csrs.write(CsrAddress.sstatus.address, sstatus, core); + core.mode = PrivilegeMode.supervisor; + final nextPc = await core.cycle(0x1000, 0x10200073); // sret + expect(nextPc, 0x300); + expect(core.mode, PrivilegeMode.supervisor); + }); + + test('ecall from U-mode is delegated to S-mode', () async { + core.csrs.write(CsrAddress.stvec.address, 0x80000000, core); + core.csrs.write(CsrAddress.mtvec.address, 0x40000000, core); + core.csrs.write(CsrAddress.medeleg.address, 1 << 8, core); // ecall-from-U + core.mode = PrivilegeMode.user; + final nextPc = await core.cycle(0x1000, 0x00000073); // ecall + expect(nextPc, 0x80000000); // S-mode handler, not mtvec + expect(core.mode, PrivilegeMode.supervisor); + }); + + test('Svinval sinval.vma executes', () async { + core.mode = PrivilegeMode.supervisor; + expect(await core.cycle(0x1000, 0x16628073), 0x1004); + }); + + test('Svinval sfence.w.inval / sfence.inval.ir execute', () async { + core.mode = PrivilegeMode.supervisor; + expect(await core.cycle(0x1000, 0x18000073), 0x1004); + expect(await core.cycle(0x1000, 0x18100073), 0x1004); + }); + }); +} diff --git a/packages/river_emulator/test/core/extensions/rva22_test.dart b/packages/river_emulator/test/core/extensions/rva22_test.dart new file mode 100644 index 0000000..c30bf43 --- /dev/null +++ b/packages/river_emulator/test/core/extensions/rva22_test.dart @@ -0,0 +1,185 @@ +import 'package:river/river.dart'; +import 'package:river_emulator/river_emulator.dart'; +import 'package:test/test.dart'; + +/// RVA22U64 user-mode instruction verification on the emulator, using the +/// RVA22 profile config. Each test executes a single instruction (encodings +/// taken from the GNU assembler) and checks the architectural result. +void main() { + group('RVA22 U-mode', () { + late Sram sram; + late RiverCore core; + late int pc; + + final config = RiverCoreConfig( + mxlen: RiscVMxlen.rv64, + extensions: kRva22S64Extensions, + type: RiverCoreType.general, + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + hasSupervisorUserMemory: true, + hasMakeExecutableReadable: true, + ), + interrupts: [], + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + ); + + setUp(() { + sram = Sram( + RiverDevice( + name: 'sram', + compatible: 'river,sram', + range: BusAddressRange(0, 0xFFFF), + clockFrequency: 10000, + ), + ); + core = RiverCore(config, memDevices: Map.fromEntries([sram.mem!])); + pc = config.resetVector; + }); + + // Execute one instruction with the given register inputs; returns nextPc. + Future run(int instr, [Map regs = const {}]) async { + core.reset(); + regs.forEach((r, v) => core.xregs[r] = v); + return core.cycle(pc, instr); + } + + int x(Register r) => core.xregs[r]!; + + // ---- Working today ---- + test('pause is a no-op hint', () async { + final next = await run(0x0100000f); + expect(next, pc + 4); + }); + test('cbo.zero executes and advances pc', () async { + final next = await run(0x0043200f, {Register.x6: 0x40}); + expect(next, pc + 4); + }); + + // The bit-manipulation extensions (Zba/Zbb/Zbs) and the Zicntr counters are + // decode-defined in Harbor but their *execution* is stubbed: RiscVAluFunct + // has no bit-manip values, the microcode uses placeholder funct (e.g. + // sh1add is `RiscVAlu(add,...)`), and the emulator/HDL ALUs don't implement + // them. These tests encode the correct expected behavior and are ready to + // enable once that lands. See project_rva22 in memory. + group('Zb + Zicntr execution', () { + // ---- Zbb: logical-with-complement ---- + test('andn (Zbb)', () async { + await run(0x4062f3b3, {Register.x5: 0xFF00, Register.x6: 0x0F0F}); + expect(x(Register.x7), 0xFF00 & ~0x0F0F); + }); + test('orn (Zbb)', () async { + await run(0x4062e433, {Register.x5: 0x0F0F, Register.x6: 0xF0F0}); + expect(x(Register.x8), 0x0F0F | ~0xF0F0); + }); + test('xnor (Zbb)', () async { + await run(0x4062c4b3, {Register.x5: 0xF0F0, Register.x6: 0x0F0F}); + expect(x(Register.x9), ~(0xF0F0 ^ 0x0F0F)); + }); + + // ---- Zbb: min/max ---- + test('min / max (Zbb, signed)', () async { + await run(0x0a62c533, {Register.x5: 5, Register.x6: -3}); + expect(x(Register.x10), -3); + await run(0x0a62e5b3, {Register.x5: 5, Register.x6: -3}); + expect(x(Register.x11), 5); + }); + test('minu / maxu (Zbb, unsigned)', () async { + // -1 is the largest unsigned value. + await run(0x0a62d633, {Register.x5: 5, Register.x6: -1}); + expect(x(Register.x12), 5); + await run(0x0a62f6b3, {Register.x5: 5, Register.x6: -1}); + expect(x(Register.x13), -1); + }); + + // ---- Zbb: bit counts ---- + test('clz (Zbb, 64-bit)', () async { + await run(0x60029713, {Register.x5: 1}); + expect(x(Register.x14), 63); + }); + test('ctz (Zbb)', () async { + await run(0x60129793, {Register.x5: 8}); + expect(x(Register.x15), 3); + }); + test('cpop (Zbb)', () async { + await run(0x60229813, {Register.x5: 0xFF}); + expect(x(Register.x16), 8); + }); + + // ---- Zbb: sign/zero extend & byte ops ---- + test('sext.b (Zbb)', () async { + await run(0x60429893, {Register.x5: 0x80}); + expect(x(Register.x17), -128); + }); + test('zext.h (Zbb)', () async { + await run(0x0802c9bb, {Register.x5: -1}); + expect(x(Register.x19), 0xFFFF); + }); + test('rev8 (Zbb, 64-bit)', () async { + await run(0x6b82da13, {Register.x5: 0x0102030405060708}); + expect(x(Register.x20), 0x0807060504030201); + }); + test('orc.b (Zbb)', () async { + await run(0x2872dc13, {Register.x5: 0x0100000000000001}); + expect(x(Register.x24), 0xFF000000000000FF); + }); + + // ---- Zbb: rotates ---- + test('ror (Zbb)', () async { + await run(0x6062db33, {Register.x5: 0x1, Register.x6: 1}); + expect(x(Register.x22), 0x8000000000000000); + }); + test('rol (Zbb)', () async { + await run(0x60629ab3, { + Register.x5: 0x8000000000000000, + Register.x6: 1, + }); + expect(x(Register.x21), 0x1); + }); + + // ---- Zba: shift-add ---- + test('sh1add / sh2add / sh3add (Zba)', () async { + await run(0x2062acb3, {Register.x5: 3, Register.x6: 10}); + expect(x(Register.x25), (3 << 1) + 10); + await run(0x2062cd33, {Register.x5: 3, Register.x6: 10}); + expect(x(Register.x26), (3 << 2) + 10); + await run(0x2062edb3, {Register.x5: 3, Register.x6: 10}); + expect(x(Register.x27), (3 << 3) + 10); + }); + test('add.uw (Zba, RV64)', () async { + await run(0x08628e3b, {Register.x5: 0x1FFFFFFF5, Register.x6: 10}); + expect(x(Register.x28), 0xFFFFFFF5 + 10); + }); + + // ---- Zbs: single-bit ---- + test('bset / bclr / bext / binv (Zbs)', () async { + await run(0x28629f33, {Register.x5: 0, Register.x6: 5}); + expect(x(Register.x30), 1 << 5); + await run(0x48629fb3, {Register.x5: 0xFF, Register.x6: 0}); + expect(x(Register.x31), 0xFE); + await run(0x4862d0b3, {Register.x5: 0x4, Register.x6: 2}); + expect(x(Register.x1), 1); + await run(0x68629133, {Register.x5: 0xF, Register.x6: 0}); + expect(x(Register.x2), 0xE); + }); + + // ---- Zicntr: counters readable ---- + test('rdcycle executes and advances pc', () async { + final next = await run(0xc0002273); + expect(core.xregs[Register.x4], isNotNull); + expect(next, pc + 4); + }); + test('rdinstret executes and advances pc', () async { + final next = await run(0xc02022f3); + expect(core.xregs[Register.x5], isNotNull); + expect(next, pc + 4); + }); + }); + }); +} diff --git a/packages/river_emulator/test/core/extensions/rva23_hypervisor_test.dart b/packages/river_emulator/test/core/extensions/rva23_hypervisor_test.dart new file mode 100644 index 0000000..9c1298d --- /dev/null +++ b/packages/river_emulator/test/core/extensions/rva23_hypervisor_test.dart @@ -0,0 +1,156 @@ +import 'package:river/river.dart'; +import 'package:river_emulator/river_emulator.dart'; +import 'package:test/test.dart'; + +/// RVA23 hypervisor (H) bring-up. H is mandatory in RVA23S64 and must be fully +/// configurable: a core that omits the extension has no hypervisor CSRs and +/// traps any access to them. See project_rva23 / project_hypervisor. +void main() { + HarborMmuConfig mmu(RiscVMxlen x, List modes) => + HarborMmuConfig( + mxlen: x, + pagingModes: modes, + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ); + const clk = HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ); + + RiverCore makeCore(RiverCoreConfig config) { + final sram = Sram( + RiverDevice( + name: 'sram', + compatible: 'river,sram', + range: BusAddressRange(0, 0xFFFF), + clockFrequency: 10000, + ), + ); + final core = RiverCore(config, memDevices: Map.fromEntries([sram.mem!])); + core.reset(); + return core; + } + + // csrr rd, csr (= csrrs rd, csr, x0); csrw csr, rs1 (= csrrw x0, csr, rs1) + int csrr(int rd, int csr) => (csr << 20) | (2 << 12) | (rd << 7) | 0x73; + int csrw(int csr, int rs1) => (csr << 20) | (rs1 << 15) | (1 << 12) | 0x73; + + group('RVA23 hypervisor CSRs', () { + test('H present (RVA23S64): hypervisor CSRs read/write', () async { + final core = makeCore( + RiverCoreConfig( + mxlen: RiscVMxlen.rv64, + extensions: kRva23S64Extensions, + type: RiverCoreType.general, + mmu: mmu(RiscVMxlen.rv64, const [RiscVPagingMode.bare]), + interrupts: [], + clock: clk, + ), + ); + expect(core.config.hasHypervisor, isTrue); + + core.xregs[Register.x5] = 0x123456789AB; + await core.cycle(0x1000, csrw(0x680, 5)); // csrw hgatp, t0 + await core.cycle(0x1004, csrr(6, 0x680)); // csrr t1, hgatp + expect(core.xregs[Register.x6], 0x123456789AB); + + // The full hypervisor + VS-mode CSR set is present and accessible. + for (final csr in [0x600, 0x602, 0x604, 0x643, 0x645, 0x200, 0x280]) { + await core.cycle(0x1008, csrr(7, csr)); + } + // hgeip is read-only: writing it traps. + core.xregs[Register.x5] = 1; + expect(() => core.cycle(0x100c, csrw(0xE12, 5)), throwsA(anything)); + }); + + test('HLV.W / HSV.W with both stages bare (functional)', () async { + final core = makeCore( + RiverCoreConfig( + mxlen: RiscVMxlen.rv64, + extensions: kRva23S64Extensions, + type: RiverCoreType.general, + mmu: mmu(RiscVMxlen.rv64, const [RiscVPagingMode.bare]), + interrupts: [], + clock: clk, + ), + ); + // vsatp/hgatp default to 0 (bare) -> two-stage translation is identity. + await core.mmu.write(0x3000, 0x0AFE1234, 4, pageTranslate: false); + core.xregs[Register.x6] = 0x3000; + // hlv.w t0, (t1) -- funct7=0x34, funct3=4 + await core.cycle( + 0x1000, + (0x34 << 25) | (6 << 15) | (4 << 12) | (5 << 7) | 0x73, + ); + expect(core.xregs[Register.x5], 0x0AFE1234); + + // hsv.w t2, (t1) -- funct7=0x35 + core.xregs[Register.x6] = 0x3400; + core.xregs[Register.x7] = 0x55667788; + await core.cycle( + 0x1004, + (0x35 << 25) | (7 << 20) | (6 << 15) | (4 << 12) | 0x73, + ); + expect(await core.mmu.read(0x3400, 4, pageTranslate: false), 0x55667788); + }); + + test('HLV.W through G-stage (Sv39x4) two-stage translation', () async { + final core = makeCore( + RiverCoreConfig( + mxlen: RiscVMxlen.rv64, + extensions: kRva23S64Extensions, + type: RiverCoreType.general, + mmu: mmu(RiscVMxlen.rv64, const [RiscVPagingMode.bare]), + interrupts: [], + clock: clk, + ), + ); + Future w(int a, int v) => + core.mmu.write(a, v, 8, pageTranslate: false); + + // G-stage Sv39x4 tables map guest-physical 0x8000 -> host 0x3000. + // GVA == GPA (VS-stage bare). VPN[2]=0, VPN[1]=0, VPN[0]=8. + const root = 0x4000; // 16 KiB-aligned x4 root + const l1 = 0x5000; + const l0 = 0x6000; + const hpa = 0x3000; + await w( + root + 0 * 8, + ((l1 >> 12) << 10) | 0x1, + ); // -> L1 (valid, non-leaf) + await w(l1 + 0 * 8, ((l0 >> 12) << 10) | 0x1); // -> L0 + // leaf: PPN(hpa), U|R|W|V (G-stage requires U) + await w(l0 + 8 * 8, ((hpa >> 12) << 10) | 0x10 | 0x4 | 0x2 | 0x1); + await core.mmu.write(hpa, 0x0BADF00D, 4, pageTranslate: false); + + // hgatp = Sv39x4 (mode 8) with root PPN; vsatp = bare. + core.csrs.write(CsrAddress.hgatp.address, (8 << 60) | (root >> 12), core); + + core.xregs[Register.x6] = 0x8000; // guest virtual == guest physical + await core.cycle( + 0x1000, + (0x34 << 25) | (6 << 15) | (4 << 12) | (5 << 7) | 0x73, + ); + expect(core.xregs[Register.x5], 0x0BADF00D); + }); + + test('H absent (RVA22S64): hypervisor CSR access is illegal', () { + final core = makeCore( + RiverCoreConfig( + mxlen: RiscVMxlen.rv64, + extensions: kRva22S64Extensions, + type: RiverCoreType.general, + mmu: mmu(RiscVMxlen.rv64, const [RiscVPagingMode.bare]), + interrupts: [], + clock: clk, + ), + ); + expect(core.config.hasHypervisor, isFalse); + expect( + () => core.cycle(0x1000, csrr(5, 0x600)), // hstatus -> illegal + throwsA(anything), + ); + }); + }); +} diff --git a/packages/river_emulator/test/core/extensions/rva23_test.dart b/packages/river_emulator/test/core/extensions/rva23_test.dart new file mode 100644 index 0000000..a9360de --- /dev/null +++ b/packages/river_emulator/test/core/extensions/rva23_test.dart @@ -0,0 +1,96 @@ +import 'package:river/river.dart'; +import 'package:river_emulator/river_emulator.dart'; +import 'package:test/test.dart'; + +/// RVA23U64 scalar additions over RVA22, verified on the emulator with the +/// RVA23 profile. (Vector is scoped separately, see project_rva23.) +void main() { + group('RVA23 scalar', () { + late Sram sram; + late RiverCore core; + late int pc; + + final config = RiverCoreConfig( + mxlen: RiscVMxlen.rv64, + extensions: kRva23S64Extensions, + type: RiverCoreType.general, + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + hasSupervisorUserMemory: true, + hasMakeExecutableReadable: true, + ), + interrupts: [], + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + ); + + setUp(() { + sram = Sram( + RiverDevice( + name: 'sram', + compatible: 'river,sram', + range: BusAddressRange(0, 0xFFFF), + clockFrequency: 10000, + ), + ); + core = RiverCore(config, memDevices: Map.fromEntries([sram.mem!])); + pc = config.resetVector; + }); + + Future run(int instr, [Map regs = const {}]) async { + core.reset(); + regs.forEach((r, v) => core.xregs[r] = v); + return core.cycle(pc, instr); + } + + int x(Register r) => core.xregs[r]!; + + // Zicond: czero.eqz rd = (rs2==0)?0:rs1 ; czero.nez rd = (rs2!=0)?0:rs1. + // czero.eqz x5,x6,x7 = 0x0e7352b3 ; czero.nez x8,x6,x7 = 0x0e737433. + test('czero.eqz: rs2!=0 -> rd=rs1', () async { + await run(0x0e7352b3, {Register.x6: 0xABCD, Register.x7: 5}); + expect(x(Register.x5), 0xABCD); + }); + test('czero.eqz: rs2==0 -> rd=0', () async { + await run(0x0e7352b3, {Register.x6: 0xABCD, Register.x7: 0}); + expect(x(Register.x5), 0); + }); + test('czero.nez: rs2!=0 -> rd=0', () async { + await run(0x0e737433, {Register.x6: 0xABCD, Register.x7: 5}); + expect(x(Register.x8), 0); + }); + test('czero.nez: rs2==0 -> rd=rs1', () async { + await run(0x0e737433, {Register.x6: 0xABCD, Register.x7: 0}); + expect(x(Register.x8), 0xABCD); + }); + + // Zawrs: wait-for-reservation hints. SKIPPED. wrs.nto/sto (SYSTEM opcode, + // funct3=0, funct7=0) are not disambiguated from ecall in the decoder + // (none of the SYSTEM ops carry a matchMask on the funct12/rs2 field), so + // they currently decode as ecall. Pre-existing decode ambiguity; hints are + // low-value. See project_rva23. + test( + 'wrs.nto / wrs.sto execute', + skip: 'SYSTEM-opcode decode ambiguity', + () async { + expect(await run(0x00d00073), pc + 4); + expect(await run(0x01d00073), pc + 4); + }, + ); + + // Zcb compressed: c.zext.b rd' = rd' & 0xFF ; c.not rd' = ~rd'. + test('c.zext.b (Zcb)', () async { + await run(0x9c61, {Register.x8: 0x1FF}); + expect(x(Register.x8), 0xFF); + }); + test('c.not (Zcb)', () async { + await run(0x9c75, {Register.x8: 0}); + expect(x(Register.x8), -1); + }); + }); +} diff --git a/packages/river_emulator/test/core/extensions/rva23_vector_test.dart b/packages/river_emulator/test/core/extensions/rva23_vector_test.dart new file mode 100644 index 0000000..05e743d --- /dev/null +++ b/packages/river_emulator/test/core/extensions/rva23_vector_test.dart @@ -0,0 +1,574 @@ +import 'dart:typed_data'; + +import 'package:river/river.dart'; +import 'package:river_emulator/river_emulator.dart'; +import 'package:test/test.dart'; + +/// RVA23 vector (V) bring-up: the canonical vsetvli + unit-stride load + +/// vadd.vv + store, on the RVA23 profile (VLEN=128). And confirmation that a +/// V-less core treats OP-V as illegal (vector is optional). See project_rva23. +void main() { + HarborMmuConfig mmu(RiscVMxlen x) => HarborMmuConfig( + mxlen: x, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ); + const clk = HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ); + + group('RVA23 vector', () { + late Sram sram; + late RiverCore core; + final config = RiverCoreConfig( + mxlen: RiscVMxlen.rv64, + extensions: kRva23S64Extensions, + type: RiverCoreType.general, + mmu: mmu(RiscVMxlen.rv64), + interrupts: [], + clock: clk, + ); + + setUp(() { + sram = Sram( + RiverDevice( + name: 'sram', + compatible: 'river,sram', + range: BusAddressRange(0, 0xFFFF), + clockFrequency: 10000, + ), + ); + core = RiverCore(config, memDevices: Map.fromEntries([sram.mem!])); + core.reset(); + }); + + test('VLEN is config-driven (128)', () { + expect(config.vlen, 128); + expect(core.hasVector, isTrue); + }); + + test('vsetvli + vle32.v + vadd.vv + vse32.v', () async { + // A = [1,2,3,4] @ 0x100 ; B = [10,20,30,40] @ 0x110 ; C @ 0x120. + const a = [1, 2, 3, 4]; + const b = [10, 20, 30, 40]; + for (var i = 0; i < 4; i++) { + await core.mmu.write(0x100 + i * 4, a[i], 4); + await core.mmu.write(0x110 + i * 4, b[i], 4); + } + core.xregs[Register.x10] = 0x100; + core.xregs[Register.x11] = 0x110; + core.xregs[Register.x12] = 0x120; + core.xregs[Register.x6] = 4; // AVL + + // vsetvli t0,t1,e32,m1,ta,ma -> vl = min(4, VLMAX=128/32=4) = 4 + await core.cycle(0x1000, 0x0d0372d7); + expect(core.vl, 4); + expect(core.xregs[Register.x5], 4); // rd = vl + + await core.cycle(0x1004, 0x02056087); // vle32.v v1,(a0) + await core.cycle(0x1008, 0x0205e107); // vle32.v v2,(a1) + await core.cycle(0x100c, 0x021101d7); // vadd.vv v3,v1,v2 + await core.cycle(0x1010, 0x020661a7); // vse32.v v3,(a2) + + for (var i = 0; i < 4; i++) { + expect(await core.mmu.read(0x120 + i * 4, 4), a[i] + b[i]); + } + }); + + test('vl/vtype/vlenb/vstart/vcsr readable via csrr', () async { + // csrrs rd, csr, x0 (a.k.a. csrr rd, csr) + int csrr(int rd, int csr) => (csr << 20) | (2 << 12) | (rd << 7) | 0x73; + // csrrw rd, csr, rs1 + int csrw(int rd, int csr, int rs1) => + (csr << 20) | (rs1 << 15) | (1 << 12) | (rd << 7) | 0x73; + + core.xregs[Register.x6] = 4; // AVL + // vsetvli t0,t1,e32,m1,ta,ma -> vl=4, vtype=0xD0. + await core.cycle(0x1000, 0x0d0372d7); + expect(core.vl, 4); + + await core.cycle(0x1004, csrr(5, 0xC20)); // csrr t0, vl + expect(core.xregs[Register.x5], 4); + await core.cycle(0x1008, csrr(6, 0xC21)); // csrr t1, vtype + expect(core.xregs[Register.x6], 0xD0); + await core.cycle(0x100c, csrr(7, 0xC22)); // csrr t2, vlenb + expect(core.xregs[Register.x7], 128 ~/ 8); // VLEN/8 = 16 + + // vstart is writable then read-back; vcsr packs {vxrm[1:0], vxsat}. + core.xregs[Register.x8] = 3; + await core.cycle(0x1010, csrw(0, 0x008, 8)); // csrw vstart, s0 + expect(core.vstart, 3); + core.xregs[Register.x9] = 0x5; // vxrm=2, vxsat=1 + await core.cycle(0x1014, csrw(0, 0x00F, 9)); // csrw vcsr, s1 + expect(core.vxsat, 1); + expect(core.vxrm, 2); + await core.cycle(0x1018, csrr(10, 0x00F)); // csrr a0, vcsr + expect(core.xregs[Register.x10], 0x5); + }); + }); + + group('RVA23 vector ops (e32, m1, vl=4)', () { + late Sram sram; + late RiverCore core; + final config = RiverCoreConfig( + mxlen: RiscVMxlen.rv64, + extensions: kRva23S64Extensions, + type: RiverCoreType.general, + mmu: mmu(RiscVMxlen.rv64), + interrupts: [], + clock: clk, + ); + + // OP-V arithmetic encoding. funct3: 0=OPIVV 3=OPIVI 4=OPIVX 2=OPMVV 6=OPMVX. + int vop(int funct6, int vm, int vs2, int f1, int funct3, int vd) => + (funct6 << 26) | + (vm << 25) | + (vs2 << 20) | + (f1 << 15) | + (funct3 << 12) | + (vd << 7) | + 0x57; + void setVreg(int v, List elems) { + for (var i = 0; i < elems.length; i++) { + core.vwriteElem(v, i, 32, elems[i]); + } + } + + List getVreg(int v, int n) => [ + for (var i = 0; i < n; i++) core.vreadElem(v, i, 32), + ]; + + setUp(() async { + sram = Sram( + RiverDevice( + name: 'sram', + compatible: 'river,sram', + range: BusAddressRange(0, 0xFFFF), + clockFrequency: 10000, + ), + ); + core = RiverCore(config, memDevices: Map.fromEntries([sram.mem!])); + core.reset(); + core.xregs[Register.x6] = 4; + await core.cycle(0x1000, 0x0d0372d7); // vsetvli -> e32,m1,vl=4 + setVreg(1, [1, 2, 3, 4]); + setVreg(2, [10, 20, 30, 40]); + }); + + test('vmul.vv', () async { + await core.cycle(0x1004, vop(0x25, 1, 2, 1, 2, 3)); // v3 = v2 * v1 + expect(getVreg(3, 4), [10, 40, 90, 160]); + }); + + test('vfadd.vv / vfsub.vv / vfmul.vv / vfdiv.vv (float, SEW=32)', () async { + int fb(double v) { + final bd = ByteData(4)..setFloat32(0, v, Endian.little); + return bd.getUint32(0, Endian.little); + } + + // funct3=1 is OPFVV; my impl reads a=vs2 elem, b=vs1 elem. + setVreg(1, [fb(1.0), fb(2.0), fb(3.0), fb(4.0)]); // vs2 + setVreg(2, [fb(2.0), fb(4.0), fb(6.0), fb(8.0)]); // vs1 + await core.cycle(0x1004, vop(0x00, 1, 1, 2, 1, 3)); // vfadd.vv v3,v1,v2 + expect(getVreg(3, 4), [fb(3.0), fb(6.0), fb(9.0), fb(12.0)]); + await core.cycle(0x1008, vop(0x02, 1, 1, 2, 1, 4)); // vfsub.vv v4 = v1-v2 + expect(getVreg(4, 4), [fb(-1.0), fb(-2.0), fb(-3.0), fb(-4.0)]); + await core.cycle(0x100c, vop(0x24, 1, 1, 2, 1, 5)); // vfmul.vv v5 = v1*v2 + expect(getVreg(5, 4), [fb(2.0), fb(8.0), fb(18.0), fb(32.0)]); + await core.cycle(0x1010, vop(0x20, 1, 2, 1, 1, 6)); // vfdiv.vv v6 = v2/v1 + expect(getVreg(6, 4), [fb(2.0), fb(2.0), fb(2.0), fb(2.0)]); + }); + + test('vfmin/vfmax/vfsgnj/vfsqrt (float, SEW=32)', () async { + int fb(double v) { + final bd = ByteData(4)..setFloat32(0, v, Endian.little); + return bd.getUint32(0, Endian.little); + } + + setVreg(1, [fb(1.0), fb(-2.0), fb(3.0), fb(4.0)]); // vs2 + setVreg(2, [fb(2.0), fb(2.0), fb(2.0), fb(2.0)]); // vs1 + await core.cycle(0x1004, vop(0x04, 1, 1, 2, 1, 3)); // vfmin v3=min(v1,v2) + expect(getVreg(3, 4), [fb(1.0), fb(-2.0), fb(2.0), fb(2.0)]); + await core.cycle(0x1008, vop(0x06, 1, 1, 2, 1, 4)); // vfmax v4=max(v1,v2) + expect(getVreg(4, 4), [fb(2.0), fb(2.0), fb(3.0), fb(4.0)]); + // vfsgnj v5 = magnitude(v1) with sign(v2) (all +) -> abs(v1) + await core.cycle(0x100c, vop(0x08, 1, 1, 2, 1, 5)); + expect(getVreg(5, 4), [fb(1.0), fb(2.0), fb(3.0), fb(4.0)]); + // vfsqrt v6 = sqrt(v2) = sqrt(2) ; funct6=0x13, vs1=0 (unary) + setVreg(2, [fb(4.0), fb(9.0), fb(16.0), fb(25.0)]); + await core.cycle(0x1010, vop(0x13, 1, 2, 0, 1, 6)); + expect(getVreg(6, 4), [fb(2.0), fb(3.0), fb(4.0), fb(5.0)]); + }); + + test('vmfeq/vmflt/vmfle/vmfne (float -> mask register)', () async { + int fb(double v) { + final bd = ByteData(4)..setFloat32(0, v, Endian.little); + return bd.getUint32(0, Endian.little); + } + + setVreg(1, [fb(1.0), fb(2.0), fb(3.0), fb(4.0)]); // vs2 (a) + setVreg(2, [fb(2.0), fb(2.0), fb(2.0), fb(2.0)]); // vs1 (b) + await core.cycle(0x1004, vop(0x1B, 1, 1, 2, 1, 3)); // vmflt v3 = afloat + vfclass (SEW=32)', () async { + int fb(double v) { + final bd = ByteData(4)..setFloat32(0, v, Endian.little); + return bd.getUint32(0, Endian.little); + } + + // vfcvt.f.x.v (signed int -> float): vs1=0x03 + setVreg(1, [1, 2, 3, 4]); + await core.cycle(0x1004, vop(0x12, 1, 1, 0x03, 1, 3)); + expect(getVreg(3, 4), [fb(1.0), fb(2.0), fb(3.0), fb(4.0)]); + // vfcvt.x.f.v (float -> signed int, truncating): vs1=0x01 + setVreg(2, [fb(1.5), fb(2.7), fb(3.9), fb(4.0)]); + await core.cycle(0x1008, vop(0x12, 1, 2, 0x01, 1, 4)); + expect(getVreg(4, 4), [1, 2, 3, 4]); + // vfclass.v: vs1=0x10 (+normal, -normal, +0, +inf) + setVreg(5, [fb(1.0), fb(-1.0), fb(0.0), fb(double.infinity)]); + await core.cycle(0x100c, vop(0x13, 1, 5, 0x10, 1, 6)); + expect(getVreg(6, 4), [0x40, 0x02, 0x10, 0x80]); + }); + + test('vfredusum/vfredmax/vfredmin (reductions -> vd[0])', () async { + int fb(double v) { + final bd = ByteData(4)..setFloat32(0, v, Endian.little); + return bd.getUint32(0, Endian.little); + } + + setVreg(2, [fb(1.0), fb(2.0), fb(3.0), fb(4.0)]); // vs2 (data) + setVreg(1, [fb(0.0), fb(0.0), fb(0.0), fb(0.0)]); // vs1[0] = init = 0 + await core.cycle(0x1004, vop(0x01, 1, 2, 1, 1, 3)); // vfredusum -> 10 + expect(core.vreadElem(3, 0, 32), fb(10.0)); + await core.cycle(0x1008, vop(0x07, 1, 2, 1, 1, 4)); // vfredmax -> 4 + expect(core.vreadElem(4, 0, 32), fb(4.0)); + await core.cycle(0x100c, vop(0x05, 1, 2, 1, 1, 5)); // vfredmin -> 0 + expect(core.vreadElem(5, 0, 32), fb(0.0)); + }); + + test('vfadd.vv / vfmul.vv half-precision (Zvfh, SEW=16)', () async { + // half bits: 1.0=0x3C00, 2.0=0x4000, 3.0=0x4200, 4.0=0x4400. + core.vtype = 0xC8; // e16, m1, ta, ma + core.vl = 4; + for (var i = 0; i < 4; i++) { + core.vwriteElem(1, i, 16, 0x3C00); // 1.0h + core.vwriteElem(2, i, 16, 0x4000); // 2.0h + } + await core.cycle(0x1004, vop(0x00, 1, 1, 2, 1, 3)); // vfadd v3 = 1+2 + await core.cycle(0x1008, vop(0x24, 1, 1, 2, 1, 4)); // vfmul v4 = 1*2 + for (var i = 0; i < 4; i++) { + expect(core.vreadElem(3, i, 16), 0x4200); // 3.0h + expect(core.vreadElem(4, i, 16), 0x4000); // 2.0h + } + }); + + test('vmand/vmor/vmxor.mm (mask logical)', () async { + core.vregs[1][0] = 0x0C; // mask 0b1100 + core.vregs[2][0] = 0x0A; // mask 0b1010 + await core.cycle(0x1004, vop(0x19, 1, 1, 2, 2, 3)); // vmand -> 0b1000 + expect(core.vregs[3][0] & 0xF, 0x08); + await core.cycle(0x1008, vop(0x1A, 1, 1, 2, 2, 4)); // vmor -> 0b1110 + expect(core.vregs[4][0] & 0xF, 0x0E); + await core.cycle(0x100c, vop(0x1B, 1, 1, 2, 2, 5)); // vmxor -> 0b0110 + expect(core.vregs[5][0] & 0xF, 0x06); + }); + + test('vmv.x.s / vmv.s.x / vcpop.m / vfirst.m', () async { + setVreg(1, [42, 0, 0, 0]); + await core.cycle(0x1004, vop(0x10, 1, 1, 0x00, 2, 5)); // vmv.x.s x5, v1 + expect(core.xregs[Register.x5], 42); + core.xregs[Register.x6] = 99; + await core.cycle(0x1008, vop(0x10, 1, 0, 6, 6, 2)); // vmv.s.x v2, x6 + expect(core.vreadElem(2, 0, 32), 99); + core.vregs[3][0] = 0x0B; // mask 0b1011 -> 3 set bits + await core.cycle(0x100c, vop(0x10, 1, 3, 0x10, 2, 7)); // vcpop.m x7, v3 + expect(core.xregs[Register.x7], 3); + core.vregs[4][0] = 0x08; // mask 0b1000 -> first set at index 3 + await core.cycle(0x1010, vop(0x10, 1, 4, 0x11, 2, 8)); // vfirst.m x8, v4 + expect(core.xregs[Register.x8], 3); + }); + + test('vslideup.vx / vslidedown.vx', () async { + setVreg(1, [1, 2, 3, 4]); + core.xregs[Register.x5] = 1; // offset + setVreg(3, [99, 0, 0, 0]); // vd[0] must stay undisturbed by slideup + await core.cycle(0x1004, vop(0x0E, 1, 1, 5, 4, 3)); // vslideup v3,v1,1 + expect(getVreg(3, 4), [99, 1, 2, 3]); + await core.cycle(0x1008, vop(0x0F, 1, 1, 5, 4, 4)); // vslidedown v4,v1,1 + expect(getVreg(4, 4), [2, 3, 4, 0]); // past VLMAX -> 0 + }); + + test('vrgather / vcompress / vslide1up / vslide1down', () async { + setVreg(2, [10, 20, 30, 40]); // data + setVreg(1, [3, 2, 1, 0]); // gather indices + await core.cycle(0x1004, vop(0x0C, 1, 2, 1, 0, 3)); // vrgather.vv + expect(getVreg(3, 4), [40, 30, 20, 10]); + core.vregs[5][0] = 0x0A; // mask 0b1010 -> elements 1,3 + await core.cycle(0x1008, vop(0x17, 1, 2, 5, 2, 4)); // vcompress.vm + expect(getVreg(4, 2), [20, 40]); // packed + core.xregs[Register.x5] = 99; + await core.cycle(0x100c, vop(0x0E, 1, 2, 5, 6, 6)); // vslide1up.vx + expect(getVreg(6, 4), [99, 10, 20, 30]); + await core.cycle(0x1010, vop(0x0F, 1, 2, 5, 6, 7)); // vslide1down.vx + expect(getVreg(7, 4), [20, 30, 40, 99]); + }); + + test('LMUL=2 register grouping (vadd.vv over 8 elements)', () async { + core.vtype = 0xD1; // e32, m2, ta, ma + core.vl = 8; // VLMAX = 128*2/32 + setVreg(2, [1, 2, 3, 4, 5, 6, 7, 8]); // group v2:v3 + setVreg(4, [10, 20, 30, 40, 50, 60, 70, 80]); // group v4:v5 + await core.cycle(0x1004, vop(0x00, 1, 2, 4, 0, 6)); // vadd.vv v6,v2,v4 + expect(getVreg(6, 8), [11, 22, 33, 44, 55, 66, 77, 88]); // spans v6:v7 + }); + + test('vlse32 / vsse32 (strided load/store)', () async { + int vmemS(int op, int rs2, int rs1, int f3, int vd) => + (2 << 26) | + (1 << 25) | + (rs2 << 20) | + (rs1 << 15) | + (f3 << 12) | + (vd << 7) | + op; + for (var i = 0; i < 4; i++) { + await core.mmu.write(0x100 + i * 8, 11 + i * 11, 4); // stride 8 + } + core.xregs[Register.x10] = 0x100; + core.xregs[Register.x11] = 8; // byte stride + await core.cycle(0x1004, vmemS(0x07, 11, 10, 6, 1)); // vlse32.v v1 + expect(getVreg(1, 4), [11, 22, 33, 44]); + core.xregs[Register.x12] = 0x200; + await core.cycle(0x1008, vmemS(0x27, 11, 12, 6, 1)); // vsse32.v v1 + for (var i = 0; i < 4; i++) { + expect(await core.mmu.read(0x200 + i * 8, 4), 11 + i * 11); + } + }); + + test('vwadd.vv / vwmul.vv (widening SEW=32 -> 64-bit results)', () async { + setVreg(2, [1000, 2000, 3000, 4000]); + setVreg(1, [100, 200, 300, 400]); + await core.cycle(0x1004, vop(0x31, 1, 2, 1, 2, 4)); // vwadd.vv v4 + const sums = [1100, 2200, 3300, 4400]; + for (var i = 0; i < 4; i++) { + expect(core.vreadElem(4, i, 64), sums[i]); // 64-bit results span v4:v5 + } + await core.cycle(0x1008, vop(0x3B, 1, 2, 1, 2, 6)); // vwmul.vv v6 + const prods = [100000, 400000, 900000, 1600000]; + for (var i = 0; i < 4; i++) { + expect(core.vreadElem(6, i, 64), prods[i]); + } + }); + + test('vzext.vf2 / vsext.vf2 (16-bit source -> SEW=32)', () async { + for (var i = 0; i < 4; i++) { + core.vwriteElem(2, i, 16, [1, 0xFFFE, 3, 0xFFFC][i]); // 1,-2,3,-4 + } + await core.cycle(0x1004, vop(0x12, 1, 2, 0x06, 2, 3)); // vzext.vf2 + expect(getVreg(3, 4), [1, 0xFFFE, 3, 0xFFFC]); // zero-extended + await core.cycle(0x1008, vop(0x12, 1, 2, 0x07, 2, 4)); // vsext.vf2 + expect(getVreg(4, 4), [1, 0xFFFFFFFE, 3, 0xFFFFFFFC]); // sign-extended + }); + + test('vnsrl.wi (narrowing 64-bit -> SEW=32 shift right)', () async { + for (var i = 0; i < 4; i++) { + core.vwriteElem(2, i, 64, (i + 1) << 16); // spans v2:v3 + } + // vd=8 must not overlap the 2*SEW source group v2:v3 (narrowing rule). + await core.cycle(0x1004, vop(0x2C, 1, 2, 16, 3, 8)); // vnsrl.wi v8,v2,16 + expect(getVreg(8, 4), [1, 2, 3, 4]); + }); + + test('vfwadd.vv / vfwmul.vv (FP widening f32 -> f64)', () async { + int f32(double v) { + final bd = ByteData(4)..setFloat32(0, v, Endian.little); + return bd.getUint32(0, Endian.little); + } + + int f64(double v) { + final bd = ByteData(8)..setFloat64(0, v, Endian.little); + return bd.getUint64(0, Endian.little); + } + + setVreg(2, [f32(1.0), f32(2.0), f32(3.0), f32(4.0)]); + setVreg(1, [f32(10.0), f32(20.0), f32(30.0), f32(40.0)]); + // dest must not overlap the 2*SEW result group's sources. + await core.cycle(0x1004, vop(0x30, 1, 2, 1, 1, 8)); // vfwadd.vv v8 + const sums = [11.0, 22.0, 33.0, 44.0]; + for (var i = 0; i < 4; i++) { + expect(core.vreadElem(8, i, 64), f64(sums[i])); + } + await core.cycle(0x1008, vop(0x38, 1, 2, 1, 1, 10)); // vfwmul.vv v10 + const prods = [10.0, 40.0, 90.0, 160.0]; + for (var i = 0; i < 4; i++) { + expect(core.vreadElem(10, i, 64), f64(prods[i])); + } + }); + + test('vfwcvt.f.f.v / vfncvt.f.f.w (FP precision convert)', () async { + int f32(double v) { + final bd = ByteData(4)..setFloat32(0, v, Endian.little); + return bd.getUint32(0, Endian.little); + } + + int f64(double v) { + final bd = ByteData(8)..setFloat64(0, v, Endian.little); + return bd.getUint64(0, Endian.little); + } + + setVreg(2, [f32(1.5), f32(2.5), f32(3.5), f32(4.5)]); + await core.cycle(0x1004, vop(0x12, 1, 2, 0x0C, 1, 8)); // vfwcvt.f.f.v v8 + const vals = [1.5, 2.5, 3.5, 4.5]; + for (var i = 0; i < 4; i++) { + expect( + core.vreadElem(8, i, 64), + f64(vals[i]), + ); // f32 -> f64, spans v8:v9 + } + // narrow back; dest v12 must not overlap the f64 source group v8:v9. + await core.cycle( + 0x1008, + vop(0x12, 1, 8, 0x14, 1, 12), + ); // vfncvt.f.f.w v12 + for (var i = 0; i < 4; i++) { + expect(core.vreadElem(12, i, 32), f32(vals[i])); // f64 -> f32 + } + }); + + test('vfwcvt/vfncvt int<->float (widen + narrow)', () async { + int f32(double v) { + final bd = ByteData(4)..setFloat32(0, v, Endian.little); + return bd.getUint32(0, Endian.little); + } + + int f64(double v) { + final bd = ByteData(8)..setFloat64(0, v, Endian.little); + return bd.getUint64(0, Endian.little); + } + + // vfwcvt.f.x.v (vs1=0x0B): signed int32 -> f64 (sign-extends; -3 included). + setVreg(2, [1, 2, (-3) & 0xFFFFFFFF, 4]); + await core.cycle(0x1004, vop(0x12, 1, 2, 0x0B, 1, 8)); + const wvals = [1.0, 2.0, -3.0, 4.0]; + for (var i = 0; i < 4; i++) { + expect(core.vreadElem(8, i, 64), f64(wvals[i])); // int32 -> f64 + } + // vfwcvt.x.f.v (vs1=0x09): f32 -> signed int64 (truncate toward zero). + setVreg(3, [f32(1.5), f32(2.7), f32(3.9), f32(4.2)]); + await core.cycle(0x1008, vop(0x12, 1, 3, 0x09, 1, 10)); + for (var i = 0; i < 4; i++) { + expect(core.vreadElem(10, i, 64), i + 1); // f32 -> int64 + } + // vfncvt.x.f.w (vs1=0x11): f64 (v8) -> signed int32 (truncate). + await core.cycle(0x100c, vop(0x12, 1, 8, 0x11, 1, 12)); + expect(getVreg(12, 4), [1, 2, (-3) & 0xFFFFFFFF, 4]); // f64 -> int32 + // vfncvt.f.x.w (vs1=0x13): signed int64 (v10) -> f32. + await core.cycle(0x1010, vop(0x12, 1, 10, 0x13, 1, 14)); + expect(getVreg(14, 4), [ + f32(1.0), + f32(2.0), + f32(3.0), + f32(4.0), + ]); // i64->f32 + }); + + test('vmin.vv / vmax.vv (signed)', () async { + setVreg(2, [10, 20, 30, 40]); + setVreg(1, [1, 2, 3, 4]); + await core.cycle(0x1004, vop(0x05, 1, 2, 1, 0, 3)); // vmin + expect(getVreg(3, 4), [1, 2, 3, 4]); + await core.cycle(0x1008, vop(0x07, 1, 2, 1, 0, 4)); // vmax + expect(getVreg(4, 4), [10, 20, 30, 40]); + }); + + test('vsll.vi / vsrl.vi / vsra.vi', () async { + await core.cycle(0x1004, vop(0x25, 1, 2, 1, 3, 3)); // vsll v2<<1 + expect(getVreg(3, 4), [20, 40, 60, 80]); + await core.cycle(0x1008, vop(0x28, 1, 2, 1, 3, 4)); // vsrl v2>>1 + expect(getVreg(4, 4), [5, 10, 15, 20]); + await core.cycle(0x100c, vop(0x29, 1, 2, 1, 3, 5)); // vsra v2>>1 + expect(getVreg(5, 4), [5, 10, 15, 20]); + }); + + test('vid.v', () async { + await core.cycle(0x1004, vop(0x14, 1, 0, 0x11, 2, 3)); // v3[i] = i + expect(getVreg(3, 4), [0, 1, 2, 3]); + }); + + test('vmerge.vvm (mask selects source)', () async { + core.vregs[0][0] = 0x05; // v0 mask = 0b0101 -> elements 0 and 2 active + await core.cycle(0x1004, vop(0x17, 0, 2, 1, 0, 3)); // vmerge v2/v1 by v0 + expect(getVreg(3, 4), [1, 20, 3, 40]); + }); + + test('masked vadd.vv leaves inactive elements undisturbed', () async { + core.vregs[0][0] = 0x05; // active: elements 0, 2 + setVreg(3, [100, 101, 102, 103]); // pre-existing destination + await core.cycle(0x1004, vop(0x00, 0, 2, 1, 0, 3)); // vadd v3,v2,v1,v0.t + expect(getVreg(3, 4), [11, 101, 33, 103]); + }); + }); + + test('V-less core treats OP-V as illegal (vector disabled)', () async { + final sram = Sram( + RiverDevice( + name: 'sram', + compatible: 'river,sram', + range: BusAddressRange(0, 0xFFFF), + clockFrequency: 10000, + ), + ); + // RC1.n is RV32IC with no V extension. + final core = RiverCore( + RiverCoreConfigV1.nano( + mmu: mmu(RiscVMxlen.rv32), + interrupts: [], + clock: clk, + ), + memDevices: Map.fromEntries([sram.mem!]), + ); + core.reset(); + expect(core.hasVector, isFalse); + expect( + () => core.cycle(0x1000, 0x021101d7), // vadd.vv -> illegal here + throwsA(anything), + ); + }); +} diff --git a/packages/river_emulator/test/core/extensions/stateen_test.dart b/packages/river_emulator/test/core/extensions/stateen_test.dart new file mode 100644 index 0000000..131647f --- /dev/null +++ b/packages/river_emulator/test/core/extensions/stateen_test.dart @@ -0,0 +1,107 @@ +import 'package:river/river.dart'; +import 'package:river_emulator/river_emulator.dart'; +import 'package:test/test.dart'; + +// Smstateen/Ssstateen state-enable CSRs. SE0 (mstateen0 bit 63) gates access to +// the lower-level state-enable CSRs from any mode below M: cleared -> illegal +// instruction. River implements only SE0; the other architectural bits gate +// features it does not have, so they are WARL-0. +void main() { + group('Smstateen (state-enable CSRs)', () { + late RiverCore core; + const causeMask = 0x7FFFFFFFFFFFFFFF; + const se0 = 1 << 63; + + // csrrs rd, csr, x0 -> a pure CSR read (rs1 = x0, no write-back). + int csrr(int rd, int csr) => (csr << 20) | (2 << 12) | (rd << 7) | 0x73; + + setUp(() { + final config = RiverCoreConfig( + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + mxlen: RiscVMxlen.rv64, + extensions: [ + rv64i, + rv32i, + rvZicsr, + rvZifencei, + rvPriv, + rvSmstateen, + rvSsstateen, + ], + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + ); + final sram = Sram( + RiverDevice( + name: 'sram', + compatible: 'river,sram', + range: BusAddressRange(0, 0xFFFF), + clockFrequency: 10000, + ), + ); + core = RiverCore(config, memDevices: Map.fromEntries([sram.mem!])); + // A valid M-mode trap handler so a denied access does not fault on entry. + core.csrs.write(CsrAddress.mtvec.address, 0x100, core); + }); + + test('SE0 clear -> S-mode sstateen0 access traps illegal (2)', () async { + core.csrs.write(CsrAddress.mstateen0.address, 0, core); // SE0 = 0 + core.mode = PrivilegeMode.supervisor; + await core.cycle(0x2000, csrr(6, CsrAddress.sstateen0.address)); + expect( + core.csrs.read(CsrAddress.mcause.address, core) & causeMask, + 2, + reason: 'sstateen0 denied -> illegal instruction', + ); + }); + + test('SE0 set -> S-mode sstateen0 reads 0, no trap', () async { + core.csrs.write(CsrAddress.mstateen0.address, se0, core); // SE0 = 1 + core.csrs.write(CsrAddress.mcause.address, 0xEE, core); // sentinel + core.mode = PrivilegeMode.supervisor; + final next = await core.cycle( + 0x2000, + csrr(6, CsrAddress.sstateen0.address), + ); + expect( + core.xregs[Register.x6], + 0, + reason: 'no U-accessible state-enabled features -> reads 0', + ); + expect(next, 0x2004, reason: 'access allowed, pc advances (no trap)'); + expect( + core.csrs.read(CsrAddress.mcause.address, core), + 0xEE, + reason: 'mcause untouched (no trap fired)', + ); + }); + + test('M-mode is never gated by stateen', () async { + core.csrs.write(CsrAddress.mstateen0.address, 0, core); // SE0 = 0 + core.mode = PrivilegeMode.machine; + final next = await core.cycle( + 0x2000, + csrr(6, CsrAddress.sstateen0.address), + ); + expect(next, 0x2004, reason: 'M-mode access proceeds regardless of SE0'); + }); + + test('mstateen0 is WARL: only SE0 (bit 63) is writable', () { + core.csrs.write(CsrAddress.mstateen0.address, -1, core); // all ones + expect( + core.csrs.read(CsrAddress.mstateen0.address, core), + se0, + reason: 'unimplemented-feature bits are WARL-0', + ); + }); + }); +} diff --git a/packages/river_emulator/test/core/extensions/vsmode_csr_test.dart b/packages/river_emulator/test/core/extensions/vsmode_csr_test.dart new file mode 100644 index 0000000..911e46a --- /dev/null +++ b/packages/river_emulator/test/core/extensions/vsmode_csr_test.dart @@ -0,0 +1,148 @@ +import 'package:river/river.dart'; +import 'package:river_emulator/river_emulator.dart'; +import 'package:test/test.dart'; + +/// H4: VS-mode (virt=1) CSR virtualization in the emulator. When virt=1, a +/// supervisor CSR access redirects to the VS shadow (sstatus->vsstatus, +/// satp->vsatp, ...) and a VS access to an HS-only hypervisor CSR raises a +/// virtual-instruction exception (cause 22). Mirrors the HDL core_vsmode_csr_test +/// / core_vsmode_virtinst_test. See project_hypervisor / project_rva23. +void main() { + RiverCore makeCore() { + final sram = Sram( + RiverDevice( + name: 'sram', + compatible: 'river,sram', + range: BusAddressRange(0, 0xFFFF), + clockFrequency: 10000, + ), + ); + final core = RiverCore( + RiverCoreConfig( + mxlen: RiscVMxlen.rv64, + extensions: kRva23S64Extensions, + type: RiverCoreType.general, + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + interrupts: [], + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + ), + memDevices: Map.fromEntries([sram.mem!]), + ); + core.reset(); + return core; + } + + int csrr(int rd, int csr) => (csr << 20) | (2 << 12) | (rd << 7) | 0x73; + int csrw(int csr, int rs1) => (csr << 20) | (rs1 << 15) | (1 << 12) | 0x73; + + const satp = 0x180, vsatp = 0x280, hstatus = 0x600; + + test('VS-mode csrw satp lands in vsatp; csrr satp reads it back', () async { + final core = makeCore(); + core.mode = PrivilegeMode.supervisor; + core.virt = true; + + core.xregs[Register.x5] = 0x8000000000012345; + await core.cycle(0x1000, csrw(satp, 5)); // VS: writes vsatp, not satp + + expect( + core.csrs.read(vsatp, core), + 0x8000000000012345, + reason: 'redirected write landed in vsatp', + ); + expect(core.csrs.read(satp, core), 0, reason: 'real satp untouched'); + + core.mode = PrivilegeMode.supervisor; + core.virt = true; + await core.cycle(0x1004, csrr(6, satp)); // VS: reads vsatp via redirect + expect(core.xregs[Register.x6], 0x8000000000012345); + }); + + test( + 'VS-mode access to an HS hypervisor CSR -> virtual instruction (22)', + () async { + final core = makeCore(); + // Valid (non-zero) mtvec so the trap doesn't double-fault on a 0 handler. + core.xregs[Register.x9] = 0x100; + await core.cycle(0x0FF0, csrw(0x305, 9)); // (M-mode) csrw mtvec, x9 + core.mode = PrivilegeMode.supervisor; + core.virt = true; + + await core.cycle( + 0x2000, + csrr(7, hstatus), + ); // VS: read hstatus -> cause 22 + + expect( + core.csrs.read(0x342, core) & 0x7FFFFFFFFFFFFFFF, + 22, + reason: 'mcause = virtual instruction (22)', + ); + }, + ); + + test( + 'VS trap delegated by medeleg+hedeleg lands at vstvec, virt stays 1', + () async { + final core = makeCore(); + // From M-mode: delegate cause 8 (ecall-from-U) M->HS (medeleg) and HS->VS + // (hedeleg); give vstvec and stvec distinct addresses. + core.xregs[Register.x1] = 1 << 8; + await core.cycle(0x10, csrw(0x302, 1)); // medeleg[8]=1 + await core.cycle(0x14, csrw(0x602, 1)); // hedeleg[8]=1 + core.xregs[Register.x2] = 0x300; + await core.cycle(0x18, csrw(0x205, 2)); // vstvec = 0x300 + core.xregs[Register.x3] = 0x200; + await core.cycle(0x1C, csrw(0x105, 3)); // stvec = 0x200 + + // Enter VU-mode (user + virt) and ecall. + core.mode = PrivilegeMode.user; + core.virt = true; + final nextPc = await core.cycle(0x2000, 0x00000073); // ecall + + expect( + core.csrs.read(0x242, core) & 0x7FFFFFFFFFFFFFFF, + 8, + reason: 'vscause = 8 (ecall delegated to VS)', + ); + expect(core.mode, PrivilegeMode.supervisor, reason: 'VS runs at S priv'); + expect(core.virt, isTrue, reason: 'trap stays virtualized'); + expect(nextPc, 0x300, reason: 'vectored to vstvec, not stvec (0x200)'); + }, + ); + + test('G-stage walk fault reports a guest page-fault cause (21)', () async { + final core = makeCore(); + Future w(int a, int v) => + core.mmu.write(a, v, 8, pageTranslate: false); + // Sv39x4 G-stage tables for guest-physical 0x8000, but the leaf is U=0 - a + // G-stage leaf must be user-accessible, so the walk faults in the G-stage. + const root = 0x4000, l1 = 0x5000, l0 = 0x6000, hpa = 0x3000; + await w(root, ((l1 >> 12) << 10) | 0x1); + await w(l1, ((l0 >> 12) << 10) | 0x1); + await w(l0 + 8 * 8, ((hpa >> 12) << 10) | 0x4 | 0x2 | 0x1); // R|W|V, NO U + core.csrs.write(CsrAddress.hgatp.address, (8 << 60) | (root >> 12), core); + core.csrs.write(CsrAddress.mtvec.address, 0x100, core); // valid handler + + core.xregs[Register.x6] = 0x8000; + // hlv.w x5, (x6): funct7=0x34, funct3=4 -> faults in the G-stage (U=0). + await core.cycle( + 0x1000, + (0x34 << 25) | (6 << 15) | (4 << 12) | (5 << 7) | 0x73, + ); + + expect( + core.csrs.read(CsrAddress.mcause.address, core) & 0x7FFFFFFFFFFFFFFF, + 21, + reason: 'G-stage fault -> loadGuestPageFault (21), not 13', + ); + }); +} diff --git a/packages/river_emulator/test/core/extensions/zacas_test.dart b/packages/river_emulator/test/core/extensions/zacas_test.dart new file mode 100644 index 0000000..ab58567 --- /dev/null +++ b/packages/river_emulator/test/core/extensions/zacas_test.dart @@ -0,0 +1,92 @@ +import 'package:river/river.dart'; +import 'package:river_emulator/river_emulator.dart'; +import 'package:test/test.dart'; + +// amocas.w/.d: compare mem[rs1] against rd; if equal store rs2; rd <- loaded. +// funct7 = funct5(00101)<<2 = 0x14, funct3 = 0x2 (w) / 0x3 (d), opcode 0x2F. +int _amocas(int rs2, int rs1, int funct3, int rd) => + (0x14 << 25) | + (rs2 << 20) | + (rs1 << 15) | + (funct3 << 12) | + (rd << 7) | + 0x2F; + +void main() { + group('Zacas (amocas)', () { + late RiverCore core; + late int pc; + + setUp(() { + final config = RiverCoreConfig( + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + mxlen: RiscVMxlen.rv64, + extensions: [rv64i, rv32i, rvZicsr, rvZifencei, rvA, rvZacas], + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + ); + final sram = Sram( + RiverDevice( + name: 'sram', + compatible: 'river,sram', + range: BusAddressRange(0, 0xFFFF), + clockFrequency: 10000, + ), + ); + core = RiverCore(config, memDevices: Map.fromEntries([sram.mem!])); + pc = config.resetVector; + }); + + test( + 'amocas.w stores rs2 when compare matches; rd gets loaded value', + () async { + await core.mmu.write(0x1000, 42, 4); + core.xregs[Register.x5] = 0x1000; // addr + core.xregs[Register.x3] = 42; // compare value (== mem) -> swap happens + core.xregs[Register.x6] = 99; // swap value + + await core.cycle(pc, _amocas(6, 5, 0x2, 3)); // amocas.w x3,x6,(x5) + + expect(core.xregs[Register.x3], 42, reason: 'rd <- loaded value'); + expect( + await core.mmu.read(0x1000, 4), + 99, + reason: 'mem swapped to rs2', + ); + }, + ); + + test('amocas.w leaves memory unchanged when compare mismatches', () async { + await core.mmu.write(0x1000, 42, 4); + core.xregs[Register.x5] = 0x1000; + core.xregs[Register.x3] = 7; // compare value (!= mem) -> no swap + core.xregs[Register.x6] = 99; + + await core.cycle(pc, _amocas(6, 5, 0x2, 3)); + + expect(core.xregs[Register.x3], 42, reason: 'rd <- loaded value'); + expect(await core.mmu.read(0x1000, 4), 42, reason: 'mem unchanged'); + }); + + test('amocas.d compare-and-swap on a full doubleword', () async { + await core.mmu.write(0x1008, 0xDEADBEEFCAFEBABE, 8); + core.xregs[Register.x5] = 0x1008; + core.xregs[Register.x3] = 0xDEADBEEFCAFEBABE; // matches + core.xregs[Register.x6] = 0x0123456789ABCDEF; + + await core.cycle(pc, _amocas(6, 5, 0x3, 3)); // amocas.d x3,x6,(x5) + + expect(core.xregs[Register.x3], 0xDEADBEEFCAFEBABE); + expect(await core.mmu.read(0x1008, 8), 0x0123456789ABCDEF); + }); + }); +} diff --git a/packages/river_emulator/test/core/extensions/zicsr_test.dart b/packages/river_emulator/test/core/extensions/zicsr_test.dart index 4e3a643..ff486bf 100644 --- a/packages/river_emulator/test/core/extensions/zicsr_test.dart +++ b/packages/river_emulator/test/core/extensions/zicsr_test.dart @@ -1,4 +1,3 @@ -import 'package:riscv/riscv.dart'; import 'package:river/river.dart'; import 'package:river_emulator/river_emulator.dart'; import 'package:test/test.dart'; @@ -9,25 +8,22 @@ void main() { cpuTests( 'Zicsr extension', (config) { - late SramEmulator sram; - late RiverCoreEmulator core; + late Sram sram; + late RiverCore core; late int pc; setUp(() { - sram = SramEmulator( - Device.simple( + sram = Sram( + RiverDevice( name: 'sram', compatible: 'river,sram', range: BusAddressRange(0, 0xFFFF), - fields: const {0: DeviceField('data', 4)}, - clock: config.clock, + clockFrequency: + (config.clock.rate as HarborFixedClockRate).frequency, ), ); - core = RiverCoreEmulator( - config, - memDevices: Map.fromEntries([sram.mem!]), - ); + core = RiverCore(config, memDevices: Map.fromEntries([sram.mem!])); pc = config.resetVector; }); @@ -146,6 +142,69 @@ void main() { (CsrAddress.misa.address << 20) | (2 << 15) | (1 << 7) | 0x1073; expect(() => core.cycle(pc, instr), throwsA(isA())); }); + + test("rpipelinectl resets to 0", () { + expect(read(CsrAddress.rpipelinectl), 0); + }); + + test("rpipelinectl is WARL: only bits [3:0] are writable", () { + write(CsrAddress.rpipelinectl, 0xFFFF); + expect(read(CsrAddress.rpipelinectl), 0xF); + write(CsrAddress.rpipelinectl, 0x5); + expect(read(CsrAddress.rpipelinectl), 0x5); + }); + + test("rpipelinectl SSBD bit round-trips via csrrw", () async { + // csrrw x6, rpipelinectl, x5 with x5 = 1 (SSBD set) + core.xregs[Register.x5] = 0x1; + final csrrw = + (CsrAddress.rpipelinectl.address << 20) | + (5 << 15) | + (6 << 7) | + 0x1073; + await core.cycle(pc, csrrw); + expect(read(CsrAddress.rpipelinectl) & 0x1, 0x1); + }); + + test("User-mode writing rpipelinectl traps", () { + core.mode = PrivilegeMode.user; + final instr = + (CsrAddress.rpipelinectl.address << 20) | + (2 << 15) | + (1 << 7) | + 0x1073; + expect(() => core.cycle(pc, instr), throwsA(isA())); + }); + + test("rpipelinecap reads the config feature bitmap", () { + expect(read(CsrAddress.rpipelinecap), config.rpipelineCap); + }); + + test("rpipelinecap read via csrrs instruction does not trap", () async { + // csrrs x3, rpipelinecap, x0 (rs1=x0 -> pure read, no write attempt) + final instr = + (CsrAddress.rpipelinecap.address << 20) | + (0 << 15) | + (2 << 12) | + (3 << 7) | + 0x73; + final newPc = await core.cycle(pc, instr); + expect(core.xregs[Register.x3], config.rpipelineCap); + expect(newPc, pc + 4); + }); + + test("rpipelinecap is read-only: writing traps", () { + // Write a value distinct from the cap so the emulator's no-op-write + // skip (core.dart) doesn't elide the write before the RO trap fires. + core.xregs[Register.x1] = 0xFF; + // csrrw x2, rpipelinecap, x1 + final instr = + (CsrAddress.rpipelinecap.address << 20) | + (1 << 15) | + (2 << 7) | + 0x1073; + expect(() => core.cycle(pc, instr), throwsA(isA())); + }); }, condition: (config) => config.extensions.any((e) => e.name == 'Zicsr'), ); diff --git a/packages/river_emulator/test/core/mmu_test.dart b/packages/river_emulator/test/core/mmu_test.dart new file mode 100644 index 0000000..e202b4f --- /dev/null +++ b/packages/river_emulator/test/core/mmu_test.dart @@ -0,0 +1,307 @@ +import 'package:river/river.dart'; +import 'package:river_emulator/river_emulator.dart'; +import 'package:test/test.dart'; + +void writeWord(Sram sram, int addr, int value) { + for (int i = 0; i < 4; i++) { + sram.data[addr + i] = (value >> (i * 8)) & 0xFF; + } +} + +int readWord(Sram sram, int addr) { + int v = 0; + for (int i = 0; i < 4; i++) { + v |= sram.data[addr + i] << (i * 8); + } + return v; +} + +void main() { + group('MMU', () { + late Sram sram; + late Mmu mmu; + + setUp(() { + sram = Sram( + RiverDevice( + name: 'sram', + compatible: 'river,sram', + range: BusAddressRange(0, 0xFFFFFF), + clockFrequency: 10000, + ), + ); + + mmu = Mmu( + HarborMmuConfig( + mxlen: RiscVMxlen.rv32, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv32], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + hasSupervisorUserMemory: true, + hasMakeExecutableReadable: true, + ), + Map.fromEntries([sram.mem!]), + ); + }); + + test('bare mode passes address through', () async { + final result = await mmu.translate(0x1000, MemoryAccess.read); + expect(result, 0x1000); + }); + + group('Sv32', () { + // Sv32: 2-level page table + // PTE format: PPN[1] (12 bits) | PPN[0] (10 bits) | RSW (2 bits) | D A G U X W R V + // VPN[1] = bits [31:22], VPN[0] = bits [21:12], offset = bits [11:0] + const pageTableBase = 0x10000; + const secondLevelBase = 0x11000; + + void setupIdentityPage( + int vaddr, { + bool r = true, + bool w = true, + bool x = true, + bool u = false, + }) { + final vpn1 = (vaddr >> 22) & 0x3FF; + final vpn0 = (vaddr >> 12) & 0x3FF; + final physPage = vaddr >> 12; + + // First-level PTE points to second-level table + final l1Pte = ((secondLevelBase >> 12) << 10) | 0x1; // V=1, not leaf + writeWord(sram, pageTableBase + vpn1 * 4, l1Pte); + + // Second-level PTE is a leaf mapping to the same physical page + int flags = 0x1; // V=1 + if (r) flags |= 0x2; + if (w) flags |= 0x4; + if (x) flags |= 0x8; + if (u) flags |= 0x10; + final l2Pte = (physPage << 10) | flags; + writeWord(sram, secondLevelBase + vpn0 * 4, l2Pte); + } + + setUp(() { + mmu.configure(1, pageTableBase >> 12); // Sv32, ppn = pageTableBase/4096 + }); + + test('translates virtual to physical with Sv32', () async { + setupIdentityPage(0x20000); + writeWord(sram, 0x20000, 0xDEADBEEF); + + final phys = await mmu.translate( + 0x20000, + MemoryAccess.read, + privilege: PrivilegeMode.supervisor, + ); + + expect(phys, 0x20000); + final val = await mmu.read( + 0x20000, + 4, + privilege: PrivilegeMode.supervisor, + ); + expect(val, 0xDEADBEEF); + }); + + test('throws load page fault for invalid PTE', () async { + // Don't set up any page table entry for 0x30000 + expect( + () => mmu.translate( + 0x30000, + MemoryAccess.read, + privilege: PrivilegeMode.supervisor, + ), + throwsA( + isA().having( + (e) => e.trap, + 'trap', + Trap.loadPageFault, + ), + ), + ); + }); + + test('throws store page fault for read-only page', () async { + setupIdentityPage(0x20000, r: true, w: false, x: false); + + expect( + () => mmu.translate( + 0x20000, + MemoryAccess.write, + privilege: PrivilegeMode.supervisor, + ), + throwsA( + isA().having( + (e) => e.trap, + 'trap', + Trap.storePageFault, + ), + ), + ); + }); + + test('throws instruction page fault for non-executable page', () async { + setupIdentityPage(0x20000, r: true, w: true, x: false); + + expect( + () => mmu.translate( + 0x20000, + MemoryAccess.instr, + privilege: PrivilegeMode.supervisor, + ), + throwsA( + isA().having( + (e) => e.trap, + 'trap', + Trap.instructionPageFault, + ), + ), + ); + }); + + test('throws page fault for user accessing supervisor page', () async { + setupIdentityPage(0x20000, u: false); + + expect( + () => mmu.translate( + 0x20000, + MemoryAccess.read, + privilege: PrivilegeMode.user, + ), + throwsA( + isA().having( + (e) => e.trap, + 'trap', + Trap.loadPageFault, + ), + ), + ); + }); + + test('sets Accessed bit on read', () async { + setupIdentityPage(0x20000); + final vpn0 = (0x20000 >> 12) & 0x3FF; + final pteBefore = readWord(sram, secondLevelBase + vpn0 * 4); + expect(pteBefore & (1 << 6), 0); // A bit not set + + await mmu.translate( + 0x20000, + MemoryAccess.read, + privilege: PrivilegeMode.supervisor, + ); + + final pteAfter = readWord(sram, secondLevelBase + vpn0 * 4); + expect(pteAfter & (1 << 6), isNot(0)); // A bit set + }); + + test('sets Dirty bit on write', () async { + setupIdentityPage(0x20000); + final vpn0 = (0x20000 >> 12) & 0x3FF; + + await mmu.translate( + 0x20000, + MemoryAccess.write, + privilege: PrivilegeMode.supervisor, + ); + + final pteAfter = readWord(sram, secondLevelBase + vpn0 * 4); + expect(pteAfter & (1 << 6), isNot(0)); // A bit set + expect(pteAfter & (1 << 7), isNot(0)); // D bit set + }); + + test('does not set Dirty bit on read', () async { + setupIdentityPage(0x20000); + final vpn0 = (0x20000 >> 12) & 0x3FF; + + await mmu.translate( + 0x20000, + MemoryAccess.read, + privilege: PrivilegeMode.supervisor, + ); + + final pteAfter = readWord(sram, secondLevelBase + vpn0 * 4); + expect(pteAfter & (1 << 7), 0); // D bit not set + }); + + test('TLB caches translation', () async { + setupIdentityPage(0x20000); + + await mmu.translate( + 0x20000, + MemoryAccess.read, + privilege: PrivilegeMode.supervisor, + ); + + expect(mmu.tlb.misses, 1); + expect(mmu.tlb.hits, 0); + + await mmu.translate( + 0x20000, + MemoryAccess.read, + privilege: PrivilegeMode.supervisor, + ); + + expect(mmu.tlb.hits, 1); + }); + + test('flushTlb invalidates cached entries', () async { + setupIdentityPage(0x20000); + + await mmu.translate( + 0x20000, + MemoryAccess.read, + privilege: PrivilegeMode.supervisor, + ); + + mmu.flushTlb(); + + await mmu.translate( + 0x20000, + MemoryAccess.read, + privilege: PrivilegeMode.supervisor, + ); + + expect(mmu.tlb.misses, 2); + }); + + test('mxr allows reading executable-only page', () async { + setupIdentityPage(0x20000, r: false, w: false, x: true); + + await mmu.translate( + 0x20000, + MemoryAccess.read, + privilege: PrivilegeMode.supervisor, + mxr: true, + ); + }); + + test('supervisor cannot access user page without sum', () async { + setupIdentityPage(0x20000, u: true); + + expect( + () => mmu.translate( + 0x20000, + MemoryAccess.read, + privilege: PrivilegeMode.supervisor, + sum: false, + ), + throwsA(isA()), + ); + }); + + test('supervisor can access user page with sum', () async { + setupIdentityPage(0x20000, u: true); + + final phys = await mmu.translate( + 0x20000, + MemoryAccess.read, + privilege: PrivilegeMode.supervisor, + sum: true, + ); + + expect(phys, 0x20000); + }); + }); + }); +} diff --git a/packages/river_emulator/test/core/privilege_test.dart b/packages/river_emulator/test/core/privilege_test.dart index 12fa923..b49966d 100644 --- a/packages/river_emulator/test/core/privilege_test.dart +++ b/packages/river_emulator/test/core/privilege_test.dart @@ -1,4 +1,3 @@ -import 'package:riscv/riscv.dart'; import 'package:river/river.dart'; import 'package:river_emulator/river_emulator.dart'; import 'package:test/test.dart'; @@ -7,26 +6,19 @@ import '../constants.dart'; void main() { cpuTests('Privilege ISA', (config) { - late SramEmulator sram; - late RiverCoreEmulator core; - late int pc; - + late Sram sram; + late RiverCore core; setUp(() { - sram = SramEmulator( - Device.simple( + sram = Sram( + RiverDevice( name: 'sram', compatible: 'river,sram', range: BusAddressRange(0, 0xFFFF), - fields: const {0: DeviceField('data', 4)}, - clock: config.clock, + clockFrequency: (config.clock.rate as HarborFixedClockRate).frequency, ), ); - core = RiverCoreEmulator( - config, - memDevices: Map.fromEntries([sram.mem!]), - ); - pc = config.resetVector; + core = RiverCore(config, memDevices: Map.fromEntries([sram.mem!])); }); test('MRET returns from trap', () async { diff --git a/packages/river_emulator/test/core/rv32i_test.dart b/packages/river_emulator/test/core/rv32i_test.dart index a2b7271..f22726b 100644 --- a/packages/river_emulator/test/core/rv32i_test.dart +++ b/packages/river_emulator/test/core/rv32i_test.dart @@ -1,4 +1,3 @@ -import 'package:riscv/riscv.dart'; import 'package:river/river.dart'; import 'package:river_emulator/river_emulator.dart'; import 'package:test/test.dart'; @@ -7,39 +6,28 @@ import '../constants.dart'; void main() { cpuTests('RV32I', (config) { - late SramEmulator sram; - late RiverCoreEmulator core; + late Sram sram; + late RiverCore core; late int pc; setUp(() { - sram = SramEmulator( - Device.simple( + sram = Sram( + RiverDevice( name: 'sram', compatible: 'river,sram', range: BusAddressRange(0, 0xFFFF), - fields: const {0: DeviceField('data', 4)}, - clock: config.clock, + clockFrequency: (config.clock.rate as HarborFixedClockRate).frequency, ), ); - core = RiverCoreEmulator( - config, - memDevices: Map.fromEntries([sram.mem!]), - ); + core = RiverCore(config, memDevices: Map.fromEntries([sram.mem!])); pc = config.resetVector; }); Future writeWord(int addr, int value) => - core.mmu.write(addr, value, MicroOpMemSize.word.bytes); - - Future readWord(int addr) => - core.mmu.read(addr, MicroOpMemSize.word.bytes); - - Future writeDword(int addr, int value) => - core.mmu.write(addr, value, MicroOpMemSize.dword.bytes); + core.mmu.write(addr, value, 4); - Future readDword(int addr) => - core.mmu.read(addr, MicroOpMemSize.dword.bytes); + Future readWord(int addr) => core.mmu.read(addr, 4); test('addi increments register', () async { core.reset(); diff --git a/packages/river_emulator/test/debug/remote_bitbang_test.dart b/packages/river_emulator/test/debug/remote_bitbang_test.dart new file mode 100644 index 0000000..dd5a762 --- /dev/null +++ b/packages/river_emulator/test/debug/remote_bitbang_test.dart @@ -0,0 +1,315 @@ +import 'dart:async'; +import 'dart:io'; + +import 'package:river/river.dart'; +import 'package:river_emulator/river_emulator.dart'; +import 'package:test/test.dart'; + +/// Drives the software JTAG TAP exactly as a JTAG adapter would, so the whole +/// chain (TAP -> DTM -> Debug Module -> RiverCore) is exercised end-to-end. +class JtagHost { + final SoftJtagDtm dtm; + JtagHost(this.dtm); + + Future _clk(int tms, [int tdi = 0]) => dtm.clock(tms, tdi); + + Future resetTap() async { + for (var i = 0; i < 5; i++) { + await _clk(1); // -> Test-Logic-Reset + } + await _clk(0); // -> Run-Test/Idle + } + + /// Scan [bits] bits through the selected DR, returning the captured value. + Future scanDr(int bits, int value) async { + await _clk(1); // Run-Test/Idle -> Select-DR + await _clk(0); // -> Capture-DR (loads DR) + await _clk(0); // -> Shift-DR + var captured = 0; + for (var i = 0; i < bits; i++) { + final last = i == bits - 1; + // Sample TDO while TCK is low, before the rising edge shifts the next bit + // out (the OpenOCD remote_bitbang convention the combinational `tdo` + // getter models). Reading after `_clk` would capture one bit too late. + if (dtm.tdo == 1) captured |= 1 << i; + await _clk(last ? 1 : 0, (value >> i) & 1); + } + await _clk(1); // Exit1-DR -> Update-DR (performs the access) + await _clk(0); // -> Run-Test/Idle + return captured; + } + + Future scanIr(int bits, int value) async { + await _clk(1); // -> Select-DR + await _clk(1); // -> Select-IR + await _clk(0); // -> Capture-IR + await _clk(0); // -> Shift-IR + var captured = 0; + for (var i = 0; i < bits; i++) { + final last = i == bits - 1; + // Sample TDO while TCK is low, before the rising edge (see scanDr). + if (dtm.tdo == 1) captured |= 1 << i; + await _clk(last ? 1 : 0, (value >> i) & 1); + } + await _clk(1); // -> Update-IR + await _clk(0); // -> Run-Test/Idle + return captured; + } + + // DMI helpers (assume IR already == DMI 0x11). op: 1=read, 2=write. + Future dmWrite(int addr, int data) => + scanDr(41, (addr << 34) | ((data & 0xFFFFFFFF) << 2) | 2); + + Future dmRead(int addr) async { + await scanDr(41, (addr << 34) | 1); // issue read + final captured = await scanDr(41, 0); // nop scan captures the result + return (captured >> 2) & 0xFFFFFFFF; + } +} + +void main() { + HarborMmuConfig mmu(RiscVMxlen x) => HarborMmuConfig( + mxlen: x, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ); + const clk = HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ); + + RiverCore makeCore() { + final sram = Sram( + RiverDevice( + name: 'sram', + compatible: 'river,sram', + range: BusAddressRange(0, 0xFFFF), + clockFrequency: 10000, + ), + ); + final core = RiverCore( + RiverCoreConfig( + mxlen: RiscVMxlen.rv64, + extensions: kRva23S64Extensions, + type: RiverCoreType.general, + mmu: mmu(RiscVMxlen.rv64), + interrupts: [], + clock: clk, + ), + memDevices: Map.fromEntries([sram.mem!]), + ); + core.reset(); + return core; + } + + group('remote bitbang debug (TAP/DTM/DM chain)', () { + late RiverCore core; + late RiverDebugTarget tgt; + late SoftJtagDtm dtm; + late JtagHost host; + + setUp(() { + core = makeCore(); + tgt = RiverDebugTarget(core); + dtm = SoftJtagDtm(SoftDebugModule(tgt), idcode: 0xDEADBEE3); + host = JtagHost(dtm); + }); + + test('reads IDCODE', () async { + await host.resetTap(); + expect(await host.scanDr(32, 0), 0xDEADBEE3); + }); + + test('dmstatus reports version and halt state; halt works', () async { + await host.resetTap(); + await host.scanIr(5, 0x11); // select DMI + + var dmstatus = await host.dmRead(0x11); + expect(dmstatus & 0xF, 2); // debug spec version 0.13.2 + expect((dmstatus >> 9) & 1, 0); // allhalted == 0 (running) + + await host.dmWrite(0x10, (1 << 31) | 1); // dmcontrol: haltreq | dmactive + expect(tgt.halted, isTrue); + dmstatus = await host.dmRead(0x11); + expect((dmstatus >> 9) & 1, 1); // allhalted + + await host.dmWrite(0x10, (1 << 30) | 1); // resumereq | dmactive + expect(tgt.halted, isFalse); + }); + + test('GPR write/read via abstract command', () async { + await host.resetTap(); + await host.scanIr(5, 0x11); + + // data0 = 0x12345678 ; command = access-register, write, 32-bit, x6 + await host.dmWrite(0x04, 0x12345678); + await host.dmWrite(0x17, (2 << 20) | (1 << 17) | (1 << 16) | 0x1006); + expect(core.xregs[Register.x6], 0x12345678); + + // read it back into data0 + await host.dmWrite(0x17, (2 << 20) | (1 << 17) | 0x1006); + expect(await host.dmRead(0x04), 0x12345678); + }); + + test('memory write/read via system bus', () async { + await host.resetTap(); + await host.scanIr(5, 0x11); + + // Default sbcs selects 32-bit access. Write then read 0x2000. + await host.dmWrite(0x39, 0x2000); // sbaddress0 + await host.dmWrite(0x3c, 0xCAFEBABE); // sbdata0 -> store + expect(await core.mmu.read(0x2000, 4, pageTranslate: false), 0xCAFEBABE); + + // sbreadonaddr: writing sbaddress0 triggers a read into sbdata0. + final sbcs = await host.dmRead(0x38); + await host.dmWrite(0x38, sbcs | (1 << 20)); + await host.dmWrite(0x39, 0x2000); + expect(await host.dmRead(0x3c), 0xCAFEBABE); + }); + + test('64-bit system-bus access combines sbdata0 + sbdata1', () async { + await host.resetTap(); + await host.scanIr(5, 0x11); + + // Select 64-bit access (sbaccess=3). A debugger downloading a 64-bit + // image writes sbdata1 (high) then sbdata0 (low, which triggers the + // write). If the DM only stored sbdata0 the high word would be zeroed, + // corrupting every other 32-bit word of the image (the bug that desynced + // the fuzz DUT's instruction fetch). + await host.dmWrite(0x38, 3 << 17); // sbcs.sbaccess = 3 (64-bit) + await host.dmWrite(0x39, 0x3000); // sbaddress0 + await host.dmWrite(0x3d, 0xCAFEBABE); // sbdata1 (high 32) + await host.dmWrite( + 0x3c, + 0xDEADBEEF, + ); // sbdata0 (low 32) -> writes 8 bytes + + expect( + await core.mmu.read(0x3000, 8, pageTranslate: false), + 0xCAFEBABEDEADBEEF, + ); + // The high word must be present, not zero (the pre-fix failure mode). + expect(await core.mmu.read(0x3004, 4, pageTranslate: false), 0xCAFEBABE); + }); + + test('ebreak enters debug halt when dcsr.ebreakm is armed', () async { + // Arm ebreakm so an ebreak in machine mode halts into Debug Mode instead + // of trapping to mtvec (the bug differential fuzzing surfaced: with + // mtvec=entry the breakpoint trap looped back into the program forever). + tgt.writeCsr(0x7b0, 1 << 15); // dcsr.ebreakm = 1 + + // Program at 0x200: addi a0, x0, 42 ; ebreak + await tgt.writeMem(0x200, 0x02A00513, 4); // addi a0,x0,42 + await tgt.writeMem(0x204, 0x00100073, 4); // ebreak + + var pc = 0x200; + var steps = 0; + while (!tgt.halted && steps < 20) { + pc = await core.runPipeline(pc); + steps++; + } + + expect(tgt.halted, isTrue, reason: 'ebreak should halt into Debug Mode'); + expect(tgt.dpc, 0x204, reason: 'dpc = address of the ebreak'); + expect( + core.xregs[Register.x10], + 42, + reason: 'body executed before ebreak', + ); + expect((tgt.readCsr(0x7b0) >> 6) & 0x7, 1, reason: 'dcsr.cause = ebreak'); + }); + + test('ebreak without ebreakm armed does NOT debug-halt', () async { + // dcsr defaults with ebreakm clear; an ebreak must trap (to mtvec), not + // enter Debug Mode. With mtvec=0 that trap double-faults and throws, which + // is exactly the non-halt path we are asserting. + await tgt.writeMem(0x200, 0x00100073, 4); // ebreak + try { + await core.runPipeline(0x200); + } catch (_) { + // Expected: breakpoint trap -> mtvec=0 -> double fault. NOT a debug halt. + } + expect( + tgt.halted, + isFalse, + reason: 'ebreak must not halt when dcsr.ebreakm is clear', + ); + }); + + test('sbcs write preserves read-only capability bits', () async { + await host.resetTap(); + await host.scanIr(5, 0x11); + + // A debugger writes sbcs to pick an access size; its write carries the + // read-only capability fields as zero. Those must survive, or a later + // reconnect reads sbcs back, sees no supported access size, and abandons + // the system bus (the iteration-1 "unsupported size" memory-write bug). + const roMask = + 0xE0000FFF; // sbversion[31:29] | sbasize[11:5] | sbaccessN[4:0] + final before = await host.dmRead(0x38); + await host.dmWrite( + 0x38, + (2 << 17) | (1 << 16), + ); // sbaccess=2, autoincrement + final after = await host.dmRead(0x38); + expect(after & roMask, before & roMask); // caps unchanged + expect((after >> 17) & 0x7, 2); // control field took the write + }); + }); + + test('IDCODE read over the remote_bitbang TCP protocol', () async { + final core = makeCore(); + final server = await startRiverDebugServer( + core, + port: 0, + idcode: 0xDEADBEE3, + ); + // port:0 asks the OS for a free port; read it back. + final port = server.boundPort!; + + final out = []; + void clk(int tms, int tdi, {bool read = false}) { + final v = (tms << 1) | tdi; + out.add(0x30 | v); // tck=0 + // Read TDO while TCK is low, before the rising edge (the OpenOCD + // convention the combinational `tdo` getter models). + if (read) out.add(0x52); // 'R' + out.add(0x30 | (4 | v)); // tck=1 (rising edge shifts) + } + + for (var i = 0; i < 5; i++) { + clk(1, 0); // reset + } + clk(0, 0); // Run-Test/Idle + clk(1, 0); + clk(0, 0); + clk(0, 0); // -> Shift-DR (IR defaults to IDCODE) + for (var i = 0; i < 32; i++) { + clk(i == 31 ? 1 : 0, 0, read: true); + } + clk(1, 0); + clk(0, 0); // Update-DR, Idle + out.add(0x51); // 'Q' + + final sock = await Socket.connect(InternetAddress.loopbackIPv4, port); + final resp = []; + final done = Completer(); + sock.listen( + resp.addAll, + onDone: () { + if (!done.isCompleted) done.complete(); + }, + ); + sock.add(out); + await sock.flush(); + await done.future.timeout(const Duration(seconds: 3)); + + var idcode = 0; + for (var i = 0; i < 32; i++) { + if (resp[i] == 0x31) idcode |= 1 << i; + } + expect(idcode, 0xDEADBEE3); + await server.stop(); + }); +} diff --git a/packages/river_emulator/test/devices/clint_test.dart b/packages/river_emulator/test/devices/clint_test.dart index c7f3b16..7f0c5ad 100644 --- a/packages/river_emulator/test/devices/clint_test.dart +++ b/packages/river_emulator/test/devices/clint_test.dart @@ -1,5 +1,4 @@ import 'dart:async'; -import 'package:riscv/riscv.dart'; import 'package:river/river.dart'; import 'package:river_emulator/river_emulator.dart'; import 'package:test/test.dart'; @@ -8,46 +7,44 @@ import '../constants.dart'; void main() { cpuTests('CLINT Device', (config) { - late SramEmulator sram; - late RiscVClintEmulator clint; - late RiverCoreEmulator core; + late Sram sram; + late Clint clint; + late RiverCore core; const clintAddr = 0x2000000; setUp(() { // Simple SRAM backing store - sram = SramEmulator( - Device.simple( + sram = Sram( + RiverDevice( name: 'sram', compatible: 'river,sram', range: BusAddressRange(0, 0xFFFF), - fields: const {0: DeviceField('data', 4)}, - clock: config.clock, + clockFrequency: (config.clock.rate as HarborFixedClockRate).frequency, ), ); // CLINT instance - clint = RiscVClintEmulator( - RiscVClint(name: 'clint', address: clintAddr, clock: config.clock), + clint = Clint( + RiverDevice( + name: 'clint', + compatible: 'riscv,clint0', + range: BusAddressRange(clintAddr, 0x10000), + clockFrequency: (config.clock.rate as HarborFixedClockRate).frequency, + ), ); - core = RiverCoreEmulator( + core = RiverCore( config, memDevices: Map.fromEntries([sram.mem!, clint.mem!]), ); }); - Future writeWord(int addr, int val) => - core.mmu.write(addr, val, MicroOpMemSize.word.bytes); - - Future readWord(int addr) => - core.mmu.read(addr, MicroOpMemSize.word.bytes); + Future writeWord(int addr, int val) => core.mmu.write(addr, val, 4); - Future writeDouble(int addr, int val) => - core.mmu.write(addr, val, MicroOpMemSize.dword.bytes); + Future writeDouble(int addr, int val) => core.mmu.write(addr, val, 8); - Future readDouble(int addr) => - core.mmu.read(addr, MicroOpMemSize.dword.bytes); + Future readDouble(int addr) => core.mmu.read(addr, 8); // Memory map offsets: final msipAddr = clintAddr + 0x0000; @@ -76,7 +73,7 @@ void main() { test('MTIP fires when mtime >= mtimecmp', () async { await writeDouble(mtimecmpAddr, 10); - await Future.delayed(Duration(milliseconds: 5)); + await Future.delayed(Duration(milliseconds: 5)); expect(clint.interrupts(0)[1], isTrue); }); @@ -88,7 +85,7 @@ void main() { }); test('Write mtime resets the base (mtime decreases)', () async { - await Future.delayed(Duration(milliseconds: 5)); + await Future.delayed(Duration(milliseconds: 5)); final before = await readDouble(mtimeAddr); await writeDouble(mtimeAddr, 5); @@ -99,7 +96,7 @@ void main() { test('MTIP clears when mtimecmp is set higher again', () async { await writeDouble(mtimecmpAddr, 5); - await Future.delayed(Duration(milliseconds: 5)); + await Future.delayed(Duration(milliseconds: 5)); expect(clint.interrupts(0)[1], isTrue); await writeDouble(mtimecmpAddr, 0xFFFFFFFF); @@ -109,7 +106,7 @@ void main() { test('mtime increases over real time', () async { final t1 = await readDouble(mtimeAddr); - await Future.delayed(Duration(milliseconds: 2)); + await Future.delayed(Duration(milliseconds: 2)); final t2 = await readDouble(mtimeAddr); diff --git a/packages/river_emulator/test/devices/ddr_boot_flow_test.dart b/packages/river_emulator/test/devices/ddr_boot_flow_test.dart new file mode 100644 index 0000000..c10dab4 --- /dev/null +++ b/packages/river_emulator/test/devices/ddr_boot_flow_test.dart @@ -0,0 +1,204 @@ +import 'package:river/river.dart'; +import 'package:river_emulator/river_emulator.dart'; +import 'package:test/test.dart'; + +/// End-to-end boot flow in the emulator: an FSBL (the kind Weir's first-stage +/// bootloader will be) runs from SRAM, SWEEPS the DDR read tap through the +/// training MMIO to find the eye, INITIALISES main RAM by writing a tiny payload +/// into the now-usable DRAM, then JUMPS to and EXECUTES that payload from DRAM. +/// Proves the DDR-training -> main-RAM -> jump leg works as a whole. CAR +/// (rcache* CSRs -> l1d.lockRange) and flash XIP are exercised separately; this +/// focuses on the DRAM bring-up that was the missing emulator piece. See +/// project_ddr_training / project_weir_bios. +void main() { + // RV64 instruction encoders (subset). + int lui(int rd, int imm20) => ((imm20 & 0xFFFFF) << 12) | (rd << 7) | 0x37; + int iimm(int rd, int rs1, int imm, int f3) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x13; + int addi(int rd, int rs1, int imm) => iimm(rd, rs1, imm, 0x0); + int store(int rs2, int rs1, int imm, int f3) { + final lo = imm & 0x1F; + final hi = (imm >> 5) & 0x7F; + return (hi << 25) | + (rs2 << 20) | + (rs1 << 15) | + (f3 << 12) | + (lo << 7) | + 0x23; + } + + int sw(int rs2, int rs1, int imm) => store(rs2, rs1, imm, 0x2); + int lw(int rd, int rs1, int imm) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (0x2 << 12) | (rd << 7) | 0x03; + int branch(int rs1, int rs2, int imm, int f3) { + final b12 = (imm >> 12) & 0x1; + final b11 = (imm >> 11) & 0x1; + final b10_5 = (imm >> 5) & 0x3F; + final b4_1 = (imm >> 1) & 0xF; + return (b12 << 31) | + (b10_5 << 25) | + (rs2 << 20) | + (rs1 << 15) | + (f3 << 12) | + (b4_1 << 8) | + (b11 << 7) | + 0x63; + } + + int beq(int rs1, int rs2, int imm) => branch(rs1, rs2, imm, 0x0); + int bne(int rs1, int rs2, int imm) => branch(rs1, rs2, imm, 0x1); + int jal(int rd, int imm) { + final b20 = (imm >> 20) & 0x1; + final b10_1 = (imm >> 1) & 0x3FF; + final b11 = (imm >> 11) & 0x1; + final b19_12 = (imm >> 12) & 0xFF; + return (b20 << 31) | + (b10_1 << 21) | + (b11 << 20) | + (b19_12 << 12) | + (rd << 7) | + 0x6F; + } + + int jalr(int rd, int rs1, int imm) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (rd << 7) | 0x67; + + // Load a 32-bit constant into rd (lui + addi with the addi sign carry). + List li(int rd, int v) { + v &= 0xFFFFFFFF; + final lo = v & 0xFFF; + var hi = (v >> 12) & 0xFFFFF; + if (lo & 0x800 != 0) hi = (hi + 1) & 0xFFFFF; + final loSigned = lo & 0x800 != 0 ? lo - 0x1000 : lo; + return [lui(rd, hi), addi(rd, rd, loSigned)]; + } + + test('FSBL trains DDR, inits main RAM, and runs a payload from DRAM', () async { + const mxlen = RiscVMxlen.rv64; + final config = RiverCoreConfigV1.small( + mmu: HarborMmuConfig( + mxlen: mxlen, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + interrupts: const [], + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + resetVector: 0, + ); + + // Base bit31 must be clear so RV64 `lui` builds a positive address (lui + // sign-extends bit31; 0x80000000 would become 0xFFFFFFFF80000000). + const dramBase = 0x40000000; + const arraySize = 0x10000; // 64KB array + const ctrlBase = dramBase + arraySize; + const eyeLo = 8, eyeHi = 40; + + final sram = Sram( + const RiverDevice( + name: 'sram', + compatible: 'river,sram', + range: BusAddressRange(0, 0x10000), + ), + ); + final dram = Dram( + const RiverDevice( + name: 'dram', + compatible: 'river,dram', + range: BusAddressRange(dramBase, arraySize + Dram.trainCtrlSize), + ), + trainable: true, + eyeLo: eyeLo, + eyeHi: eyeHi, + ); + + // The payload that runs from DRAM: store the boot magic to SRAM[0x100], + // then return (jr ra). Built as data, copied into DRAM by the FSBL. + const magic = 0xB0074EE7; + const markerAddr = 0x100; // in SRAM + final payload0 = sw(23, 22, 0); // sw x23, 0(x22) (x22=marker, x23=magic) + final payload1 = jalr(0, 1, 0); // jr ra + + const pattern = 0x600DCAFE; // sweep test pattern (bit31 clear: load-safe) + const payloadDram = dramBase + 0x400; // 0x40000400 + + // FSBL program (at 0x0 in SRAM). Registers: + // x10=ctrl base, x20=dram base, x21=pattern, x5=tap, x22=marker, x23=magic + final prog = [ + lui(10, 0x40010), // x10 = ctrlBase (0x40010000) + lui(20, 0x40000), // x20 = dramBase (0x40000000) + ...li(21, pattern), // x21 = pattern + addi(5, 0, 0), // x5 = tap = 0 + // sweep: (pc of this instr = sweepPc) + sw(5, 10, 0x00), // RDTAP_TARGET = tap + addi(6, 0, 1), + sw(6, 10, 0x08), // CTL = SET + sw(21, 20, 0x00), // DRAM[0] = pattern + lw(7, 20, 0x00), // read back + beq(7, 21, 0), // placeholder offset -> patched to 'found' + addi(5, 5, 1), // tap++ + addi(8, 0, 128), + bne(5, 8, 0), // placeholder -> back to sweep + jal(0, 0), // fail: halt-in-place (offset 0 = self loop) + // found: + addi(22, 0, markerAddr), // x22 = SRAM marker addr + ...li(23, magic), // x23 = boot magic + ...li(24, payload0), // payload instr 0 + sw(24, 20, 0x400), // DRAM[0x400] = payload0 + ...li(25, payload1), // payload instr 1 + sw(25, 20, 0x404), // DRAM[0x404] = payload1 + sw(5, 0, 0x104), // SRAM[0x104] = found tap + ...li(26, payloadDram), // x26 = DRAM payload addr + jalr(1, 26, 0), // jump+link: EXECUTE the payload from DRAM + // returns here: + jal(0, 0), // done: halt-in-place + ]; + + // Patch the branch offsets now that the layout is known (4 bytes/instr). + // Indices are into the FLATTENED prog list, so they count li()'s two words. + final sweepIdx = prog.indexOf(sw(5, 10, 0x00)); // first sweep instr + final beqIdx = prog.indexOf(beq(7, 21, 0)); // the beq placeholder + final bneIdx = prog.indexOf(bne(5, 8, 0)); // the bne placeholder + final foundIdx = prog.indexOf(addi(22, 0, markerAddr)); // 'found:' instr + prog[beqIdx] = beq(7, 21, (foundIdx - beqIdx) * 4); + prog[bneIdx] = bne(5, 8, (sweepIdx - bneIdx) * 4); + + final core = RiverCore( + config, + memDevices: Map.fromEntries([sram.mem!, dram.mem!]), + ); + core.reset(); + + // Load the FSBL into SRAM at 0. + for (var i = 0; i < prog.length; i++) { + await core.mmu.write(i * 4, prog[i], 4); + } + + // Run until the program parks in a self-loop (pc stops advancing) or a cap. + var pc = config.resetVector; + for (var i = 0; i < 200000; i++) { + final next = await core.runPipeline(pc); + if (next == pc) break; // hit a `jal x0, 0` self-loop + pc = next; + } + + // The payload executed from DRAM and wrote the magic into SRAM. + final marker = await core.mmu.read(markerAddr, 4); + expect( + marker & 0xFFFFFFFF, + magic, + reason: 'payload should have run from DRAM and written the magic', + ); + + // The FSBL recorded a working tap, and it is inside the eye. + final tap = await core.mmu.read(0x104, 4); + expect( + tap, + inInclusiveRange(eyeLo, eyeHi), + reason: 'FSBL should have trained the read tap into the eye', + ); + }); +} diff --git a/packages/river_emulator/test/devices/ddr_test_loop_test.dart b/packages/river_emulator/test/devices/ddr_test_loop_test.dart new file mode 100644 index 0000000..93e393d --- /dev/null +++ b/packages/river_emulator/test/devices/ddr_test_loop_test.dart @@ -0,0 +1,110 @@ +import 'dart:async'; + +import 'package:river/river.dart'; +import 'package:river_emulator/river_emulator.dart'; +import 'package:river_maskrom/river_maskrom.dart'; +import 'package:test/test.dart'; + +/// Runs the looping [RiverDdrTest] straight from ROM against a WORKING DRAM +/// (a plain Sram) in the emulator and captures the UART. With sound storage the +/// verdict must be a clean, REPEATED "DDR OK" - this validates the looping +/// program's control flow (the hardware-readout fix) independently of any real +/// DDR PHY, so a garbled/ER result on silicon can be attributed to hardware. +RiverCoreConfig _rv64(int romBase) => RiverCoreConfigV1.small( + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + hasSupervisorUserMemory: true, + hasMakeExecutableReadable: true, + ), + interrupts: [], + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(12000000), + ), + resetVector: romBase, +); + +void main() { + test( + 'looping RiverDdrTest prints repeated clean "DDR OK" on good DRAM', + () async { + const romBase = 0x10000; + const dramBase = 0x80000000; + const uartBase = 0x10000000; + final config = _rv64(romBase); + + final prog = RiverDdrTest( + isa: config.isa, + uartBase: uartBase, + dramBase: dramBase, + clockHz: 12000000, + loopForever: true, + ); + await prog.build(); + final progBytes = prog.generateBinary(); + + final romMem = Sram( + RiverDevice( + name: 'rom', + compatible: 'river,sram', + range: BusAddressRange(romBase, 0x10000), + clockFrequency: 12000000, + ), + ); + final dram = Sram( + RiverDevice( + name: 'dram', + compatible: 'river,sram', + range: BusAddressRange(dramBase, 0x8000000), + clockFrequency: 12000000, + ), + ); + final uartOut = []; + final outCtl = StreamController>(sync: true); + final inCtl = StreamController>(sync: true); + outCtl.stream.listen(uartOut.addAll); + final uart = Uart( + RiverDevice( + name: 'uart0', + compatible: 'ns16550a', + range: BusAddressRange(uartBase, 0x1000), + interrupts: [0], + clockFrequency: 12000000, + ), + input: inCtl.stream, + output: outCtl.sink, + ); + + for (var i = 0; i < progBytes.length; i++) { + romMem.data[i] = progBytes[i]; + } + + final core = RiverCore( + config, + memDevices: Map.fromEntries([romMem.mem!, dram.mem!, uart.mem!]), + ); + + var pc = romBase; + for (var i = 0; i < 2000000; i++) { + final instr = await core.fetch(pc); + pc = await core.cycle(pc, instr); + // Stop once we have caught at least two verdict lines. + final s = String.fromCharCodes(uartOut); + if ('DDR OK'.allMatches(s).length >= 2) break; + } + + final out = String.fromCharCodes(uartOut); + expect(out, contains('DDR OK'), reason: 'output was: ${out.codeUnits}'); + expect(out, isNot(contains('DDR ER')), reason: 'got: $out'); + // Looping must produce more than one copy. + expect( + 'DDR OK'.allMatches(out).length, + greaterThanOrEqualTo(2), + reason: 'looping should repeat the verdict; got: $out', + ); + }, + ); +} diff --git a/packages/river_emulator/test/devices/dram_exec_test.dart b/packages/river_emulator/test/devices/dram_exec_test.dart new file mode 100644 index 0000000..bcecd97 --- /dev/null +++ b/packages/river_emulator/test/devices/dram_exec_test.dart @@ -0,0 +1,117 @@ +import 'dart:async'; + +import 'package:river/river.dart'; +import 'package:river_emulator/river_emulator.dart'; +import 'package:river_maskrom/river_maskrom.dart'; +import 'package:test/test.dart'; + +/// Validates [RiverDramExec]'s logic functionally: it must print "DEXEC", copy +/// its banner stub into DRAM (a plain Sram here), jalr into it, and then stream +/// "DRAM EXEC OK" from code running IN DRAM. If this passes in the emulator but +/// the same program goes silent after "DEXEC" on real silicon, the copy+jump is +/// sound and the hardware fetch-from-DRAM path is the suspect, not the program. +RiverCoreConfig _rv64(int romBase) => RiverCoreConfigV1.small( + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + hasSupervisorUserMemory: true, + hasMakeExecutableReadable: true, + ), + interrupts: [], + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(12000000), + ), + resetVector: romBase, +); + +void main() { + test( + 'RiverDramExec copies a stub into DRAM and executes it from there', + () async { + const romBase = 0x10000; + const dramBase = 0x80000000; + const uartBase = 0x10000000; + final config = _rv64(romBase); + + final stub = RiverHelloWorld( + isa: config.isa, + uartBase: uartBase, + ramBase: dramBase + 0x10000, + clockHz: 12000000, + message: 'DRAM EXEC OK\r\n', + loop: true, + ); + await stub.build(); + + final prog = RiverDramExec( + isa: config.isa, + uartBase: uartBase, + dramBase: dramBase, + clockHz: 12000000, + stubBytes: stub.generateBinary(), + ); + await prog.build(); + final progBytes = prog.generateBinary(); + + final romMem = Sram( + RiverDevice( + name: 'rom', + compatible: 'river,sram', + range: BusAddressRange(romBase, 0x10000), + clockFrequency: 12000000, + ), + ); + final dram = Sram( + RiverDevice( + name: 'dram', + compatible: 'river,sram', + range: BusAddressRange(dramBase, 0x8000000), + clockFrequency: 12000000, + ), + ); + final uartOut = []; + final outCtl = StreamController>(sync: true); + final inCtl = StreamController>(sync: true); + outCtl.stream.listen(uartOut.addAll); + final uart = Uart( + RiverDevice( + name: 'uart0', + compatible: 'ns16550a', + range: BusAddressRange(uartBase, 0x1000), + interrupts: [0], + clockFrequency: 12000000, + ), + input: inCtl.stream, + output: outCtl.sink, + ); + + for (var i = 0; i < progBytes.length; i++) { + romMem.data[i] = progBytes[i]; + } + + final core = RiverCore( + config, + memDevices: Map.fromEntries([romMem.mem!, dram.mem!, uart.mem!]), + ); + + var pc = romBase; + for (var i = 0; i < 4000000; i++) { + final instr = await core.fetch(pc); + pc = await core.cycle(pc, instr); + final s = String.fromCharCodes(uartOut); + if ('DRAM EXEC OK'.allMatches(s).length >= 2) break; + } + + final out = String.fromCharCodes(uartOut); + expect(out, contains('DEXEC'), reason: 'boot ROM program must run: $out'); + expect( + out, + contains('DRAM EXEC OK'), + reason: 'stub must execute FROM DRAM; got: ${out.codeUnits}', + ); + }, + ); +} diff --git a/packages/river_emulator/test/devices/dram_train_test.dart b/packages/river_emulator/test/devices/dram_train_test.dart new file mode 100644 index 0000000..687f6df --- /dev/null +++ b/packages/river_emulator/test/devices/dram_train_test.dart @@ -0,0 +1,123 @@ +import 'package:river/river.dart'; +import 'package:river_emulator/river_emulator.dart'; +import 'package:test/test.dart'; + +/// The emulator DRAM read-training model: the array is unusable until the read +/// tap is walked into the valid eye via the MMIO control window, so a BIOS +/// training sweep is testable in the emulator. Mirrors the HDL +/// HarborDdrController trainable path. See project_ddr_training. +void main() { + const arraySize = 0x1000; + const ctrlSize = Dram.trainCtrlSize; // 0x1000 + const eyeLo = 8, eyeHi = 40; + + // Control-window register offsets (relative to the device base). + const rdtap = arraySize + 0x00; + const ctl = arraySize + 0x08; + const rdslack = arraySize + 0x10; + const status = arraySize + 0x18; + const setBit = 0x1, loadBit = 0x2; + + Dram makeDram() => Dram( + const RiverDevice( + name: 'dram', + compatible: 'river,dram', + range: BusAddressRange(0x80000000, arraySize + ctrlSize), + ), + trainable: true, + eyeLo: eyeLo, + eyeHi: eyeHi, + ); + + test('untrained array reads return garbage; in-eye tap fixes it', () async { + final d = makeDram(); + final acc = d.memAccessor!; + + // Write a pattern (writes always land, even untrained). + await acc.write(0x100, 0xDEADBEEF, 4); + + // Untrained (tap 0, below the eye): read is corrupted. + expect(await acc.read(0x100, 4), isNot(0xDEADBEEF)); + + // Train: target tap 20 (in the eye), pulse SET. + await acc.write(rdtap, 20, 4); + await acc.write(ctl, setBit, 4); + + // Now the array reads correctly. + expect(await acc.read(0x100, 4), 0xDEADBEEF); + // STATUS reports the current tap in bits [8:1], busy (bit0) clear. + expect(await acc.read(status, 4), 20 << 1); + }); + + test('a tap outside the eye corrupts reads again', () async { + final d = makeDram(); + final acc = d.memAccessor!; + await acc.write(0x200, 0xCAFEF00D, 4); + + // In-eye -> good. + await acc.write(rdtap, eyeHi, 4); + await acc.write(ctl, setBit, 4); + expect(await acc.read(0x200, 4), 0xCAFEF00D); + + // One past the eye -> garbage. + await acc.write(rdtap, eyeHi + 1, 4); + await acc.write(ctl, setBit, 4); + expect(await acc.read(0x200, 4), isNot(0xCAFEF00D)); + }); + + test('LOAD resets the tap to 0 (out of eye)', () async { + final d = makeDram(); + final acc = d.memAccessor!; + await acc.write(0x10, 0x12345678, 4); + await acc.write(rdtap, 16, 4); + await acc.write(ctl, setBit, 4); + expect(await acc.read(0x10, 4), 0x12345678); + + await acc.write(ctl, loadBit, 4); + expect(await acc.read(status, 4), 0); // tap back to 0 + expect(await acc.read(0x10, 4), isNot(0x12345678)); + }); + + test('RDSLACK round-trips through the control window', () async { + final d = makeDram(); + final acc = d.memAccessor!; + await acc.write(rdslack, 3, 4); + expect(await acc.read(rdslack, 4), 3); + }); + + test('a sweep finds the eye (the BIOS training algorithm)', () async { + final d = makeDram(); + final acc = d.memAccessor!; + const probe = 0xA5A5A5A5; + await acc.write(0x000, probe, 4); + + // Sweep every tap, recording which ones read the pattern back correctly. + final good = []; + for (var tap = 0; tap < 128; tap++) { + await acc.write(rdtap, tap, 4); + await acc.write(ctl, setBit, 4); + if (await acc.read(0x000, 4) == probe) good.add(tap); + } + + // The contiguous good window is exactly the configured eye. + expect(good.first, eyeLo); + expect(good.last, eyeHi); + expect(good.length, eyeHi - eyeLo + 1); + }); + + test( + 'untrainable DRAM ignores the control window and is always reliable', + () async { + final d = Dram( + const RiverDevice( + name: 'dram', + compatible: 'river,dram', + range: BusAddressRange(0x80000000, arraySize), + ), + ); + final acc = d.memAccessor!; + await acc.write(0x40, 0x99887766, 4); + expect(await acc.read(0x40, 4), 0x99887766); // no training needed + }, + ); +} diff --git a/packages/river_emulator/test/devices/plic_test.dart b/packages/river_emulator/test/devices/plic_test.dart index 9576c07..f9487d3 100644 --- a/packages/river_emulator/test/devices/plic_test.dart +++ b/packages/river_emulator/test/devices/plic_test.dart @@ -1,6 +1,5 @@ import 'dart:async'; -import 'package:riscv/riscv.dart'; import 'package:river/river.dart'; import 'package:river_emulator/river_emulator.dart'; import 'package:test/test.dart'; @@ -9,44 +8,42 @@ import '../constants.dart'; void main() { cpuTests('PLIC Device', (config) { - late SramEmulator sram; - late RiscVPlicEmulator plic; - late RiverCoreEmulator core; + late Sram sram; + late Plic plic; + late RiverCore core; const plicAddr = 0x40000; setUp(() { - sram = SramEmulator( - Device.simple( + sram = Sram( + RiverDevice( name: 'sram', compatible: 'river,sram', range: BusAddressRange(0, 0xFFFF), - fields: const {0: DeviceField('data', 4)}, - clock: config.clock, + clockFrequency: (config.clock.rate as HarborFixedClockRate).frequency, ), ); - plic = RiscVPlicEmulator( - RiscVPlic( + plic = Plic( + RiverDevice( name: 'plic', - address: plicAddr, - interrupt: 0, - clock: config.clock, + compatible: 'riscv,plic0', + range: BusAddressRange(plicAddr, 0x4000000), + interrupts: [0], + clockFrequency: (config.clock.rate as HarborFixedClockRate).frequency, ), numSources: 8, ); - core = RiverCoreEmulator( + core = RiverCore( config, memDevices: Map.fromEntries([sram.mem!, plic.mem!]), ); }); - Future writeWord(int addr, int val) => - core.mmu.write(addr, val, MicroOpMemSize.word.bytes); + Future writeWord(int addr, int val) => core.mmu.write(addr, val, 4); - Future readWord(int addr) => - core.mmu.read(addr, MicroOpMemSize.word.bytes); + Future readWord(int addr) => core.mmu.read(addr, 4); test('No interrupt when pending=0', () { final irq = plic.interrupts(0)[0]; @@ -59,8 +56,8 @@ void main() { }); test('Interrupt fires when pending AND enabled', () async { - await writeWord(plicAddr + 0, 1); - await writeWord(plicAddr + 0x200, 1 << 1); + await writeWord(plicAddr + 0x4, 1); + await writeWord(plicAddr + 0x2000, 1 << 1); await writeWord(plicAddr + 0x200000, 0); plic.setSourcePending(1, true); @@ -69,8 +66,8 @@ void main() { }); test('Claim returns correct ID and clears pending', () async { - await writeWord(plicAddr + 0, 1); - await writeWord(plicAddr + 0x200, 1 << 1); + await writeWord(plicAddr + 0x4, 1); + await writeWord(plicAddr + 0x2000, 1 << 1); await writeWord(plicAddr + 0x200000, 0); // Assert interrupt @@ -80,15 +77,15 @@ void main() { final id = await readWord(plicAddr + 0x200004); expect(id, 1); - final pending = await readWord(plicAddr + 0x100); + final pending = await readWord(plicAddr + 0x1000); expect((pending & (1 << 1)) != 0, isFalse); expect(plic.interrupts(0)[0], isFalse); }); test('Threshold blocks lower priority interrupts', () async { - await writeWord(plicAddr + 0, 1); - await writeWord(plicAddr + 0x200, 1 << 1); + await writeWord(plicAddr + 0x4, 1); + await writeWord(plicAddr + 0x2000, 1 << 1); await writeWord(plicAddr + 0x200000, 2); plic.setSourcePending(1, true); @@ -96,11 +93,11 @@ void main() { }); test('Higher priority interrupt wins', () async { - await writeWord(plicAddr + 0, 1); + await writeWord(plicAddr + 0x4, 1); plic.setPriority(2, 3); - await writeWord(plicAddr + 0x200, (1 << 1) | (1 << 2)); + await writeWord(plicAddr + 0x2000, (1 << 1) | (1 << 2)); await writeWord(plicAddr + 0x200000, 0); plic.setSourcePending(1, true); diff --git a/packages/river_emulator/test/devices/uart_test.dart b/packages/river_emulator/test/devices/uart_test.dart index 3866fc1..25172ef 100644 --- a/packages/river_emulator/test/devices/uart_test.dart +++ b/packages/river_emulator/test/devices/uart_test.dart @@ -1,34 +1,30 @@ import 'dart:async'; -import 'dart:io'; -import 'package:riscv/riscv.dart'; import 'package:river/river.dart'; import 'package:river_emulator/river_emulator.dart'; import 'package:test/test.dart'; import '../constants.dart'; -/** - * ``` - * li x5, 0x20000 - * - * /* Set LCR, DLAB=1 */ - * li x6, 0x80 - * sb x6, 3(x5) - * - * /* Set DLL=3 */ - * li x6, 3 - * sb x6, 8(x5) - * - * /* Set DLM=0 */ - * li x6, 0 - * sb x6, 1(x5) - * - * /* Set LCR=3, DLAB=0, 8N1 */ - * li x6, 0x3, - * sb x6, 3(x5) - * ``` - */ +/// ``` +/// li x5, 0x20000 +/// +/// /* Set LCR, DLAB=1 +/// li x6, 0x80 +/// sb x6, 3(x5) +/// +/// /* Set DLL=3 +/// li x6, 3 +/// sb x6, 8(x5) +/// +/// /* Set DLM=0 +/// li x6, 0 +/// sb x6, 1(x5) +/// +/// /* Set LCR=3, DLAB=0, 8N1 +/// li x6, 0x3, +/// sb x6, 3(x5) +/// ``` const kInitProg = [ 0x000202b7, 0x08000313, @@ -43,13 +39,12 @@ const kInitProg = [ void main() { cpuTests('UART Device', (config) { - late SramEmulator sram; - late UartEmulator uart; - late RiverCoreEmulator core; + late Sram sram; + late Uart uart; + late RiverCore core; late StreamController> inputController; late StreamController> outputController; late List uartOutput; - late int pc; setUp(() { inputController = StreamController>(sync: true); @@ -58,46 +53,35 @@ void main() { outputController.stream.listen(uartOutput.addAll); - sram = SramEmulator( - Device.simple( + sram = Sram( + RiverDevice( name: 'sram', compatible: 'river,sram', range: BusAddressRange(0, 0xFFFF), - fields: const {0: DeviceField('data', 4)}, - clock: config.clock, + clockFrequency: (config.clock.rate as HarborFixedClockRate).frequency, ), ); - uart = UartEmulator( - RiverUart( + uart = Uart( + RiverDevice( name: 'uart0', - address: 0x20000, - clock: config.clock, - interrupt: 0, + compatible: 'ns16550a', + range: BusAddressRange(0x20000, 0x8), + interrupts: [0], + clockFrequency: (config.clock.rate as HarborFixedClockRate).frequency, ), input: inputController.stream, output: outputController.sink, ); - core = RiverCoreEmulator( + core = RiverCore( config, memDevices: Map.fromEntries([sram.mem!, uart.mem!]), ); - - pc = config.resetVector; }); Future writeWord(int addr, int value) => - core.mmu.write(addr, value, MicroOpMemSize.word.bytes); - - Future readWord(int addr) => - core.mmu.read(addr, MicroOpMemSize.word.bytes); - - void writeDword(int addr, int value) => - core.mmu.write(addr, value, MicroOpMemSize.dword.bytes); - - Future readDword(int addr) => - core.mmu.read(addr, MicroOpMemSize.dword.bytes); + core.mmu.write(addr, value, 4); Future exec(List prog) async { sram.reset(); @@ -140,7 +124,7 @@ void main() { final prog = [...kInitProg, 0x04100313, 0x00628023, 0x00000013]; await exec(prog); - await Future.delayed(Duration.zero); + await Future.delayed(Duration.zero); expect(uart.lcr & 0x83, 0x03); expect(uart.divisor, 3); @@ -166,7 +150,7 @@ void main() { ]; await exec(prog); - await Future.delayed(Duration.zero); + await Future.delayed(Duration.zero); expect(uart.lcr & 0x83, 0x03); expect(uart.divisor, 3); diff --git a/packages/river_emulator/test/elf_loading_test.dart b/packages/river_emulator/test/elf_loading_test.dart new file mode 100644 index 0000000..5006a80 --- /dev/null +++ b/packages/river_emulator/test/elf_loading_test.dart @@ -0,0 +1,142 @@ +import 'package:bintools/bintools.dart'; +import 'package:river/river.dart'; +import 'package:river_emulator/river_emulator.dart'; +import 'package:test/test.dart'; + +import 'constants.dart'; + +Elf _buildElf(List words, {int addr = 0}) { + final section = Section('.text'); + for (final w in words) { + section.emitWord(w); + } + final writer = ElfWriter(entryPoint: addr); + writer.addSection(section, address: addr); + return Elf.load(writer.write()); +} + +RiverSoC _makeSoC(RiverCoreConfig config, Sram sram) { + final core = RiverCore(config, memDevices: Map.fromEntries([sram.mem!])); + return RiverSoC.fromDevicesAndCores(cores: [core], devices: [sram]); +} + +void main() { + group('ELF loading', () { + test('loadBytes writes data at correct offset', () { + final config = kCpuConfigs['RC1.mi']!; + final sram = Sram( + RiverDevice( + name: 'sram', + compatible: 'river,sram', + range: BusAddressRange(0x1000, 0x2000), + clockFrequency: 10000, + ), + ); + + final soc = _makeSoC(config, sram); + soc.loadBytes(0x1000, [0xDE, 0xAD, 0xBE, 0xEF]); + + expect(sram.data[0], 0xDE); + expect(sram.data[1], 0xAD); + expect(sram.data[2], 0xBE); + expect(sram.data[3], 0xEF); + }); + + test('loadBytes at offset within device', () { + final config = kCpuConfigs['RC1.mi']!; + final sram = Sram( + RiverDevice( + name: 'sram', + compatible: 'river,sram', + range: BusAddressRange(0x1000, 0x2000), + clockFrequency: 10000, + ), + ); + + final soc = _makeSoC(config, sram); + soc.loadBytes(0x1010, [0x01, 0x02]); + + expect(sram.data[0x10], 0x01); + expect(sram.data[0x11], 0x02); + }); + + test('loadElf loads PT_LOAD segment into memory', () { + final config = kCpuConfigs['RC1.mi']!; + final sram = Sram( + RiverDevice( + name: 'sram', + compatible: 'river,sram', + range: BusAddressRange(0, 0xFFFF), + clockFrequency: 10000, + ), + ); + + final soc = _makeSoC(config, sram); + + // addi x5, x0, 42 -> 0x02A00293 + final elf = _buildElf([0x02A00293, 0x00700313]); + soc.loadElf(elf); + + // Little-endian: 0x02A00293 -> [0x93, 0x02, 0xA0, 0x02] + expect(sram.data[0], 0x93); + expect(sram.data[1], 0x02); + expect(sram.data[2], 0xA0); + expect(sram.data[3], 0x02); + }); + + test('loaded ELF executes correctly', () async { + final config = kCpuConfigs['RC1.mi']!; + final sram = Sram( + RiverDevice( + name: 'sram', + compatible: 'river,sram', + range: BusAddressRange(0, 0xFFFF), + clockFrequency: 10000, + ), + ); + + final soc = _makeSoC(config, sram); + final core = soc.cores[0]; + + // addi x5, x0, 42 + soc.loadElf(_buildElf([0x02A00293])); + + var pc = config.resetVector; + pc = await core.runPipeline(pc); + + expect(core.xregs[Register.x5], 42); + }); + + test('multiple ELFs load to different regions', () { + final config = kCpuConfigs['RC1.mi']!; + final sram = Sram( + RiverDevice( + name: 'sram', + compatible: 'river,sram', + range: BusAddressRange(0, 0xFFFF), + clockFrequency: 10000, + ), + ); + + final soc = _makeSoC(config, sram); + + // Firmware at 0x0000 + soc.loadElf(_buildElf([0x02A00293], addr: 0x0000)); + // Payload at 0x1000 + soc.loadElf(_buildElf([0x00700313], addr: 0x1000)); + + // Check firmware at 0x0000 + expect(sram.data[0], 0x93); + expect(sram.data[3], 0x02); + + // Check payload at 0x1000 + expect(sram.data[0x1000], 0x13); + expect(sram.data[0x1003], 0x00); + }); + + test('ELF entry point is preserved', () { + final elf = _buildElf([0x02A00293], addr: 0x8000); + expect(elf.header.entry, 0x8000); + }); + }); +} diff --git a/packages/river_emulator/test/river_emulator_test.dart b/packages/river_emulator/test/river_emulator_test.dart index bee0383..a350800 100644 --- a/packages/river_emulator/test/river_emulator_test.dart +++ b/packages/river_emulator/test/river_emulator_test.dart @@ -1,17 +1,66 @@ -import 'dart:convert'; - -import 'package:riscv/riscv.dart'; import 'package:river/river.dart'; import 'package:river_emulator/river_emulator.dart'; import 'package:test/test.dart'; +RiverSoCConfig _testConfig() { + final sysclk = HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ); + + return RiverSoCConfig( + devices: [ + const RiverDevice( + name: 'clint', + compatible: 'riscv,clint0', + range: BusAddressRange(0x02000000, 0x10000), + ), + const RiverDevice( + name: 'plic', + compatible: 'riscv,plic0', + range: BusAddressRange(0x04000000, 0x4000000), + interrupts: [0], + ), + const RiverDevice( + name: 'uart0', + compatible: 'ns16550a', + range: BusAddressRange(0x10000000, 0x8), + interrupts: [1], + ), + const RiverDevice( + name: 'flash', + compatible: 'river,flash', + range: BusAddressRange(0x20000000, 0x1000000), + ), + const RiverDevice( + name: 'sram', + compatible: 'river,sram', + range: BusAddressRange(0x80000000, 0x100000), + ), + ], + cores: [ + RiverCoreConfigV1.nano( + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv32, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + interrupts: [], + clock: sysclk, + resetVector: 0x20000000, + ), + ], + ); +} + void main() { - group('Stream V1 - iCESugar', () { - final config = StreamV1SoC.icesugar(); - late RiverSoCEmulator soc; + group('Emulator', () { + final config = _testConfig(); + late RiverSoC soc; setUp(() { - soc = RiverSoCEmulator( + soc = RiverSoC( config, deviceOptions: { 'uart0': {'input.empty': 'true', 'output.empty': 'true'}, @@ -22,12 +71,12 @@ void main() { test('Configure', () { soc.reset(); - expect(soc.devices.length, 6); + expect(soc.devices.length, 5); expect(soc.cores.length, 1); }); test('Read data', () async { - final soc = RiverSoCEmulator( + final soc = RiverSoC( config, deviceOptions: { 'flash': {'bytes': '002081B3'}, @@ -35,18 +84,18 @@ void main() { }, ); - final mmap = soc.getDevice('flash')!.config.mmap!; + final range = soc.getDevice('flash')!.config.range!; soc.reset(); expect( - await soc.cores[0].read(mmap.start, soc.cores[0].config.mxlen.width), + await soc.cores[0].read(range.start, soc.cores[0].config.mxlen.bytes), 0x002081B3, ); }); test('Reset & execute', () async { - final soc = RiverSoCEmulator( + final soc = RiverSoC( config, deviceOptions: { 'flash': {'bytes': '00A08293'}, @@ -54,14 +103,14 @@ void main() { }, ); - final mmap = soc.getDevice('flash')!.config.mmap!; + final range = soc.getDevice('flash')!.config.range!; soc.reset(); soc.cores[0].xregs[Register.x1] = 12; final pc = (await soc.runPipelines({}))[0]!; - expect(config.cores[0].resetVector, mmap!.start); + expect(config.cores[0].resetVector, range.start); expect(config.cores[0].resetVector, pc - 4); expect(soc.cores[0].xregs[Register.x5], 22); }); diff --git a/packages/river_hdl/analysis_options.yaml b/packages/river_hdl/analysis_options.yaml index dee8927..f5d48c9 100644 --- a/packages/river_hdl/analysis_options.yaml +++ b/packages/river_hdl/analysis_options.yaml @@ -1,30 +1,2 @@ -# This file configures the static analysis results for your project (errors, -# warnings, and lints). -# -# This enables the 'recommended' set of lints from `package:lints`. -# This set helps identify many issues that may lead to problems when running -# or consuming Dart code, and enforces writing Dart using a single, idiomatic -# style and format. -# -# If you want a smaller set of lints you can change this to specify -# 'package:lints/core.yaml'. These are just the most critical lints -# (the recommended set includes the core lints). -# The core lints are also what is used by pub.dev for scoring packages. - -include: package:lints/recommended.yaml - -# Uncomment the following section to specify additional rules. - -# linter: -# rules: -# - camel_case_types - -# analyzer: -# exclude: -# - path/to/excluded/files/** - -# For more information about the core and recommended set of lints, see -# https://dart.dev/go/core-lints - -# For additional information about configuring this file, see -# https://dart.dev/guides/language/analysis-options +# Inherits the workspace production analysis baseline. +include: ../../analysis_options.yaml diff --git a/packages/river_hdl/bin/river_genip.dart b/packages/river_hdl/bin/river_genip.dart new file mode 100644 index 0000000..fbef0e1 --- /dev/null +++ b/packages/river_hdl/bin/river_genip.dart @@ -0,0 +1,221 @@ +import 'dart:io' show Platform, Directory, File; + +import 'package:args/args.dart'; +import 'package:harbor/harbor.dart' show HarborBoard; +import 'package:logging/logging.dart'; +import 'package:path/path.dart' as path; +import 'package:river_hdl/river_hdl.dart'; + +Future main(List arguments) async { + final parser = ArgParser() + ..addOption( + 'name', + abbr: 'n', + help: 'SoC top module name', + defaultsTo: 'river_soc', + ) + ..addMultiOption( + 'core', + abbr: 'c', + help: 'Core model', + defaultsTo: ['rc1-mi'], + allowed: ['rc1-n', 'rc1-mi', 'rc1-s', 'rc1-m'], + ) + ..addOption( + 'interconnect', + abbr: 'i', + help: 'Bus protocol', + defaultsTo: 'wishbone', + allowed: ['wishbone', 'axi', 'tilelink'], + ) + ..addOption( + 'clock-freq', + help: 'System clock frequency (Hz)', + defaultsTo: '48000000', + ) + ..addOption( + 'osc-freq', + help: 'External oscillator frequency (Hz)', + defaultsTo: '12000000', + ) + ..addMultiOption( + 'device', + abbr: 'd', + // Params use commas (key=val,key=val), so do NOT split values on commas; + // each device is its own -d flag. + splitCommas: false, + help: + 'A device in the SoC: [name=]type:addr[:size][:board|compat][:key=val,...]. ' + 'Memory-backed regions (sram/flash/dram) need addr+size and may carry a ' + 'board + tuning params; MMIO peripherals (uart/clint/plic/gpio) need an ' + 'addr; pseudo-devices (usb-dfu/debug-jtag/flash-firmware) drive a ' + 'subsystem. Examples: sram:0x08000000:64K | uart:0x10000000:ns16550a | ' + 'dram:0x80000000:128M:arty-s7-x8:ddr3fast=true,clockfreq=200000000 | ' + 'usb-dfu:0x0C000000:mode=software | debug-jtag | ' + 'flash-firmware:0x100000:path=weir-fsbl.bin', + ) + ..addOption( + 'target', + abbr: 't', + help: + 'Target (FPGA: ecp5:dev:pkg, ice40:dev:pkg; ASIC: sky130:hd, gf180mcu:3v3)', + ) + ..addOption( + 'board', + abbr: 'b', + help: + 'FPGA board from the Harbor catalog (${HarborBoard.byName.keys.join(', ')}): ' + 'supplies the target (when --target is unset) and the board standard ' + 'pins (clk/uart/...), so those need not be given as --target/--pin. ' + '--pin still overrides individual signals.', + ) + ..addOption( + 'pdk-root', + help: 'PDK installation root (required for ASIC targets)', + ) + ..addMultiOption( + 'pin', + abbr: 'p', + help: 'Pin assignment (name=device@port:pin or name=pin)', + ) + // Diagnostic, kept global (a build-wide bring-up switch, not board tuning). + ..addFlag( + 'ddr-single-word', + help: + 'Diagnostic: the "ddrtest" boot program writes/reads ONLY the first ' + 'DRAM word (isolates a broken read path from BL8 DM-mask clobber).', + defaultsTo: false, + ) + ..addOption('maskrom-path', help: 'Maskrom binary to bake into SRAM init') + ..addOption( + 'boot-program', + help: + 'Bake a built-in program into the boot ROM (SRAM systems: skip ' + 'cache-as-RAM, run from ROM, use RAM directly). "hello" prints a ' + 'banner; "monitor" loads payloads into RAM over the UART; "hexdump" ' + 'hex-dumps two flash windows over the UART (the bitstream preamble at ' + 'offset 0 and the firmware slot at 0x100000) straight from ROM, with ' + 'no flash-write or maskrom-copy dependency (a SILENT-bring-up probe). ' + '"bundleselftest" mirrors the maskrom flash->SRAM copy+jump from ROM ' + 'with per-boundary checkpoints (A/F:/B/S:/C/J) so one boot localizes ' + 'whether the flash read, the copy, or the jump is what breaks.', + allowed: [ + 'hello', + 'monitor', + 'hexdump', + 'bundleselftest', + 'trapwfi', + 'ddrtest', + 'ddrprobe', + 'ddrlevel', + 'ddrlevelx', + 'ddrdiag', + 'ddreye', + 'ddrverify', + 'dramexec', + 'dramping', + 'dramstress', + 'dramstress64', + 'dramstresshi', + 'xipboot', + ], + ) + ..addOption( + 'output', + abbr: 'o', + help: 'Output directory', + defaultsTo: 'output', + ) + ..addOption( + 'log', + help: 'Log level', + allowed: Level.LEVELS.map((v) => v.name.toLowerCase()).toList(), + ) + ..addFlag('help', abbr: 'h', help: 'Print usage'); + + final args = parser.parse(arguments); + + if (args.flag('help')) { + print('Usage: ${path.basename(Platform.script.toFilePath())} [options]'); + print(''); + print('River SoC IP generator'); + print(''); + print('Options:'); + print(parser.usage); + return; + } + + Logger.root.onRecord.listen((record) { + print('${record.level.name}: ${record.time}: ${record.message}'); + }); + + if (args.option('log') != null) { + Logger.root.level = Level.LEVELS.firstWhere( + (v) => v.name.toLowerCase() == args.option('log'), + ); + } + + final config = RiverGenIpConfig( + name: args.option('name')!, + cores: args.multiOption('core'), + interconnect: args.option('interconnect')!, + clockFrequency: int.parse(args.option('clock-freq')!), + oscFrequency: int.parse(args.option('osc-freq')!), + devices: args.multiOption('device').map(Device.parse).toList(), + target: args.option('target') != null + ? Target.parse(args.option('target')!) + : null, + boardName: args.option('board'), + pins: args.multiOption('pin').map(PinAssignment.parse).toList(), + maskromPath: args.option('maskrom-path'), + pdkRoot: args.option('pdk-root'), + bootProgram: args.option('boot-program'), + ddrSingleWord: args.flag('ddr-single-word'), + ); + + print('Generating SoC: ${config.name}'); + print(' Cores: ${config.cores.join(', ')}'); + print(' Interconnect: ${config.interconnect}'); + print(' Clock: ${config.clockFrequency} Hz'); + print(' Memories: ${config.memories.length}'); + print(' Devices: ${config.devices.length}'); + if (config.boardName case final b?) { + print(' Board: $b'); + } + if (config.effectiveTarget case final t?) { + switch (t) { + case FpgaTarget(): + print(' Target: ${t.vendor} ${t.device} (${t.package})'); + case AsicTarget(): + print(' Target: ${t.pdk} (${t.variant})'); + } + } + + final soc = await config.buildSoC(); + final outputDir = Directory(args.option('output')!); + await soc.generateAll(outputDir); + + // Bundled flash firmware: emit the firmware bytes as a standalone file to be + // flashed at the firmware offset (the maskrom copies it from there to SRAM). + if (config.flashFirmwarePath != null) { + final firmware = await File(config.flashFirmwarePath!).readAsBytes(); + final fwPath = path.join(outputDir.path, 'firmware.bin'); + await File(fwPath).writeAsBytes(firmware); + print( + ' Flash firmware (external): ${config.flashFirmwarePath} -> $fwPath ' + '(${firmware.length} bytes, flash offset ' + '0x${config.flashFirmwareOffset.toRadixString(16)})', + ); + } else if (config.flashFirmware != null) { + final firmware = await config.buildFlashFirmwareImage(); + final fwPath = path.join(outputDir.path, 'firmware.bin'); + await File(fwPath).writeAsBytes(firmware); + print( + ' Flash firmware: ${config.flashFirmware} -> $fwPath ' + '(${firmware.length} bytes, flash offset ' + '0x${config.flashFirmwareOffset.toRadixString(16)})', + ); + } + + print('Done: ${args.option('output')}'); +} diff --git a/packages/river_hdl/bin/river_hdlgen.dart b/packages/river_hdl/bin/river_hdlgen.dart deleted file mode 100644 index b606a68..0000000 --- a/packages/river_hdl/bin/river_hdlgen.dart +++ /dev/null @@ -1,176 +0,0 @@ -import 'dart:io' show Platform, File; - -import 'package:args/args.dart'; -import 'package:logging/logging.dart'; -import 'package:path/path.dart' as path; -import 'package:river/river.dart'; -import 'package:river_hdl/river_hdl.dart'; - -Future main(List arguments) async { - var parser = ArgParser(); - parser.addOption( - 'soc', - help: 'Sets the SoC to generate', - allowed: RiverSoCChoice.values.map((v) => v.name).toList(), - ); - - parser.addMultiOption( - 'soc-option', - help: 'Adds an option when configuring the SoC', - splitCommas: false, - ); - - parser.addOption( - 'platform', - help: 'Sets the platform to generate', - allowed: RiverPlatformChoice.values.map((v) => v.name).toList(), - ); - - parser.addMultiOption( - 'device-option', - help: 'Adds an option when configuring a device', - splitCommas: false, - ); - - parser.addOption( - 'output', - help: 'Sets the output path to generate the SystemVerilog to', - ); - - parser.addOption( - 'log', - help: 'Sets the log level', - allowed: Level.LEVELS.map((v) => v.name.toLowerCase()).toList(), - ); - - parser.addFlag('help', help: 'Prints the usage'); - - final args = parser.parse(arguments); - - if (args.flag('help')) { - print('Usage: ${path.basename(Platform.script.toFilePath())}'); - print(''); - print('Options:'); - print(parser.usage); - return; - } - - Logger.root.onRecord.listen((record) { - print('${record.level.name}: ${record.time}: ${record.message}'); - }); - - if (args.option('log') != null) { - Logger.root.level = Level.LEVELS.firstWhere( - (v) => v.name.toLowerCase() == args.option('log'), - ); - Logger.root.finest('Logging set to ${Logger.root.level}'); - } - - RiverPlatformChoice? platformChoice; - RiverSoCChoice? socChoice; - - if (args.option('platform') == null && args.option('soc') == null) { - print('Missing platform or soc option'); - return; - } else if (args.option('platform') != null && args.option('soc') == null) { - platformChoice = RiverPlatformChoice.getChoice(args.option('platform')!); - - if (platformChoice == null) { - print('Invalid argument for platform option'); - return; - } - - socChoice = platformChoice!.soc; - } else if (args.option('platform') == null && args.option('soc') != null) { - socChoice = RiverSoCChoice.getChoice(args.option('soc')!); - - if (socChoice == null) { - print('Invalid argument for soc option'); - return Future.value(); - } - } else { - platformChoice = RiverPlatformChoice.getChoice(args.option('platform')!); - socChoice = RiverSoCChoice.getChoice(args.option('soc')!); - - if (platformChoice?.soc != socChoice) { - print( - "Platform's SoC and the value given for \"--soc\" do not align, unable to handle...", - ); - return Future.value(); - } - } - - if (platformChoice == null) { - print('Platform is not set, unable to handle...'); - return; - } - - final platform = platformChoice ?? (throw 'Bad state, platform is not set'); - final soc = socChoice ?? (throw 'Bad state, soc is not set'); - - final socConfig = - soc.configure({ - ...Map.fromEntries( - args.multiOption('soc-option').map((entry) { - final i = entry.indexOf('='); - assert(i > 0); - return MapEntry(entry.substring(0, i), entry.substring(i + 1)); - }), - ), - 'platform': platform.name, - }) ?? - (throw 'Invalid platform configuration'); - - Logger.root.finest('River SoC configured: $socConfig'); - - List staticInstructions = []; - - final ip = RiverSoCIP( - socConfig, - deviceOptions: Map.fromEntries( - args - .multiOption('device-option') - .map((option) { - final i = option.indexOf('.'); - assert(i > 0); - return option.substring(0, i); - }) - .map( - (key) => MapEntry( - key, - Map.fromEntries( - args - .multiOption('device-option') - .where((option) { - final i = option.indexOf('.'); - assert(i > 0); - return option.substring(0, i) == key; - }) - .map((option) { - final i = option.indexOf('.'); - assert(i > 0); - - final entry = option.substring(i + 1); - - final x = entry.indexOf('='); - assert(x > 0); - - return MapEntry( - entry.substring(0, x), - entry.substring(x + 1), - ); - }), - ), - ), - ), - ), - staticInstructions: staticInstructions, - ); - - Logger.root.finest('River SoC module created: $ip'); - - await ip.buildAndGenerateRTL( - logger: Logger.root, - outputPath: args.option('output') ?? 'output', - ); -} diff --git a/packages/river_hdl/bin/river_sim.dart b/packages/river_hdl/bin/river_sim.dart new file mode 100644 index 0000000..2eade4b --- /dev/null +++ b/packages/river_hdl/bin/river_sim.dart @@ -0,0 +1,546 @@ +import 'dart:async'; +import 'dart:io' show Platform, File, exit, stdout; + +import 'package:args/args.dart'; +import 'package:bintools/bintools.dart'; +import 'package:logging/logging.dart'; +import 'package:path/path.dart' as path; +import 'package:rohd/rohd.dart'; +import 'package:rohd_hcl/rohd_hcl.dart' hide DataPortInterface, DataPortGroup; +import 'package:river/river.dart'; +import 'package:river_hdl/river_hdl.dart'; + +String elfToMemString(Elf elf, int dataWidth) { + final segments = elf.programHeaders.where((ph) => ph.type == 1).toList(); + final buf = StringBuffer(); + + for (final ph in segments) { + final data = elf.segmentData(ph); + if (data.isEmpty) continue; + + buf.writeln('@${ph.pAddr.toRadixString(16)}'); + + for (var i = 0; i < data.length; i++) { + buf.write(data[i].toRadixString(16).padLeft(2, '0')); + if ((i + 1) % 16 == 0) { + buf.writeln(); + } else { + buf.write(' '); + } + } + + if (ph.memSize > ph.fileSize) { + for (var i = ph.fileSize; i < ph.memSize; i++) { + buf.write('00'); + if ((i + 1) % 16 == 0) { + buf.writeln(); + } else { + buf.write(' '); + } + } + } + + buf.writeln(); + } + + return buf.toString(); +} + +Future main(List arguments) async { + final parser = ArgParser() + ..addMultiOption( + 'core', + abbr: 'c', + help: 'Core model', + defaultsTo: ['rc1-mi'], + allowed: ['rc1-n', 'rc1-mi', 'rc1-s', 'rc1-m'], + ) + ..addOption( + 'clock-freq', + help: 'System clock frequency (Hz)', + defaultsTo: '48000000', + ) + ..addOption('maskrom-path', help: 'Path to an ELF to load into the maskrom') + ..addOption('firmware', help: 'Path to an ELF to load into memory') + ..addOption('payload', help: 'Path to an ELF to load after firmware') + ..addOption( + 'max-cycles', + help: 'Maximum simulation cycles', + defaultsTo: '0', + ) + ..addFlag( + 'remote-bitbang', + help: 'Expose the core over an OpenOCD remote_bitbang JTAG debug server', + ) + ..addOption( + 'remote-bitbang-port', + help: 'TCP port for the remote_bitbang debug server', + defaultsTo: '44853', + ) + ..addOption( + 'log', + help: 'Log level', + allowed: Level.LEVELS.map((v) => v.name.toLowerCase()).toList(), + ) + ..addFlag( + 'debug-trace', + help: 'Log debug-halt/request/SBA line transitions (remote-bitbang)', + ) + ..addFlag('trace', help: 'Print a per-cycle PC/state trace') + ..addOption( + 'resume-budget', + help: + 'Max core clocks to free-run on a debug RESUME edge before ' + 'falling back to one-clock-per-bit', + defaultsTo: '2000000', + ) + ..addFlag('help', abbr: 'h', help: 'Prints usage'); + + final args = parser.parse(arguments); + + if (args.flag('help')) { + print('Usage: ${path.basename(Platform.script.toFilePath())} [options]'); + print(''); + print('River HDL simulator'); + print(''); + print('Options:'); + print(parser.usage); + return; + } + + Logger.root.onRecord.listen((record) { + print('${record.level.name}: ${record.time}: ${record.message}'); + }); + + if (args.option('log') != null) { + Logger.root.level = Level.LEVELS.firstWhere( + (v) => v.name.toLowerCase() == args.option('log'), + ); + } + + final coreModels = { + 'rc1-n': RiverCoreConfigV1.nano, + 'rc1-mi': RiverCoreConfigV1.micro, + 'rc1-s': RiverCoreConfigV1.small, + 'rc1-m': RiverCoreConfigV1.macro, + }; + + // --core matches the emulator/genip surface (multi-option), but the sim builds + // a single core; if several are given it simulates the first and says so. + final coreList = args.multiOption('core'); + if (coreList.length > 1) { + print( + 'Note: sim builds a single core; using the first (${coreList.first})', + ); + } + final coreModel = coreList.first; + final factory = coreModels[coreModel]; + if (factory == null) { + print('Unknown core model: $coreModel'); + return; + } + + final mxlen = (coreModel == 'rc1-n' || coreModel == 'rc1-mi') + ? RiscVMxlen.rv32 + : RiscVMxlen.rv64; + + final sysclk = HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(int.parse(args.option('clock-freq')!)), + ); + + final coreConfig = factory( + interrupts: [], + mmu: HarborMmuConfig( + mxlen: mxlen, + pagingModes: mxlen == RiscVMxlen.rv64 + ? const [RiscVPagingMode.bare, RiscVPagingMode.sv39] + : const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + clock: sysclk, + resetVector: 0, + ); + + final addrWidth = coreConfig.mxlen.size; + + final clk = SimpleClockGenerator(20).clk; + final reset = Logic(); + + final wbConfig = WishboneConfig( + addressWidth: addrWidth, + dataWidth: coreConfig.mxlen.size, + selWidth: coreConfig.mxlen.size ~/ 8, + ); + + final storage = SparseMemoryStorage( + addrWidth: addrWidth, + dataWidth: coreConfig.mxlen.size, + alignAddress: (addr) => addr, + onInvalidRead: (addr, dataWidth) => + LogicValue.filled(dataWidth, LogicValue.zero), + ); + + final remoteBitbang = args.flag('remote-bitbang'); + final core = RiverCore( + coreConfig, + busConfig: wbConfig, + withDebug: remoteBitbang, + ); + + core.input('clk').srcConnection! <= clk; + // Hart reset = external reset OR the DM's ndmreset (below); the DM resets only + // on external reset, so a debugger can reset the hart without dropping JTAG. + final coreReset = Logic(name: 'coreReset'); + core.input('reset').srcConnection! <= coreReset; + + await core.build(); + + final coreDataBus = core.interface('dataBus'); + final wb = coreDataBus.interface as WishboneInterface; + + final memRead = DataPortInterface(coreConfig.mxlen.size, addrWidth); + final memWrite = DataPortInterface(coreConfig.mxlen.size, addrWidth); + + // ignore: unused_local_variable + final mem = MemoryModel( + clk, + reset, + [wrapWriteForRegisterFile(memWrite)], + [wrapReadForRegisterFile(memRead)], + storage: storage, + ); + + memRead.en <= wb.cyc & wb.stb & ~wb.we; + memRead.addr <= wb.adr; + memWrite.en <= wb.cyc & wb.stb & wb.we; + memWrite.addr <= wb.adr; + memWrite.data <= wb.datMosi; + + final wbAckReg = Logic(name: 'wbAck'); + Sequential(clk, [ + If( + reset, + then: [wbAckReg < 0], + orElse: [ + If( + wb.cyc & wb.stb & ~wbAckReg, + then: [wbAckReg < 1], + orElse: [wbAckReg < 0], + ), + ], + ), + ]); + wb.ack <= wbAckReg; + wb.datMiso <= memRead.data; + + // Optional JTAG debug bridge. The TAP/DTM/DM live in the system clock domain + // and edge-detect TCK, so OpenOCD's remote_bitbang drives the real RTL. SBA is + // serviced against the same storage the core uses. + final tck = Logic(name: 'tck'); + final tms = Logic(name: 'tms'); + final tdi = Logic(name: 'tdi'); + final trstN = Logic(name: 'trst_n'); + final sbaRdata = Logic(name: 'sba_rdata', width: coreConfig.mxlen.size); + final sbaAck = Logic(name: 'sba_ack'); + RiverDebugModule? dbg; + if (remoteBitbang) { + dbg = RiverDebugModule( + clk, + reset, + tck, + tms, + tdi, + trstN, + hartHalted: core.output('debug_halted'), + regRdata: core.output('debug_reg_rdata'), + regReady: core.output('debug_reg_ready'), + sbaRdata: sbaRdata, + sbaAck: sbaAck, + xlen: coreConfig.mxlen.size, + idcode: 0x10000001, + ); + await dbg.build(); + // Close the loop: the Debug Module halts/resumes the core, accesses its + // registers via abstract commands, and the core reports state back. + core.input('debug_halt_req').srcConnection! <= dbg.haltReq; + core.input('debug_resume_req').srcConnection! <= dbg.resumeReq; + core.input('debug_reg_read').srcConnection! <= dbg.regRead; + core.input('debug_reg_write').srcConnection! <= dbg.regWrite; + core.input('debug_reg_addr').srcConnection! <= dbg.regAddr; + core.input('debug_reg_wdata').srcConnection! <= dbg.regWdata; + } + + // ndmreset (dmcontrol bit 1) resets the hart but not the DM. + if (dbg != null) { + coreReset <= reset | dbg.ndmreset; + } else { + coreReset <= reset; + } + + final maskromPath = args.option('maskrom-path'); + final firmwarePath = args.option('firmware'); + final payloadPath = args.option('payload'); + + if (maskromPath == null && firmwarePath == null) { + print('Provide --maskrom-path or --firmware'); + return; + } + + reset.inject(1); + + if (remoteBitbang) { + tck.inject(0); + tms.inject(0); + tdi.inject(0); + trstN.inject(1); + sbaRdata.inject(0); + sbaAck.inject(0); + } + + Simulator.registerAction(20, () { + reset.put(0); + + if (maskromPath != null) { + final elf = Elf.load(File(maskromPath).readAsBytesSync()); + storage.loadMemString(elfToMemString(elf, coreConfig.mxlen.size)); + print( + 'Loaded maskrom: entry 0x${elf.header.entry.toRadixString(16)}, ' + '${elf.programHeaders.where((ph) => ph.type == 1).length} segments', + ); + } + + if (firmwarePath != null) { + final elf = Elf.load(File(firmwarePath).readAsBytesSync()); + storage.loadMemString(elfToMemString(elf, coreConfig.mxlen.size)); + print( + 'Loaded firmware: entry 0x${elf.header.entry.toRadixString(16)}, ' + '${elf.programHeaders.where((ph) => ph.type == 1).length} segments', + ); + } + + if (payloadPath != null) { + final elf = Elf.load(File(payloadPath).readAsBytesSync()); + storage.loadMemString(elfToMemString(elf, coreConfig.mxlen.size)); + print( + 'Loaded payload: entry 0x${elf.header.entry.toRadixString(16)}, ' + '${elf.programHeaders.where((ph) => ph.type == 1).length} segments', + ); + } + }); + + final maxCycles = int.parse(args.option('max-cycles')!); + if (maxCycles > 0) { + // Margin so the run-loop's maxCycles check fires (and dumps regs) before + // the simulator force-ends. + Simulator.setMaxSimTime((maxCycles + 50) * 20); + } + + var cycles = 0; + var lastPc = -1; + var samePc = 0; + + // The remote_bitbang path drives the simulator by hand (below) so it can + // yield to the Dart event loop and service the JTAG socket; `Simulator.run()` + // never yields mid-run and would starve it. The normal path free-runs. + if (!remoteBitbang) { + unawaited(Simulator.run()); + + await clk.nextPosedge; + + while (reset.value.toBool()) { + await clk.nextPosedge; + } + } + + if (remoteBitbang) { + final d = dbg!; + final dataBytes = coreConfig.mxlen.size ~/ 8; + final zeroWord = LogicValue.filled(coreConfig.mxlen.size, LogicValue.zero); + var sbaAcked = false; + + // Service one System Bus Access against the same storage the core uses. + // Sub-word accesses read-modify-write the containing word; reads shift the + // requested bytes to the low end so sbdata0 holds them. + void serviceSba() { + final reqV = d.sbaReq.value; + if (reqV.isValid && reqV.toBool() && !sbaAcked) { + final byteAddr = d.sbaAddr.value.toInt(); + final off = byteAddr % dataBytes; + final addrLv = LogicValue.ofInt(byteAddr - off, addrWidth); + final size = d.sbaSize.value.isValid ? d.sbaSize.value.toInt() : 0; + final nbits = (1 << size) * 8; + final cur = (storage.getData(addrLv) ?? zeroWord).toBigInt(); + if (d.sbaWe.value.toBool()) { + final wdata = d.sbaWdata.value.toBigInt(); + final mask = ((BigInt.one << nbits) - BigInt.one) << (off * 8); + final spliced = (cur & ~mask) | ((wdata << (off * 8)) & mask); + storage.setData( + addrLv, + LogicValue.ofBigInt(spliced, coreConfig.mxlen.size), + ); + } + final rd = + (storage.getData(addrLv) ?? zeroWord).toBigInt() >> (off * 8); + sbaRdata.inject(LogicValue.ofBigInt(rd, coreConfig.mxlen.size)); + sbaAck.inject(1); + sbaAcked = true; + } else { + sbaAck.inject(0); + sbaAcked = false; + } + } + + final port = int.parse(args.option('remote-bitbang-port')!); + + // Optional debug trace (--debug-trace): log transitions of the debug-halt + // and request lines plus SBA activity. + final trace = args.flag('debug-trace'); + int sv(Logic l) => l.value.isValid ? l.value.toInt() : -1; + var pH = -9, pHR = -9, pRR = -9, pReq = -9; + var prevClkHigh = clk.value.isValid && clk.value.toBool(); + + // Drive the simulator on demand from each JTAG transition rather than a + // free-running loop, removing the per-bit Timer latency that made bring-up + // ~1.8s per DMI op. One core clock per JTAG bit (the TAP shifts once per bit + // since TCK transitions once), then keep clocking while a multi-cycle DM FSM + // (abstract command / SBA) is in flight so it settles before OpenOCD reads + // the result. One clock per bit with no drain would starve those FSMs. + // Advances exactly one core clock (one rising edge), servicing SBA on the + // edge. Primitive for both the one-clock-per-bit path and the resume free-run. + Future advanceOneClock() async { + while (Simulator.hasStepsRemaining()) { + await Simulator.tick(); + final cur = clk.value.isValid && clk.value.toBool(); + final rising = cur && !prevClkHigh; + prevClkHigh = cur; + if (!rising) continue; + if (!reset.value.toBool()) { + serviceSba(); + cycles++; + if (trace) { + final h = sv(core.output('debug_halted')); + final hr = sv(d.haltReq); + final rr = sv(d.resumeReq); + final rq = sv(d.sbaReq); + if (h != pH || hr != pHR || rr != pRR || rq != pReq) { + print( + '[trace cyc=$cycles] halted=$h haltReq=$hr ' + 'resumeReq=$rr sbaReq=$rq', + ); + pH = h; + pHR = hr; + pRR = rr; + pReq = rq; + } + } + } + return; + } + } + + bool coreHalted() { + final h = core.output('debug_halted').value; + return h.isValid && h.toBool(); + } + + // Backstop for a resumed program that never self-halts (no ebreak): cap the + // free-run so it falls back to one-clock-per-bit instead of wedging. Real + // firmware self-halts long before this; override via --resume-budget. + final resumeBudget = int.parse(args.option('resume-budget')!); + + // One core clock per JTAG bit, but on a resume edge free-run the core to its + // self-halt so a resumed program executes instead of starving at OpenOCD's + // one-clock-per-poll cadence. + final pump = ResumePump( + advanceOneClock: advanceOneClock, + coreHalted: coreHalted, + resumeBudget: resumeBudget, + // The core runs after reset; the first real halt makes the next resume an + // observable edge. + initiallyHalted: false, + ); + + await startJtagRemote( + tck: tck, + tms: tms, + tdi: tdi, + tdo: d.tdo, + port: port, + onTick: pump.pump, + ); + print( + 'remote_bitbang debug server listening on port $port ' + '(core $coreModel)', + ); + // Flush so external scripts (Heimdall/OpenOCD launchers) can detect that + // the server is ready; piped stdout is otherwise block-buffered. + await stdout.flush(); + + // The JTAG server runs in the background and drives the simulator via + // pumpOneClock on each transition; block here so the process stays alive + // until the harness or OpenOCD terminates it. + await Completer().future; + } + + while (true) { + await clk.nextPosedge; + cycles++; + + if (args.flag('trace')) { + String h(LogicValue v) => + v.isValid ? '0x${v.toInt().toRadixString(16)}' : 'x'; + print( + 'cyc=$cycles pc=${h(core.pipeline.nextPc.value)} ' + 'done=${core.pipeline.done.value.toBool()} ' + 'adr=${h(wb.adr.value)} stb=${wb.stb.value.toBool()} ' + 'we=${wb.we.value.toBool()} miso=${h(memRead.data.value)}', + ); + } + + final pc = core.pipeline.nextPc.value; + if (pc.isValid) { + final pcInt = pc.toInt(); + // A stable nextPc for many cycles means a self-loop (program done). + // Requiring several identical cycles avoids pipeline-warmup false halts; + // ignore pc==0 which appears as a transient glitch during pipeline bubbles. + if (pcInt == lastPc && pcInt != 0) { + samePc++; + if (samePc >= 16) { + print( + 'Halted at PC=0x${pcInt.toRadixString(16)} after $cycles cycles', + ); + break; + } + } else { + samePc = 0; + lastPc = pcInt; + } + } + + if (maxCycles > 0 && cycles >= maxCycles) { + print( + 'Reached max cycles ($maxCycles) at PC=0x${lastPc.toRadixString(16)}', + ); + break; + } + } + + // Dump the integer register file (sim/flop model) for verification. + final buf = StringBuffer(); + for (var i = 1; i < 32; i++) { + final v = core.regs.getData(LogicValue.ofInt(i, 5)); + if (v != null && v.isValid && v.toInt() != 0) { + buf.write(' x$i=0x${v.toInt().toRadixString(16)}'); + } + } + print('regs:$buf'); + + await Simulator.endSimulation(); + await Simulator.simulationEnded; + + print('Simulation complete: $cycles cycles'); + + exit(0); +} diff --git a/packages/river_hdl/lib/river_hdl.dart b/packages/river_hdl/lib/river_hdl.dart index f12e301..0f810cf 100644 --- a/packages/river_hdl/lib/river_hdl.dart +++ b/packages/river_hdl/lib/river_hdl.dart @@ -1,15 +1,36 @@ library; +export 'src/compat.dart'; +export 'src/data_port.dart'; export 'src/core/csr.dart'; +export 'src/core/debug.dart'; +export 'src/core/debug_subsystem.dart'; +export 'src/core/jtag_bscan_tunnel.dart'; +export 'src/core/sba_wishbone.dart'; +export 'src/core/debug_pump.dart'; export 'src/core/decoder.dart'; export 'src/core/exec.dart'; export 'src/core/fetcher.dart'; +export 'src/core/fu_alu.dart'; +export 'src/core/microcode_alu.dart'; +export 'src/core/fu_branch.dart'; +export 'src/core/fu_csr.dart'; +export 'src/core/fu_mem.dart'; export 'src/core/int.dart'; +export 'src/core/issue.dart'; export 'src/core/mmu.dart'; +export 'src/core/compressed_fetch_buffer.dart'; +export 'src/core/instruction_aligner.dart'; export 'src/core/pipeline.dart'; +export 'src/core/prefetch_fetcher.dart'; +export 'src/core/pipelined_fetcher.dart'; +export 'src/core/pipelined_fetch_memory.dart'; +export 'src/core/rename.dart'; +export 'src/core/rob.dart'; +export 'src/core/stages.dart'; export 'src/core.dart'; -export 'src/dev.dart'; -export 'src/devices.dart'; - +export 'src/genip.dart'; +export 'src/microcode_rom.dart'; export 'src/memory/port.dart'; export 'src/soc.dart'; +export 'src/usb_dfu_subsystem.dart'; diff --git a/packages/river_hdl/lib/src/boards.dart b/packages/river_hdl/lib/src/boards.dart new file mode 100644 index 0000000..30eb313 --- /dev/null +++ b/packages/river_hdl/lib/src/boards.dart @@ -0,0 +1,547 @@ +import 'package:harbor/harbor.dart'; + +/// Board-level DDR definitions: the pad constraint table and part +/// configuration for each supported board. +/// +/// A `dram` memory region names its board (`addr:size:dram:board`), and +/// genip merges that board's pad sites into the FPGA pin map and picks the +/// matching [HarborDdrConfig]. Pin map values are `SITE [IO_TYPE] +/// [ATTR=VAL...]`, the format [HarborFpgaTarget] renders into constraints. +class DdrBoard { + /// The DRAM part/geometry configuration. + final HarborDdrConfig config; + + /// Pad constraints, keyed by the controller's pad port names (vector + /// ports use `port[index]` comp naming, matching synthesis output). + /// + /// The DQS entries here are the DLL-ON style: a single TRUE-DIFFERENTIAL pad + /// (`sdram_dqs[*]` SSTL135D_I on the LDQS _p ball), so nextpnr derives the + /// LDQSN _n rail and there is NO `sdram_dqs_n`. [pinsFor] rewrites these for + /// the DLL-OFF build (the explicit pseudo-differential pair). + final Map pins; + + /// DLL-OFF DQS override: the EXPLICIT pseudo-differential `sdram_dqs_n[*]` _n + /// pad sites (single-ended SSTL135_I). When DLL-off the controller drives an + /// explicit complement ODDR (the hardware-proven 48 MHz write strobe, like + /// CK#), so the _n ball needs its own constraint AND `sdram_dqs[*]` drops to + /// single-ended SSTL135_I (see [pinsFor]). Empty for boards with no _n ball. + final Map dqsComplementPins; + + /// Whether the controller exposes the opt-in CPU read-training MMIO window + /// (see [HarborDdrController.trainableRead]). DLL-off DDR3 boards want it so + /// the FSBL can sweep the read tap per board; the proven static path stays + /// the default when false. + final bool trainableRead; + + /// Whether the controller must hardware write-verify-retry every array write + /// (read back, re-issue until it matches, bounded). The openXC7 Arty x8 path + /// needs it: no output ODELAY and the MMCM 90-degree write-launch phase is + /// inert under openXC7, so the DQ-vs-DQS write eye cannot be centred (reads are + /// clean). False for boards whose write eye closes on its own (ECP5/x16). + final bool writeVerify; + + /// Per-board DDR tuning defaults, forwarded to the controller when a memory + /// region does not override them (see genip's effective-value merge). Null + /// leaves the genip global default in force. cmdSlot/wrShift/wrBeat/window + /// are the ddr3Fast (Xilinx) write/read-window knobs; trainable/readTap/ + /// readSlack/readRetry apply to both PHY paths. + final int? cmdSlot; + final int? wrShift; + final int? wrBeat; + final bool? trainable; + final int? readTap; + final int? readSlack; + final int? readRetry; + final int? window; + + const DdrBoard({ + required this.config, + required this.pins, + this.dqsComplementPins = const {}, + this.trainableRead = false, + this.writeVerify = false, + this.cmdSlot, + this.wrShift, + this.wrBeat, + this.trainable, + this.readTap, + this.readSlack, + this.readRetry, + this.window, + }); + + /// The pin/constraint table for a given DLL engagement. DLL-ON returns [pins] + /// unchanged (the single SSTL135D_I diff DQS pad nextpnr derives _n from). + /// DLL-OFF rewrites every `sdram_dqs[*]` from SSTL135D_I to single-ended + /// SSTL135_I (keeping its site + extra attrs) and merges in + /// [dqsComplementPins] (the explicit `sdram_dqs_n[*]` the PHY now drives), + /// matching the explicit pseudo-differential DQS the controller builds DLL-off. + Map pinsFor({required bool dllOn}) { + if (dllOn || dqsComplementPins.isEmpty) return pins; + final out = {}; + for (final e in pins.entries) { + if (e.key.startsWith('sdram_dqs[')) { + // Drop the differential IO-type to single-ended; keep site + attrs. + out[e.key] = e.value.replaceFirst('SSTL135D_I', 'SSTL135_I'); + } else { + out[e.key] = e.value; + } + } + out.addAll(dqsComplementPins); + return out; + } + + /// Boards by name. `dram` memory regions must reference one of these. + /// The OrangeCrab revisions differ materially: r0.1 moves CKE (D6) and + /// RESET# (B1) and shuffles the address lines, so an r0.2 map on an r0.1 + /// board leaves the part's CKE/RESET# floating (eternally silent DRAM). + static const byName = { + 'orangecrab': _orangeCrab, + 'orangecrab-r01': _orangeCrabR01, + 'arty-s7': _artyS7, + 'arty-s7-x8': _artyS7x8, + 'arty-s7-x8-hi': _artyS7x8hi, + }; + + /// Digilent Arty S7-50: Micron MT41K128M16 DDR3L (256MB, 16-bit), sites from + /// the litex/migen `arty_s7` platform. Xilinx xc7s50-csga324. The [DdrPhyXilinx] + /// DLL-off PHY drives an explicit pseudo-differential complement, so CK/DQS are + /// single-ended SSTL135 on both _p and _n balls (dqs_n via [dqsComplementPins]); + /// the litex true-diff DIFF_SSTL135 is for a hard OBUFDS pair this soft PHY does + /// not build. 14 row lines (a[13:0]) => rowWidth 14 (part is 16K x 1K x 8). The + /// XDC renderer emits only PACKAGE_PIN + IOSTANDARD, so migen's IN_TERM / + /// SLEW attrs are dropped for now. + static const _artyS7 = DdrBoard( + config: HarborDdrConfig( + type: HarborDdrType.ddr3l, + size: 256 * 1024 * 1024, + dataWidth: 16, + frequency: 333333333, + banks: 8, + rowWidth: 14, + colWidth: 10, + casLatency: 6, + ), + pins: { + 'sdram_ck': 'R5 SSTL135', + 'sdram_ck_n': 'T4 SSTL135', + 'sdram_cke': 'T2 SSTL135', + 'sdram_cs_n': 'R3 SSTL135', + 'sdram_ras_n': 'U1 SSTL135', + 'sdram_cas_n': 'V3 SSTL135', + 'sdram_we_n': 'P7 SSTL135', + 'sdram_odt': 'P5 SSTL135', + 'sdram_reset_n': 'J6 SSTL135', + 'sdram_ba[0]': 'V5 SSTL135', + 'sdram_ba[1]': 'T1 SSTL135', + 'sdram_ba[2]': 'U3 SSTL135', + 'sdram_addr[0]': 'U2 SSTL135', + 'sdram_addr[1]': 'R4 SSTL135', + 'sdram_addr[2]': 'V2 SSTL135', + 'sdram_addr[3]': 'V4 SSTL135', + 'sdram_addr[4]': 'T3 SSTL135', + 'sdram_addr[5]': 'R7 SSTL135', + 'sdram_addr[6]': 'V6 SSTL135', + 'sdram_addr[7]': 'T6 SSTL135', + 'sdram_addr[8]': 'U7 SSTL135', + 'sdram_addr[9]': 'V7 SSTL135', + 'sdram_addr[10]': 'P6 SSTL135', + 'sdram_addr[11]': 'T5 SSTL135', + 'sdram_addr[12]': 'R6 SSTL135', + 'sdram_addr[13]': 'U6 SSTL135', + // Lane 0 = DM0/DQS0 (K4/K1,L1) + DQ[0..7]; lane 1 = DM1/DQS1 (M3/N3,N2) + // + DQ[8..15]. Sites in litex order. + 'sdram_dm[0]': 'K4 SSTL135', + 'sdram_dm[1]': 'M3 SSTL135', + 'sdram_dq[0]': 'K2 SSTL135', + 'sdram_dq[1]': 'K3 SSTL135', + 'sdram_dq[2]': 'L4 SSTL135', + 'sdram_dq[3]': 'M6 SSTL135', + 'sdram_dq[4]': 'K6 SSTL135', + 'sdram_dq[5]': 'M4 SSTL135', + 'sdram_dq[6]': 'L5 SSTL135', + 'sdram_dq[7]': 'L6 SSTL135', + 'sdram_dq[8]': 'N4 SSTL135', + 'sdram_dq[9]': 'R1 SSTL135', + 'sdram_dq[10]': 'N1 SSTL135', + 'sdram_dq[11]': 'N5 SSTL135', + 'sdram_dq[12]': 'M2 SSTL135', + 'sdram_dq[13]': 'P1 SSTL135', + 'sdram_dq[14]': 'M1 SSTL135', + 'sdram_dq[15]': 'P2 SSTL135', + // DQS _p balls (K1/N3) AND the explicit _n complement balls (L1/N2). The + // DdrPhyXilinx PHY always drives both rails, so both are constrained here in + // `pins` rather than the dllOff-only dqsComplementPins (else the dllOn path + // drops the _n pads and PnR fails "no IOSTANDARD"). + 'sdram_dqs[0]': 'K1 SSTL135', + 'sdram_dqs[1]': 'N3 SSTL135', + 'sdram_dqs_n[0]': 'L1 SSTL135', + 'sdram_dqs_n[1]': 'N2 SSTL135', + }, + ); + + /// Arty S7-50 DDR3 as x8 (low byte-lane only). The MT41K128M16 is physically + /// x16, but DDR3 byte lanes capture on independent per-byte DQS, so the low lane + /// (DQ[7:0]/DQS0/DM0) behaves as a standalone x8 DDR3 of half the capacity + /// (128 MB): same geometry, 1 byte/column. Working-DDR path while the x16 + /// high-lane write alignment (per-lane write-leveling) is under debug; the low + /// lane reads and writes cleanly at cmdSlot=2/WRSHIFT=-1. The high-lane DRAM pins + /// float. dataWidth=8 builds one byte lane (dmLanes=1), so only DQS0/DM0 drive. + static const _artyS7x8 = DdrBoard( + config: HarborDdrConfig( + type: HarborDdrType.ddr3l, + size: 128 * 1024 * 1024, + dataWidth: 8, + frequency: 333333333, + banks: 8, + rowWidth: 14, + colWidth: 10, + casLatency: 6, + ), + // x8 write eye is marginal-but-recoverable on openXC7 (no output ODELAY, MMCM + // 90-degree phase inert): reads clean, a re-driven write always lands, so + // write-verify-retry makes CPU writes correct. + writeVerify: true, + // HW-proven x8 DDR3 tuning, baked in so a plain build needs no per-region params. + cmdSlot: 2, + wrShift: -1, + wrBeat: 0, + trainable: true, + readRetry: 6, + window: 5, + pins: { + 'sdram_ck': 'R5 SSTL135', + 'sdram_ck_n': 'T4 SSTL135', + 'sdram_cke': 'T2 SSTL135', + 'sdram_cs_n': 'R3 SSTL135', + 'sdram_ras_n': 'U1 SSTL135', + 'sdram_cas_n': 'V3 SSTL135', + 'sdram_we_n': 'P7 SSTL135', + 'sdram_odt': 'P5 SSTL135', + 'sdram_reset_n': 'J6 SSTL135', + 'sdram_ba[0]': 'V5 SSTL135', + 'sdram_ba[1]': 'T1 SSTL135', + 'sdram_ba[2]': 'U3 SSTL135', + 'sdram_addr[0]': 'U2 SSTL135', + 'sdram_addr[1]': 'R4 SSTL135', + 'sdram_addr[2]': 'V2 SSTL135', + 'sdram_addr[3]': 'V4 SSTL135', + 'sdram_addr[4]': 'T3 SSTL135', + 'sdram_addr[5]': 'R7 SSTL135', + 'sdram_addr[6]': 'V6 SSTL135', + 'sdram_addr[7]': 'T6 SSTL135', + 'sdram_addr[8]': 'U7 SSTL135', + 'sdram_addr[9]': 'V7 SSTL135', + 'sdram_addr[10]': 'P6 SSTL135', + 'sdram_addr[11]': 'T5 SSTL135', + 'sdram_addr[12]': 'R6 SSTL135', + 'sdram_addr[13]': 'U6 SSTL135', + // Low byte lane only: DM0/DQS0 + DQ[0..7]; the high lane is omitted so those + // DRAM balls float. With a single byte lane (dmLanes=1) the DM/DQS/DQS# ports + // are scalar (sdram_dm, not sdram_dm[0]); only DQ stays an indexed vector. + 'sdram_dm': 'K4 SSTL135', + 'sdram_dq[0]': 'K2 SSTL135', + 'sdram_dq[1]': 'K3 SSTL135', + 'sdram_dq[2]': 'L4 SSTL135', + 'sdram_dq[3]': 'M6 SSTL135', + 'sdram_dq[4]': 'K6 SSTL135', + 'sdram_dq[5]': 'M4 SSTL135', + 'sdram_dq[6]': 'L5 SSTL135', + 'sdram_dq[7]': 'L6 SSTL135', + 'sdram_dqs': 'K1 SSTL135', + 'sdram_dqs_n': 'L1 SSTL135', + }, + ); + + /// Diagnostic: x8 on the high physical byte lane (DQ[15:8]/DQS1/DM1). Identical + /// to [_artyS7x8] but the single logical lane maps to the upper-byte balls (litex + /// arty_s7 lane-1 sites). Isolates the x16 lane1 write bug: if x8-on-lane1 works + /// the lane1 nets are fine and the x16 failure is a dual-lane RTL bug; if it + /// fails, lane1 is electrical. + static const _artyS7x8hi = DdrBoard( + config: HarborDdrConfig( + type: HarborDdrType.ddr3l, + size: 128 * 1024 * 1024, + dataWidth: 8, + frequency: 333333333, + banks: 8, + rowWidth: 14, + colWidth: 10, + casLatency: 6, + ), + writeVerify: true, + cmdSlot: 2, + wrShift: -1, + wrBeat: 0, + trainable: true, + readRetry: 6, + window: 5, + pins: { + 'sdram_ck': 'R5 SSTL135', + 'sdram_ck_n': 'T4 SSTL135', + 'sdram_cke': 'T2 SSTL135', + 'sdram_cs_n': 'R3 SSTL135', + 'sdram_ras_n': 'U1 SSTL135', + 'sdram_cas_n': 'V3 SSTL135', + 'sdram_we_n': 'P7 SSTL135', + 'sdram_odt': 'P5 SSTL135', + 'sdram_reset_n': 'J6 SSTL135', + 'sdram_ba[0]': 'V5 SSTL135', + 'sdram_ba[1]': 'T1 SSTL135', + 'sdram_ba[2]': 'U3 SSTL135', + 'sdram_addr[0]': 'U2 SSTL135', + 'sdram_addr[1]': 'R4 SSTL135', + 'sdram_addr[2]': 'V2 SSTL135', + 'sdram_addr[3]': 'V4 SSTL135', + 'sdram_addr[4]': 'T3 SSTL135', + 'sdram_addr[5]': 'R7 SSTL135', + 'sdram_addr[6]': 'V6 SSTL135', + 'sdram_addr[7]': 'T6 SSTL135', + 'sdram_addr[8]': 'U7 SSTL135', + 'sdram_addr[9]': 'V7 SSTL135', + 'sdram_addr[10]': 'P6 SSTL135', + 'sdram_addr[11]': 'T5 SSTL135', + 'sdram_addr[12]': 'R6 SSTL135', + 'sdram_addr[13]': 'U6 SSTL135', + // High byte lane: single logical lane maps to the upper-byte balls + // (physical DQ[8..15]/DQS1/DM1). Low-byte balls float. + 'sdram_dm': 'M3 SSTL135', + 'sdram_dq[0]': 'N4 SSTL135', + 'sdram_dq[1]': 'R1 SSTL135', + 'sdram_dq[2]': 'N1 SSTL135', + 'sdram_dq[3]': 'N5 SSTL135', + 'sdram_dq[4]': 'M2 SSTL135', + 'sdram_dq[5]': 'P1 SSTL135', + 'sdram_dq[6]': 'M1 SSTL135', + 'sdram_dq[7]': 'P2 SSTL135', + 'sdram_dqs': 'N3 SSTL135', + 'sdram_dqs_n': 'N2 SSTL135', + }, + ); + + /// OrangeCrab r0.2: MT41K64M16 DDR3L, sites from the litex-boards gsd_orangecrab + /// platform; CK#/DQS# complement balls from the prjtrellis LFE5U-25F/CSFBGA285 + /// pair database (J18/K18, B15/A16, G18/H17). CK# stays single-ended SSTL135 + /// (RTL drives the complement explicitly, since nextpnr does not build the B + /// side of "D"-suffixed OUTPUT types). DQS is the exception: a true differential + /// pad (SSTL135D_I on the LDQS _p ball B15/G18) whose LDQSN _n partner (A16/H17) + /// nextpnr drives as the complement for a clean DQSBUFM.DQSI read strobe. + static const _orangeCrab = DdrBoard( + // Static DELAYG read path (trainableRead=false) so the bitstream fits the 25F + // alongside the MMU (the runtime DELAYF training controller will not route). + // The read tap is swept at build time via readTaps (RIVER_DDR_READTAPS env, + // default 40) to centre the eye across a few static bitstreams. + config: HarborDdrConfig.orangeCrab(), + pins: { + 'sdram_ck': 'J18 SSTL135_I SLEWRATE=FAST', + 'sdram_ck_n': 'K18 SSTL135_I SLEWRATE=FAST', + 'sdram_cke': 'D18 SSTL135_I SLEWRATE=FAST', + 'sdram_cs_n': 'A12 SSTL135_I SLEWRATE=FAST', + 'sdram_ras_n': 'C12 SSTL135_I SLEWRATE=FAST', + 'sdram_cas_n': 'D13 SSTL135_I SLEWRATE=FAST', + 'sdram_we_n': 'B12 SSTL135_I SLEWRATE=FAST', + 'sdram_odt': 'C13 SSTL135_I SLEWRATE=FAST', + 'sdram_reset_n': 'L18 SSTL135_I SLEWRATE=FAST', + 'sdram_ba[0]': 'D6 SSTL135_I SLEWRATE=FAST', + 'sdram_ba[1]': 'B7 SSTL135_I SLEWRATE=FAST', + 'sdram_ba[2]': 'A6 SSTL135_I SLEWRATE=FAST', + 'sdram_addr[0]': 'C4 SSTL135_I SLEWRATE=FAST', + 'sdram_addr[1]': 'D2 SSTL135_I SLEWRATE=FAST', + 'sdram_addr[2]': 'D3 SSTL135_I SLEWRATE=FAST', + 'sdram_addr[3]': 'A3 SSTL135_I SLEWRATE=FAST', + 'sdram_addr[4]': 'A4 SSTL135_I SLEWRATE=FAST', + 'sdram_addr[5]': 'D4 SSTL135_I SLEWRATE=FAST', + 'sdram_addr[6]': 'C3 SSTL135_I SLEWRATE=FAST', + 'sdram_addr[7]': 'B2 SSTL135_I SLEWRATE=FAST', + 'sdram_addr[8]': 'B1 SSTL135_I SLEWRATE=FAST', + 'sdram_addr[9]': 'D1 SSTL135_I SLEWRATE=FAST', + 'sdram_addr[10]': 'A7 SSTL135_I SLEWRATE=FAST', + 'sdram_addr[11]': 'C2 SSTL135_I SLEWRATE=FAST', + 'sdram_addr[12]': 'B6 SSTL135_I SLEWRATE=FAST', + 'sdram_addr[13]': 'C1 SSTL135_I SLEWRATE=FAST', + 'sdram_addr[14]': 'A2 SSTL135_I SLEWRATE=FAST', + // DM sites in litex order so each lane's DM shares its lane's ECP5 DQS group: + // D16 in LDQ20 with DQ[0..7]+DQS[0] (lane 0), G16 in LDQ32 with DQ[8..15]+ + // DQS[1] (lane 1). nextpnr enforces DQS-group membership via the DQSBUFM + // path, so a swapped order fails packing with a DQS-group mismatch. + 'sdram_dm[0]': 'D16 SSTL135_I SLEWRATE=FAST', + 'sdram_dm[1]': 'G16 SSTL135_I SLEWRATE=FAST', + 'sdram_dq[0]': 'C17 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + 'sdram_dq[1]': 'D15 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + 'sdram_dq[2]': 'B17 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + 'sdram_dq[3]': 'C16 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + 'sdram_dq[4]': 'A15 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + 'sdram_dq[5]': 'B13 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + 'sdram_dq[6]': 'A17 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + 'sdram_dq[7]': 'A13 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + 'sdram_dq[8]': 'F17 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + 'sdram_dq[9]': 'F16 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + 'sdram_dq[10]': 'G15 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + 'sdram_dq[11]': 'F15 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + 'sdram_dq[12]': 'J16 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + 'sdram_dq[13]': 'C18 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + 'sdram_dq[14]': 'H16 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + 'sdram_dq[15]': 'F18 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + // DQS is a true differential strobe: SSTL135D_I on the LDQS (_p) ball + // (B15/G18, PIOA of DQS group 20/32) makes nextpnr-ecp5 drive/receive the + // LDQSN (_n) partner (A16/H17, PIOB) as the complement, so DQSBUFM.DQSI sees + // a clean differential read strobe. The _n ball is the implicit complement, + // so it gets no separate constraint. Keep TERMINATION=75 on the strobe. + 'sdram_dqs[0]': 'B15 SSTL135D_I SLEWRATE=FAST TERMINATION=75', + 'sdram_dqs[1]': 'G18 SSTL135D_I SLEWRATE=FAST TERMINATION=75', + }, + // DLL-OFF explicit DQS# complement: the LDQSN _n balls (A16/H17), single- + // ended SSTL135_I, driven by the PHY's complement ODDR (the hardware-proven + // 48 MHz write strobe). [pinsFor] adds these and drops sdram_dqs[*] to + // SSTL135_I when DLL-off; DLL-on the single SSTL135D_I diff pad is used. + dqsComplementPins: { + 'sdram_dqs_n[0]': 'A16 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + 'sdram_dqs_n[1]': 'H17 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + }, + ); + + /// OrangeCrab r0.1: same DRAM part and same DQ/DQS/CK/DM/command balls + /// as r0.2, but CKE at D6, RESET# at B1, ba[0] at B6, and a 13-line + /// reshuffled address bus (sites from the litex-boards gsd_orangecrab + /// _io_r0_1 list). rowWidth drops to 13 to match the routed lines (a 1Gb + /// part needs no more). + static const _orangeCrabR01 = DdrBoard( + config: HarborDdrConfig( + type: HarborDdrType.ddr3, + size: 128 * 1024 * 1024, + dataWidth: 16, + frequency: 400000000, + banks: 8, + rowWidth: 13, + colWidth: 10, + casLatency: 6, + ), + pins: { + 'sdram_ck': 'J18 SSTL135_I SLEWRATE=FAST', + 'sdram_ck_n': 'K18 SSTL135_I SLEWRATE=FAST', + 'sdram_cke': 'D6 SSTL135_I SLEWRATE=FAST', + 'sdram_cs_n': 'A12 SSTL135_I SLEWRATE=FAST', + 'sdram_ras_n': 'C12 SSTL135_I SLEWRATE=FAST', + 'sdram_cas_n': 'D13 SSTL135_I SLEWRATE=FAST', + 'sdram_we_n': 'B12 SSTL135_I SLEWRATE=FAST', + 'sdram_odt': 'C13 SSTL135_I SLEWRATE=FAST', + 'sdram_reset_n': 'B1 SSTL135_I SLEWRATE=FAST', + 'sdram_ba[0]': 'B6 SSTL135_I SLEWRATE=FAST', + 'sdram_ba[1]': 'B7 SSTL135_I SLEWRATE=FAST', + 'sdram_ba[2]': 'A6 SSTL135_I SLEWRATE=FAST', + 'sdram_addr[0]': 'A4 SSTL135_I SLEWRATE=FAST', + 'sdram_addr[1]': 'D2 SSTL135_I SLEWRATE=FAST', + 'sdram_addr[2]': 'C3 SSTL135_I SLEWRATE=FAST', + 'sdram_addr[3]': 'C7 SSTL135_I SLEWRATE=FAST', + 'sdram_addr[4]': 'D3 SSTL135_I SLEWRATE=FAST', + 'sdram_addr[5]': 'D4 SSTL135_I SLEWRATE=FAST', + 'sdram_addr[6]': 'D1 SSTL135_I SLEWRATE=FAST', + 'sdram_addr[7]': 'B2 SSTL135_I SLEWRATE=FAST', + 'sdram_addr[8]': 'C1 SSTL135_I SLEWRATE=FAST', + 'sdram_addr[9]': 'A2 SSTL135_I SLEWRATE=FAST', + 'sdram_addr[10]': 'A7 SSTL135_I SLEWRATE=FAST', + 'sdram_addr[11]': 'C2 SSTL135_I SLEWRATE=FAST', + 'sdram_addr[12]': 'C4 SSTL135_I SLEWRATE=FAST', + // DM in litex order so each lane's DM shares its lane's DQS group + // (D16=LDQ20/lane0, G16=LDQ32/lane1), same balls as r0.2. + 'sdram_dm[0]': 'D16 SSTL135_I SLEWRATE=FAST', + 'sdram_dm[1]': 'G16 SSTL135_I SLEWRATE=FAST', + 'sdram_dq[0]': 'C17 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + 'sdram_dq[1]': 'D15 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + 'sdram_dq[2]': 'B17 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + 'sdram_dq[3]': 'C16 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + 'sdram_dq[4]': 'A15 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + 'sdram_dq[5]': 'B13 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + 'sdram_dq[6]': 'A17 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + 'sdram_dq[7]': 'A13 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + 'sdram_dq[8]': 'F17 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + 'sdram_dq[9]': 'F16 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + 'sdram_dq[10]': 'G15 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + 'sdram_dq[11]': 'F15 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + 'sdram_dq[12]': 'J16 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + 'sdram_dq[13]': 'C18 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + 'sdram_dq[14]': 'H16 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + 'sdram_dq[15]': 'F18 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + // TRUE DIFFERENTIAL DQS (see the r0.2 block): SSTL135D_I on the LDQS (_p) + // ball pairs the LDQSN (_n) partner automatically, so no _n constraint. + 'sdram_dqs[0]': 'B15 SSTL135D_I SLEWRATE=FAST TERMINATION=75', + 'sdram_dqs[1]': 'G18 SSTL135D_I SLEWRATE=FAST TERMINATION=75', + }, + // DLL-OFF explicit DQS# complement (same LDQSN _n balls as r0.2: A16/H17). + dqsComplementPins: { + 'sdram_dqs_n[0]': 'A16 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + 'sdram_dqs_n[1]': 'H17 SSTL135_I SLEWRATE=FAST TERMINATION=OFF', + }, + ); + + /// The controller pad ports a `dram` region exposes at the SoC top. + static const padPorts = [ + 'sdram_ck', + 'sdram_ck_n', + 'sdram_cke', + 'sdram_cs_n', + 'sdram_ras_n', + 'sdram_cas_n', + 'sdram_we_n', + 'sdram_ba', + 'sdram_addr', + 'sdram_dm', + 'sdram_dq', + // DQS is a TRUE DIFFERENTIAL pad (SSTL135D_I on the LDQS _p ball): the + // LDQSN _n complement is generated by nextpnr, so there is no sdram_dqs_n + // top-level port to expose. + 'sdram_dqs', + 'sdram_odt', + 'sdram_reset_n', + ]; +} + +/// On-board SPI NOR flash pin table for a `flash:` memory region. The +/// flash CLOCK is intentionally absent: on the ECP5 it is driven through the +/// USRMCLK macro (no I/O pad), so genip wires spi_clk into USRMCLK and only the +/// chip-select and data lines are real pads. +class FlashBoard { + /// Pad constraints keyed by the controller's exposed pad port names (vector + /// ports use `port[index]`, matching synthesis output). + final Map pins; + + const FlashBoard({required this.pins}); + + static const byName = { + 'orangecrab': _orangeCrab, + 'orangecrab-r01': _orangeCrab, // identical quad-SPI pinout on both revs + 'arty-s7': _artyS7, + }; + + /// Digilent Arty S7-50 (xc7s50csga324) on-board Spansion S25FL128 (16MB) quad + /// SPI config flash. The CCLK is driven through STARTUPE2 (USRCCLKO -> CCLK, no + /// I/O pad), so only CS + DQ[0..3] are real pads. Balls from the Digilent + /// Arty-S7-50 master XDC "Quad SPI Flash" section. + /// VERIFY these against the board's master XDC before flashing hardware. + static const _artyS7 = FlashBoard( + pins: { + 'spi_cs_n': 'M13 LVCMOS33', + 'spi_io[0]': 'K17 LVCMOS33', // IO0 / MOSI + 'spi_io[1]': 'K18 LVCMOS33', // IO1 / MISO + 'spi_io[2]': 'L14 LVCMOS33', // IO2 / WP# + 'spi_io[3]': 'M15 LVCMOS33', // IO3 / HOLD# + }, + ); + + /// OrangeCrab GD25Q128 (16MB) quad SPI flash, from the litex-boards + /// gsd_orangecrab platform (CS_N=U17, DQ=U18/T18/R18/N18, clock via USRMCLK). + /// IO0/MOSI=U18, IO1/MISO=T18, IO2/WP=R18, IO3/HOLD=N18. + static const _orangeCrab = FlashBoard( + pins: { + 'spi_cs_n': 'U17 LVCMOS33', + 'spi_io[0]': 'U18 LVCMOS33', + 'spi_io[1]': 'T18 LVCMOS33', + 'spi_io[2]': 'R18 LVCMOS33', + 'spi_io[3]': 'N18 LVCMOS33', + }, + ); + + /// The pad ports exposed at the top for a board-qualified flash region (the + /// clock is absorbed by USRMCLK, so it is not a pad). + static const padPorts = ['spi_cs_n', 'spi_io']; +} diff --git a/packages/river_hdl/lib/src/compat.dart b/packages/river_hdl/lib/src/compat.dart new file mode 100644 index 0000000..be5bae9 --- /dev/null +++ b/packages/river_hdl/lib/src/compat.dart @@ -0,0 +1,778 @@ +/// Compatibility layer for migrating from old riscv package types +/// to Harbor equivalents. +library; + +import 'package:harbor/harbor.dart' hide PrivilegeMode; +import 'package:river/river.dart' show Trap, Register, RiscVMxlen; +import 'microcode_rom.dart' show MicroOpEncoding, BitRange, BitStruct; + +/// Compatibility wrapper for RiscVMicroOp with encoding fields. +abstract class MicroOp { + /// Bit range of the funct field in the micro-op encoding. + static const BitRange functRange = BitRange(0, 4); +} + +// Funct constants for each micro-op type, matching MicrocodeRom._mopFunct +abstract class ReadCsrMicroOp { + static const int funct = 22; +} + +abstract class WriteCsrMicroOp { + static const int funct = 1; +} + +abstract class ReadRegisterMicroOp { + static const int funct = 2; +} + +abstract class WriteRegisterMicroOp { + static const int funct = 3; +} + +abstract class AluMicroOp { + static const int funct = 5; +} + +abstract class UpdatePCMicroOp { + static const int funct = 7; +} + +abstract class MemLoadMicroOp { + static const int funct = 8; +} + +abstract class MemStoreMicroOp { + static const int funct = 9; +} + +abstract class TrapMicroOp { + static const int funct = 10; +} + +abstract class ReturnMicroOp { + static const int funct = 14; +} + +// wfi's wait micro-op. funct mirrors MicrocodeRom._mopFunct (20). A real funct, +// not the 0 catch-all (which is the dynamic interpreter's empty padding case). +abstract class WaitForInterruptMicroOp { + static const int funct = 20; +} + +abstract class BranchIfMicroOp { + static const int funct = 6; +} + +abstract class WriteLinkRegisterMicroOp { + static const int funct = 15; +} + +abstract class FenceMicroOp { + static const int funct = 13; +} + +abstract class TlbFenceMicroOp { + static const int funct = 11; +} + +abstract class TlbInvalidateMicroOp { + static const int funct = 12; +} + +abstract class InterruptHoldMicroOp { + static const int funct = 16; +} + +abstract class CopyFieldMicroOp { + static const int funct = 23; +} + +abstract class SetFieldMicroOpFunct { + static const int funct = 24; +} + +/// Placeholder micro-op types that don't exist in Harbor. +abstract class ValidateFieldMicroOp { + static const int funct = 100; +} + +abstract class SetFieldMicroOp { + static const int funct = 101; +} + +abstract class ModifyLatchMicroOp { + static const int funct = 102; +} + +abstract class FpuMicroOp { + static const int funct = 25; +} + +// Atomic micro-ops (funct values mirror MicrocodeRom._mopFunct). +abstract class LoadReservedMicroOp { + static const int funct = 17; +} + +abstract class StoreConditionalMicroOp { + static const int funct = 18; +} + +abstract class AtomicMemoryMicroOp { + static const int funct = 19; + // RiscVAtomicFunct has 10 members -> 4-bit op selector in the ROM word. + static const int functWidth = 4; +} + +class MicroOpFpuFunct { + static int get width => RiscVFpuFunct.values.length.bitLength; + + static const int fadd = 0; + static const int fsub = 1; + static const int fmul = 2; + static const int fdiv = 3; + static const int fsqrt = 4; + static const int fcvtWS = 5; + static const int fcvtSW = 6; + static const int fcvtLS = 7; + static const int fcvtSL = 8; + static const int fcvtWD = 9; + static const int fcvtDW = 10; + static const int fcvtLD = 11; + static const int fcvtDL = 12; + static const int fcvtSD = 13; + static const int fcvtDS = 14; + static const int feq = 15; + static const int flt = 16; + static const int fle = 17; + static const int fmv = 18; + static const int fclass = 19; + static const int fsgnj = 20; + static const int fsgnjn = 21; + static const int fsgnjx = 22; + static const int fmin = 23; + static const int fmax = 24; + + MicroOpFpuFunct._(); +} + +/// ALU function codes with old API names. +class MicroOpAluFunct { + static int get width => RiscVAluFunct.values.length.bitLength; + + static const int add = 0; + static const int sub = 1; + static const int and = 2; + static const int or = 3; + static const int xor = 4; + static const int sll = 5; + static const int srl = 6; + static const int sra = 7; + static const int slt = 8; + static const int sltu = 9; + static const int mul = 10; + static const int mulh = 11; + static const int mulhsu = 12; + static const int mulhu = 13; + static const int div = 14; + static const int divu = 15; + static const int rem = 16; + static const int remu = 17; + static const int addw = 18; + static const int subw = 19; + static const int sllw = 20; + static const int srlw = 21; + static const int sraw = 22; + static const int mulw = 23; + static const int divw = 24; + static const int divuw = 25; + static const int remw = 26; + static const int remuw = 27; + static const int masked = 28; + // Zicond: conditional-zero. Values are the RiscVAluFunct enum indices (the + // funct stored in the microcode ROM), not a dense local numbering. + static const int czeroEqz = 61; + static const int czeroNez = 62; + + MicroOpAluFunct._(); +} + +/// Branch/comparison conditions with old API names. +class MicroOpCondition { + static const int width = 4; + + static const int eq = 0; + static const int ne = 1; + static const int lt = 2; + static const int ge = 3; + static const int ltu = 4; + static const int geu = 5; + static const int gt = 6; + static const int le = 7; + + MicroOpCondition._(); +} + +/// Micro-op field references with old API names. +class MicroOpField { + static const int width = 3; + + static const int rd = 0; + static const int rs1 = 1; + static const int rs2 = 2; + static const int rs3 = 3; + static const int imm = 4; + static const int pc = 5; + static const int sp = 5; + + MicroOpField._(); +} + +/// Micro-op data sources with old API names. +class MicroOpSource { + static const int width = 3; + + static const int alu = 0; + static const int imm = 1; + static const int rs1 = 2; + static const int rs2 = 3; + static const int pc = 4; + static const int rd = 5; + + MicroOpSource._(); +} + +/// Memory size encoding with old API names. +class MicroOpMemSize { + static int get width => RiscVMemSize.values.length.bitLength; + + static const List values = RiscVMemSize.values; + + MicroOpMemSize._(); +} + +/// Link register targets for WriteLinkRegister micro-op. +enum MicroOpLink { + rd, + ra; + + int get value => index; + static int get width => MicroOpLink.values.length.bitLength; + + /// Register target for the link. + Register? get reg => switch (this) { + MicroOpLink.ra => Register.x1, + _ => null, + }; + + /// Source for dynamic link register. + RiscVMicroOpSource? get source => switch (this) { + MicroOpLink.rd => RiscVMicroOpSource.rd, + _ => null, + }; +} + +/// Extension to add `bits` and `value` getters to RiscVMemSize. +extension RiscVMemSizeBitsExt on RiscVMemSize { + int get bits => bytes * 8; + int get value => index; +} + +/// Extension to add `value` getter to RiscVMicroOpSource. +extension RiscVMicroOpSourceValueExt on RiscVMicroOpSource { + int get value => id; +} + +/// Extension to add `value` getter to RiscVMicroOpField. +extension RiscVMicroOpFieldValueExt on RiscVMicroOpField { + int get value => id; +} + +/// Extension to add `mcauseCode` getter to Trap. +extension TrapMcauseCodeExt on Trap { + int get mcauseCode => causeCode; +} + +/// Extension to add `width` (bytes) getter to RiscVMxlen. +extension RiscVMxlenWidthExt on RiscVMxlen { + int get width => bytes; +} + +/// Extension to add `indexedMicrocode` to RiscVOperation. +extension RiscVOperationIndexedExt on RiscVOperation { + /// Returns microcode as a map indexed by position. + Map get indexedMicrocode => Map.fromEntries( + microcode.asMap().entries.map((e) => MapEntry(e.key, e.value)), + ); +} + +/// Microcode table: maps each micro-op type to its ROM encoding layout. +final List kMicroOpTable = [ + MicroOpEncoding( + name: 'ReadRegister', + funct: ReadRegisterMicroOp.funct, + struct: (mxlen) => BitStruct({ + 'funct': BitRange(0, 4), + 'source': BitRange(5, 5 + MicroOpField.width - 1), + 'offset': BitRange( + 5 + MicroOpField.width, + 5 + MicroOpField.width + mxlen.size - 1, + ), + 'valueOffset': BitRange( + 5 + MicroOpField.width + mxlen.size, + 5 + MicroOpField.width + mxlen.size * 2 - 1, + ), + }), + toMap: (mop) { + final m = mop as RiscVReadRegister; + return { + 'funct': ReadRegisterMicroOp.funct, + 'source': m.source.id, + 'offset': m.offset, + 'valueOffset': 0, + }; + }, + ), + MicroOpEncoding( + name: 'WriteRegister', + funct: WriteRegisterMicroOp.funct, + struct: (mxlen) => BitStruct({ + 'funct': BitRange(0, 4), + 'field': BitRange(5, 5 + MicroOpField.width - 1), + 'source': BitRange( + 5 + MicroOpField.width, + 5 + MicroOpField.width + MicroOpSource.width - 1, + ), + 'offset': BitRange( + 5 + MicroOpField.width + MicroOpSource.width, + 5 + MicroOpField.width + MicroOpSource.width + mxlen.size - 1, + ), + 'valueOffset': BitRange( + 5 + MicroOpField.width + MicroOpSource.width + mxlen.size, + 5 + MicroOpField.width + MicroOpSource.width + mxlen.size * 2 - 1, + ), + }), + toMap: (mop) { + final m = mop as RiscVWriteRegister; + return { + 'funct': WriteRegisterMicroOp.funct, + 'field': m.dest.id, + 'source': m.source.id, + 'offset': 0, + 'valueOffset': m.valueOffset, + }; + }, + ), + MicroOpEncoding( + name: 'Alu', + funct: AluMicroOp.funct, + struct: (mxlen) => BitStruct({ + 'funct': BitRange(0, 4), + 'alu': BitRange(5, 5 + MicroOpAluFunct.width - 1), + 'a': BitRange( + 5 + MicroOpAluFunct.width, + 5 + MicroOpAluFunct.width + MicroOpField.width - 1, + ), + 'b': BitRange( + 5 + MicroOpAluFunct.width + MicroOpField.width, + 5 + MicroOpAluFunct.width + MicroOpField.width * 2 - 1, + ), + }), + toMap: (mop) { + final m = mop as RiscVAlu; + return { + 'funct': AluMicroOp.funct, + 'alu': m.funct.index, + 'a': m.a.id, + 'b': m.b.id, + }; + }, + ), + MicroOpEncoding( + name: 'BranchIf', + funct: BranchIfMicroOp.funct, + struct: (mxlen) => BitStruct({ + 'funct': BitRange(0, 4), + 'condition': BitRange(5, 5 + MicroOpCondition.width - 1), + 'target': BitRange( + 5 + MicroOpCondition.width, + 5 + MicroOpCondition.width + MicroOpField.width - 1, + ), + 'hasField': BitRange( + 5 + MicroOpCondition.width + MicroOpField.width, + 5 + MicroOpCondition.width + MicroOpField.width, + ), + 'offset': BitRange( + 5 + MicroOpCondition.width + MicroOpField.width + 1, + 5 + MicroOpCondition.width + MicroOpField.width + mxlen.size, + ), + 'offsetField': BitRange( + 5 + MicroOpCondition.width + MicroOpField.width + mxlen.size + 1, + 5 + MicroOpCondition.width + MicroOpField.width * 2 + mxlen.size, + ), + }), + toMap: (mop) { + final m = mop as RiscVBranch; + return { + 'funct': BranchIfMicroOp.funct, + 'condition': m.condition.index, + 'target': 0, + 'hasField': 0, + 'offset': 0, + 'offsetField': 0, + }; + }, + ), + MicroOpEncoding( + name: 'UpdatePC', + funct: UpdatePCMicroOp.funct, + struct: (mxlen) => BitStruct({ + 'funct': BitRange(0, 4), + 'absolute': BitRange(5, 5), + 'align': BitRange(6, 6), + 'hasField': BitRange(7, 7), + 'hasSource': BitRange(8, 8), + 'offset': BitRange(9, 9 + mxlen.size - 1), + 'offsetField': BitRange( + 9 + mxlen.size, + 9 + mxlen.size + MicroOpField.width - 1, + ), + 'offsetSource': BitRange( + 9 + mxlen.size + MicroOpField.width, + 9 + mxlen.size + MicroOpField.width + MicroOpSource.width - 1, + ), + }), + toMap: (mop) { + final m = mop as RiscVUpdatePc; + return { + 'funct': UpdatePCMicroOp.funct, + 'absolute': m.absolute ? 1 : 0, + 'align': m.align ? 1 : 0, + 'hasField': m.offsetField != null ? 1 : 0, + 'hasSource': m.offsetSource != null ? 1 : 0, + 'offset': m.offset, + 'offsetField': m.offsetField?.id ?? 0, + 'offsetSource': m.offsetSource?.id ?? 0, + }; + }, + ), + MicroOpEncoding( + name: 'MemLoad', + funct: MemLoadMicroOp.funct, + struct: (mxlen) => BitStruct({ + 'funct': BitRange(0, 4), + 'base': BitRange(5, 5 + MicroOpField.width - 1), + 'dest': BitRange(5 + MicroOpField.width, 5 + MicroOpField.width * 2 - 1), + 'size': BitRange( + 5 + MicroOpField.width * 2, + 5 + MicroOpField.width * 2 + MicroOpMemSize.width - 1, + ), + 'unsigned': BitRange( + 5 + MicroOpField.width * 2 + MicroOpMemSize.width, + 5 + MicroOpField.width * 2 + MicroOpMemSize.width, + ), + }), + toMap: (mop) { + final m = mop as RiscVMemLoad; + return { + 'funct': MemLoadMicroOp.funct, + 'base': m.base.id, + 'dest': m.dest.id, + 'size': m.size.index, + 'unsigned': m.unsigned ? 1 : 0, + }; + }, + ), + MicroOpEncoding( + name: 'MemStore', + funct: MemStoreMicroOp.funct, + struct: (mxlen) => BitStruct({ + 'funct': BitRange(0, 4), + 'base': BitRange(5, 5 + MicroOpField.width - 1), + 'src': BitRange(5 + MicroOpField.width, 5 + MicroOpField.width * 2 - 1), + 'size': BitRange( + 5 + MicroOpField.width * 2, + 5 + MicroOpField.width * 2 + MicroOpMemSize.width - 1, + ), + }), + toMap: (mop) { + final m = mop as RiscVMemStore; + return { + 'funct': MemStoreMicroOp.funct, + 'base': m.base.id, + 'src': m.src.id, + 'size': m.size.index, + }; + }, + ), + MicroOpEncoding( + name: 'Trap', + funct: TrapMicroOp.funct, + struct: (mxlen) => BitStruct({ + 'funct': BitRange(0, 4), + 'causeCode': BitRange(5, 10), + 'isInterrupt': BitRange(11, 11), + }), + toMap: (mop) { + final m = mop as RiscVTrapOp; + return { + 'funct': TrapMicroOp.funct, + 'causeCode': m.causeCode, + 'isInterrupt': m.isInterrupt ? 1 : 0, + }; + }, + ), + // MRET/SRET. The interpreter recovers the target privilege (3=M mret, 1=S + // sret) from this encoded field so core.dart picks {m,s}epc / {m,s}status.xPP. + // Without it the ROM stores a bare funct=14 and mret/sret are indistinguishable. + MicroOpEncoding( + name: 'Return', + funct: ReturnMicroOp.funct, + struct: (mxlen) => + BitStruct({'funct': BitRange(0, 4), 'privilegeLevel': BitRange(5, 7)}), + toMap: (mop) { + final m = mop as RiscVReturnOp; + return {'funct': ReturnMicroOp.funct, 'privilegeLevel': m.privilegeLevel}; + }, + ), + MicroOpEncoding( + name: 'WriteLinkRegister', + funct: WriteLinkRegisterMicroOp.funct, + struct: (mxlen) => BitStruct({ + 'funct': BitRange(0, 4), + 'link': BitRange(5, 5 + MicroOpLink.width - 1), + 'pcOffset': BitRange( + 5 + MicroOpLink.width, + 5 + MicroOpLink.width + mxlen.size - 1, + ), + }), + toMap: (mop) => { + 'funct': WriteLinkRegisterMicroOp.funct, + 'link': MicroOpLink.rd.value, + 'pcOffset': 4, + }, + ), + MicroOpEncoding( + name: 'ReadCsr', + funct: ReadCsrMicroOp.funct, + struct: (mxlen) => BitStruct({ + 'funct': BitRange(0, 4), + 'source': BitRange(5, 5 + MicroOpField.width - 1), + }), + toMap: (mop) { + final m = mop as RiscVReadCsr; + return {'funct': ReadCsrMicroOp.funct, 'source': m.source.id}; + }, + ), + MicroOpEncoding( + name: 'WriteCsr', + funct: WriteCsrMicroOp.funct, + struct: (mxlen) => BitStruct({ + 'funct': BitRange(0, 4), + 'field': BitRange(5, 5 + MicroOpField.width - 1), + 'source': BitRange( + 5 + MicroOpField.width, + 5 + MicroOpField.width + MicroOpSource.width - 1, + ), + }), + toMap: (mop) { + final m = mop as RiscVWriteCsr; + return { + 'funct': WriteCsrMicroOp.funct, + 'field': m.dest.id, + 'source': m.source.id, + }; + }, + ), + MicroOpEncoding( + name: 'Fence', + funct: FenceMicroOp.funct, + struct: (mxlen) => BitStruct({'funct': BitRange(0, 4)}), + toMap: (mop) => {'funct': FenceMicroOp.funct}, + ), + MicroOpEncoding( + name: 'InterruptHold', + funct: InterruptHoldMicroOp.funct, + struct: (mxlen) => BitStruct({'funct': BitRange(0, 4)}), + toMap: (mop) => {'funct': InterruptHoldMicroOp.funct}, + ), + MicroOpEncoding( + name: 'CopyField', + funct: CopyFieldMicroOp.funct, + struct: (mxlen) => BitStruct({ + 'funct': BitRange(0, 4), + 'src': BitRange(5, 5 + MicroOpField.width - 1), + 'dest': BitRange(5 + MicroOpField.width, 5 + MicroOpField.width * 2 - 1), + }), + toMap: (mop) { + final m = mop as RiscVCopyField; + return { + 'funct': CopyFieldMicroOp.funct, + 'src': m.src.id, + 'dest': m.dest.id, + }; + }, + ), + MicroOpEncoding( + name: 'MoveToField', + funct: SetFieldMicroOpFunct.funct, + struct: (mxlen) => BitStruct({ + 'funct': BitRange(0, 4), + 'src': BitRange(5, 5 + MicroOpSource.width - 1), + 'dest': BitRange( + 5 + MicroOpSource.width, + 5 + MicroOpSource.width + MicroOpField.width - 1, + ), + }), + toMap: (mop) { + final m = mop as RiscVSetField; + return { + 'funct': SetFieldMicroOpFunct.funct, + 'src': m.src.id, + 'dest': m.dest.id, + }; + }, + ), + MicroOpEncoding( + name: 'TlbFence', + funct: TlbFenceMicroOp.funct, + struct: (mxlen) => BitStruct({'funct': BitRange(0, 4)}), + toMap: (mop) => {'funct': TlbFenceMicroOp.funct}, + ), + MicroOpEncoding( + name: 'TlbInvalidate', + funct: TlbInvalidateMicroOp.funct, + struct: (mxlen) => BitStruct({'funct': BitRange(0, 4)}), + toMap: (mop) => {'funct': TlbInvalidateMicroOp.funct}, + ), + MicroOpEncoding( + name: 'FpuOp', + funct: FpuMicroOp.funct, + struct: (mxlen) => BitStruct({ + 'funct': BitRange(0, 4), + 'fpuFunct': BitRange(5, 5 + MicroOpFpuFunct.width - 1), + 'a': BitRange( + 5 + MicroOpFpuFunct.width, + 5 + MicroOpFpuFunct.width + MicroOpField.width - 1, + ), + 'dest': BitRange( + 5 + MicroOpFpuFunct.width + MicroOpField.width, + 5 + MicroOpFpuFunct.width + MicroOpField.width * 2 - 1, + ), + 'hasB': BitRange( + 5 + MicroOpFpuFunct.width + MicroOpField.width * 2, + 5 + MicroOpFpuFunct.width + MicroOpField.width * 2, + ), + 'b': BitRange( + 5 + MicroOpFpuFunct.width + MicroOpField.width * 2 + 1, + 5 + MicroOpFpuFunct.width + MicroOpField.width * 3, + ), + 'doublePrecision': BitRange( + 5 + MicroOpFpuFunct.width + MicroOpField.width * 3 + 1, + 5 + MicroOpFpuFunct.width + MicroOpField.width * 3 + 1, + ), + }), + toMap: (mop) { + final m = mop as RiscVFpuOp; + return { + 'funct': FpuMicroOp.funct, + 'fpuFunct': m.funct.index, + 'a': m.a.id, + 'dest': m.dest.id, + 'hasB': m.b != null ? 1 : 0, + 'b': m.b?.id ?? 0, + 'doublePrecision': m.doublePrecision ? 1 : 0, + }; + }, + ), + // Load-reserved: like MemLoad (base -> dest, size) but tags a reservation. + MicroOpEncoding( + name: 'LoadReserved', + funct: LoadReservedMicroOp.funct, + struct: (mxlen) => BitStruct({ + 'funct': BitRange(0, 4), + 'base': BitRange(5, 5 + MicroOpField.width - 1), + 'dest': BitRange(5 + MicroOpField.width, 5 + MicroOpField.width * 2 - 1), + 'size': BitRange( + 5 + MicroOpField.width * 2, + 5 + MicroOpField.width * 2 + MicroOpMemSize.width - 1, + ), + }), + toMap: (mop) { + final m = mop as RiscVLoadReserved; + return { + 'funct': LoadReservedMicroOp.funct, + 'base': m.base.id, + 'dest': m.dest.id, + 'size': m.size.index, + }; + }, + ), + // Store-conditional: store src to [base], write success/fail flag to dest. + MicroOpEncoding( + name: 'StoreConditional', + funct: StoreConditionalMicroOp.funct, + struct: (mxlen) => BitStruct({ + 'funct': BitRange(0, 4), + 'base': BitRange(5, 5 + MicroOpField.width - 1), + 'src': BitRange(5 + MicroOpField.width, 5 + MicroOpField.width * 2 - 1), + 'dest': BitRange( + 5 + MicroOpField.width * 2, + 5 + MicroOpField.width * 3 - 1, + ), + 'size': BitRange( + 5 + MicroOpField.width * 3, + 5 + MicroOpField.width * 3 + MicroOpMemSize.width - 1, + ), + }), + toMap: (mop) { + final m = mop as RiscVStoreConditional; + return { + 'funct': StoreConditionalMicroOp.funct, + 'base': m.base.id, + 'src': m.src.id, + 'dest': m.dest.id, + 'size': m.size.index, + }; + }, + ), + // AMO: read-modify-write. afunct selects the operation, old value -> dest. + MicroOpEncoding( + name: 'AtomicMemory', + funct: AtomicMemoryMicroOp.funct, + struct: (mxlen) => BitStruct({ + 'funct': BitRange(0, 4), + 'afunct': BitRange(5, 5 + AtomicMemoryMicroOp.functWidth - 1), + 'base': BitRange( + 5 + AtomicMemoryMicroOp.functWidth, + 5 + AtomicMemoryMicroOp.functWidth + MicroOpField.width - 1, + ), + 'src': BitRange( + 5 + AtomicMemoryMicroOp.functWidth + MicroOpField.width, + 5 + AtomicMemoryMicroOp.functWidth + MicroOpField.width * 2 - 1, + ), + 'dest': BitRange( + 5 + AtomicMemoryMicroOp.functWidth + MicroOpField.width * 2, + 5 + AtomicMemoryMicroOp.functWidth + MicroOpField.width * 3 - 1, + ), + 'size': BitRange( + 5 + AtomicMemoryMicroOp.functWidth + MicroOpField.width * 3, + 5 + + AtomicMemoryMicroOp.functWidth + + MicroOpField.width * 3 + + MicroOpMemSize.width - + 1, + ), + }), + toMap: (mop) { + final m = mop as RiscVAtomicMemory; + return { + 'funct': AtomicMemoryMicroOp.funct, + 'afunct': m.funct.index, + 'base': m.base.id, + 'src': m.src.id, + 'dest': m.dest.id, + 'size': m.size.index, + }; + }, + ), +]; diff --git a/packages/river_hdl/lib/src/core.dart b/packages/river_hdl/lib/src/core.dart index 0cdceb7..455a10b 100644 --- a/packages/river_hdl/lib/src/core.dart +++ b/packages/river_hdl/lib/src/core.dart @@ -1,93 +1,156 @@ -import 'dart:math' show max; - import 'package:rohd/rohd.dart'; import 'package:rohd_bridge/rohd_bridge.dart'; -import 'package:rohd_hcl/rohd_hcl.dart'; -import 'package:riscv/riscv.dart'; +import 'package:rohd_hcl/rohd_hcl.dart' hide DataPortInterface, DataPortGroup; import 'package:river/river.dart'; +import 'data_port.dart'; import 'core/csr.dart'; -import 'core/int.dart'; import 'core/mmu.dart'; import 'core/pipeline.dart'; +import 'inferred_rom.dart'; -import 'memory/port.dart'; - -import 'dev.dart'; +import 'compat.dart' show kMicroOpTable; +import 'microcode_rom.dart'; -class RiverCoreIP extends BridgeModule { - final RiverCore config; +class RiverCore extends BridgeModule { + final RiverCoreConfig config; - late final RegisterFile regs; + late final HarborRegisterFile regs; + late final DataPortInterface regWritePort; late final RiverPipeline pipeline; - RiverCoreIP( + RiverCore( this.config, { Map srcIrqs = const {}, List staticInstructions = const [], + WishboneConfig? busConfig, + HarborDeviceTarget? target, + bool withDebug = false, + // Expose plain bustap_ack/bustap_datmiso outputs mirroring the Wishbone + // master's incoming ACK/read data for a logic analyzer. ACK is an input + // here, so it must be mirrored to a plain output to stay hierarchy-legal. + // Off in production. + bool busTap = false, + // Test-only backdoor: when high, an architectural regWritePort write also + // seeds the OoO physical regfile. Asserted only while frozen during seeding; + // null leaves it tied off. + Logic? prfSeedMode, super.name = 'river_core', }) : super('RiverCore') { + final wbConfig = + busConfig ?? + WishboneConfig( + addressWidth: config.mxlen.size, + dataWidth: config.mxlen.size, + selWidth: config.mxlen.size ~/ 8, + ); + createPort('clk', PortDirection.input); createPort('reset', PortDirection.input); final clk = input('clk'); final reset = input('reset'); - final devices = Map.fromEntries( - config.mmu.blocks.indexed.map((e) { - final index = e.$1; - final mmap = e.$2; - - final mmioRead = addInterface( - MmioReadInterface(config.mxlen.size, mmap.size.bitLength), - name: 'mmioRead$index', - role: PairRole.consumer, - ); - final mmioWrite = addInterface( - MmioWriteInterface(config.mxlen.size, mmap.size.bitLength), - name: 'mmioWrite$index', - role: PairRole.provider, - ); - - final devRead = DataPortInterface( - config.mxlen.size, - mmap.size.bitLength, - ); - final devWrite = DataPortInterface( - config.mxlen.size, - mmap.size.bitLength, - ); - - mmioRead.internalInterface!.en <= devRead.en; - mmioRead.internalInterface!.addr <= devRead.addr; - devRead.data <= mmioRead.internalInterface!.data; - devRead.done <= mmioRead.internalInterface!.done; - devRead.valid <= mmioRead.internalInterface!.valid; - - mmioWrite.internalInterface!.en <= devWrite.en; - mmioWrite.internalInterface!.addr <= devWrite.addr; - mmioWrite.internalInterface!.data <= devWrite.data; - devWrite.done <= mmioWrite.internalInterface!.done; - devWrite.valid <= mmioWrite.internalInterface!.valid; - - return MapEntry(mmap, (devRead, devWrite)); - }), - ); + final microcode = MicrocodeRom(config.isa, encodings: kMicroOpTable); final pipelineEnable = Logic(name: 'pipelineEnable'); final pc = Logic(name: 'pc', width: config.mxlen.size); final sp = Logic(name: 'sp', width: config.mxlen.size); final mode = Logic(name: 'mode', width: 3); + // Virtualization (V) mode bit, only meaningful with H. Pushed to + // {m,s}status.{MPV,SPV} and restored on MRET/SRET. + final virt = config.hasHypervisor ? Logic(name: 'virt') : null; + // Per-access "treat as guest" = virt | (HLV/HSV in flight). Drives the MMU's + // VS/G-stage routing. Forward-declared; driven after the pipeline. + final guestAccessWire = config.hasHypervisor + ? Logic(name: 'guestAccess') + : null; final interruptHold = Logic(name: 'interruptHold'); final fence = Logic(name: 'fence'); + // Optional external debug (RISC-V Debug Module) halt/resume. Freezes the + // core at an instruction boundary and latches its PC into dpc. + Logic? debugHalted; + Logic? debugDpc; + // Debug control/status register (dcsr, CSR 0x7b0). Must be a real + // readable/writable register (OpenOCD reads cause/priv and writes + // ebreak/step bits during resume) or resume wedges. + Logic? debugDcsr; + // High when a committing ebreak should enter Debug Mode (dcsr.ebreak* set for + // the current privilege) instead of taking a breakpoint trap. + Logic? ebreakDebug; + Logic? haltReqIn; + Logic? resumeReqIn; + // Abstract-command register access (driven by the Debug Module while halted). + Logic? dbgGprRead; // read a GPR onto the regfile read port + Logic? dbgGprWrite; // write a GPR through the regfile write port + Logic? dbgGprIdx; // 5-bit GPR index + Logic? dbgIsDpc; // regno == dpc (0x7b1) + Logic? dbgIsDcsr; // regno == dcsr (0x7b0) + Logic? dbgIsMisa; // regno == misa (0x301) + Logic? dbgRegWdata; + Logic? dbgIsGpr; // regno is a GPR (bit 12 set) + Logic? dbgRegAddr12; // low 12 bits of the regno = the CSR address + Logic? dbgCsrSel; // halted && the regno is a CSR (borrow the CSR read port) + Logic? dbgCsrData; // CSR file read result for a debug CSR access + if (withDebug) { + createPort('debug_halt_req', PortDirection.input); + createPort('debug_resume_req', PortDirection.input); + createPort('debug_reg_read', PortDirection.input); + createPort('debug_reg_write', PortDirection.input); + createPort('debug_reg_addr', PortDirection.input, width: 16); + createPort( + 'debug_reg_wdata', + PortDirection.input, + width: config.mxlen.size, + ); + addOutput('debug_halted'); + addOutput('debug_dpc', width: config.mxlen.size); + addOutput('debug_reg_rdata', width: config.mxlen.size); + addOutput('debug_reg_ready'); + haltReqIn = input('debug_halt_req'); + resumeReqIn = input('debug_resume_req'); + debugHalted = Logic(name: 'debugHalted'); + debugDpc = Logic(name: 'debugDpc', width: config.mxlen.size); + debugDcsr = Logic(name: 'debugDcsr', width: 32); + ebreakDebug = Logic(name: 'ebreakDebug'); + output('debug_halted') <= debugHalted; + output('debug_dpc') <= debugDpc; + + final regAddr = input('debug_reg_addr'); + // GPR regnos are 0x1000..0x101f (bit 12 set); CSRs are < 0x1000. + final isGpr = regAddr[12]; + dbgGprIdx = regAddr.getRange(0, 5); + dbgIsDpc = regAddr.eq(0x7b1); + dbgIsDcsr = regAddr.eq(0x7b0); + // misa is a read-only constant (the configured ISA). Serve it directly so + // a debugger can probe extensions over JTAG; else the abstract CSR read + // falls through to the GPR port and reads 0. + dbgIsMisa = regAddr.eq(0x301); + dbgRegWdata = input('debug_reg_wdata'); + dbgGprRead = input('debug_reg_read') & isGpr; + dbgGprWrite = input('debug_reg_write') & isGpr & debugHalted; + // CSR abstract reads: while halted the pipeline is frozen, so the Debug + // Module borrows the CSR read port. The regno IS the CSR address (regnos + // < 0x1000), so present regAddr[11:0] and route the result back. Only the + // read port is borrowed; CSR writes over abstract command are unimplemented. + dbgIsGpr = isGpr; + dbgRegAddr12 = regAddr.getRange(0, 12); + if (config.hasCsrs) { + dbgCsrSel = ~isGpr & debugHalted; + dbgCsrData = Logic(name: 'dbgCsrData', width: config.mxlen.size); + } + // The register file is zero-latency, so the access is always ready. + output('debug_reg_ready') <= Const(1); + } + final pagingMode = Logic( name: 'pagingMode', - width: PagingMode.values - .where((m) => m.isSupported(config.mxlen)) + width: config.mmu.pagingModes .map((m) => m.id) - .fold((0), (a, b) => a > b ? a : b) - .bitLength, + .fold(0, (a, b) => a > b ? a : b) + .bitLength + .clamp(1, 64), ); final pageTableAddress = Logic( @@ -95,147 +158,596 @@ class RiverCoreIP extends BridgeModule { width: config.mxlen.size, ); + // satp.MODE (4 bits) and root PPN, forward-declared to feed the MMU (built + // before the CSR file). Assigned from the CSR file's satp once it exists. + final satpModeWire = Logic(name: 'satpModeWire', width: 4); + final satpRootWire = Logic(name: 'satpRootWire', width: config.mxlen.size); + + // Hypervisor G-stage (hgatp) mode/root for two-stage translation, fed to the + // MMU when the config has H. Driven from an hgatp shadow register below. + final gModeWire = config.hasHypervisor + ? Logic(name: 'gModeWire', width: 4) + : null; + final gRootWire = config.hasHypervisor + ? Logic(name: 'gRootWire', width: config.mxlen.size) + : null; + final enableMxr = Logic(name: 'enableMxr'); final enableSum = Logic(name: 'enableSum'); + // DTLBFC (rpipelinectl[3]): drives the MMU's flush-data-TLB-on-priv-change. + // Forward-declared here, driven from the CSR file below (mirrors enableMxr). + final dtlbFlushOnPriv = Logic(name: 'dtlbFlushOnPriv'); + + // Pipeline uses DataPortInterfaces internally; bridge them to the MMU ports. - final mmuFetchRead = DataPortInterface( + final dualDispatch = config.issueWidth == IssueWidth.dual; + + // Fetch read: pipeline drives en/addr, MMU responds with data/done/valid + final pipeFetchRead = DataPortInterface( config.mxlen.size, config.mxlen.size, ); - final mmuExecRead = DataPortInterface(config.mxlen.size, config.mxlen.size); - final mmuWritebackRead = DataPortInterface( + // Dual-dispatch: a second fetch port (lane 1). Both lanes arbitrate onto the + // MMU's single ifetch port below (lane 0 priority), serialising on the shared + // bus, but each lane keeps its own request/response interface so the + // front-end can present a 2-instruction bundle to rename. + final pipeFetchRead1 = dualDispatch + ? DataPortInterface(config.mxlen.size, config.mxlen.size) + : null; + // Exec read: same pattern + final pipeExecRead = DataPortInterface( config.mxlen.size, config.mxlen.size, ); - - final mmuWrite = DataPortInterface(config.mxlen.size, config.mxlen.size); - final sizedMmuWrite = DataPortInterface( + // Exec write: pipeline drives en/addr/data (with sized prefix), MMU responds done/valid + final pipeExecWrite = DataPortInterface( config.mxlen.size + 7, config.mxlen.size, ); - SizedWriteSingleDataPort( - clk, - reset, - backingRead: mmuWritebackRead, - backingWrite: mmuWrite, - source: sizedMmuWrite, + // Bridge fetch → MMU ifetch + // Bridge exec read/write → single dport + final execWriteActive = pipeExecWrite.en; + + // swizzle layout: {size[6:0], value[xlen-1:0]} MSB-first + // So value is bits [xlen-1:0] and size is bits [xlen+6:xlen] + final writeValue = pipeExecWrite.data.getRange(0, config.mxlen.size); + final writeSizePrefix = pipeExecWrite.data.getRange( + config.mxlen.size, + config.mxlen.size + 7, ); + final writeLog2Size = mux( + writeSizePrefix[0], + Const(0, width: 3), + mux( + writeSizePrefix[1], + Const(1, width: 3), + mux( + writeSizePrefix[2], + Const(2, width: 3), + mux(writeSizePrefix[3], Const(3, width: 3), Const(2, width: 3)), + ), + ), + ); + + final dportEn = mux(execWriteActive, Const(1), pipeExecRead.en); + final dportAddr = mux( + execWriteActive, + pipeExecWrite.addr, + pipeExecRead.addr, + ); + final dportWe = execWriteActive; + final dportWdata = mux( + execWriteActive, + writeValue.zeroExtend(config.mxlen.size), + Const(0, width: config.mxlen.size), + ); + final dportSize = mux(execWriteActive, writeLog2Size, Const(2, width: 3)); + + // Wishbone ACK/MISO from external bus + final wbAckExt = Logic(name: 'wbAckExt'); + final wbDatMisoExt = Logic(name: 'wbDatMisoExt', width: wbConfig.dataWidth); + + // Fetch arbiter (dual-dispatch): multiplex the two fetch lanes onto the + // MMU's single ifetch port. Round-robin so both lanes make progress (a + // FetchUnit keeps its request asserted while holding a delivered instruction, + // so fixed priority would starve the other lane). A grant is held until the + // in-flight fetch completes; the next grant prefers the lane not served last. + final fetchActive = Logic(name: 'fetchActive'); + final fetchGrantP1 = Logic(name: 'fetchGrantP1'); + final lastGrantP1 = Logic(name: 'lastGrantP1'); + final bothReq = dualDispatch + ? (pipeFetchRead.en & pipeFetchRead1!.en) + : Const(0); + final onlyP1 = dualDispatch + ? (~pipeFetchRead.en & pipeFetchRead1!.en) + : Const(0); + final newGrantP1 = mux(bothReq, ~lastGrantP1, onlyP1); + final grantP1Now = dualDispatch + ? mux(fetchActive, fetchGrantP1, newGrantP1) + : Const(0); + final ifetchEnArb = dualDispatch + ? mux(grantP1Now, pipeFetchRead1!.en, pipeFetchRead.en) + : pipeFetchRead.en; + final ifetchAddrArb = dualDispatch + ? mux(grantP1Now, pipeFetchRead1!.addr, pipeFetchRead.addr) + : pipeFetchRead.addr; + + // Optional L1 instruction cache between the fetch unit(s) and the MMU ifetch + // port. Hits in one cycle; misses fill a line from the MMU (its miss port + // drives the MMU ifetch instead of the arbiter). Dual-dispatch serves both + // lanes the same cycle on a shared-line hit. + // On creek (DDR behind the FPGA PHY) the L1 is a correctness lever: each miss + // fills one paced word at a time, so the PHY only sees single reads it + // captures correctly, never a back-to-back burst. The D-cache extends the + // same pacing to data loads. + final l1 = config.l1cache; + final useICache = l1?.i != null; + final useDCache = l1 != null; + + final icMemDone = Logic(name: 'icMemDone'); + final icMemValid = Logic(name: 'icMemValid'); + final icMemRdata = Logic(name: 'icMemRdata', width: config.mxlen.size); + final icFlush = Logic(name: 'icFlush'); + // Driven from pipeline.fence below (forward ref); flushes the MMU fetch TLB. + final mmuTlbFlush = Logic(name: 'mmuTlbFlush'); + + HarborL1ICache? icache; + if (useICache) { + icache = HarborL1ICache( + config: l1!.i!, + xlen: config.mxlen.size, + dualPort: dualDispatch, + // 32 physical bits cover the fetch space (DRAM at 0x80000000 + <=1GB); a + // narrower tag packs far fewer LUTs than a full xlen compare. + physAddrBits: 32, + // Maps the per-line data to a block RAM (DP16KD / RAMB36E1). + target: target, + ); + addSubModule(icache); + icache.input('clk').srcConnection! <= clk; + icache.input('reset').srcConnection! <= reset; + icache.input('req_addr').srcConnection! <= pipeFetchRead.addr; + icache.input('req_valid').srcConnection! <= pipeFetchRead.en; + icache.input('flush').srcConnection! <= icFlush; + icache.input('mem_done').srcConnection! <= icMemDone; + icache.input('mem_valid').srcConnection! <= icMemValid; + icache.input('mem_rdata').srcConnection! <= icMemRdata; + if (dualDispatch) { + icache.input('req_addr1').srcConnection! <= pipeFetchRead1!.addr; + icache.input('req_valid1').srcConnection! <= pipeFetchRead1.en; + } + } + final ifetchEnFinal = useICache ? icache!.memEn : ifetchEnArb; + final ifetchAddrFinal = useICache ? icache!.memAddr : ifetchAddrArb; + + // L1 data cache. Instantiated before the MMU because it drives the MMU dport + // (load fills and write-through stores); the response feeds back through the + // dc* wires. Write-through, no-write-allocate: stores go straight to DRAM + // and invalidate any resident line, so no dirty-eviction burst is launched + // into the marginal PHY. + final dcMemDone = Logic(name: 'dcMemDone'); + final dcMemValid = Logic(name: 'dcMemValid'); + final dcMemRdata = Logic(name: 'dcMemRdata', width: config.mxlen.size); + final dFlush = Logic(name: 'dFlush'); + HarborL1DCache? dcache; + if (useDCache) { + dcache = HarborL1DCache( + config: l1.d, + xlen: config.mxlen.size, + physAddrBits: 32, + target: target, + ); + addSubModule(dcache); + dcache.input('clk').srcConnection! <= clk; + dcache.input('reset').srcConnection! <= reset; + dcache.input('req_addr').srcConnection! <= dportAddr; + dcache.input('req_valid').srcConnection! <= dportEn; + dcache.input('req_write').srcConnection! <= dportWe; + dcache.input('req_data').srcConnection! <= writeValue; + dcache.input('req_size').srcConnection! <= dportSize; + dcache.input('flush').srcConnection! <= dFlush; + dcache.input('mem_done').srcConnection! <= dcMemDone; + dcache.input('mem_valid').srcConnection! <= dcMemValid; + dcache.input('mem_rdata').srcConnection! <= dcMemRdata; + } + // Data-port request to the MMU: from the D-cache when present, else direct. + final dportEnFinal = useDCache ? dcache!.memEn : dportEn; + final dportAddrFinal = useDCache ? dcache!.memAddr : dportAddr; + final dportWeFinal = useDCache ? dcache!.memWe : dportWe; + final dportWdataFinal = useDCache ? dcache!.memWdata : dportWdata; + final dportSizeFinal = useDCache ? dcache!.memSize : dportSize; - MmuModule( + // MMU. + final mmu = RiverMmu( clk, reset, - [(MemoryAccess.write, mmuWrite)], - [ - (MemoryAccess.instr, mmuFetchRead), - (MemoryAccess.read, mmuExecRead), - (MemoryAccess.read, mmuWritebackRead), - ], - config: config.mmu, - privilegeMode: mode, - pagingMode: config.mmu.hasPaging ? pagingMode : null, - pageTableAddress: config.mmu.hasPaging ? pageTableAddress : null, - devices: devices, - enableSum: config.mmu.hasSum ? enableSum : null, - enableMxr: config.mmu.hasMxr ? enableMxr : null, - fence: fence, + ifetchEnFinal, + ifetchAddrFinal, + dportEnFinal, + dportAddrFinal, + dportWeFinal, + dportWdataFinal, + dportSizeFinal, + wbAckExt, + wbDatMisoExt, + mmuConfig: config.mmu, + busConfig: wbConfig, + satpMode: config.mmu.hasPaging ? satpModeWire : null, + satpRoot: config.mmu.hasPaging ? satpRootWire : null, + virtIn: config.hasHypervisor ? guestAccessWire : null, + gMode: config.hasHypervisor ? gModeWire : null, + gRoot: config.hasHypervisor ? gRootWire : null, + privMode: config.mmu.hasPaging ? mode : null, + sum: config.mmu.hasPaging ? enableSum : null, + mxr: config.mmu.hasPaging ? enableMxr : null, + // Translate instruction fetches (below M-mode). Gated off when an icache + // sits in front, since the icache does not yet propagate ifetch_fault. + translateFetch: config.mmu.hasPaging && !useICache, + tlbFlush: config.mmu.hasPaging ? mmuTlbFlush : null, + dtlbFlushOnPrivChange: config.mmu.hasPaging ? dtlbFlushOnPriv : null, + ); + + if (useICache) { + // The icache owns the MMU ifetch port (its miss fills); fetch responses + // come from the cache. flush on fence.i (driven from the pipeline below). + icMemDone <= mmu.ifetchDone; + icMemValid <= mmu.ifetchValid; + icMemRdata <= mmu.ifetchRdata; + pipeFetchRead.done <= icache!.respValid; + pipeFetchRead.valid <= icache.respValid; + pipeFetchRead.data <= icache.respData; + if (dualDispatch) { + pipeFetchRead1!.done <= icache.respValid1; + pipeFetchRead1.valid <= icache.respValid1; + pipeFetchRead1.data <= icache.respData1; + } + } else if (dualDispatch) { + // Route the ifetch response to whichever lane currently holds the grant. + pipeFetchRead.done <= mmu.ifetchDone & ~grantP1Now; + pipeFetchRead.valid <= mmu.ifetchValid & ~grantP1Now; + pipeFetchRead.data <= mmu.ifetchRdata; + pipeFetchRead1!.done <= mmu.ifetchDone & grantP1Now; + pipeFetchRead1.valid <= mmu.ifetchValid & grantP1Now; + pipeFetchRead1.data <= mmu.ifetchRdata; + Sequential(clk, [ + If( + reset, + then: [fetchActive < 0, fetchGrantP1 < 0, lastGrantP1 < 0], + orElse: [ + If( + ~fetchActive, + then: [ + If( + pipeFetchRead.en | pipeFetchRead1.en, + then: [ + fetchActive < 1, + fetchGrantP1 < newGrantP1, + lastGrantP1 < newGrantP1, + ], + ), + ], + orElse: [ + If(mmu.ifetchDone, then: [fetchActive < 0]), + ], + ), + ], + ), + ]); + } else { + pipeFetchRead.done <= mmu.ifetchDone; + pipeFetchRead.valid <= mmu.ifetchValid; + pipeFetchRead.data <= mmu.ifetchRdata; + } + + if (useDCache) { + // MMU dport response feeds the D-cache; the D-cache serves the pipeline + // (a hit in one cycle, a miss after its paced fill, a store once memory + // acknowledges the write-through). + dcMemDone <= mmu.dportDone; + dcMemValid <= mmu.dportValid; + dcMemRdata <= mmu.dportRdata; + pipeExecRead.done <= dcache!.respValid & ~execWriteActive; + pipeExecRead.valid <= dcache.respValid & ~execWriteActive; + pipeExecRead.data <= dcache.respData; + pipeExecWrite.done <= dcache.respValid & execWriteActive; + pipeExecWrite.valid <= dcache.respValid & execWriteActive; + } else { + pipeExecRead.done <= mmu.dportDone & ~execWriteActive; + pipeExecRead.valid <= mmu.dportValid & ~execWriteActive; + pipeExecRead.data <= mmu.dportRdata; + + pipeExecWrite.done <= mmu.dportDone & execWriteActive; + pipeExecWrite.valid <= mmu.dportValid & execWriteActive; + } + + // Expose Wishbone bus master as a proper interface + final dataBusRef = addInterface( + WishboneInterface(wbConfig), + name: 'dataBus', + role: PairRole.provider, ); + final wb = dataBusRef.internalInterface as WishboneInterface; + + wb.cyc <= mmu.wbCyc; + wb.stb <= mmu.wbStb; + wb.we <= mmu.wbWe; + wb.adr <= mmu.wbAdr; + wb.datMosi <= mmu.wbDatMosi; + wb.sel <= mmu.wbSel; + wbAckExt <= wb.ack; + wbDatMisoExt <= wb.datMiso; + + // Logic-analyzer bus taps: mirror the consumer-direction signals (ACK, read + // data) to plain outputs for GPIO routing. These inputs cannot be read in + // the parent without violating module hierarchy, so the core exposes them. + if (busTap) { + addOutput('bustap_ack') <= wb.ack; + addOutput('bustap_datmiso', width: wbConfig.dataWidth) <= wb.datMiso; + // Master-side control so a stuck transaction is visible: a hung load shows + // cyc=stb=1, we=0, ack=0 held forever, with adr at the wedged address. + addOutput('bustap_cyc') <= mmu.wbCyc; + addOutput('bustap_stb') <= mmu.wbStb; + addOutput('bustap_we') <= mmu.wbWe; + addOutput('bustap_adr', width: wbConfig.addressWidth) <= mmu.wbAdr; + } + + // Register file. Dual-commit (config.commitLanes > 1) adds a second write + // port. Single-write-port storage can't take two writes/cycle, so the file + // is split into one bank per write port; same-bank collisions are arbitrated + // and back-pressured via the wr*_ready outputs. + final numWritePorts = config.commitLanes; + final dualCommit = numWritePorts > 1; + String wrPort(int w, String s) => + numWritePorts == 1 ? 'wr_$s' : 'wr${w}_$s'; final rs1Read = DataPortInterface(config.mxlen.size, 5); final rs2Read = DataPortInterface(config.mxlen.size, 5); final rdWrite = DataPortInterface(config.mxlen.size, 5); + regWritePort = rdWrite; + final rdWrite1 = dualCommit + ? DataPortInterface(config.mxlen.size, 5) + : null; - regs = RegisterFile( - clk, - reset, - [rdWrite], - [rs1Read, rs2Read], + regs = HarborRegisterFile( numEntries: 32, + dataWidth: config.mxlen.size, + // Dual-dispatch (4 read ports) is a follow-on; commit drives writes. + numReadPorts: 2, + numWritePorts: numWritePorts, + numBanks: numWritePorts, + writeBufferDepth: config.writeBufferDepth, + target: target, + forceReadLatency: config.regfileReadLatency, name: 'riscv_regfile', ); - - int computeNumIrqs(InterruptController ic) { - final irqs = ic.lines.map((l) => l.irq).toList(); - if (irqs.isEmpty) return 1; - final maxIrq = irqs.reduce((a, b) => a > b ? a : b); - return max(1, maxIrq + 1); + addSubModule(regs); + regs.input('clk').srcConnection! <= clk; + regs.input('reset').srcConnection! <= reset; + // While halted, the Debug Module borrows read/write port 0 to service + // abstract register-access commands (the pipeline is frozen). + regs.input('rd0_addr').srcConnection! <= + (withDebug ? mux(dbgGprRead!, dbgGprIdx!, rs1Read.addr) : rs1Read.addr); + regs.input('rd1_addr').srcConnection! <= rs2Read.addr; + regs.input(wrPort(0, 'en')).srcConnection! <= + (withDebug ? mux(dbgGprWrite!, Const(1), rdWrite.en) : rdWrite.en); + regs.input(wrPort(0, 'addr')).srcConnection! <= + (withDebug + ? mux(dbgGprWrite!, dbgGprIdx!, rdWrite.addr) + : rdWrite.addr); + regs.input(wrPort(0, 'data')).srcConnection! <= + (withDebug + ? mux(dbgGprWrite!, dbgRegWdata!, rdWrite.data) + : rdWrite.data); + Logic? wr0Ready; + Logic? wr1Ready; + if (dualCommit) { + regs.input(wrPort(1, 'en')).srcConnection! <= rdWrite1!.en; + regs.input(wrPort(1, 'addr')).srcConnection! <= rdWrite1.addr; + regs.input(wrPort(1, 'data')).srcConnection! <= rdWrite1.data; + wr0Ready = regs.writeReady(0); + wr1Ready = regs.writeReady(1); + rdWrite1.done <= rdWrite1.en; + rdWrite1.valid <= rdWrite1.en; } - - final interruptBundles = - < - ({ - InterruptController cfg, - Logic srcIrq, - InterruptPortInterface ipi, - RiscVInterruptController ctrl, - }) - >[]; - - for (final ic in config.interrupts) { - final numIrqs = computeNumIrqs(ic); - - final isExternal = srcIrqs.containsKey(ic.name); - final srcIrq = isExternal - ? addInput( - 'srcIrqLevel_${interruptBundles.length}', - srcIrqs[ic.name]!, - width: numIrqs, - ) - : Logic( - name: 'srcIrqLevel_${interruptBundles.length}', - width: numIrqs, - ); - - final ipi = InterruptPortInterface(config.mxlen.size, config.mxlen.size); - - final ctrl = RiscVInterruptController(ic, clk, reset, srcIrq, ipi); - - ipi.en <= Const(0); - ipi.write <= Const(0); - ipi.addr <= Const(0, width: ipi.addr.width); - ipi.wdata <= Const(0, width: ipi.wdata.width); - ipi.wstrb <= Const(0, width: ipi.wstrb.width); - - interruptBundles.add((cfg: ic, srcIrq: srcIrq, ipi: ipi, ctrl: ctrl)); + // Preserve the rohd_hcl semantics: read data is zero when the port is + // disabled (and x0 reads zero, handled inside HarborRegisterFile). + rs1Read.data <= + mux(rs1Read.en, regs.rd0Data, Const(0, width: config.mxlen.size)); + // Abstract-command read result: dcsr, dpc, misa, a general CSR (borrowed + // read port), or the GPR on read port 0. dcsr/dpc/misa are special-cased so + // they serve even when the CSR file does not implement them as readable CSRs. + if (withDebug) { + // For a GPR access read port 0; for a non-special CSR read the borrowed + // CSR port (dbgCsrData, null when the core has no CSR file). + final gprOrCsr = dbgCsrData == null + ? regs.rd0Data + : mux(dbgIsGpr!, regs.rd0Data, dbgCsrData); + output('debug_reg_rdata') <= + mux( + dbgIsDcsr!, + debugDcsr!.zeroExtend(config.mxlen.size), + mux( + dbgIsMisa!, + Const(config.isa.misaValue, width: config.mxlen.size), + mux(dbgIsDpc!, debugDpc!, gprOrCsr), + ), + ); } + rs2Read.data <= + mux(rs2Read.en, regs.rd1Data, Const(0, width: config.mxlen.size)); + // Read data is [regs.readLatency] cycles behind the address (0 for the + // combinational/iCE40 negedge-EBR read, 1 for the ECP5 posedge-EBR read). + // Delay done/valid by the same latency so the operand-read handshake latches + // the data on the cycle it is valid. Writes are single-cycle, unaffected. + Logic delayReadHandshake(Logic en, String name) { + var s = en; + for (var i = 0; i < regs.readLatency; i++) { + final q = Logic(name: '${name}_q$i'); + Sequential(clk, [q < s]); + s = q; + } + return s; + } + + rs1Read.done <= delayReadHandshake(rs1Read.en, 'rs1RdDone'); + rs1Read.valid <= delayReadHandshake(rs1Read.en, 'rs1RdValid'); + rs2Read.done <= delayReadHandshake(rs2Read.en, 'rs2RdDone'); + rs2Read.valid <= delayReadHandshake(rs2Read.en, 'rs2RdValid'); + rdWrite.done <= rdWrite.en; + rdWrite.valid <= rdWrite.en; + // Interrupts. Logic externalPending = Const(0); - for (final b in interruptBundles) { - final v = b.ctrl.irqToTargets; - Logic anyFromThis = Const(0); - for (var i = 0; i < v.width; i++) { - anyFromThis = anyFromThis | v[i]; - } + for (final entry in srcIrqs.entries) { + final sig = addInput(entry.key, entry.value); + final anyFromThis = sig.or(); externalPending = externalPending | anyFromThis; } + // CSR file. final csrRead = DataPortInterface(config.mxlen.size, 12); final csrWrite = DataPortInterface(config.mxlen.size, 12); - final csrs = config.type.hasCsrs + // Interface handed to the CSR file. Normally the pipeline's csrRead, but + // while halted the Debug Module borrows the frozen read port: it presents + // the debug regno (the CSR address) and routes the result back. + final DataPortInterface csrReadCsr; + if (dbgCsrData != null) { + csrReadCsr = DataPortInterface(config.mxlen.size, 12); + csrReadCsr.addr <= mux(dbgCsrSel!, dbgRegAddr12!, csrRead.addr); + csrReadCsr.en <= mux(dbgCsrSel, Const(1), csrRead.en); + // Feed the CSR read result back to the pipeline and to the debugger. + csrRead.data <= csrReadCsr.data; + csrRead.done <= csrReadCsr.done; + csrRead.valid <= csrReadCsr.valid; + dbgCsrData <= csrReadCsr.data; + } else { + csrReadCsr = csrRead; + } + + // satp shadow register. The CsrTop backdoor read (csrs.satp) only reflects + // the register during a write and reads X otherwise, so snapshot the + // architectural satp write into a stable register the MMU walks against. + // (satp has a full WARL mask, so the raw write data is the value.) + final satpShadow = Logic(name: 'satpShadow', width: config.mxlen.size); + if (config.mmu.hasPaging) { + Sequential(clk, [ + If( + reset, + then: [satpShadow < 0], + orElse: [ + If( + csrWrite.en & + csrWrite.addr + .slice(11, 0) + .eq(Const(CsrAddress.satp.address, width: 12)) & + (virt == null ? Const(1) : ~virt), + then: [satpShadow < csrWrite.data], + ), + ], + ), + ]); + } else { + satpShadow <= Const(0, width: config.mxlen.size); + } + + // VS-stage page-table root for guest (virt=1) data accesses. Snapshotted + // from HS-mode writes to vsatp, same shadow trick as satpShadow. + final vsatpShadow = Logic(name: 'vsatpShadow', width: config.mxlen.size); + if (config.hasHypervisor && config.mmu.hasPaging) { + Sequential(clk, [ + If( + reset, + then: [vsatpShadow < 0], + orElse: [ + If( + csrWrite.en & + (csrWrite.addr + .slice(11, 0) + .eq(Const(CsrAddress.vsatp.address, width: 12)) | + (csrWrite.addr + .slice(11, 0) + .eq(Const(CsrAddress.satp.address, width: 12)) & + (virt ?? Const(0)))), + then: [vsatpShadow < csrWrite.data], + ), + ], + ), + ]); + } else { + vsatpShadow <= Const(0, width: config.mxlen.size); + } + + // G-stage root (hgatp), snapshotted from HS-mode writes. Same MODE/PPN + // layout as satp. Feeds the MMU's two-stage walk when virt=1. + final hgatpShadow = Logic(name: 'hgatpShadow', width: config.mxlen.size); + if (config.hasHypervisor && config.mmu.hasPaging) { + Sequential(clk, [ + If( + reset, + then: [hgatpShadow < 0], + orElse: [ + If( + csrWrite.en & + csrWrite.addr + .slice(11, 0) + .eq(Const(CsrAddress.hgatp.address, width: 12)), + then: [hgatpShadow < csrWrite.data], + ), + ], + ), + ]); + } else { + hgatpShadow <= Const(0, width: config.mxlen.size); + } + + // Trap save-state / xRET restore controls, driven from the pipeline's + // retire-cycle outputs below (forward-declared so they can feed the CSR file + // which is built before the pipeline). + final xlen = config.mxlen.size; + final csrTrapActive = Logic(name: 'csrTrapActive'); + final csrTrapTargetIsM = Logic(name: 'csrTrapTargetIsM'); + final csrTrapPc = Logic(name: 'csrTrapPc', width: xlen); + final csrTrapCauseVal = Logic(name: 'csrTrapCauseVal', width: xlen); + final csrTrapTval = Logic(name: 'csrTrapTval', width: xlen); + final csrReturnActive = Logic(name: 'csrReturnActive'); + final csrReturnFromM = Logic(name: 'csrReturnFromM'); + // A trap delegated to VS-mode (virt stays 1, target vstvec, save to vs*). + final csrTrapToVS = config.hasHypervisor + ? Logic(name: 'csrTrapToVS') + : null; + + final csrs = config.hasCsrs ? RiscVCsrFile( clk, reset, mode, mxlen: config.mxlen, - misa: - config.extensions - .map((ext) => ext.mask) - .fold(0, (t, i) => t | i) | - config.mxlen.misa | - ((config.hasSupervisor ? 1 : 0) << 18) | - ((config.hasUser ? 1 : 0) << 20), + misa: config.isa.misaValue, mvendorid: config.vendorId, marchid: config.archId, mimpid: config.impId, mhartid: config.hartId, + rpipelineCap: config.rpipelineCap, externalPending: externalPending, hasSupervisor: config.hasSupervisor, hasUser: config.hasUser, + hasHypervisor: config.hasHypervisor, + hasStateen: config.hasStateen, hasPaging: config.mmu.hasPaging, - hasMxr: config.mmu.hasMxr, - hasSum: config.mmu.hasSum, - csrRead: csrRead, + hasMxr: config.mmu.hasMakeExecutableReadable, + hasSum: config.mmu.hasSupervisorUserMemory, + trapActive: csrTrapActive, + trapTargetIsM: csrTrapTargetIsM, + trapPc: csrTrapPc, + trapCauseVal: csrTrapCauseVal, + trapTval: csrTrapTval, + returnActive: csrReturnActive, + returnFromM: csrReturnFromM, + virtInput: config.hasHypervisor ? virt : null, + trapToVS: csrTrapToVS, + csrRead: csrReadCsr, csrWrite: csrWrite, ) : null; @@ -257,49 +769,291 @@ class RiverCoreIP extends BridgeModule { pageTableAddress <= Const(0, width: config.mxlen.size); } + // satp.MODE / root PPN for the MMU come from the stable shadow register. + // In guest (virt=1) mode, data accesses translate through vsatp not HS satp. + final effectiveSatp = guestAccessWire == null + ? satpShadow + : mux(guestAccessWire, vsatpShadow, satpShadow); + satpModeWire <= + ((effectiveSatp >> + Const( + config.mxlen.satpModeShift, + width: config.mxlen.size, + )) & + Const(config.mxlen.satpModeMask, width: config.mxlen.size)) + .slice(3, 0); + satpRootWire <= + (effectiveSatp & + Const(config.mxlen.satpPpnMask, width: config.mxlen.size)); + + if (gModeWire != null) { + gModeWire <= + ((hgatpShadow >> + Const( + config.mxlen.satpModeShift, + width: config.mxlen.size, + )) & + Const(config.mxlen.satpModeMask, width: config.mxlen.size)) + .slice(3, 0); + gRootWire! <= + (hgatpShadow & + Const(config.mxlen.satpPpnMask, width: config.mxlen.size)); + } + if (csrs != null) { enableMxr <= ((csrs.mstatus >> 19) & Const(1, width: config.mxlen.size)).neq(0); enableSum <= ((csrs.mstatus >> 18) & Const(1, width: config.mxlen.size)).neq(0); } + // DTLBFC bit (rpipelinectl[3]) -> MMU data-TLB priv-change flush. + dtlbFlushOnPriv <= (csrs == null ? Const(0) : csrs.rpipelinectl[3]); + // Microcode ROMs (optionally PATCHABLE at runtime via the rmicrocode* CSRs). final microcodeDecodeRead = DataPortInterface( - config.microcode.patternWidth, - config.microcode.map.length.bitLength, + microcode.patternWidth, + microcode.map.length.bitLength, + ); + final microcodeExecRead = DataPortInterface( + microcode.mopWidth(config.mxlen), + microcode.mopIndexWidth(config.mxlen), ); - if (config.microcodeMode.onDecoder != MicrocodePipelineMode.none) { - RegisterFile( - clk, - reset, - [], - [microcodeDecodeRead], - numEntries: config.microcode.map.length, - resetValue: config.microcode.encodedPatterns, - definitionName: 'RiverMicrocodeLookup', + final decodeRowW = microcode.patternWidth; + final decodeIdxW = microcode.map.length.bitLength; + final execRowW = microcode.mopWidth(config.mxlen); + final execIdxW = microcode.mopIndexWidth(config.mxlen); + + // Runtime microcode update: a ROM row can be wider than XLEN, so the CPU + // shifts the row in over rmicrocodedata (XLEN bits per push) and commits it + // into the selected ROM. The rmicrocodectl strobes come from the csrWrite + // write-pulse for that address, so each fires for one cycle and never + // re-triggers. Built only when the core has CSRs and a microcode ROM. + DataPortInterface? decodeWrite; + DataPortInterface? execWrite; + if (csrs != null && config.microcodeMode != MicrocodeMode.none) { + final xlen = config.mxlen.size; + final stagingW = decodeRowW > execRowW ? decodeRowW : execRowW; + final staging = Logic(name: 'microcodeStaging', width: stagingW); + + final isCtl = csrWrite.addr.eq( + Const(CsrAddress.rmicrocodectl.address, width: csrWrite.addr.width), ); + final pulse = csrWrite.en & isCtl; + final push = pulse & csrWrite.data[0]; + final commit = pulse & csrWrite.data[1]; + final clear = pulse & csrWrite.data[2]; + + final patchAddr = csrs.rmicrocodeaddr; + final patchData = csrs.rmicrocodedata; + // bit[XLEN-1] of the address selects the decode ROM (1) vs exec ROM (0). + final targetDecode = patchAddr[xlen - 1]; + + Sequential(clk, reset: reset, [ + If( + clear, + then: [staging < 0], + orElse: [ + If( + push, + then: [ + staging < ((staging << xlen) | patchData.zeroExtend(stagingW)), + ], + ), + ], + ), + ]); + + if (config.microcodeMode.onDecoder != MicrocodePipelineMode.none) { + decodeWrite = DataPortInterface(decodeRowW, decodeIdxW); + decodeWrite.en <= commit & targetDecode; + decodeWrite.addr <= patchAddr.slice(decodeIdxW - 1, 0); + decodeWrite.data <= staging.slice(decodeRowW - 1, 0); + } + if (config.microcodeMode.onExec != MicrocodePipelineMode.none) { + execWrite = DataPortInterface(execRowW, execIdxW); + execWrite.en <= commit & ~targetDecode; + execWrite.addr <= patchAddr.slice(execIdxW - 1, 0); + execWrite.data <= staging.slice(execRowW - 1, 0); + } } - final microcodeExecRead = DataPortInterface( - config.microcode.mopWidth(config.mxlen), - config.microcode.mopIndexWidth(config.mxlen), - ); + if (config.microcodeMode.onDecoder != MicrocodePipelineMode.none) { + // Decode pattern ROM (microcode.map.length x decodeRowW ~= 18k FF as a + // resetValue RegisterFile). On ECP5 a DP16KD ROM (registered read), + // elsewhere a flop ROM with a pipeline register so both paths have read + // latency 1. done/valid lag `en` by 1 to match; the decoder holds its + // address until `done`, so the registered read costs one fill cycle/probe. + final useEbrRom = + target is HarborFpgaTarget && target.vendor == HarborFpgaVendor.ecp5; + final useXilinxRom = + target is HarborFpgaTarget && + (target.vendor == HarborFpgaVendor.openXc7 || + target.vendor == HarborFpgaVendor.vivado); + + if (useEbrRom) { + final rom = Ecp5InitRom( + clk, + contents: microcode.encodedPatterns, + width: decodeRowW, + rdAddr: microcodeDecodeRead.addr, + wrEn: decodeWrite?.en, + wrAddr: decodeWrite?.addr, + wrData: decodeWrite?.data, + definitionName: 'RiverMicrocodeLookup', + ); + microcodeDecodeRead.data <= rom.rdData; + } else if (useXilinxRom) { + // Xilinx: a behavioural BRAM-inferable ROM (synth_xilinx -> RAMB) so + // the decode ROM does not explode into flops. + final rom = InferredInitRom( + clk, + contents: microcode.encodedPatterns, + width: decodeRowW, + rdAddr: microcodeDecodeRead.addr, + wrEn: decodeWrite?.en, + wrAddr: decodeWrite?.addr, + wrData: decodeWrite?.data, + definitionName: 'RiverMicrocodeLookup', + ); + microcodeDecodeRead.data <= rom.rdData; + } else { + final decodeRaw = DataPortInterface(decodeRowW, decodeIdxW); + decodeRaw.en <= microcodeDecodeRead.en; + decodeRaw.addr <= microcodeDecodeRead.addr; + RegisterFile( + clk, + reset, + decodeWrite != null ? [wrapWriteForRegisterFile(decodeWrite)] : [], + [wrapReadForRegisterFile(decodeRaw)], + numEntries: microcode.map.length, + resetValue: microcode.encodedPatterns, + definitionName: 'RiverMicrocodeLookup', + ); + final decodeDataReg = Logic( + name: 'microcodeDecodeDataReg', + width: decodeRowW, + ); + Sequential(clk, [decodeDataReg < decodeRaw.data]); + microcodeDecodeRead.data <= decodeDataReg; + } + + final decodeHsReg = Logic(name: 'microcodeDecodeHsReg'); + Sequential(clk, reset: reset, [decodeHsReg < microcodeDecodeRead.en]); + microcodeDecodeRead.done <= microcodeDecodeRead.en & decodeHsReg; + microcodeDecodeRead.valid <= microcodeDecodeRead.en & decodeHsReg; + } if (config.microcodeMode.onExec != MicrocodePipelineMode.none) { - final mops = config.microcode.encodedMops(config.mxlen); + final mops = microcode.encodedMops(config.mxlen); - RegisterFile( - clk, - reset, - [], - [microcodeExecRead], - numEntries: mops.length, - resetValue: mops, - definitionName: 'RiverMicrocodeOperations', - ); + // Pipeline the exec ROM read: the addr -> ROM -> funct-decode + ALU-tree + // path is the microcode Fmax bottleneck. Register the ROM data so + // addr->ROM and ROM-data->ALU are separate stages, and delay the read + // handshake to match (one extra read-latency cycle; the exec FSM already + // stalls on done/valid). valid is gated by `en` so the registered + // handshake does not leave a stale valid high after en deasserts. + // The exec ROM is the largest memory in the core (mops.length x execRowW): + // as a flop RegisterFile ~94k FF, 4x the whole LFE5U-25F. On ECP5 it MUST + // be EBR (DP16KD, contents baked in via INITVAL); port B's registered read + // IS the pipeline stage (1-cycle, matching the sim combinational-ROM + + // execDataReg), the update-CSR write goes to port A. Sim has no DP16KD + // model, so non-ECP5 targets keep the flop ROM (microcode via resetValue). + final useEbrRom = + target is HarborFpgaTarget && target.vendor == HarborFpgaVendor.ecp5; + final useXilinxRom = + target is HarborFpgaTarget && + (target.vendor == HarborFpgaVendor.openXc7 || + target.vendor == HarborFpgaVendor.vivado); + + if (useEbrRom) { + final rom = Ecp5InitRom( + clk, + contents: mops, + width: execRowW, + rdAddr: microcodeExecRead.addr, + wrEn: execWrite?.en, + wrAddr: execWrite?.addr, + wrData: execWrite?.data, + definitionName: 'RiverMicrocodeOperations', + ); + microcodeExecRead.data <= rom.rdData; + } else if (useXilinxRom) { + // Xilinx: BRAM-inferable ROM instead of the ~94k-FF flop RegisterFile. + final rom = InferredInitRom( + clk, + contents: mops, + width: execRowW, + rdAddr: microcodeExecRead.addr, + wrEn: execWrite?.en, + wrAddr: execWrite?.addr, + wrData: execWrite?.data, + definitionName: 'RiverMicrocodeOperations', + ); + microcodeExecRead.data <= rom.rdData; + } else { + final execRaw = DataPortInterface(execRowW, execIdxW); + execRaw.en <= microcodeExecRead.en; + execRaw.addr <= microcodeExecRead.addr; + + RegisterFile( + clk, + reset, + execWrite != null ? [wrapWriteForRegisterFile(execWrite)] : [], + [wrapReadForRegisterFile(execRaw)], + numEntries: mops.length, + resetValue: mops, + definitionName: 'RiverMicrocodeOperations', + ); + + final execDataReg = Logic( + name: 'microcodeExecDataReg', + width: execRowW, + ); + Sequential(clk, [execDataReg < execRaw.data]); + microcodeExecRead.data <= execDataReg; + } + + final execHsReg = Logic(name: 'microcodeExecHsReg'); + Sequential(clk, reset: reset, [execHsReg < microcodeExecRead.en]); + microcodeExecRead.done <= microcodeExecRead.en & execHsReg; + microcodeExecRead.valid <= microcodeExecRead.en & execHsReg; + } + + // Multiple-outstanding fetch port (decoupled, latency-agnostic). When + // fetchOutstanding > 1, fetch runs over a decoupled request/response port + // the PipelinedFetchUnit drives, keeping several reads in flight (the + // unified bus/icache is single-outstanding). Exposed at the core boundary so + // the system can attach any fetch memory (fixed-latency BRAM/TCM or a + // variable-latency DRAM/cache/AXI source) driving rsp_valid/req_ready; the + // core makes no latency assumption. + FetchReadInterface? fetchReadPort; + if (config.fetchOutstanding > 1) { + // Instructions are 32-bit, so the fetch port carries a 32-bit word with an + // mxlen-wide address (one instruction per fetch, no 64-bit packing). + final aw = config.mxlen.size; + addOutput('fetchReq_valid'); + addOutput('fetchReq_addr', width: aw); + createPort('fetchReq_ready', PortDirection.input); + createPort('fetchRsp_valid', PortDirection.input); + createPort('fetchRsp_data', PortDirection.input, width: 32); + + fetchReadPort = FetchReadInterface(32, aw); + output('fetchReq_valid') <= fetchReadPort.reqValid; + output('fetchReq_addr') <= fetchReadPort.reqAddr; + fetchReadPort.reqReady <= input('fetchReq_ready'); + fetchReadPort.rspValid <= input('fetchRsp_valid'); + fetchReadPort.rspData <= input('fetchRsp_data'); } + // Backdoor prf seed: when prfSeedMode is asserted (frozen seed window), an + // architectural regWritePort write also seeds the OoO physical regfile at + // the same (arch == phys under the reset-identity rename map) index. + final prfSeedModeIn = prfSeedMode == null + ? null + : addInput('prfSeedMode', prfSeedMode); + + // Pipeline. pipeline = RiverPipeline( clk, reset, @@ -307,12 +1061,11 @@ class RiverCoreIP extends BridgeModule { sp, pc, mode, - config.type.hasCsrs ? csrRead : null, - config.type.hasCsrs ? csrWrite : null, - // TODO: have a cache backed memory interface - mmuFetchRead, - mmuExecRead, - sizedMmuWrite, + config.hasCsrs ? csrRead : null, + config.hasCsrs ? csrWrite : null, + pipeFetchRead, + pipeExecRead, + pipeExecWrite, rs1Read, rs2Read, rdWrite, @@ -322,59 +1075,303 @@ class RiverCoreIP extends BridgeModule { config.microcodeMode.onExec != MicrocodePipelineMode.none ? microcodeExecRead : null, + useOoO: config.executionMode == ExecutionMode.outOfOrder, useMixedDecoders: - config.microcodeMode.onDecoder == MicrocodePipelineMode.in_parallel, + config.microcodeMode.onDecoder == MicrocodePipelineMode.inParallel, useMixedExecution: - config.microcodeMode.onExec == MicrocodePipelineMode.in_parallel, - microcode: config.microcode, + config.microcodeMode.onExec == MicrocodePipelineMode.inParallel, + microcode: microcode, mxlen: config.mxlen, + vlen: config.vlen, hasSupervisor: config.hasSupervisor, hasUser: config.hasUser, - hasCompressed: config.extensions.any((e) => e.name == 'RVC'), + hasCompressed: config.extensions.any((e) => e.name == 'C'), mideleg: csrs?.mideleg, medeleg: csrs?.medeleg, mtvec: csrs?.mtvec, stvec: csrs?.stvec, + mepc: csrs?.mepc, + sepc: (csrs != null && config.hasSupervisor) ? csrs.sepc : null, + virt: virt, + mstateen0Se0: csrs?.mstateen0Se0, + hstateen0Se0: csrs?.hstateen0Se0, + memFaultGuest: config.hasHypervisor ? mmu.dportFaultGuest : null, + specCtl: csrs?.rpipelinectl.getRange(0, 4), + prfSeedEn: prfSeedModeIn == null ? null : (prfSeedModeIn & rdWrite.en), + prfSeedAddr: prfSeedModeIn == null ? null : rdWrite.addr, + prfSeedData: prfSeedModeIn == null ? null : rdWrite.data, + ifetchFault: (config.mmu.hasPaging && !useICache) + ? mmu.ifetchFault + : null, + rdWrite1: rdWrite1, + wr0Ready: wr0Ready, + wr1Ready: wr1Ready, + speculative: config.speculativeFetch, + dualDispatch: dualDispatch, + prefetchFetch: config.prefetchFetch, + prefetchDepth: config.prefetchDepth, + fetchOutstanding: config.fetchOutstanding, + fetchReadPort: fetchReadPort, + branchPredictor: config.branchPredictor, + loadStoreQueue: config.loadStoreQueue, + robDepth: config.robDepth, + storeQueueDepth: config.storeQueueDepth, + loadQueueDepth: config.loadQueueDepth, + memFetchRead1: pipeFetchRead1, staticInstructions: staticInstructions, ); - Sequential(clk, [ + // Flush the instruction cache on fence.i (the pipeline's fence signal). + icFlush <= pipeline.fence; + mmuTlbFlush <= pipeline.fence; + // Flush the D-cache on the same fence. It is virtually addressed, so a fence + // drops any line a translation change could alias, keeping paged-mode data + // coherent without an sfence path (conservative on creek where VA == PA). + if (useDCache) dFlush <= pipeline.fence; + + // An access is guest-translated when the core is virtualized OR the current + // access is an HLV/HSV (memGuest). Drives the MMU's VS/G-stage routing. + if (guestAccessWire != null) { + guestAccessWire <= virt! | pipeline.memGuest; + } + + // Drive the CSR file's trap/return controls from the pipeline retire-cycle + // outputs. `committing` matches the PC-latch gate so each event fires once. + if (csrs != null) { + // One-shot commit: pipelineEnable is 1 only on the first done cycle. + final committing = ~interruptHold & pipeline.done & pipelineEnable; + // An ebreak commits as a breakpoint trap (cause 3). If dcsr.ebreak* is set + // for the current privilege, redirect it to Debug Mode: suppress the + // architectural trap and let the halt FSM latch dpc/cause. + Logic trapSuppress = Const(0); + if (withDebug) { + final ebreakForMode = + (mode.eq(Const(PrivilegeMode.machine.id, width: 3)) & + debugDcsr![15]) | + (mode.eq(Const(PrivilegeMode.supervisor.id, width: 3)) & + debugDcsr[13]) | + (mode.eq(Const(PrivilegeMode.user.id, width: 3)) & debugDcsr[12]); + ebreakDebug! <= + committing & + pipeline.trap & + pipeline.trapCause.eq(Const(3, width: 6)) & + ebreakForMode; + trapSuppress = ebreakDebug; + } + csrTrapActive <= committing & pipeline.trap & ~trapSuppress; + csrTrapTargetIsM <= + pipeline.nextMode.eq(Const(PrivilegeMode.machine.id, width: 3)); + csrTrapPc <= pipeline.trapEpc; + csrTrapCauseVal <= pipeline.trapCause.zeroExtend(xlen); + csrTrapTval <= pipeline.trapTval; + csrReturnActive <= committing & pipeline.isReturn; + csrReturnFromM <= pipeline.returnLevel.eq(Const(3, width: 3)); + if (csrTrapToVS != null) { + // exec already routed this trap to S (medeleg-delegated); upgrade to VS + // when virtualized and hedeleg further delegates this cause. + csrTrapToVS <= + committing & + pipeline.trap & + virt! & + pipeline.nextMode.eq( + Const(PrivilegeMode.supervisor.id, width: 3), + ) & + csrs.hedeleg![pipeline.trapCause]; + } + } else { + csrTrapActive <= Const(0); + csrTrapTargetIsM <= Const(0); + csrTrapPc <= Const(0, width: xlen); + csrTrapCauseVal <= Const(0, width: xlen); + csrTrapTval <= Const(0, width: xlen); + csrReturnActive <= Const(0); + csrReturnFromM <= Const(0); + } + + // xRET PC/mode restore values (read combinationally from the CSR backdoor). + final retPc = csrs == null + ? pipeline.nextPc + : mux( + csrReturnFromM, + csrs.mepc, + config.hasSupervisor ? csrs.sepc : Const(0, width: xlen), + ); + final retMode = csrs == null + ? pipeline.nextMode + : mux( + csrReturnFromM, + // MPP = mstatus[12:11] + csrs.mstatus.slice(12, 11).zeroExtend(3), + // SPP = sstatus[8] ? supervisor : user + config.hasSupervisor + ? mux( + csrs.sstatus![8], + Const(PrivilegeMode.supervisor.id, width: 3), + Const(PrivilegeMode.user.id, width: 3), + ) + : Const(PrivilegeMode.machine.id, width: 3), + ); + + // V-bit restore on xRET: MRET enters virt iff MPP!=M and mstatus.MPV; an + // HS-mode SRET (virt=0) enters the guest iff hstatus.SPV (a guest-mode SRET + // keeps virt=1). Trap entry clears virt. + final retVirt = (csrs == null || !config.hasHypervisor) + ? Const(0) + : mux( + csrReturnFromM, + retMode.neq(Const(PrivilegeMode.machine.id, width: 3)) & + csrs.mstatus[39], + mux(virt!, Const(1), csrs.hstatus![7]), + ); + + // VS-delegated trap vector (vstvec base, direct mode). The trap stays in + // VS-mode (virt=1) and saves to vs* (handled in the CSR file). + final vsTrapPc = (csrTrapToVS == null) + ? Const(0, width: xlen) + : (csrs!.vstvec! & ~Const(0x3, width: xlen)); + + // Core state machine. The normal (non-halted) advance body, captured so + // debug-halt can gate it. + final coreBody = [ If( - reset, + interruptHold & externalPending, + then: [interruptHold < 0, pipelineEnable < 1, fence < 0], + ), + If( + ~interruptHold, then: [ - pipelineEnable < 0, - pc < config.resetVector, - sp < 0, - mode < 0, - fence < 0, - interruptHold < 0, - ], - orElse: [ - If( - interruptHold & externalPending, - then: [interruptHold < 0, pipelineEnable < 1, fence < 0], - ), - + // Commit exactly once: pipeline.done can stay asserted for several + // drain cycles, but pipelineEnable is 1 only on the first done cycle. + // Critical for xRET/trap where the commit mutates CSR state (mstatus + // pop); a second fire would read the popped value and corrupt the mode. If( - ~interruptHold, + pipeline.done & pipelineEnable, then: [ + // On xRET, restore PC/mode from {m,s}epc/{m,s}status; the CSR + // file pops the status stack in parallel. Otherwise advance + // normally (doTrap already redirected nextPc to tvec). If( - pipeline.done, + pipeline.isReturn, then: [ - pc < pipeline.nextPc, - sp < pipeline.nextSp, + pc < retPc, + mode < retMode, + if (virt != null) virt < retVirt, + ], + orElse: [ + // A trap delegated to VS-mode targets vstvec and STAYS + // virtualized; all other traps go to HS/M and clear virt. + pc < + (csrTrapToVS == null + ? pipeline.nextPc + : mux(csrTrapToVS, vsTrapPc, pipeline.nextPc)), mode < pipeline.nextMode, - interruptHold < pipeline.interruptHold, - fence < pipeline.fence, - pipelineEnable < 0, + if (virt != null) + virt < mux(pipeline.trap, csrTrapToVS ?? Const(0), virt), ], - orElse: [pipelineEnable < 1, fence < 0], ), + sp < pipeline.nextSp, + interruptHold < pipeline.interruptHold, + fence < pipeline.fence, + // Lockstep commits once then drops enable to force a re-fetch. + // Speculative fetch keeps the pipeline enabled and self-sequences, + // so the commit fires every `done` cycle (distinct instructions). + if (!config.speculativeFetch) pipelineEnable < 0, ], - orElse: [pipelineEnable < 0, fence < 0], ), + // Re-enable the pipeline once `done` drops (the next fetch is + // underway); do not re-enable during the drain cycles. + If(~pipeline.done, then: [pipelineEnable < 1, fence < 0]), ], + orElse: [pipelineEnable < 0, fence < 0], + ), + ]; + + Sequential(clk, [ + If( + reset, + then: [ + pipelineEnable < 0, + pc < config.resetVector, + sp < 0, + // RISC-V resets to machine mode (PrivilegeMode.machine == 3). + mode < PrivilegeMode.machine.id, + if (virt != null) virt < 0, + fence < 0, + interruptHold < 0, + if (withDebug) debugHalted! < 0, + if (withDebug) debugDpc! < config.resetVector, + // dcsr reset: debugver=4 (0.13.2), prv=3 (machine), cause=0. + if (withDebug) debugDcsr! < Const(0x40000003, width: 32), + ], + orElse: withDebug + ? [ + // While halted, freeze the pipeline and hold the PC; resume on + // the debugger's request. Otherwise enter debug mode at the + // next instruction boundary on haltreq, latching dpc. + If( + debugHalted!, + then: [ + pipelineEnable < 0, + // A debugger may rewrite dpc to redirect where we resume. + If( + input('debug_reg_write') & dbgIsDpc!, + then: [debugDpc! < dbgRegWdata!], + ), + // A debugger may write dcsr (ebreak/step/prv bits). debugver + // (31:28) is read-only and cause (8:6) is hardware-set, so + // force the former and preserve the latter on every write. + If( + input('debug_reg_write') & dbgIsDcsr!, + then: [ + debugDcsr! < + (dbgRegWdata.getRange(0, 32) & + Const(0x0FFFFE3F, width: 32)) | + Const(0x40000000, width: 32) | + (debugDcsr & Const(0x000001C0, width: 32)), + ], + ), + If(resumeReqIn!, then: [debugHalted < 0, pc < debugDpc]), + ], + orElse: [ + If( + haltReqIn!, + then: [ + debugHalted < 1, + pipelineEnable < 0, + debugDpc < pc, + // Halt cause = 3 (haltreq); keep the other dcsr bits. + debugDcsr < + (debugDcsr & Const(0xFFFFFE3F, width: 32)) | + Const(3 << 6, width: 32), + ], + orElse: [ + If( + ebreakDebug!, + then: [ + // ebreak entered Debug Mode: freeze at the ebreak, + // latch its pc into dpc, cause = 1 (ebreak). + debugHalted < 1, + pipelineEnable < 0, + debugDpc < pipeline.trapEpc, + debugDcsr < + (debugDcsr & Const(0xFFFFFE3F, width: 32)) | + Const(1 << 6, width: 32), + ], + orElse: coreBody, + ), + ], + ), + ], + ), + ] + : coreBody, ), ]); + + // Expose the V-bit for observability (no behavioral effect until VS-mode / + // two-stage translation consume it). + if (virt != null) { + addOutput('virt') <= virt; + } } } diff --git a/packages/river_hdl/lib/src/core/alu_ops.dart b/packages/river_hdl/lib/src/core/alu_ops.dart new file mode 100644 index 0000000..ccab4a7 --- /dev/null +++ b/packages/river_hdl/lib/src/core/alu_ops.dart @@ -0,0 +1,169 @@ +// Width-generic combinational building blocks: bit manipulation (Zbb/Zba/Zbs) +// plus the M-family multiply/divide helpers (BmMulSet, bmDiv*/bmRem*), shared +// by the in-order ALU (exec.dart) and the out-of-order ALU (fu_alu.dart) so +// both datapaths compute the same results. `w` is the operand width in bits. +import 'package:rohd/rohd.dart'; + +/// Population count (number of set bits), result [w] bits wide. +Logic bmPopcount(Logic x, int w) => + [for (var i = 0; i < w; i++) x[i].zeroExtend(w)].reduce((a, b) => a + b); + +/// Count leading zeros: smear the highest set bit downward, then w - popcount. +Logic bmClz(Logic x, int w) { + var y = x; + for (var s = 1; s < w; s <<= 1) { + y = y | (y >>> s); + } + return Const(w, width: w) - bmPopcount(y, w); +} + +/// Count trailing zeros: popcount of the trailing-zero mask `(x-1) & ~x`. +Logic bmCtz(Logic x, int w) => bmPopcount((x - Const(1, width: w)) & ~x, w); + +/// Signed less-than: differing signs pick a's sign bit, same signs use the +/// unsigned comparison. +Logic bmSignedLt(Logic a, Logic b, int w) { + final sa = a[w - 1]; + final differ = sa ^ b[w - 1]; + return mux(differ, sa, a.lt(b)); +} + +/// Rotate right by `b mod w` (complement shift masked to stay in [0, w)). +Logic bmRotr(Logic a, Logic b, int w) { + final s = b & Const(w - 1, width: w); + final cs = (Const(w, width: w) - s) & Const(w - 1, width: w); + return (a >>> s) | (a << cs); +} + +/// Rotate left by `b mod w`. +Logic bmRotl(Logic a, Logic b, int w) { + final s = b & Const(w - 1, width: w); + final cs = (Const(w, width: w) - s) & Const(w - 1, width: w); + return (a << s) | (a >>> cs); +} + +/// orc.b: each byte becomes 0xFF if any bit is set, else 0x00. +Logic bmOrcb(Logic x, int w) => [ + for (var i = 0; i < w ~/ 8; i++) + mux( + x.slice(i * 8 + 7, i * 8).or(), + Const(0xFF, width: 8), + Const(0, width: 8), + ), +].reversed.toList().swizzle(); + +/// rev8: reverse byte order. +Logic bmRev8(Logic x, int w) => + [for (var i = 0; i < w ~/ 8; i++) x.slice(i * 8 + 7, i * 8)].swizzle(); + +Logic _abs(Logic x, int w) => mux(x[w - 1], ~x + Const(1, width: w), x); + +/// One shared multiplier for the whole mul family. A single ZERO-extended +/// product (which synthesis folds to a w*w array, unlike sign-extended +/// operands) yields every flavor through the modular identity +/// +/// high_ss = hiUU - (a<0 ? b : 0) - (b<0 ? a : 0) (mod 2^w) +/// high_su = hiUU - (a<0 ? b : 0) +/// +/// so mulh/mulhsu/mulhu cost two w-wide subtractors instead of three +/// separate 2w-wide multiplier arrays. `low` serves mul and mulw. +class BmMulSet { + /// Low w bits of the product (identical for every signedness flavor). + late final Logic low; + + /// High w bits, both operands signed (mulh). + late final Logic highSS; + + /// High w bits, a signed and b unsigned (mulhsu). + late final Logic highSU; + + /// High w bits, both unsigned (mulhu). + late final Logic highUU; + + BmMulSet(Logic a, Logic b, int w) { + final z = Const(0, width: w); + final uu = a.zeroExtend(w * 2) * b.zeroExtend(w * 2); + low = uu.slice(w - 1, 0); + highUU = uu.slice(w * 2 - 1, w); + highSU = highUU - mux(a[w - 1], b, z); + highSS = highSU - mux(b[w - 1], a, z); + } +} + +/// Unsigned divide with RISC-V div-by-zero result (all ones). The divisor is +/// forced to 1 when zero so the hardware divider never divides by zero. +Logic bmDivU(Logic a, Logic b, int w) { + final z = Const(0, width: w); + return mux(b.eq(z), ~z, a / mux(b.eq(z), Const(1, width: w), b)); +} + +/// Unsigned remainder with RISC-V div-by-zero result (the dividend). +Logic bmRemU(Logic a, Logic b, int w) { + final z = Const(0, width: w); + return mux(b.eq(z), a, a % mux(b.eq(z), Const(1, width: w), b)); +} + +/// Signed divide (truncating toward zero). div-by-zero => all ones; +/// overflow (INT_MIN / -1) => INT_MIN. +Logic bmDivS(Logic a, Logic b, int w) { + final z = Const(0, width: w); + final allOnes = ~z; // also == -1 + final intMin = Const(1, width: w) << (w - 1); + final ub = _abs(b, w); + final q = _abs(a, w) / mux(ub.eq(z), Const(1, width: w), ub); + final res = mux(a[w - 1] ^ b[w - 1], ~q + Const(1, width: w), q); + return mux(b.eq(z), allOnes, mux(a.eq(intMin) & b.eq(allOnes), intMin, res)); +} + +/// Signed remainder (sign of dividend). div-by-zero => dividend; overflow => 0. +Logic bmRemS(Logic a, Logic b, int w) { + final z = Const(0, width: w); + final allOnes = ~z; + final intMin = Const(1, width: w) << (w - 1); + final ub = _abs(b, w); + final r = _abs(a, w) % mux(ub.eq(z), Const(1, width: w), ub); + final res = mux(a[w - 1], ~r + Const(1, width: w), r); + return mux(b.eq(z), a, mux(a.eq(intMin) & b.eq(allOnes), z, res)); +} + +// Iterative-divider result fixups. The in-order core runs one shared multi-cycle +// IterativeDivider over unsigned magnitudes, then applies the same sign/edge +// handling as bmDiv*/bmRem* here on the magnitude quotient [q] (= |a|/|b|, b +// forced non-zero) or remainder [r]. Results match bmDiv*/bmRem* bit for bit. + +/// Unsigned magnitude |x| of a signed w-bit value, exposed so the divider's +/// pre-stage can feed magnitudes. |INT_MIN| wraps to INT_MIN, whose unsigned +/// value 2^(w-1) is the correct magnitude. +Logic bmAbs(Logic x, int w) => _abs(x, w); + +/// Unsigned divide fixup: div-by-zero yields all ones, else the quotient. +Logic divFixupU(Logic a, Logic b, Logic q, int w) { + final z = Const(0, width: w); + return mux(b.eq(z), ~z, q); +} + +/// Unsigned remainder fixup: div-by-zero yields the dividend, else the remainder. +Logic remFixupU(Logic a, Logic b, Logic r, int w) { + final z = Const(0, width: w); + return mux(b.eq(z), a, r); +} + +/// Signed divide fixup over magnitude quotient [q] (= |a|/|b|): apply the result +/// sign, then div-by-zero (all ones) and INT_MIN/-1 overflow (INT_MIN) corners. +Logic divFixupS(Logic a, Logic b, Logic q, int w) { + final z = Const(0, width: w); + final allOnes = ~z; + final intMin = Const(1, width: w) << (w - 1); + final res = mux(a[w - 1] ^ b[w - 1], ~q + Const(1, width: w), q); + return mux(b.eq(z), allOnes, mux(a.eq(intMin) & b.eq(allOnes), intMin, res)); +} + +/// Signed remainder fixup over magnitude remainder [r] (= |a| % |b|): sign of +/// dividend, then div-by-zero (dividend) and INT_MIN/-1 overflow (0) corners. +Logic remFixupS(Logic a, Logic b, Logic r, int w) { + final z = Const(0, width: w); + final allOnes = ~z; + final intMin = Const(1, width: w) << (w - 1); + final res = mux(a[w - 1], ~r + Const(1, width: w), r); + return mux(b.eq(z), a, mux(a.eq(intMin) & b.eq(allOnes), z, res)); +} diff --git a/packages/river_hdl/lib/src/core/compressed_fetch_buffer.dart b/packages/river_hdl/lib/src/core/compressed_fetch_buffer.dart new file mode 100644 index 0000000..9ba4931 --- /dev/null +++ b/packages/river_hdl/lib/src/core/compressed_fetch_buffer.dart @@ -0,0 +1,277 @@ +import 'package:rohd/rohd.dart'; +import '../data_port.dart'; +import 'instruction_aligner.dart'; + +/// Superscalar compressed (variable-length) fetch buffer. +/// +/// Decouples word-granular memory fetch from instruction-granular dispatch so a +/// dual-issue front-end can extract TWO variable-length instructions per cycle. +/// Aligned words stream into a small word FIFO; a halfword offset (`headOff`) +/// tracks the current PC within the head word; a barrel-shifted 4-halfword +/// window feeds an [InstructionAligner] that resolves the two instructions' +/// boundaries. Dispatch consumes 1 or 2 instructions (`consume0`/`consume1`), +/// advancing headOff/head by their byte lengths. A redirect flushes the buffer +/// and restarts at any 2-byte-aligned PC (mid-word offsets supported). +/// +/// This removes the classic dual-fetch `lane1.pc == lane0.pc + 4` assumption, so +/// RV64GC (compressed) can run dual-issue. The read engine is the held-`en`, +/// response-attributed single-outstanding handshake proven in +/// [PrefetchFetchUnit] (see project_hdl_prefetch / project_hdl_interconnect). +class CompressedFetchBuffer extends Module { + Logic get instr0 => output('instr0'); + Logic get pc0 => output('pc0'); + Logic get valid0 => output('valid0'); + Logic get compressed0 => output('compressed0'); + Logic get instr1 => output('instr1'); + Logic get pc1 => output('pc1'); + Logic get valid1 => output('valid1'); + Logic get compressed1 => output('compressed1'); + + /// FIFO depth in words (power of two >= 4 so a 4-halfword window always spans + /// available words even at 32-bit data width). + final int depth; + + CompressedFetchBuffer( + Logic clk, + Logic reset, + Logic enable, + Logic pc, + DataPortInterface memRead, { + Logic? redirect, + Logic? redirectPc, + Logic? consume0, + Logic? consume1, + this.depth = 4, + super.name = 'compressed_fetch_buffer', + }) : super(definitionName: 'CompressedFetchBuffer') { + assert( + depth >= 4 && (depth & (depth - 1)) == 0, + 'word FIFO depth must be a power of two >= 4 (got $depth)', + ); + clk = addInput('clk', clk); + reset = addInput('reset', reset); + enable = addInput('enable', enable); + final w = pc.width; + pc = addInput('pc', pc, width: w); + redirect = addInput('redirect', redirect ?? Const(0)); + redirectPc = addInput( + 'redirect_pc', + redirectPc ?? Const(0, width: w), + width: w, + ); + consume0 = addInput('consume0', consume0 ?? Const(0)); + consume1 = addInput('consume1', consume1 ?? Const(0)); + + memRead = memRead.clone() + ..connectIO( + this, + memRead, + outputTags: {DataPortGroup.control}, + inputTags: {DataPortGroup.data, DataPortGroup.integrity}, + uniquify: (og) => 'memRead_$og', + ); + + addOutput('instr0', width: 32); + addOutput('pc0', width: w); + addOutput('valid0'); + addOutput('compressed0'); + addOutput('instr1', width: 32); + addOutput('pc1', width: w); + addOutput('valid1'); + addOutput('compressed1'); + + final dataW = memRead.data.width; + final wordBytes = dataW ~/ 8; + final wordHalves = dataW ~/ 16; // halfwords per word + final offW = (wordHalves - 1).bitLength; // headOff width + final ptrBits = (depth - 1).bitLength; + final alignMask = Const(~(wordBytes - 1), width: w); + + // -- Word FIFO --------------------------------------------------------- + final wordArr = List.generate( + depth, + (i) => Logic(name: 'word_$i', width: dataW), + ); + final head = Logic(name: 'head', width: ptrBits + 1); + final tail = Logic(name: 'tail', width: ptrBits + 1); + final headIdx = head.slice(ptrBits - 1, 0); + final tailIdx = tail.slice(ptrBits - 1, 0); + final wordCount = (tail - head).named('word_count'); // words buffered + final fifoFull = (headIdx.eq(tailIdx) & (head[ptrBits] ^ tail[ptrBits])) + .named('fifo_full'); + + final headOff = Logic(name: 'head_off', width: offW); // halfword in head wd + final headPc = Logic(name: 'head_pc', width: w); // PC of current head half + final fetchPc = Logic(name: 'fetch_pc', width: w); // next word to read + final reading = Logic(name: 'reading'); + final discard = Logic(name: 'discard'); + final started = Logic(name: 'started'); + + Logic wordAtRel(int rel) { + // wordArr[(head + rel) mod depth] + final idx = (head + Const(rel, width: ptrBits + 1)).slice(ptrBits - 1, 0); + Logic r = wordArr[0]; + for (var i = 1; i < depth; i++) { + r = mux(idx.eq(Const(i, width: ptrBits)), wordArr[i], r); + } + return r; + } + + // 4-halfword (64-bit) window starting at headOff. Concatenate the first + // three buffered words (enough to cover headOff+4 halfwords at any width) + // and barrel-shift right by headOff halfwords. + final cat = [wordAtRel(2), wordAtRel(1), wordAtRel(0)].swizzle(); + // Shift right by headOff halfwords (headOff*16 bits). + final shiftAmt = (headOff.zeroExtend(cat.width) << 4).named( + 'win_shift_amt', + ); + final shifted = (cat >> shiftAmt).named('win_sh'); + final window = shifted.slice(63, 0).named('align_window'); + + // Number of valid halfwords from headOff, capped at 4 (the window width). + // headOff < wordHalves always, so with >= 1 buffered word the subtraction is + // non-negative; with 0 words there are 0 valid halves (guard the underflow). + // Zero-extend BEFORE multiplying: wordCount is only ptrBits+1 bits, so a full + // FIFO (wordCount == depth) times wordHalves would overflow and truncate to 0 + // in wordCount's width, making a full buffer falsely read as empty. + final log2WHb = (wordHalves - 1).bitLength; + final totalHalves = (wordCount.zeroExtend(8) << log2WHb).named( + 'total_halves', + ); + final availHalves = mux( + wordCount.eq(0), + Const(0, width: 8), + totalHalves - headOff.zeroExtend(8), + ).named('avail_halves'); + final validHalves = mux( + availHalves.gt(4), + Const(4, width: 3), + availHalves.slice(2, 0), + ).named('valid_halves'); + + final aligner = InstructionAligner(window, validHalves, laneCount: 4); + + instr0 <= aligner.instr0; + pc0 <= headPc; + valid0 <= aligner.valid0 & enable; + compressed0 <= aligner.compressed0; + instr1 <= aligner.instr1; + // pc1 = headPc + size0*2. + pc1 <= headPc + (aligner.size0.zeroExtend(w) << 1); + valid1 <= aligner.valid1 & enable; + compressed1 <= aligner.compressed1; + + // -- Consume / advance ------------------------------------------------- + final c0 = (consume0 & aligner.valid0 & enable & ~redirect).named('c0'); + final c1 = (c0 & consume1 & aligner.valid1).named('c1'); + // Halfwords consumed this cycle: size0 (if c0) + size1 (if c1). + final consumed = + (mux(c0, aligner.size0.zeroExtend(4), Const(0, width: 4)) + + mux(c1, aligner.size1.zeroExtend(4), Const(0, width: 4))) + .named('consumed_halves'); + // New absolute halfword index = headOff + consumed; split into word-advance + // (>> log2 wordHalves) and new offset (& wordHalves-1). wordHalves is 2^k. + final log2WH = (wordHalves - 1).bitLength; + final newOffFull = (headOff.zeroExtend(4) + consumed).named('new_off_full'); + // Max wordsPopped = (maxHeadOff + maxConsumed)/wordHalves <= 2, so 2 bits. + final wordsPopped = (newOffFull >> log2WH) + .slice(1, 0) + .named('words_popped'); + final newHeadOff = (newOffFull & Const(wordHalves - 1, width: 4)).named( + 'new_head_off', + ); + + // -- Read engine (fill the word FIFO; held-en, response-attributed) ----- + final readDone = (memRead.done & memRead.valid).named('read_done'); + final produce = + (reading & readDone & ~discard & ~redirect & enable & ~fifoFull).named( + 'produce', + ); + final nFetchPc = mux( + produce, + fetchPc + Const(wordBytes, width: w), + fetchPc, + ).named('n_fetch_pc'); + + Sequential(clk, [ + If( + reset, + then: [ + head < 0, + tail < 0, + headOff < 0, + headPc < 0, + fetchPc < 0, + reading < 0, + discard < 0, + started < 0, + memRead.en < 0, + memRead.addr < 0, + ], + orElse: [ + If( + ~enable, + then: [reading < 0, discard < 0, memRead.en < 0], + orElse: [ + If( + redirect, + then: [ + // Flush and resteer to redirectPc (any 2-byte alignment). + head < 0, + tail < 0, + headOff < redirectPc.slice(offW, 1), + headPc < redirectPc, + fetchPc < (redirectPc & alignMask), + reading < 1, + discard < 1, // drop the one stale in-flight word + memRead.en < 1, + memRead.addr < (redirectPc & alignMask), + ], + orElse: [ + // -- word FIFO push (produce) + pop (consume) -- + If( + produce, + then: [ + for (var i = 0; i < depth; i++) + If( + tailIdx.eq(Const(i, width: ptrBits)), + then: [wordArr[i] < memRead.data], + ), + tail < tail + 1, + ], + ), + head < head + wordsPopped.zeroExtend(ptrBits + 1), + headOff < newHeadOff.slice(offW - 1, 0), + headPc < headPc + (consumed.zeroExtend(w) << 1), + fetchPc < nFetchPc, + reading < 1, + memRead.en < 1, + If( + ~started, + then: [ + started < 1, + headOff < pc.slice(offW, 1), + headPc < pc, + fetchPc < (pc & alignMask), + memRead.addr < (pc & alignMask), + ], + orElse: [ + If( + discard, + then: [ + discard < ~memRead.done, + memRead.addr < (fetchPc & alignMask), + ], + orElse: [memRead.addr < (nFetchPc & alignMask)], + ), + ], + ), + ], + ), + ], + ), + ], + ), + ]); + } +} diff --git a/packages/river_hdl/lib/src/core/csr.dart b/packages/river_hdl/lib/src/core/csr.dart index 6f4c25c..c749d76 100644 --- a/packages/river_hdl/lib/src/core/csr.dart +++ b/packages/river_hdl/lib/src/core/csr.dart @@ -1,9 +1,14 @@ import 'package:rohd/rohd.dart'; -import 'package:rohd_hcl/rohd_hcl.dart'; -import 'package:riscv/riscv.dart'; +import 'package:rohd_hcl/rohd_hcl.dart' hide DataPortInterface, DataPortGroup; +import 'package:rohd_hcl/rohd_hcl.dart' as hcl show DataPortInterface; +import 'package:river/river.dart'; +import '../data_port.dart'; class RiscVMstatusCsr extends CsrConfig { - RiscVMstatusCsr() + // [hyp] adds the MPV field (bit 39, RV64 hypervisor) so the V-bit can be + // pushed/popped on trap/MRET. Only declared field bits are read back, so MPV + // must be a field to be readable/writable. + RiscVMstatusCsr({bool hyp = false}) : super( name: 'mstatus', access: CsrAccess.readWrite, @@ -26,18 +31,52 @@ class RiscVMstatusCsr extends CsrConfig { name: 'mpp', access: CsrFieldAccess.readWrite, ), + if (hyp) + CsrFieldConfig( + start: 39, + width: 1, + name: 'mpv', + access: CsrFieldAccess.readWrite, + ), ], ); } class ReadOnlyNoFieldCsr extends CsrConfig { - ReadOnlyNoFieldCsr(String name) - : super(name: name, access: CsrAccess.readOnly, fields: const []); + // A full-width read-only field is needed for the value to be readable: a + // CsrTop register with no fields reads back as X (only declared field bits are + // reconstructed). The reset value still drives the bits. + ReadOnlyNoFieldCsr(String name, int width) + : super( + name: name, + access: CsrAccess.readOnly, + fields: [ + CsrFieldConfig( + start: 0, + width: width, + name: 'value', + access: CsrFieldAccess.readOnly, + ), + ], + ); } class SimpleRwCsr extends CsrConfig { - SimpleRwCsr(String name) - : super(name: name, access: CsrAccess.readWrite, fields: const []); + // Full-width read/write field so csrr reads back the stored value (a no-field + // register reads as X). Per-CSR WARL masking is applied in _maskWriteData. + SimpleRwCsr(String name, int width) + : super( + name: name, + access: CsrAccess.readWrite, + fields: [ + CsrFieldConfig( + start: 0, + width: width, + name: 'value', + access: CsrFieldAccess.readWrite, + ), + ], + ); } class CounterCsr extends CsrConfig { @@ -46,19 +85,22 @@ class CounterCsr extends CsrConfig { } class RiscVCsrFile extends Module { - final Mxlen mxlen; + final RiscVMxlen mxlen; final int misaValue; final int mvendoridValue; final int marchidValue; final int mimpidValue; final int mhartidValue; + final int rpipelineCapValue; final bool hasSupervisor; final bool hasUser; final bool hasPaging; final bool hasMxr; final bool hasSum; + final bool hasHypervisor; + final bool hasStateen; late final Logic clk; late final Logic reset; @@ -69,8 +111,8 @@ class RiscVCsrFile extends Module { late final CsrTop _csrTop; - late final DataPortInterface _fdRead; - late final DataPortInterface _fdWrite; + late final hcl.DataPortInterface _fdRead; + late final hcl.DataPortInterface _fdWrite; late final List _implementedAddrs; late final Set _frontdoorWritableAddrs; @@ -78,6 +120,19 @@ class RiscVCsrFile extends Module { CsrBackdoorInterface? _mcycleBd; CsrBackdoorInterface? _minstretBd; + // Trap save-state / xRET restore controls (driven by core.dart). All + // optional; when null the trap CSRs are not hardware-written (csrr/csrw work). + Logic? _trapActive; // 1-cycle pulse: a synchronous trap is retiring + Logic? _trapTargetIsM; // 1 = trap delegated/routed to M, 0 = to S + Logic? _trapPc; // PC of the trapping instruction → {m,s}epc + Logic? _trapCauseVal; // full mcause value (interrupt< illegal (below + // M); set but hstateen0.SE0 clear in VS -> virtual. + if (hasStateen) { + addOutput('mstateen0_se0'); + if (hasHypervisor) addOutput('hstateen0_se0'); } - void _checkFits(String n, int v) { - final max = (mxlen.size >= 63) ? null : (1 << mxlen.size); - if (v < 0) { + void checkFits(String n, int v) { + if (mxlen.size < 64 && v < 0) { throw ArgumentError('$n must be non-negative, got $v'); } - if (max != null && v >= max) { - throw ArgumentError( - '$n (0x${v.toRadixString(16)}) does not fit in XLEN=${mxlen.size}', - ); + if (mxlen.size < 63) { + final max = 1 << mxlen.size; + if (v >= max) { + throw ArgumentError( + '$n (0x${v.toRadixString(16)}) does not fit in XLEN=${mxlen.size}', + ); + } } } - _checkFits('misa', misaValue); - _checkFits('mvendorid', mvendoridValue); - _checkFits('marchid', marchidValue); - _checkFits('mimpid', mimpidValue); - _checkFits('mhartid', mhartidValue); + checkFits('misa', misaValue); + checkFits('mvendorid', mvendoridValue); + checkFits('marchid', marchidValue); + checkFits('mimpid', mimpidValue); + checkFits('mhartid', mhartidValue); this.csrRead = csrRead.clone() ..connectIO( @@ -163,8 +284,8 @@ class RiscVCsrFile extends Module { final cfg = _buildConfig(mxlen); - _fdRead = DataPortInterface(mxlen.size, 12); - _fdWrite = DataPortInterface(mxlen.size, 12); + _fdRead = hcl.DataPortInterface(mxlen.size, 12); + _fdWrite = hcl.DataPortInterface(mxlen.size, 12); _csrTop = CsrTop( config: cfg, @@ -190,6 +311,7 @@ class RiscVCsrFile extends Module { _bindBackdoorForCounters(); _wireCounters(); + _wireTrapState(); mstatus <= _csrTop.getBackdoorPortsByAddr(0, CsrAddress.mstatus.address).rdData!; @@ -201,6 +323,19 @@ class RiscVCsrFile extends Module { _csrTop.getBackdoorPortsByAddr(0, CsrAddress.medeleg.address).rdData!; mtvec <= _csrTop.getBackdoorPortsByAddr(0, CsrAddress.mtvec.address).rdData!; + mepc <= _csrTop.getBackdoorPortsByAddr(0, CsrAddress.mepc.address).rdData!; + output('rpipelinectl') <= + _csrTop + .getBackdoorPortsByAddr(0, CsrAddress.rpipelinectl.address) + .rdData!; + output('rmicrocodeaddr') <= + _csrTop + .getBackdoorPortsByAddr(0, CsrAddress.rmicrocodeaddr.address) + .rdData!; + output('rmicrocodedata') <= + _csrTop + .getBackdoorPortsByAddr(0, CsrAddress.rmicrocodedata.address) + .rdData!; if (hasSupervisor) { stvec! <= @@ -208,16 +343,58 @@ class RiscVCsrFile extends Module { satp! <= _csrTop.getBackdoorPortsByAddr(0, CsrAddress.satp.address).rdData!; + + output('sepc') <= + _csrTop.getBackdoorPortsByAddr(0, CsrAddress.sepc.address).rdData!; + output('sstatus') <= + _csrTop.getBackdoorPortsByAddr(0, CsrAddress.sstatus.address).rdData!; } + if (hasHypervisor) { + output('hstatus') <= + _csrTop.getBackdoorPortsByAddr(0, CsrAddress.hstatus.address).rdData!; + output('hedeleg') <= + _csrTop.getBackdoorPortsByAddr(0, CsrAddress.hedeleg.address).rdData!; + output('vstvec') <= + _csrTop.getBackdoorPortsByAddr(0, CsrAddress.vstvec.address).rdData!; + } + + if (hasStateen) { + output('mstateen0_se0') <= + _csrTop + .getBackdoorPortsByAddr(0, CsrAddress.mstateen0.address) + .rdData![mxlen.size - 1]; + if (hasHypervisor) { + output('hstateen0_se0') <= + _csrTop + .getBackdoorPortsByAddr(0, CsrAddress.hstateen0.address) + .rdData![mxlen.size - 1]; + } + } + + final mipBd = _csrTop.getBackdoorPortsByAddr(0, CsrAddress.mip.address); if (externalPending != null) { - final mip = _csrTop.getBackdoorPortsByAddr(0, CsrAddress.mip.address); - mip.wrEn! <= Const(1); - mip.wrData! <= this.mip.withSet(11, externalPending); + mipBd.wrEn! <= Const(1); + mipBd.wrData! <= mip.withSet(11, externalPending); + } else { + // Must still drive the backdoor write port: an undriven wrEn floats to X + // and the CsrBlock's ElseIf(backdoorWrEn) corrupts mip to X. + mipBd.wrEn! <= Const(0); + mipBd.wrData! <= Const(0, width: mxlen.size); } + + // mscratch has no hardware writer but is backdoor-writable so tests can seed + // it via setData. Tie wrEn to 0 (as for mip) so it never floats to X; + // setData's inject overrides this during seeding. + final mscratchBd = _csrTop.getBackdoorPortsByAddr( + 0, + CsrAddress.mscratch.address, + ); + mscratchBd.wrEn! <= Const(0); + mscratchBd.wrData! <= Const(0, width: mxlen.size); } - CsrTopConfig _buildConfig(Mxlen mxlen) { + CsrTopConfig _buildConfig(RiscVMxlen mxlen) { const sstatusMask = 0x800DE133; const ustatusMask = 0x11; const supervisorInterruptMask = 0x222; @@ -225,35 +402,35 @@ class RiscVCsrFile extends Module { final regs = [ CsrInstanceConfig( - arch: ReadOnlyNoFieldCsr('mvendorid'), + arch: ReadOnlyNoFieldCsr('mvendorid', mxlen.size), addr: CsrAddress.mvendorid.address, width: mxlen.size, resetValue: mvendoridValue, isBackdoorWritable: false, ), CsrInstanceConfig( - arch: ReadOnlyNoFieldCsr('marchid'), + arch: ReadOnlyNoFieldCsr('marchid', mxlen.size), addr: CsrAddress.marchid.address, width: mxlen.size, resetValue: marchidValue, isBackdoorWritable: false, ), CsrInstanceConfig( - arch: ReadOnlyNoFieldCsr('mimpid'), + arch: ReadOnlyNoFieldCsr('mimpid', mxlen.size), addr: CsrAddress.mimpid.address, width: mxlen.size, resetValue: mimpidValue, isBackdoorWritable: false, ), CsrInstanceConfig( - arch: ReadOnlyNoFieldCsr('mhartid'), + arch: ReadOnlyNoFieldCsr('mhartid', mxlen.size), addr: CsrAddress.mhartid.address, width: mxlen.size, resetValue: mhartidValue, isBackdoorWritable: false, ), CsrInstanceConfig( - arch: ReadOnlyNoFieldCsr('misa'), + arch: ReadOnlyNoFieldCsr('misa', mxlen.size), addr: CsrAddress.misa.address, width: mxlen.size, resetValue: misaValue, @@ -261,133 +438,177 @@ class RiscVCsrFile extends Module { ), CsrInstanceConfig( - arch: RiscVMstatusCsr(), + arch: RiscVMstatusCsr(hyp: hasHypervisor), addr: CsrAddress.mstatus.address, resetValue: 0, width: mxlen.size, - isBackdoorWritable: false, + // Hardware-written on trap entry / xRET; wrEn driven in _wireTrapState. + isBackdoorWritable: true, ), CsrInstanceConfig( - arch: SimpleRwCsr('mie'), + arch: SimpleRwCsr('mie', mxlen.size), addr: CsrAddress.mie.address, resetValue: 0, width: mxlen.size, + // No hardware writer, must be false or the undriven backdoor wrEn floats + // to X and corrupts the register. + isBackdoorWritable: false, ), CsrInstanceConfig( - arch: SimpleRwCsr('mip'), + arch: SimpleRwCsr('mip', mxlen.size), addr: CsrAddress.mip.address, resetValue: 0, width: mxlen.size, isBackdoorWritable: true, ), CsrInstanceConfig( - arch: SimpleRwCsr('mtvec'), + arch: SimpleRwCsr('mtvec', mxlen.size), addr: CsrAddress.mtvec.address, resetValue: 0, width: mxlen.size, isBackdoorWritable: false, ), CsrInstanceConfig( - arch: SimpleRwCsr('mscratch'), + arch: SimpleRwCsr('mscratch', mxlen.size), addr: CsrAddress.mscratch.address, resetValue: 0, width: mxlen.size, + // Backdoor-writable so tests can seed it via setData; its wrEn is tied + // to 0 below (see mip) so it never floats to X in normal operation. isBackdoorWritable: true, ), CsrInstanceConfig( - arch: SimpleRwCsr('mepc'), + arch: SimpleRwCsr('mepc', mxlen.size), addr: CsrAddress.mepc.address, resetValue: 0, width: mxlen.size, - isBackdoorWritable: false, + // Hardware-written on trap entry (wrEn driven in _wireTrapState). + isBackdoorWritable: true, ), CsrInstanceConfig( - arch: SimpleRwCsr('mcause'), + arch: SimpleRwCsr('mcause', mxlen.size), addr: CsrAddress.mcause.address, resetValue: 0, width: mxlen.size, - isBackdoorWritable: false, + isBackdoorWritable: true, ), CsrInstanceConfig( - arch: SimpleRwCsr('mtval'), + arch: SimpleRwCsr('mtval', mxlen.size), addr: CsrAddress.mtval.address, resetValue: 0, width: mxlen.size, - isBackdoorWritable: false, + isBackdoorWritable: true, ), CsrInstanceConfig( - arch: SimpleRwCsr('medeleg'), + arch: SimpleRwCsr('medeleg', mxlen.size), addr: CsrAddress.medeleg.address, resetValue: 0, width: mxlen.size, + // No hardware writer, must be false (undriven backdoor wrEn -> X, which + // silently broke S/VS-mode trap delegation when medeleg[cause] read X). + isBackdoorWritable: false, ), CsrInstanceConfig( - arch: SimpleRwCsr('mideleg'), + arch: SimpleRwCsr('mideleg', mxlen.size), addr: CsrAddress.mideleg.address, resetValue: 0, width: mxlen.size, isBackdoorWritable: false, ), + // Smstateen machine-level state-enable CSRs. Only SE0 (bit 63) is writable + // (masked in _maskWriteData); the access gating lives in the legality path. + if (hasStateen) + for (final a in [ + CsrAddress.mstateen0, + CsrAddress.mstateen1, + CsrAddress.mstateen2, + CsrAddress.mstateen3, + ]) + CsrInstanceConfig( + arch: SimpleRwCsr(a.name, mxlen.size), + addr: a.address, + resetValue: 0, + width: mxlen.size, + isBackdoorWritable: false, + ), + if (hasSupervisor) ...[ CsrInstanceConfig( - arch: SimpleRwCsr('sstatus'), + arch: SimpleRwCsr('sstatus', mxlen.size), addr: CsrAddress.sstatus.address, resetValue: 0, width: mxlen.size, - isBackdoorWritable: false, + // Hardware-written on S-trap entry / SRET (wrEn in _wireTrapState). + isBackdoorWritable: true, ), CsrInstanceConfig( - arch: SimpleRwCsr('sie'), + arch: SimpleRwCsr('sie', mxlen.size), addr: CsrAddress.sie.address, resetValue: 0, width: mxlen.size, isBackdoorWritable: false, ), CsrInstanceConfig( - arch: SimpleRwCsr('sip'), + arch: SimpleRwCsr('sip', mxlen.size), addr: CsrAddress.sip.address, resetValue: 0, width: mxlen.size, isBackdoorWritable: false, ), + // Ssstateen supervisor-level state-enable CSRs. No U-accessible + // state-enabled features in River, so all bits are WARL-0 (mask 0). + if (hasStateen) + for (final a in [ + CsrAddress.sstateen0, + CsrAddress.sstateen1, + CsrAddress.sstateen2, + CsrAddress.sstateen3, + ]) + CsrInstanceConfig( + arch: SimpleRwCsr(a.name, mxlen.size), + addr: a.address, + resetValue: 0, + width: mxlen.size, + isBackdoorWritable: false, + ), CsrInstanceConfig( - arch: SimpleRwCsr('stvec'), + arch: SimpleRwCsr('stvec', mxlen.size), addr: CsrAddress.stvec.address, resetValue: 0, width: mxlen.size, isBackdoorWritable: false, ), CsrInstanceConfig( - arch: SimpleRwCsr('sscratch'), + arch: SimpleRwCsr('sscratch', mxlen.size), addr: CsrAddress.sscratch.address, resetValue: 0, width: mxlen.size, isBackdoorWritable: false, ), CsrInstanceConfig( - arch: SimpleRwCsr('sepc'), + arch: SimpleRwCsr('sepc', mxlen.size), addr: CsrAddress.sepc.address, resetValue: 0, width: mxlen.size, - isBackdoorWritable: false, + isBackdoorWritable: true, ), CsrInstanceConfig( - arch: SimpleRwCsr('scause'), + arch: SimpleRwCsr('scause', mxlen.size), addr: CsrAddress.scause.address, resetValue: 0, width: mxlen.size, - isBackdoorWritable: false, + isBackdoorWritable: true, ), CsrInstanceConfig( - arch: SimpleRwCsr('stval'), + arch: SimpleRwCsr('stval', mxlen.size), addr: CsrAddress.stval.address, resetValue: 0, width: mxlen.size, - isBackdoorWritable: false, + isBackdoorWritable: true, ), CsrInstanceConfig( - arch: SimpleRwCsr('satp'), + arch: SimpleRwCsr('satp', mxlen.size), addr: CsrAddress.satp.address, resetValue: 0, width: mxlen.size, @@ -395,58 +616,130 @@ class RiscVCsrFile extends Module { ), ], + // Hypervisor (H) + VS-shadow CSRs. Gated on hasHypervisor. hgeip is + // read-only. + if (hasHypervisor) ...[ + // hstatus is hardware-touched (SRET clears SPV), so backdoor-writable + // and exposed as an output; the rest are plain RW CSRs. + CsrInstanceConfig( + arch: SimpleRwCsr('hstatus', mxlen.size), + addr: CsrAddress.hstatus.address, + resetValue: 0, + width: mxlen.size, + isBackdoorWritable: true, + ), + // Hypervisor state-enable CSRs (only SE0 writable on hstateen0). + if (hasStateen) + for (final a in [ + CsrAddress.hstateen0, + CsrAddress.hstateen1, + CsrAddress.hstateen2, + CsrAddress.hstateen3, + ]) + CsrInstanceConfig( + arch: SimpleRwCsr(a.name, mxlen.size), + addr: a.address, + resetValue: 0, + width: mxlen.size, + isBackdoorWritable: false, + ), + for (final name in const [ + 'hedeleg', + 'hideleg', + 'hie', + 'hcounteren', + 'hgeie', + 'htval', + 'hip', + 'hvip', + 'htinst', + 'henvcfg', + 'htimedelta', + 'hgatp', + 'vsie', + 'vstvec', + 'vsscratch', + 'vsip', + 'vsatp', + ]) + CsrInstanceConfig( + arch: SimpleRwCsr(name, mxlen.size), + addr: CsrAddress.values.firstWhere((a) => a.name == name).address, + resetValue: 0, + width: mxlen.size, + isBackdoorWritable: false, + ), + // VS trap save-state CSRs: hardware-written when a trap is delegated to + // VS-mode (vsepc/vscause/vstval + vsstatus push), so backdoor-writable. + for (final name in const ['vsstatus', 'vsepc', 'vscause', 'vstval']) + CsrInstanceConfig( + arch: SimpleRwCsr(name, mxlen.size), + addr: CsrAddress.values.firstWhere((a) => a.name == name).address, + resetValue: 0, + width: mxlen.size, + isBackdoorWritable: true, + ), + CsrInstanceConfig( + arch: ReadOnlyNoFieldCsr('hgeip', mxlen.size), + addr: CsrAddress.hgeip.address, + resetValue: 0, + width: mxlen.size, + isBackdoorWritable: false, + ), + ], + if (hasUser) ...[ CsrInstanceConfig( - arch: SimpleRwCsr('ustatus'), + arch: SimpleRwCsr('ustatus', mxlen.size), addr: CsrAddress.ustatus.address, resetValue: 0, width: mxlen.size, isBackdoorWritable: false, ), CsrInstanceConfig( - arch: SimpleRwCsr('uie'), + arch: SimpleRwCsr('uie', mxlen.size), addr: CsrAddress.uie.address, resetValue: 0, width: mxlen.size, isBackdoorWritable: false, ), CsrInstanceConfig( - arch: SimpleRwCsr('uip'), + arch: SimpleRwCsr('uip', mxlen.size), addr: CsrAddress.uip.address, resetValue: 0, width: mxlen.size, isBackdoorWritable: false, ), CsrInstanceConfig( - arch: SimpleRwCsr('utvec'), + arch: SimpleRwCsr('utvec', mxlen.size), addr: CsrAddress.utvec.address, resetValue: 0, width: mxlen.size, isBackdoorWritable: false, ), CsrInstanceConfig( - arch: SimpleRwCsr('uscratch'), + arch: SimpleRwCsr('uscratch', mxlen.size), addr: CsrAddress.uscratch.address, resetValue: 0, width: mxlen.size, isBackdoorWritable: false, ), CsrInstanceConfig( - arch: SimpleRwCsr('uepc'), + arch: SimpleRwCsr('uepc', mxlen.size), addr: CsrAddress.uepc.address, resetValue: 0, width: mxlen.size, isBackdoorWritable: false, ), CsrInstanceConfig( - arch: SimpleRwCsr('ucause'), + arch: SimpleRwCsr('ucause', mxlen.size), addr: CsrAddress.ucause.address, resetValue: 0, width: mxlen.size, isBackdoorWritable: false, ), CsrInstanceConfig( - arch: SimpleRwCsr('utval'), + arch: SimpleRwCsr('utval', mxlen.size), addr: CsrAddress.utval.address, resetValue: 0, width: mxlen.size, @@ -468,6 +761,72 @@ class RiscVCsrFile extends Module { resetValue: 0, isBackdoorWritable: true, ), + + // River custom cache control CSRs + CsrInstanceConfig( + arch: SimpleRwCsr('rcachectl', mxlen.size), + addr: CsrAddress.rcachectl.address, + resetValue: 0, + width: mxlen.size, + isBackdoorWritable: false, + ), + // Pipeline / speculation control. WARL bits [3:0] + // (SSBD/BPD/SERIALIZE/DTLBFC), masked in _maskWriteData. Read back through + // the rpipelinectl output port. + CsrInstanceConfig( + arch: SimpleRwCsr('rpipelinectl', mxlen.size), + addr: CsrAddress.rpipelinectl.address, + resetValue: 0, + width: mxlen.size, + isBackdoorWritable: false, + ), + // Read-only pipeline feature-discovery bitmap (writes trap, RO address). + CsrInstanceConfig( + arch: ReadOnlyNoFieldCsr('rpipelinecap', mxlen.size), + addr: CsrAddress.rpipelinecap.address, + width: mxlen.size, + resetValue: rpipelineCapValue, + isBackdoorWritable: false, + ), + CsrInstanceConfig( + arch: SimpleRwCsr('rcacheaddr', mxlen.size), + addr: CsrAddress.rcacheaddr.address, + resetValue: 0, + width: mxlen.size, + isBackdoorWritable: false, + ), + CsrInstanceConfig( + arch: SimpleRwCsr('rcachesize', mxlen.size), + addr: CsrAddress.rcachesize.address, + resetValue: 0, + width: mxlen.size, + isBackdoorWritable: false, + ), + // Microcode update: addr/data are plain RW (their stored values feed the + // core's ROM-patch staging); ctl is RW too but the core acts on the + // csrWrite write-pulse for its address, not the stored bits (so the + // strobes self-clear and never re-fire). + CsrInstanceConfig( + arch: SimpleRwCsr('rmicrocodeaddr', mxlen.size), + addr: CsrAddress.rmicrocodeaddr.address, + resetValue: 0, + width: mxlen.size, + isBackdoorWritable: false, + ), + CsrInstanceConfig( + arch: SimpleRwCsr('rmicrocodedata', mxlen.size), + addr: CsrAddress.rmicrocodedata.address, + resetValue: 0, + width: mxlen.size, + isBackdoorWritable: false, + ), + CsrInstanceConfig( + arch: SimpleRwCsr('rmicrocodectl', mxlen.size), + addr: CsrAddress.rmicrocodectl.address, + resetValue: 0, + width: mxlen.size, + isBackdoorWritable: false, + ), ]; final block = CsrBlockConfig(name: 'csr', baseAddr: 0, registers: regs); @@ -494,17 +853,17 @@ class RiscVCsrFile extends Module { Logic _privOk(Logic addr12) { final privBits = addr12.getRange(8, 10); + // CSR address bits[9:8] encode the lowest privilege: 00=user, 01=supervisor, + // 10=hypervisor (accessible from HS-mode or M), 11=machine. Hypervisor (2) + // maps to supervisor-level for the mode check; its existence is gated on + // hasHypervisor via _addrExists. final req = mux( privBits.eq(Const(0, width: 2)), Const(PrivilegeMode.user.id, width: 3), mux( - privBits.eq(Const(1, width: 2)), - Const(PrivilegeMode.supervisor.id, width: 3), - mux( - privBits.eq(Const(3, width: 2)), - Const(PrivilegeMode.machine.id, width: 3), - Const(7, width: 3), - ), + privBits.eq(Const(3, width: 2)), + Const(PrivilegeMode.machine.id, width: 3), + Const(PrivilegeMode.supervisor.id, width: 3), // 01 and 10 ), ); @@ -516,6 +875,26 @@ class RiscVCsrFile extends Module { return mode.gte(req) & userOk & supOk; } + // Smstateen access gating: deny a lower-level state-enable CSR + // (sstateen*/hstateen*) from any mode below M when mstateen0.SE0 (MSB) is + // clear, else allow. Only SE0 is implemented; the VS-mode virtual-instruction + // distinction (hstateen0.SE0) is not modelled here. + Logic _stateenOk(Logic addr12) { + if (!hasStateen) return Const(1); + Logic inRange(int lo, int hi) => + addr12.gte(Const(lo, width: 12)) & addr12.lte(Const(hi, width: 12)); + final isSstateen = inRange(0x10C, 0x10F); + final isHstateen = hasHypervisor ? inRange(0x60C, 0x60F) : Const(0); + final isGated = isSstateen | isHstateen; + final belowM = ~mode.gte( + Const(PrivilegeMode.machine.id, width: mode.width), + ); + final mse0 = _csrTop + .getBackdoorPortsByAddr(0, CsrAddress.mstateen0.address) + .rdData![mxlen.size - 1]; + return ~(isGated & belowM & ~mse0); + } + Logic _addrExists(Logic addr12) { Logic hit = Const(0, width: 1); for (final a in _implementedAddrs) { @@ -581,6 +960,37 @@ class RiscVCsrFile extends Module { ); } + if (hasStateen) { + // Only SE0 (bit 63) is writable on *stateen0; everything else is WARL-0 + // (gates features River does not implement). + final se0Mask = (Const(1, width: mxlen.size) << (mxlen.size - 1)).named( + 'stateenSe0Mask', + ); + final zeroMask = Const(0, width: mxlen.size); + out = applyMask(CsrAddress.mstateen0.address, se0Mask); + out = applyMask(CsrAddress.mstateen1.address, zeroMask); + out = applyMask(CsrAddress.mstateen2.address, zeroMask); + out = applyMask(CsrAddress.mstateen3.address, zeroMask); + if (hasSupervisor) { + out = applyMask(CsrAddress.sstateen0.address, zeroMask); + out = applyMask(CsrAddress.sstateen1.address, zeroMask); + out = applyMask(CsrAddress.sstateen2.address, zeroMask); + out = applyMask(CsrAddress.sstateen3.address, zeroMask); + } + if (hasHypervisor) { + out = applyMask(CsrAddress.hstateen0.address, se0Mask); + out = applyMask(CsrAddress.hstateen1.address, zeroMask); + out = applyMask(CsrAddress.hstateen2.address, zeroMask); + out = applyMask(CsrAddress.hstateen3.address, zeroMask); + } + } + + // rpipelinectl: only the low 4 control bits are writable (WARL). + out = applyMask( + CsrAddress.rpipelinectl.address, + Const(0xF, width: mxlen.size), + ); + return out; } @@ -588,20 +998,38 @@ class RiscVCsrFile extends Module { final rdAddr12 = Logic(width: 12, name: 'csrReadAddr12'); final wrAddr12 = Logic(width: 12, name: 'csrWriteAddr12'); - rdAddr12 <= csrRead.addr.slice(11, 0); - wrAddr12 <= csrWrite.addr.slice(11, 0); + // VS-mode CSR redirect: when virt=1, a supervisor-CSR access (addr[9:8]==01, + // 0x1xx) is redirected to the VS shadow CSR (0x2xx) by adding 0x100 + // (sstatus->vsstatus, satp->vsatp, …). + Logic vsRedirect(Logic a, String tag) { + if (_virtInput == null) return a; + final isSup = a.slice(9, 8).eq(Const(1, width: 2)).named('csrIsSup_$tag'); + return mux( + _virtInput! & isSup, + a + Const(0x100, width: 12), + a, + ).named('csrVsRed_$tag'); + } + + rdAddr12 <= vsRedirect(csrRead.addr.slice(11, 0), 'rd'); + wrAddr12 <= vsRedirect(csrWrite.addr.slice(11, 0), 'wr'); - final rdLegal = _addrExists(rdAddr12) & _privOk(rdAddr12); + final rdLegal = + _addrExists(rdAddr12) & _privOk(rdAddr12) & _stateenOk(rdAddr12); + // _isFrontdoorWritable is a strict subset of _addrExists (same register + // list, readWrite regs only), so it implies _addrExists. Dropping the + // redundant existence term removes the _addrExists OR-tree from + // write-legality (area diet). Read-legality still uses _addrExists. final wrLegal = - _addrExists(wrAddr12) & _privOk(wrAddr12) & + _stateenOk(wrAddr12) & _isFrontdoorWritable(wrAddr12); _fdRead.addr <= rdAddr12; _fdRead.en <= csrRead.en & rdLegal; csrRead.data <= _fdRead.data; - csrRead.done <= _fdRead.done & csrRead.en; - csrRead.valid <= _fdRead.valid & csrRead.en & rdLegal; + csrRead.done <= csrRead.en; + csrRead.valid <= csrRead.en & rdLegal; _fdWrite.addr <= wrAddr12; @@ -609,8 +1037,8 @@ class RiscVCsrFile extends Module { _fdWrite.data <= maskedWriteData; _fdWrite.en <= csrWrite.en & wrLegal; - csrWrite.done <= _fdWrite.done & csrWrite.en; - csrWrite.valid <= _fdWrite.valid & csrWrite.en & wrLegal; + csrWrite.done <= csrWrite.en; + csrWrite.valid <= csrWrite.en & wrLegal; } void _bindBackdoorForCounters() { @@ -655,6 +1083,108 @@ class RiscVCsrFile extends Module { ], reset: reset); } + /// Hardware trap save-state and xRET restore, driven by core.dart's + /// retire-cycle controls. On a synchronous trap: {m,s}epc←pc, {m,s}cause←cause, + /// {m,s}tval←tval, and the status privilege stack is pushed (xPP←currentMode, + /// xPIE←xIE, xIE←0). On xRET: xIE←xPIE, xPIE←1, xPP←U. All backdoor wrEn lines + /// are driven every cycle (0 when idle). PC/mode restore itself is in + /// core.dart; this method only manages the CSR contents. + void _wireTrapState() { + if (_trapActive == null) return; + + final trapToM = _trapActive! & _trapTargetIsM!; + final retFromM = _returnActive! & _returnFromM!; + + CsrBackdoorInterface bd(int addr) => + getBackdoor(LogicValue.ofInt(addr, 12)); + + final mstatusBd = bd(CsrAddress.mstatus.address); + final mepcBd = bd(CsrAddress.mepc.address); + final mcauseBd = bd(CsrAddress.mcause.address); + final mtvalBd = bd(CsrAddress.mtval.address); + + final mcur = mstatusBd.rdData!; + // mstatus bits: MIE=3, MPIE=7, MPP=[12:11]. + final mTrap = mcur + .withSet(3, Const(0, width: 1)) // MIE <- 0 + .withSet(7, mcur[3]) // MPIE <- old MIE + .withSet(11, mode.slice(1, 0)); // MPP <- current mode + final mRet = mcur + .withSet(3, mcur[7]) // MIE <- MPIE + .withSet(7, Const(1, width: 1)) // MPIE <- 1 + .withSet(11, Const(0, width: 2)); // MPP <- U + + mstatusBd.wrEn! <= (trapToM | retFromM); + mstatusBd.wrData! <= mux(trapToM, mTrap, mRet); + mepcBd.wrEn! <= trapToM; + mepcBd.wrData! <= _trapPc!; + mcauseBd.wrEn! <= trapToM; + mcauseBd.wrData! <= _trapCauseVal!; + mtvalBd.wrEn! <= trapToM; + mtvalBd.wrData! <= _trapTval!; + + if (hasSupervisor) { + // A trap delegated to VS-mode (vsTrap) saves to the vs* CSRs below, not the + // HS s* CSRs, so exclude it from trapToS. + final vsTrap = _trapToVS ?? Const(0); + final trapToS = _trapActive! & ~_trapTargetIsM! & ~vsTrap; + final retFromS = _returnActive! & ~_returnFromM!; + + final sstatusBd = bd(CsrAddress.sstatus.address); + final sepcBd = bd(CsrAddress.sepc.address); + final scauseBd = bd(CsrAddress.scause.address); + final stvalBd = bd(CsrAddress.stval.address); + + final scur = sstatusBd.rdData!; + // sstatus bits: SIE=1, SPIE=5, SPP=8. + final sTrap = scur + .withSet(1, Const(0, width: 1)) // SIE <- 0 + .withSet(5, scur[1]) // SPIE <- old SIE + .withSet(8, mode[0]); // SPP <- current mode (S=1/U=0) + final sRet = scur + .withSet(1, scur[5]) // SIE <- SPIE + .withSet(5, Const(1, width: 1)) // SPIE <- 1 + .withSet(8, Const(0, width: 1)); // SPP <- U + + sstatusBd.wrEn! <= (trapToS | retFromS); + sstatusBd.wrData! <= mux(trapToS, sTrap, sRet); + sepcBd.wrEn! <= trapToS; + sepcBd.wrData! <= _trapPc!; + scauseBd.wrEn! <= trapToS; + scauseBd.wrData! <= _trapCauseVal!; + stvalBd.wrEn! <= trapToS; + stvalBd.wrData! <= _trapTval!; + + if (hasHypervisor) { + // An SRET from HS-mode (the guest-entry case) clears hstatus.SPV (bit 7) + // after the V-bit has captured it. Other bits preserved. + final hstatusBd = bd(CsrAddress.hstatus.address); + hstatusBd.wrEn! <= retFromS; + hstatusBd.wrData! <= hstatusBd.rdData!.withSet(7, Const(0, width: 1)); + + // Trap delegated to VS-mode: save VS state (vsepc/vscause/vstval) and + // push the VS status stack (vsstatus: SPP<-mode, SPIE<-SIE, SIE<-0). + final vsstatusBd = bd(CsrAddress.vsstatus.address); + final vsepcBd = bd(CsrAddress.vsepc.address); + final vscauseBd = bd(CsrAddress.vscause.address); + final vstvalBd = bd(CsrAddress.vstval.address); + final vcur = vsstatusBd.rdData!; + vsstatusBd.wrEn! <= vsTrap; + vsstatusBd.wrData! <= + vcur + .withSet(1, Const(0, width: 1)) // SIE <- 0 + .withSet(5, vcur[1]) // SPIE <- old SIE + .withSet(8, mode[0]); // SPP <- current mode + vsepcBd.wrEn! <= vsTrap; + vsepcBd.wrData! <= _trapPc!; + vscauseBd.wrEn! <= vsTrap; + vscauseBd.wrData! <= _trapCauseVal!; + vstvalBd.wrEn! <= vsTrap; + vstvalBd.wrData! <= _trapTval!; + } + } + } + void setData(LogicValue address, LogicValue data) { assert(address.width == 12); @@ -690,8 +1220,7 @@ class RiscVCsrFile extends Module { Logic get mtvec => output('mtvec'); Logic get mscratch => _csrTop.getBackdoorPortsByAddr(0, CsrAddress.mscratch.address).rdData!; - Logic get mepc => - _csrTop.getBackdoorPortsByAddr(0, CsrAddress.mepc.address).rdData!; + Logic get mepc => output('mepc'); Logic get mcause => _csrTop.getBackdoorPortsByAddr(0, CsrAddress.mcause.address).rdData!; Logic get mtval => @@ -700,11 +1229,27 @@ class RiscVCsrFile extends Module { Logic get mideleg => output('mideleg'); Logic? get stvec => hasSupervisor ? output('stvec') : null; - Logic get sepc => - _csrTop.getBackdoorPortsByAddr(0, CsrAddress.sepc.address).rdData!; + Logic? get sstatus => hasSupervisor ? output('sstatus') : null; + Logic? get hstatus => hasHypervisor ? output('hstatus') : null; + Logic? get hedeleg => hasHypervisor ? output('hedeleg') : null; + Logic? get vstvec => hasHypervisor ? output('vstvec') : null; + Logic? get mstateen0Se0 => hasStateen ? output('mstateen0_se0') : null; + Logic? get hstateen0Se0 => + (hasStateen && hasHypervisor) ? output('hstateen0_se0') : null; + Logic get sepc => output('sepc'); Logic get scause => _csrTop.getBackdoorPortsByAddr(0, CsrAddress.scause.address).rdData!; Logic get stval => _csrTop.getBackdoorPortsByAddr(0, CsrAddress.stval.address).rdData!; Logic? get satp => hasSupervisor ? output('satp') : null; + + Logic get rcachectl => + _csrTop.getBackdoorPortsByAddr(0, CsrAddress.rcachectl.address).rdData!; + Logic get rcacheaddr => + _csrTop.getBackdoorPortsByAddr(0, CsrAddress.rcacheaddr.address).rdData!; + Logic get rcachesize => + _csrTop.getBackdoorPortsByAddr(0, CsrAddress.rcachesize.address).rdData!; + Logic get rpipelinectl => output('rpipelinectl'); + Logic get rmicrocodeaddr => output('rmicrocodeaddr'); + Logic get rmicrocodedata => output('rmicrocodedata'); } diff --git a/packages/river_hdl/lib/src/core/debug.dart b/packages/river_hdl/lib/src/core/debug.dart new file mode 100644 index 0000000..2127ff6 --- /dev/null +++ b/packages/river_hdl/lib/src/core/debug.dart @@ -0,0 +1,646 @@ +import 'package:rohd/rohd.dart'; + +/// RISC-V external debug for the River HDL sim: a JTAG TAP, a Debug Transport +/// Module (DTM), and a Debug Module (DM) fused into one [Module] so an external +/// debugger (OpenOCD `remote_bitbang`, driving Heimdall) can attach to the RTL. +/// +/// The whole block lives in the system clock domain. `tck` is sampled and +/// rising-edge detected, so one bitbang TCK pulse advances the TAP by exactly +/// one step and there is no JTAG-to-core clock-domain crossing to reason about. +/// This mirrors the emulator's software path (`SoftJtagDtm` + `SoftDebugModule`) +/// bit for bit, so both report the same DMI behaviour to OpenOCD. +/// +/// JTAG: IR width 5, IDCODE=0x01 (reset default), DTMCS=0x10, DMI=0x11, +/// BYPASS=0x1F. DMI DR is `abits + 34` = 41 bits `{addr[6:0], data[31:0], +/// op[1:0]}`. +/// +/// DMI register map (RISC-V Debug Spec, matches the emulator, NOT Harbor's +/// older `HarborDebugModule` which mis-maps dmstatus): dmstatus=0x11, +/// dmcontrol=0x10, data0=0x04, data1=0x05, abstractcs=0x16, command=0x17, +/// sbcs=0x38, sbaddress0=0x39, sbdata0=0x3c, sbdata1=0x3d. +/// +/// Memory inspection uses System Bus Access (SBA): the DM is a tiny bus master +/// exposing a single-outstanding request/ack memory port (`sba_*`). The hart is +/// untouched by SBA, so this works whether the core is halted or running. +class RiverDebugModule extends Module { + /// Machine xlen (32 or 64). Drives SBA data width and the abstract register + /// data path. + final int xlen; + + /// JTAG IDCODE presented over the IDCODE instruction. + final int idcode; + + /// IR width (RISC-V convention is 5). + final int irWidth; + + static const int _abits = 7; + static const int _dmiWidth = _abits + 34; // 41 + + // JTAG instruction opcodes. + static const int _irIdcode = 0x01; + static const int _irDtmcs = 0x10; + static const int _irDmi = 0x11; + + /// JTAG data out to the debugger. + Logic get tdo => output('tdo'); + + // Core control (driven from dmcontrol; consumed in Phase 1+). + Logic get haltReq => output('halt_req'); + Logic get resumeReq => output('resume_req'); + Logic get ndmreset => output('ndmreset'); + + /// High while a multi-cycle DM FSM (abstract command or system-bus access) + /// is in flight. A bit-banged simulation testbench can drain these to + /// completion instead of advancing one core clock per JTAG bit. + Logic get dmBusy => output('dm_busy'); + + // Abstract-command register port to the hart (Phase 2). + Logic get regRead => output('reg_read'); + Logic get regWrite => output('reg_write'); + Logic get regAddr => output('reg_addr'); + Logic get regWdata => output('reg_wdata'); + + // System bus access memory port. + Logic get sbaReq => output('sba_req'); + Logic get sbaWe => output('sba_we'); + Logic get sbaAddr => output('sba_addr'); + Logic get sbaWdata => output('sba_wdata'); + Logic get sbaSize => output('sba_size'); + + RiverDebugModule( + Logic clk, + Logic reset, + Logic tck, + Logic tms, + Logic tdi, + Logic trstN, { + Logic? hartHalted, + Logic? regRdata, + Logic? regReady, + Logic? sbaRdata, + Logic? sbaAck, + this.xlen = 64, + this.idcode = 0x10000001, + this.irWidth = 5, + super.name = 'river_debug', + }) : super(definitionName: 'RiverDebugModule') { + clk = addInput('clk', clk); + reset = addInput('reset', reset); + tck = addInput('tck', tck); + tms = addInput('tms', tms); + tdi = addInput('tdi', tdi); + trstN = addInput('trst_n', trstN); + + final hartHaltedIn = hartHalted == null + ? Const(0) + : addInput('hart_halted', hartHalted); + final regRdataIn = regRdata == null + ? Const(0, width: xlen) + : addInput('reg_rdata', regRdata, width: xlen); + final regReadyIn = regReady == null + ? Const(1) + : addInput('reg_ready', regReady); + final sbaRdataIn = sbaRdata == null + ? Const(0, width: xlen) + : addInput('sba_rdata', sbaRdata, width: xlen); + final sbaAckIn = sbaAck == null ? Const(0) : addInput('sba_ack', sbaAck); + + addOutput('tdo'); + addOutput('halt_req'); + addOutput('resume_req'); + addOutput('ndmreset'); + addOutput('reg_read'); + addOutput('reg_write'); + addOutput('reg_addr', width: 16); + addOutput('reg_wdata', width: xlen); + addOutput('sba_req'); + addOutput('sba_we'); + addOutput('sba_addr', width: xlen); + addOutput('sba_wdata', width: xlen); + addOutput('sba_size', width: 3); + addOutput('dm_busy'); + + // TAP state encoding (matches the emulator's TapState order). + const sTlr = 0; + const sRti = 1; + const sSelDr = 2; + const sCapDr = 3; + const sShDr = 4; + const sEx1Dr = 5; + const sPauseDr = 6; + const sEx2Dr = 7; + const sUpdDr = 8; + const sSelIr = 9; + const sCapIr = 10; + const sShIr = 11; + const sEx1Ir = 12; + const sPauseIr = 13; + const sEx2Ir = 14; + const sUpdIr = 15; + + final tapState = Logic(name: 'tap_state', width: 4); + final tapNext = Logic(name: 'tap_next', width: 4); + final irReg = Logic(name: 'ir_reg', width: irWidth); + final irShift = Logic(name: 'ir_shift', width: irWidth); + final dr = Logic(name: 'dr', width: _dmiWidth); + final drLen = Logic(name: 'dr_len', width: 7); + final tckPrev = Logic(name: 'tck_prev'); + + // Latched result of the previous DMI transaction (captured next scan). + final dmiData = Logic(name: 'dmi_data', width: 32); + final dmiAddr = Logic(name: 'dmi_addr', width: _abits); + final dmiStatus = Logic(name: 'dmi_status', width: 2); + + // Debug Module registers. + final dmactive = Logic(name: 'dmactive'); + final data0 = Logic(name: 'data0', width: 32); + final data1 = Logic(name: 'data1', width: 32); + final cmderr = Logic(name: 'cmderr', width: 3); + final sbaddress = Logic(name: 'sbaddress', width: xlen); + final sbdata0 = Logic(name: 'sbdata0', width: 32); + final sbdata1 = Logic(name: 'sbdata1', width: 32); + final sbAccessSize = Logic(name: 'sb_access_size', width: 3); + final sbAutoincr = Logic(name: 'sb_autoincr'); + final sbReadOnAddr = Logic(name: 'sb_read_on_addr'); + final sbReadOnData = Logic(name: 'sb_read_on_data'); + final sbError = Logic(name: 'sb_error', width: 3); + + // SBA bus-master FSM. + const sbIdle = 0; + const sbReqState = 1; + final sbState = Logic(name: 'sb_state', width: 2); + final sbWeReg = Logic(name: 'sb_we_reg'); + final sbAddrReg = Logic(name: 'sb_addr_reg', width: xlen); + final sbWdataReg = Logic(name: 'sb_wdata_reg', width: xlen); + final sbBusy = Logic(name: 'sb_busy'); + + // Abstract-command register port latches. + final regReadReg = Logic(name: 'reg_read_reg'); + final regWriteReg = Logic(name: 'reg_write_reg'); + final regAddrReg = Logic(name: 'reg_addr_reg', width: 16); + final regWdataReg = Logic(name: 'reg_wdata_reg', width: xlen); + final cmdPending = Logic(name: 'cmd_pending'); + final cmdActive = Logic(name: 'cmd_active'); + final cmdIs64 = Logic(name: 'cmd_is64'); + final cmdWrite = Logic(name: 'cmd_write'); + final haltReqReg = Logic(name: 'halt_req_reg'); + // dmcontrol.ndmreset (bit 1): holds the rest of the system (the hart) in + // reset while set, leaving the Debug Module itself alive. The SoC reset tree + // ORs this into the core reset; the DM is reset only by the external reset. + final ndmresetReg = Logic(name: 'ndmreset_reg'); + + final tckRise = tck & ~tckPrev; + + // TAP next-state combinational logic. + CaseItem fsm(int from, int hi, int lo) => CaseItem(Const(from, width: 4), [ + If( + tms, + then: [tapNext < Const(hi, width: 4)], + orElse: [tapNext < Const(lo, width: 4)], + ), + ]); + Combinational([ + tapNext < Const(sTlr, width: 4), + Case(tapState, [ + fsm(sTlr, sTlr, sRti), + fsm(sRti, sSelDr, sRti), + fsm(sSelDr, sSelIr, sCapDr), + fsm(sCapDr, sEx1Dr, sShDr), + fsm(sShDr, sEx1Dr, sShDr), + fsm(sEx1Dr, sUpdDr, sPauseDr), + fsm(sPauseDr, sEx2Dr, sPauseDr), + fsm(sEx2Dr, sUpdDr, sShDr), + fsm(sUpdDr, sSelDr, sRti), + fsm(sSelIr, sTlr, sCapIr), + fsm(sCapIr, sEx1Ir, sShIr), + fsm(sShIr, sEx1Ir, sShIr), + fsm(sEx1Ir, sUpdIr, sPauseIr), + fsm(sPauseIr, sEx2Ir, sPauseIr), + fsm(sEx2Ir, sUpdIr, sShIr), + fsm(sUpdIr, sSelDr, sRti), + ]), + ]); + + // TDO is combinational: the LSB of whichever shift register is active, i.e. + // the bit about to be shifted out. Per IEEE 1149.1 the host samples TDO + // while TCK is low (before the rising edge that shifts), which is exactly + // how OpenOCD's remote_bitbang reads it. (A registered-on-rising-edge TDO + // presents the bit one step late for that convention.) + output('tdo') <= + mux( + tapState.eq(sShIr), + irShift[0], + mux(tapState.eq(sShDr), dr[0], Const(0)), + ); + + // dtmcs read word: version=1, abits=7, dmistat, idle hint. + final dtmcsVal = + Const(0x1071, width: 32) | (dmiStatus.zeroExtend(32) << 10); + + // dmstatus: version=2 (0.13.2), authenticated, all/anyhalted or + // all/anyrunning, all/anyresumeack. + final dmstatusVal = + Const(2, width: 32) | + Const(1 << 7, width: 32) | + Const((1 << 17) | (1 << 16), width: 32) | + mux( + hartHaltedIn, + Const((1 << 9) | (1 << 8), width: 32), + Const((1 << 11) | (1 << 10), width: 32), + ); + + // sbcs read word: sbversion=1, sbaccess size, sbasize=xlen, busy, error, + // the supported access-size flags. + final sbcsVal = + Const(1 << 29, width: 32) | + (sbAccessSize.zeroExtend(32) << 17) | + Const(xlen << 5, width: 32) | + (sbBusy.zeroExtend(32) << 21) | + (sbError.zeroExtend(32) << 12) | + (sbAutoincr.zeroExtend(32) << 16) | + (sbReadOnAddr.zeroExtend(32) << 20) | + (sbReadOnData.zeroExtend(32) << 15) | + Const(0xF, width: 32); // sbaccess 8/16/32/64 supported + + // DMI read value selected by the address shifted into dr. + final dmiReadAddr = dr.getRange(34, 41); + final dmiReadVal = Logic(name: 'dmi_read_val', width: 32); + Combinational([ + dmiReadVal < Const(0, width: 32), + Case(dmiReadAddr, [ + CaseItem(Const(0x11, width: 7), [dmiReadVal < dmstatusVal]), + CaseItem(Const(0x10, width: 7), [ + dmiReadVal < + (dmactive.zeroExtend(32) | (ndmresetReg.zeroExtend(32) << 1)), + ]), + CaseItem(Const(0x16, width: 7), [ + dmiReadVal < + (Const(0x2, width: 32) | + (cmderr.zeroExtend(32) << 8) | + ((cmdPending | cmdActive).zeroExtend(32) << 12)), + ]), + CaseItem(Const(0x04, width: 7), [dmiReadVal < data0]), + CaseItem(Const(0x05, width: 7), [dmiReadVal < data1]), + CaseItem(Const(0x38, width: 7), [dmiReadVal < sbcsVal]), + CaseItem(Const(0x39, width: 7), [ + dmiReadVal < sbaddress.getRange(0, 32), + ]), + CaseItem(Const(0x3c, width: 7), [dmiReadVal < sbdata0]), + CaseItem(Const(0x3d, width: 7), [dmiReadVal < sbdata1]), + ]), + ]); + + // Fields of a DMI scan once shifted into dr. + final scanOp = dr.getRange(0, 2); + final scanData = dr.getRange(2, 34); + final scanAddr = dr.getRange(34, 41); + + // Bus-master combinational outputs. + output('sba_req') <= sbState.eq(sbReqState); + // Busy while an abstract command or a system-bus access is mid-flight. + output('dm_busy') <= cmdPending | cmdActive | ~sbState.eq(sbIdle); + output('sba_we') <= sbWeReg; + output('sba_addr') <= sbAddrReg; + output('sba_wdata') <= sbWdataReg; + output('sba_size') <= sbAccessSize; + output('reg_read') <= regReadReg; + output('reg_write') <= regWriteReg; + output('reg_addr') <= regAddrReg; + output('reg_wdata') <= regWdataReg; + output('halt_req') <= haltReqReg; + output('ndmreset') <= ndmresetReg; + + // A pulse that asks the SBA FSM to start an access this cycle. + final sbStart = Logic(name: 'sb_start'); + final sbStartWe = Logic(name: 'sb_start_we'); + final sbStartAddr = Logic(name: 'sb_start_addr', width: xlen); + final sbStartWdata = Logic(name: 'sb_start_wdata', width: xlen); + + Sequential(clk, [ + If( + reset, + then: [ + tapState < Const(sTlr, width: 4), + irReg < Const(_irIdcode, width: irWidth), + irShift < Const(0, width: irWidth), + dr < Const(0, width: _dmiWidth), + drLen < Const(1, width: 7), + tckPrev < Const(0), + dmiData < Const(0, width: 32), + dmiAddr < Const(0, width: _abits), + dmiStatus < Const(0, width: 2), + dmactive < Const(0), + data0 < Const(0, width: 32), + data1 < Const(0, width: 32), + cmderr < Const(0, width: 3), + sbaddress < Const(0, width: xlen), + sbdata0 < Const(0, width: 32), + sbdata1 < Const(0, width: 32), + sbAccessSize < Const(xlen == 64 ? 3 : 2, width: 3), + sbAutoincr < Const(0), + sbReadOnAddr < Const(0), + sbReadOnData < Const(0), + sbError < Const(0, width: 3), + sbState < Const(sbIdle, width: 2), + sbWeReg < Const(0), + sbAddrReg < Const(0, width: xlen), + sbWdataReg < Const(0, width: xlen), + sbBusy < Const(0), + output('resume_req') < Const(0), + regReadReg < Const(0), + regWriteReg < Const(0), + regAddrReg < Const(0, width: 16), + regWdataReg < Const(0, width: xlen), + cmdPending < Const(0), + cmdActive < Const(0), + cmdIs64 < Const(0), + cmdWrite < Const(0), + haltReqReg < Const(0), + ndmresetReg < Const(0), + sbStart < Const(0), + sbStartWe < Const(0), + sbStartAddr < Const(0, width: xlen), + sbStartWdata < Const(0, width: xlen), + ], + orElse: [ + tckPrev < tck, + output('resume_req') < Const(0), + + // Defaults for the per-cycle start pulse (overridden in the tap step). + sbStart < Const(0), + sbStartWe < Const(0), + sbStartAddr < sbaddress, + sbStartWdata < sbdata0.zeroExtend(xlen), + + // ---- TAP step (one per rising TCK) ---- + If( + tckRise, + then: [ + // Shift the active register while in a shift state. + If( + tapState.eq(sShIr), + then: [ + irShift < + ((tdi.zeroExtend(irWidth) << + Const(irWidth - 1, width: irWidth)) | + (irShift >>> 1)), + ], + ), + If( + tapState.eq(sShDr), + then: [ + dr < + ((tdi.zeroExtend(_dmiWidth) << (drLen - 1)) | (dr >>> 1)), + ], + ), + + // Entering-state actions, keyed on tapNext. + If( + tapNext.eq(sTlr), + then: [irReg < Const(_irIdcode, width: irWidth)], + ), + If( + tapNext.eq(sCapIr), + then: [irShift < Const(0x01, width: irWidth)], + ), + If(tapNext.eq(sUpdIr), then: [irReg < irShift]), + + // Capture-DR loads the DR per the current instruction. + If( + tapNext.eq(sCapDr), + then: [ + If( + irReg.eq(_irIdcode), + then: [ + dr < Const(idcode & 0xFFFFFFFF, width: _dmiWidth), + drLen < Const(32, width: 7), + ], + orElse: [ + If( + irReg.eq(_irDtmcs), + then: [ + dr < dtmcsVal.zeroExtend(_dmiWidth), + drLen < Const(32, width: 7), + ], + orElse: [ + If( + irReg.eq(_irDmi), + then: [ + dr < [dmiAddr, dmiData, dmiStatus].swizzle(), + drLen < Const(_dmiWidth, width: 7), + ], + orElse: [ + dr < Const(0, width: _dmiWidth), + drLen < Const(1, width: 7), + ], + ), + ], + ), + ], + ), + ], + ), + + // Update-DR performs the DMI transaction. + If( + tapNext.eq(sUpdDr), + then: [ + If( + irReg.eq(_irDmi), + then: [ + dmiAddr < scanAddr, + dmiStatus < Const(0, width: 2), + // Read. + If( + scanOp.eq(1), + then: [ + dmiData < dmiReadVal, + // sbdata0 read with sbreadondata kicks another access. + If( + scanAddr.eq(0x3c) & sbReadOnData, + then: [sbStart < Const(1), sbStartWe < Const(0)], + ), + ], + ), + // Write. + If( + scanOp.eq(2), + then: [ + Case(scanAddr, [ + CaseItem(Const(0x10, width: 7), [ + dmactive < scanData[0], + ndmresetReg < scanData[1], + If(scanData[31], then: [haltReqReg < Const(1)]), + If( + scanData[30], + then: [ + haltReqReg < Const(0), + output('resume_req') < Const(1), + ], + ), + ]), + CaseItem(Const(0x04, width: 7), [data0 < scanData]), + CaseItem(Const(0x05, width: 7), [data1 < scanData]), + CaseItem(Const(0x17, width: 7), [ + // Abstract command: only access-register (cmdtype 0). + cmderr < Const(0, width: 3), + If( + scanData.getRange(24, 32).eq(0), + then: [ + If( + scanData[17], + then: [ + // transfer=1: kick a register access. + cmdPending < Const(1), + cmdWrite < scanData[16], + cmdIs64 < scanData.getRange(20, 23).eq(3), + regAddrReg < scanData.getRange(0, 16), + ], + ), + ], + orElse: [ + cmderr < + Const(2, width: 3), // unsupported cmdtype + ], + ), + ]), + CaseItem(Const(0x38, width: 7), [ + sbAccessSize < scanData.getRange(17, 20), + sbAutoincr < scanData[16], + sbReadOnAddr < scanData[20], + sbReadOnData < scanData[15], + sbError < (sbError & ~scanData.getRange(12, 15)), + ]), + CaseItem(Const(0x39, width: 7), [ + sbaddress < scanData.zeroExtend(xlen), + If( + sbReadOnAddr, + then: [ + sbStart < Const(1), + sbStartWe < Const(0), + sbStartAddr < scanData.zeroExtend(xlen), + ], + ), + ]), + CaseItem(Const(0x3c, width: 7), [ + sbdata0 < scanData, + sbStart < Const(1), + sbStartWe < Const(1), + sbStartWdata < scanData.zeroExtend(xlen), + ]), + CaseItem(Const(0x3d, width: 7), [ + sbdata1 < scanData, + ]), + ]), + ], + ), + ], + ), + // DTMCS dmireset/dmihardreset clears sticky status. + If( + irReg.eq(_irDtmcs), + then: [ + If( + scanData[16] | scanData[17], + then: [dmiStatus < Const(0, width: 2)], + ), + ], + ), + ], + ), + + tapState < tapNext, + ], + ), + + // ---- SBA bus-master FSM (one per system clock) ---- + Case(sbState, [ + CaseItem(Const(sbIdle, width: 2), [ + If( + sbStart, + then: [ + sbState < Const(sbReqState, width: 2), + sbBusy < Const(1), + sbWeReg < sbStartWe, + sbAddrReg < sbStartAddr, + sbWdataReg < sbStartWdata, + ], + ), + ]), + CaseItem(Const(sbReqState, width: 2), [ + If( + sbaAckIn, + then: [ + sbState < Const(sbIdle, width: 2), + sbBusy < Const(0), + If( + ~sbWeReg, + then: [ + sbdata0 < sbaRdataIn.getRange(0, 32), + if (xlen == 64) sbdata1 < sbaRdataIn.getRange(32, 64), + ], + ), + If( + sbAutoincr, + then: [ + sbaddress < (sbAddrReg + sbBytes(sbAccessSize, xlen)), + ], + ), + ], + ), + ]), + ]), + + // ---- Abstract register-access FSM (Phase 2 hook) ---- + // A command first asserts the request (cmdActive), then completes once + // the core reports ready. This guarantees the request pulse is visible + // even when the core's regfile is zero-latency (ready always high). + If( + cmdActive, + then: [ + If( + regReadyIn, + then: [ + cmdActive < Const(0), + regReadReg < Const(0), + regWriteReg < Const(0), + // Only a read pulls the result back into data0/data1. + If( + ~cmdWrite, + then: [ + data0 < regRdataIn.getRange(0, 32), + if (xlen == 64) data1 < regRdataIn.getRange(32, 64), + ], + ), + ], + ), + ], + orElse: [ + If( + cmdPending, + then: [ + cmdPending < Const(0), + cmdActive < Const(1), + regReadReg < ~cmdWrite, + regWriteReg < cmdWrite, + regWdataReg < + (xlen == 64 + ? mux( + cmdIs64, + [data1, data0].swizzle(), + data0.zeroExtend(xlen), + ) + : data0.zeroExtend(xlen)), + ], + ), + ], + ), + ], + ), + ]); + } +} + +/// Bytes-per-access from the sbaccess size field (0->1, 1->2, 2->4, 3->8). +Logic sbBytes(Logic size, int xlen) => + (Const(1, width: xlen) << size.zeroExtend(xlen)); diff --git a/packages/river_hdl/lib/src/core/debug_pump.dart b/packages/river_hdl/lib/src/core/debug_pump.dart new file mode 100644 index 0000000..2648c58 --- /dev/null +++ b/packages/river_hdl/lib/src/core/debug_pump.dart @@ -0,0 +1,85 @@ +import 'dart:async'; + +/// Paces the remote-bitbang sim clock against JTAG activity, with a resume-aware +/// free-run so a resumed program actually executes. +/// +/// The remote_bitbang JTAG transport advances the simulator on demand: normally +/// one core clock per JTAG bit (the TAP shifts once per bit). That cadence is +/// fine for examine/halt/abstract-command traffic, but it STARVES a running +/// program. After the debugger resumes the hart, OpenOCD only clocks the core +/// while it is polling `dmstatus`, so a multi-instruction program never reaches +/// its result before OpenOCD force-halts. The half-run state then reads back as +/// a spurious "divergence" against a free-running golden model (spike/emulator). +/// +/// [ResumePump] fixes that: on a halted -> running RESUME EDGE it free-runs the +/// core to its self-halt (an armed `ebreak`), bounded by [resumeBudget] so a +/// program that never self-halts falls back to one-clock-per-bit instead of +/// wedging. It yields to the event loop every [yieldEvery] clocks so a long +/// free-run does not monopolize the loop (the failure mode of `Simulator.run()`, +/// which starves all I/O and timers). +/// +/// NOTE: the remote_bitbang server processes JTAG bits serially +/// (`await for (data) { ... await onTick() }`), so an OpenOCD halt request that +/// arrives DURING the free-run is not read until the free-run returns. The +/// free-run therefore terminates on the program's own self-halt or the budget, +/// not on a mid-run debugger halt. That is correct for the verification flow +/// (Heimdall loads self-halting firmware). Honoring a mid-run halt would require +/// driving the core clock from a background loop decoupled from `onTick`; that is +/// a future refinement, see project_debug_jtag. +/// +/// Critically, the free-run is gated on the halted -> running EDGE, not on +/// "the core is running". The core also runs after reset/examine (the default +/// firmware is an idle loop that never self-halts); free-running THAT would spin +/// the budget on every bit and wedge examine. Only a real debugger resume (the +/// hart was halted on the previous observation and is running now) triggers it. +class ResumePump { + /// Advance the simulator by exactly one core clock (one rising edge), + /// servicing whatever the sim needs to service on that edge (e.g. SBA). + final Future Function() advanceOneClock; + + /// Read the core's current debug-halt state (true = halted in Debug Mode). + final bool Function() coreHalted; + + /// Maximum clocks to free-run after a resume before falling back to + /// one-clock-per-bit. Real firmware self-halts long before this. + final int resumeBudget; + + /// Yield to the event loop (to service the JTAG socket) every this many + /// free-run clocks. Must be a power of two minus one is not required; this is + /// used as a modulus. + final int yieldEvery; + + bool _wasHalted; + + ResumePump({ + required this.advanceOneClock, + required this.coreHalted, + this.resumeBudget = 2000000, + this.yieldEvery = 256, + bool initiallyHalted = false, + }) : _wasHalted = initiallyHalted; + + /// The halt state observed at the end of the most recent [pump]. Exposed for + /// tests and tracing. + bool get wasHalted => _wasHalted; + + /// Drive one JTAG bit's worth of clocking. Advances one core clock; if that + /// clock completed a resume edge, free-runs to self-halt (bounded). + Future pump() async { + await advanceOneClock(); + if (_wasHalted && !coreHalted()) { + var budget = resumeBudget; + while (budget > 0 && !coreHalted()) { + await advanceOneClock(); + budget--; + if (budget % yieldEvery == 0) { + // Hand the event loop a turn so a long free-run does not monopolize it + // (keeps timers / other I/O alive). Does not let the parked JTAG read + // process a new bit; see the class note. + await Future.delayed(Duration.zero); + } + } + } + _wasHalted = coreHalted(); + } +} diff --git a/packages/river_hdl/lib/src/core/debug_subsystem.dart b/packages/river_hdl/lib/src/core/debug_subsystem.dart new file mode 100644 index 0000000..54102a5 --- /dev/null +++ b/packages/river_hdl/lib/src/core/debug_subsystem.dart @@ -0,0 +1,124 @@ +import 'package:rohd/rohd.dart'; +import 'package:rohd_bridge/rohd_bridge.dart'; +import 'package:river/river.dart'; + +import 'debug.dart'; +import 'jtag_bscan_tunnel.dart'; +import 'sba_wishbone.dart'; + +/// SoC-level JTAG debug subsystem. On ECP5 it reaches the debugger over the FPGA +/// config JTAG (dirtyJtag) via the `JTAGG` ER1 user register + a SiFive bscan +/// tunnel, so no extra JTAG pads and no second probe. Wraps: +/// Ecp5Jtagg (config-JTAG user register taps) +/// -> JtagBscanTunnel (frame decode -> inner TAP drive) +/// -> RiverDebugModule (TAP + DTM + DM + SBA, sim-proven) +/// -> SbaWishboneAdapter (SBA -> Wishbone master `bus`) +/// +/// Exposes a Wishbone master `bus` (second fabric master for memory access) and +/// the core-facing debug control ports; JTAG pins are internal to `JTAGG`. genip +/// wires `bus` via `soc.addMaster` and the control ports to a +/// `RiverCore(withDebug: true)`. +/// +/// OpenOCD reaches it with `riscv use_bscan_tunnel 6 1` over the ECP5 TAP. +/// HW-validation pending; the tunnel framing is the piece to confirm live. +class RiverDebugSubsystem extends BridgeModule { + RiverDebugSubsystem( + WishboneConfig config, { + required int xlen, + int idcode = 0x10000001, + String? name, + }) : super('RiverDebugSubsystem', name: name ?? 'debug_jtag') { + createPort('clk', PortDirection.input); + createPort('reset', PortDirection.input); + // Core-facing: from the core. + createPort('hart_halted', PortDirection.input); + createPort('reg_rdata', PortDirection.input, width: xlen); + createPort('reg_ready', PortDirection.input); + // Core-facing: to the core. + createPort('halt_req', PortDirection.output); + createPort('resume_req', PortDirection.output); + createPort('ndmreset', PortDirection.output); + createPort('reg_read', PortDirection.output); + createPort('reg_write', PortDirection.output); + createPort('reg_addr', PortDirection.output, width: 16); + createPort('reg_wdata', PortDirection.output, width: xlen); + + // Wishbone master (provider): drives the fabric, reads ack/datMiso back. + final busRef = addInterface( + WishboneInterface(config), + name: 'bus', + role: PairRole.provider, + ); + final bus = busRef.internalInterface as WishboneInterface; + + // ECP5 config-JTAG user register taps (ER1). + final jtagg = Ecp5Jtagg(); + + // Tunnel: ER1 framed scan -> inner TAP signals. + final tunnel = JtagBscanTunnel(maxScanBits: xlen); + tunnel.input('clk').srcConnection! <= input('clk'); + tunnel.input('reset').srcConnection! <= input('reset'); + tunnel.input('jtck').srcConnection! <= jtagg.output('JTCK'); + tunnel.input('jtdi').srcConnection! <= jtagg.output('JTDI'); + tunnel.input('jshift').srcConnection! <= jtagg.output('JSHIFT'); + tunnel.input('jupdate').srcConnection! <= jtagg.output('JUPDATE'); + tunnel.input('jce1').srcConnection! <= jtagg.output('JCE1'); + tunnel.input('jrstn').srcConnection! <= jtagg.output('JRSTN'); + jtagg.input('JTDO1').srcConnection! <= tunnel.output('jtdo1'); + jtagg.input('JTDO2').srcConnection! <= Const(0); + + // Nets feeding the DM's SBA response, driven by the adapter below. + final sbaRdata = Logic(name: 'sba_rdata', width: xlen); + final sbaAck = Logic(name: 'sba_ack'); + + final dm = RiverDebugModule( + input('clk'), + input('reset'), + tunnel.output('inner_tck'), + tunnel.output('inner_tms'), + tunnel.output('inner_tdi'), + tunnel.output('inner_trst_n'), + hartHalted: input('hart_halted'), + regRdata: input('reg_rdata'), + regReady: input('reg_ready'), + sbaRdata: sbaRdata, + sbaAck: sbaAck, + xlen: xlen, + idcode: idcode, + ); + tunnel.input('inner_tdo').srcConnection! <= dm.tdo; + + // DM outputs to the core. + output('halt_req') <= dm.haltReq; + output('resume_req') <= dm.resumeReq; + output('ndmreset') <= dm.ndmreset; + output('reg_read') <= dm.regRead; + output('reg_write') <= dm.regWrite; + output('reg_addr') <= dm.regAddr; + output('reg_wdata') <= dm.regWdata; + + // SBA -> Wishbone. + final adapter = SbaWishboneAdapter( + dataWidth: config.dataWidth, + addressWidth: config.addressWidth, + xlen: xlen, + ); + adapter.input('sba_req').srcConnection! <= dm.sbaReq; + adapter.input('sba_we').srcConnection! <= dm.sbaWe; + adapter.input('sba_addr').srcConnection! <= dm.sbaAddr; + adapter.input('sba_wdata').srcConnection! <= dm.sbaWdata; + adapter.input('sba_size').srcConnection! <= dm.sbaSize; + adapter.input('wb_ack').srcConnection! <= bus.ack; + adapter.input('wb_dat_miso').srcConnection! <= bus.datMiso; + + sbaRdata <= adapter.output('sba_rdata'); + sbaAck <= adapter.output('sba_ack'); + + bus.cyc <= adapter.output('wb_cyc'); + bus.stb <= adapter.output('wb_stb'); + bus.we <= adapter.output('wb_we'); + bus.adr <= adapter.output('wb_adr'); + bus.datMosi <= adapter.output('wb_dat_mosi'); + bus.sel <= adapter.output('wb_sel'); + } +} diff --git a/packages/river_hdl/lib/src/core/decode_control.dart b/packages/river_hdl/lib/src/core/decode_control.dart new file mode 100644 index 0000000..a70973d --- /dev/null +++ b/packages/river_hdl/lib/src/core/decode_control.dart @@ -0,0 +1,260 @@ +import 'package:rohd/rohd.dart'; +import 'package:harbor/harbor.dart'; + +import 'issue.dart' show FuType; + +/// Single-cycle control signals for an instruction, derived at build time from +/// an operation's microcode. +/// +/// The in-order pipeline executes by stepping through +/// [RiscVOperation.microcode] one micro-op at a time. The out-of-order pipeline +/// instead needs every control signal up front so it can rename, enqueue, and +/// dispatch in a single cycle. [decodeControlForOp] collapses the microcode +/// sequence into this flat bundle; a hardware ROM indexed by the decoder's op +/// index then drives the issue queue's `enq*` ports. See +/// project_hdl_ooo_state in memory for how this fits the OoO bring-up. +class DecodeControl { + /// Which functional unit executes this instruction. + final FuType fuType; + + /// ALU operation (meaningful when [fuType] is [FuType.alu], and for the + /// address calculation of memory ops). + final RiscVAluFunct aluFunct; + + /// Writes an architectural destination register (rd or the link register). + final bool writesRd; + + final bool isLoad; + final bool isStore; + + /// Access size for loads/stores; null for non-memory ops. + final RiscVMemSize? memSize; + + /// Zero-extend (vs sign-extend) a load result. + final bool memUnsigned; + + /// Condition for conditional branches; null for non-branch ops. + final RiscVBranchCondition? branchCond; + + /// Unconditional control transfer (jal/jalr). + final bool isJump; + + /// Register-indirect jump target (jalr), as opposed to PC-relative (jal). + final bool isJalr; + + /// The ALU's second operand is the immediate (I-type) rather than rs2. + final bool useImm; + + final bool isCsr; + + /// Privileged return (mret/sret). The ROB carries this so the commit stage + /// redirects to {m,s}epc and restores the privilege mode. + final bool isReturn; + + /// Return privilege level (3=MRET, 1=SRET); meaningful when [isReturn]. + final int returnLevel; + + const DecodeControl({ + required this.fuType, + this.aluFunct = RiscVAluFunct.add, + this.writesRd = false, + this.isLoad = false, + this.isStore = false, + this.memSize, + this.memUnsigned = false, + this.branchCond, + this.isJump = false, + this.isJalr = false, + this.useImm = false, + this.isCsr = false, + this.isReturn = false, + this.returnLevel = 0, + }); + + @override + String toString() => + 'DecodeControl($fuType, alu=$aluFunct, writesRd=$writesRd, ' + 'load=$isLoad, store=$isStore, branch=$branchCond, jump=$isJump, ' + 'jalr=$isJalr, useImm=$useImm, csr=$isCsr)'; +} + +/// Collapses [op]'s microcode sequence into a flat [DecodeControl] bundle. +/// +/// Functional-unit selection is a priority: CSR > memory > branch/jump > ALU +/// (a load still has an ALU address-calc micro-op, but it dispatches to the +/// memory unit). +DecodeControl decodeControlForOp(RiscVOperation op) { + RiscVAlu? alu; + RiscVMemLoad? load; + RiscVMemStore? store; + RiscVBranch? branch; + // Every op ends with a RiscVUpdatePc (the implicit pc+=4), so it does not mark + // a jump. Only jal/jalr write a link register, and that is the jump signal. + RiscVWriteLinkRegister? link; + RiscVUpdatePc? pcUpdate; + var hasCsr = false; + var writesRd = false; + // Some compressed ops (c.li, c.lui) write rd directly from the immediate with + // no ALU micro-op. The in-order microcode engine handles that, but the OoO + // datapath routes results through the ALU, so it needs useImm set and an add + // of x0 + imm (the decoder gives these ops rs1 == x0, so add(x0, imm) == imm). + // Without this the OoO ALU ignores the immediate and writes 0. + var directImmWrite = false; + // mret/sret: carried to commit so the OoO commit stage redirects to {m,s}epc + // and restores the mode (the in-order path handles this in exec.dart). + RiscVReturnOp? ret; + + for (final m in op.microcode) { + switch (m) { + case RiscVReturnOp r: + ret ??= r; + case RiscVAlu a: + alu ??= a; + case RiscVMemLoad l: + load ??= l; + // A load commits its result to rd (no separate RiscVWriteRegister in + // the microcode), so mark it as writing rd for rename/ROB commit. + writesRd = true; + case RiscVMemStore s: + store ??= s; + case RiscVBranch b: + branch ??= b; + case RiscVUpdatePc u: + pcUpdate ??= u; + case RiscVReadCsr _ || RiscVWriteCsr _: + hasCsr = true; + case RiscVWriteRegister w when w.dest == RiscVMicroOpField.rd: + writesRd = true; + if (w.source == RiscVMicroOpSource.imm) directImmWrite = true; + case RiscVWriteLinkRegister l: + link ??= l; + writesRd = true; + default: + break; + } + } + + final isJump = link != null; + final FuType fuType; + if (hasCsr) { + fuType = FuType.csr; + } else if (load != null || store != null) { + fuType = FuType.memory; + } else if (branch != null || isJump) { + fuType = FuType.branch; + } else { + fuType = FuType.alu; + } + + return DecodeControl( + fuType: fuType, + aluFunct: alu?.funct ?? RiscVAluFunct.add, + writesRd: writesRd, + isLoad: load != null, + isStore: store != null, + memSize: load?.size ?? store?.size, + memUnsigned: load?.unsigned ?? false, + branchCond: branch?.condition, + isJump: isJump, + // jalr computes an absolute target (rs1+imm via the ALU); jal is the + // PC-relative form. The linking PC update's `absolute` flag distinguishes. + isJalr: isJump && (pcUpdate?.absolute ?? false), + useImm: (alu != null && alu.b == RiscVMicroOpField.imm) || directImmWrite, + isCsr: hasCsr, + isReturn: ret != null, + returnLevel: ret?.privilegeLevel ?? 0, + ); +} + +/// fu_branch expects the RISC-V funct3 branch encoding, not the +/// [RiscVBranchCondition] declaration order. +int branchCondFunct3(RiscVBranchCondition? c) => switch (c) { + RiscVBranchCondition.eq => 0, + RiscVBranchCondition.ne => 1, + RiscVBranchCondition.lt => 4, + RiscVBranchCondition.ge => 5, + RiscVBranchCondition.ltu => 6, + RiscVBranchCondition.geu => 7, + null => 0, +}; + +/// Combinational ROM mapping the decoder's op index to the flat control signals +/// the out-of-order issue queue and functional units consume. Built at +/// elaboration time from [decodeControlForOp] over the operation table, so it +/// carries no runtime decode cost. Outputs use the FU-side encodings: +/// `fuType`=[FuType.index], `aluFunct`=[RiscVAluFunct.index], `memSize`=byte +/// count, `branchCond`=funct3 (see [branchCondFunct3]). +class DecodeControlRom extends Module { + Logic get fuType => output('fu_type'); + Logic get aluFunct => output('alu_funct'); + Logic get writesRd => output('writes_rd'); + Logic get isLoad => output('is_load'); + Logic get isStore => output('is_store'); + Logic get memSize => output('mem_size'); + Logic get memUnsigned => output('mem_unsigned'); + Logic get branchCond => output('branch_cond'); + Logic get isJump => output('is_jump'); + Logic get isJalr => output('is_jalr'); + Logic get useImm => output('use_imm'); + Logic get isCsr => output('is_csr'); + Logic get isReturn => output('is_return'); + Logic get returnLevel => output('return_level'); + + DecodeControlRom( + Logic index, { + required Map operations, + super.name = 'decode_control_rom', + }) { + index = addInput('index', index, width: index.width); + + addOutput('fu_type', width: 2); + addOutput('alu_funct', width: 7); + addOutput('writes_rd'); + addOutput('is_load'); + addOutput('is_store'); + addOutput('mem_size', width: 3); + addOutput('mem_unsigned'); + addOutput('branch_cond', width: 3); + addOutput('is_jump'); + addOutput('is_jalr'); + addOutput('use_imm'); + addOutput('is_csr'); + addOutput('is_return'); + addOutput('return_level', width: 2); + + List drive(DecodeControl c) { + // memSize is the access byte count in 3 bits (1/2/4). dword (8) only + // appears on RV64 cores, which fu_mem's 3-bit size port does not yet + // support; clamp so the ROM still elaborates for those configs. + final sizeBytes = (c.memSize?.bytes ?? 0) <= 4 + ? (c.memSize?.bytes ?? 0) + : 4; + return [ + fuType < Const(c.fuType.index, width: 2), + aluFunct < Const(c.aluFunct.index, width: 7), + writesRd < Const(c.writesRd ? 1 : 0), + isLoad < Const(c.isLoad ? 1 : 0), + isStore < Const(c.isStore ? 1 : 0), + memSize < Const(sizeBytes, width: 3), + memUnsigned < Const(c.memUnsigned ? 1 : 0), + branchCond < Const(branchCondFunct3(c.branchCond), width: 3), + isJump < Const(c.isJump ? 1 : 0), + isJalr < Const(c.isJalr ? 1 : 0), + useImm < Const(c.useImm ? 1 : 0), + isCsr < Const(c.isCsr ? 1 : 0), + isReturn < Const(c.isReturn ? 1 : 0), + returnLevel < Const(c.returnLevel & 0x3, width: 2), + ]; + } + + Combinational([ + Case(index, [ + for (final e in operations.entries) + CaseItem( + Const(e.key, width: index.width), + drive(decodeControlForOp(e.value)), + ), + ], defaultItem: drive(const DecodeControl(fuType: FuType.alu))), + ]); + } +} diff --git a/packages/river_hdl/lib/src/core/decoder.dart b/packages/river_hdl/lib/src/core/decoder.dart index 0366039..97f0095 100644 --- a/packages/river_hdl/lib/src/core/decoder.dart +++ b/packages/river_hdl/lib/src/core/decoder.dart @@ -1,10 +1,12 @@ import 'package:rohd/rohd.dart'; -import 'package:rohd_hcl/rohd_hcl.dart'; -import 'package:riscv/riscv.dart'; +import 'package:harbor/harbor.dart' hide PrivilegeMode; +import 'package:river/river.dart'; +import '../data_port.dart'; +import '../microcode_rom.dart'; abstract class InstructionDecoder extends Module { - final Mxlen mxlen; - final Microcode microcode; + final RiscVMxlen mxlen; + final MicrocodeRom microcode; final List staticInstructions; Logic get done => output('done'); @@ -12,6 +14,12 @@ abstract class InstructionDecoder extends Module { Logic get index => output('index'); Logic get counter => output('counter'); + /// The PC of the instruction whose decode is on the outputs. Passed in + /// alongside the raw instruction and registered with the decode, so the PC, + /// instruction, and decoded fields all describe the same instruction (fixes + /// the PC/decode skew that mis-routes branches). + Logic get pcOut => output('pc_out'); + Map get fields => Map.fromEntries( fieldWidths.entries.map( (entry) => MapEntry(entry.key, output(computeName(entry.key))), @@ -28,6 +36,7 @@ abstract class InstructionDecoder extends Module { Logic input, { int counterWidth = 32, DataPortInterface? microcodeRead, + Logic? pcIn, required this.microcode, required this.mxlen, this.staticInstructions = const [], @@ -37,12 +46,17 @@ abstract class InstructionDecoder extends Module { reset = addInput('reset', reset); enable = addInput('enable', enable); input = addInput('instr', input, width: 32); + pcIn = addInput( + 'pc_in', + pcIn ?? Const(0, width: mxlen.size), + width: mxlen.size, + ); if (microcodeRead != null) { - microcodeRead = microcodeRead!.clone() + microcodeRead = microcodeRead.clone() ..connectIO( this, - microcodeRead!, + microcodeRead, outputTags: {DataPortGroup.control}, inputTags: {DataPortGroup.data, DataPortGroup.integrity}, uniquify: (og) => 'microcodeRead_$og', @@ -54,6 +68,7 @@ abstract class InstructionDecoder extends Module { addOutput('index', width: microcode.opIndexWidth); addOutput('imm', width: mxlen.size); addOutput('counter', width: counterWidth); + addOutput('pc_out', width: mxlen.size); for (final entry in fieldWidths.entries) { if (entry.key == 'imm') continue; @@ -75,12 +90,13 @@ abstract class InstructionDecoder extends Module { index < 0, done < 0, counter < 0, + pcOut < 0, if (microcodeRead != null) ...[ - microcodeRead!.en < 0, - microcodeRead!.addr < 0, + microcodeRead.en < 0, + microcodeRead.addr < 0, ], - ...instrTypeMap.entries.map((entry) => entry.value < 0).toList(), - ...fields.entries.map((entry) => entry.value < 0).toList(), + ...instrTypeMap.entries.map((entry) => entry.value < 0), + ...fields.entries.map((entry) => entry.value < 0), ...this.reset(), ], orElse: [ @@ -88,20 +104,21 @@ abstract class InstructionDecoder extends Module { enable, then: [ counter < (counter + 1), + pcOut < pcIn, ...decode(input), if (microcodeRead != null) - ...decodeMicrocode(input, microcodeRead!), + ...decodeMicrocode(input, microcodeRead), ], orElse: [ valid < 0, index < 0, done < 0, if (microcodeRead != null) ...[ - microcodeRead!.en < 0, - microcodeRead!.addr < 0, + microcodeRead.en < 0, + microcodeRead.addr < 0, ], - ...instrTypeMap.entries.map((entry) => entry.value < 0).toList(), - ...fields.entries.map((entry) => entry.value < 0).toList(), + ...instrTypeMap.entries.map((entry) => entry.value < 0), + ...fields.entries.map((entry) => entry.value < 0), ...this.reset(), ], ), @@ -115,7 +132,7 @@ abstract class InstructionDecoder extends Module { 'SType' => [ input.slice(31, 25), input.slice(11, 7), - ].swizzle().zeroExtend(mxlen.size).signExtend(mxlen.size), + ].swizzle().signExtend(mxlen.size), 'BType' => [ input.slice(31, 31), input.slice(7, 7), @@ -135,9 +152,103 @@ abstract class InstructionDecoder extends Module { Const(0, width: 1), ].swizzle().signExtend(mxlen.size), 'SystemIType' => input.slice(31, 20).signExtend(mxlen.size), + // CJ/CB now go through immFor()/rvcImmLogic via op.immKind; these legacy + // cases remain for the dynamic (microcoded) decoder's type-string path. + // CJ-type (c.j, c.jal): offset[11|4|9:8|10|6|7|3:1|5], sign-extended. + 'CJType' => [ + input.slice(12, 12), // off[11] + input.slice(8, 8), // off[10] + input.slice(10, 10), // off[9] + input.slice(9, 9), // off[8] + input.slice(6, 6), // off[7] + input.slice(7, 7), // off[6] + input.slice(2, 2), // off[5] + input.slice(11, 11), // off[4] + input.slice(5, 5), // off[3] + input.slice(4, 4), // off[2] + input.slice(3, 3), // off[1] + Const(0, width: 1), // off[0] + ].swizzle().signExtend(mxlen.size), + // CB-type (c.beqz, c.bnez): offset[8|4:3|7:6|2:1|5], sign-extended. + 'CBType' => [ + input.slice(12, 12), // off[8] + input.slice(6, 6), // off[7] + input.slice(5, 5), // off[6] + input.slice(2, 2), // off[5] + input.slice(11, 11), // off[4] + input.slice(10, 10), // off[3] + input.slice(4, 4), // off[2] + input.slice(3, 3), // off[1] + Const(0, width: 1), // off[0] + ].swizzle().signExtend(mxlen.size), _ => Const(0, width: mxlen.size), }; + /// Immediate for [op]: compressed instructions use their per-instruction RVC + /// descramble ([RiscVOperation.immKind]); everything else uses the format's + /// type-based layout via [decodeImm]. + Logic immFor(RiscVOperation op, Logic input) => op.immKind != null + ? rvcImmLogic(op.immKind!, input, mxlen.size) + : decodeImm(MicrocodeRom.instrType(op), input); + + /// Computes the canonical 5-bit register index for [role] ('rd'/'rs1'/'rs2') + /// of a compressed operation [op] from [instr]. Handles implicit (fixed) + /// registers, the rd_rs1 alias, and the 3-bit prime fields that map to + /// x8-x15. Mirrors [DecodedInstruction.fromCompressed] in the emulator. + /// Shared by the static and dynamic (microcode) decoders. + Logic compReg(RiscVOperation op, Logic instr, String role) { + final fixed = switch (role) { + 'rd' => op.fixedRd, + 'rs1' => op.fixedRs1, + 'rs2' => op.fixedRs2, + _ => null, + }; + if (fixed != null) return Const(fixed, width: 5); + + final f = op.format.fields; + String? key; + var prime = false; + switch (role) { + case 'rd': + if (f.containsKey('rd_rs1_prime')) { + key = 'rd_rs1_prime'; + prime = true; + } else if (f.containsKey('rd_prime')) { + key = 'rd_prime'; + prime = true; + } else if (f.containsKey('rd_rs1')) { + key = 'rd_rs1'; + } else if (f.containsKey('rd')) { + key = 'rd'; + } + case 'rs1': + if (f.containsKey('rd_rs1_prime')) { + key = 'rd_rs1_prime'; + prime = true; + } else if (f.containsKey('rs1_prime')) { + key = 'rs1_prime'; + prime = true; + } else if (f.containsKey('rd_rs1')) { + key = 'rd_rs1'; + } else if (f.containsKey('rs1')) { + key = 'rs1'; + } + case 'rs2': + if (f.containsKey('rs2_prime')) { + key = 'rs2_prime'; + prime = true; + } else if (f.containsKey('rs2')) { + key = 'rs2'; + } + } + if (key == null) return Const(0, width: 5); + + final range = f[key]!; + final raw = instr.slice(range.end, range.start); + // Prime fields are 3 bits and map to x8-x15: {2'b01, raw} == raw + 8. + return prime ? [Const(1, width: 2), raw].swizzle() : raw.zeroExtend(5); + } + void initState() {} List decode(Logic instr) => []; @@ -152,7 +263,7 @@ abstract class InstructionDecoder extends Module { List get instrTypes { List result = []; for (final i in microcode.map.values) { - final t = Microcode.instrType(i); + final t = MicrocodeRom.instrType(i); if (result.contains(t)) continue; result.add(t); } @@ -183,29 +294,25 @@ abstract class InstructionDecoder extends Module { class DynamicInstructionDecoder extends InstructionDecoder { late final Logic _counter; + /// Latched once the pattern search matches, holding the decode result stable + /// while the multi-cycle exec unit consumes it. The base decoder clears it + /// (via [reset]) when `enable` drops at the commit boundary, so the next + /// instruction re-searches fresh. + late final Logic _held; + DynamicInstructionDecoder( - Logic clk, - Logic reset, - Logic enable, - Logic input, + super.clk, + super.reset, + super.enable, + super.input, DataPortInterface microcodeRead, { - required Microcode microcode, - required Mxlen mxlen, - int counterWidth = 32, - List staticInstructions = const [], - String name = 'river_dynamic_instruction_decoder', - }) : super( - clk, - reset, - enable, - input, - microcodeRead: microcodeRead, - microcode: microcode, - mxlen: mxlen, - counterWidth: counterWidth, - staticInstructions: staticInstructions, - name: name, - ); + required super.microcode, + required super.mxlen, + super.counterWidth, + super.staticInstructions, + super.pcIn, + super.name = 'river_dynamic_instruction_decoder', + }) : super(microcodeRead: microcodeRead); @override void initState() { @@ -213,20 +320,20 @@ class DynamicInstructionDecoder extends InstructionDecoder { name: 'counter', width: microcode.decodeLookup.length.bitLength, ); + _held = Logic(name: 'held'); } @override - List reset() => [_counter < 0]; + List reset() => [_counter < 0, _held < 0]; @override List decodeMicrocode( - Logic input, + Logic instr, DataPortInterface microcodeRead, ) { final patternStruct = OperationDecodePattern.struct( - microcode.opIndices.length.bitLength, + microcode.opIndexWidth, microcode.typeStructs.length.bitLength, - microcode.fieldIndices, ); final pattern = Map.fromEntries( @@ -238,92 +345,146 @@ class DynamicInstructionDecoder extends InstructionDecoder { }), ); + // opIndex -> operation, using the same running offset the ROM assigns + // (i += microcode.length + 1). Lets the per-op override below key on the + // runtime opIndex; the generic type-based extraction is blind to + // op.fixedRs1/fixedRd/fixedRs2 and op.immKind (so c.sdsp/c.ldsp would else + // decode rs1=0/imm=0 -> store/load @ 0). + final opByIndex = {}; + { + var i = 0; + for (final e in microcode.map.entries) { + opByIndex[i] = e.value; + i += e.value.microcode.length + 1; + } + } + // Ops needing an override: anything compressed, or carrying a fixed implicit + // register or a per-instruction RVC immediate kind. + bool needsOverride(RiscVOperation op) => + (op.opcode & 0x3) != 0x3 || + op.immKind != null || + op.fixedRd != null || + op.fixedRs1 != null || + op.fixedRs2 != null; + final overrideOps = opByIndex.entries + .where((e) => needsOverride(e.value)) + .toList(); + final opIdxWidth = pattern['opIndex']!.width; + final nzfMatch = mux( pattern['nzfMask']!.neq(0), - (input & pattern['nzfMask']!).neq(0), + (instr & pattern['nzfMask']!).neq(0), Const(1), ).named('nzfMatch'); final zfMatch = mux( pattern['zfMask']!.neq(0), - (input & pattern['zfMask']!).eq(0), + (instr & pattern['zfMask']!).eq(0), Const(1), ).named('zfMatch'); - final patternMatch = (input & pattern['mask']!) + final patternMatch = (instr & pattern['mask']!) .eq(pattern['value']!) .named('patternMatch'); return [ - microcodeRead.en < 1, - microcodeRead.addr < _counter, If( - microcodeRead.done, - then: [ + _held, + // Decode already found: hold the latched result and re-assert done/valid + // so the multi-cycle exec sees a stable decode. Base clears _held via + // reset() at the commit boundary. + then: [microcodeRead.en < 0, done < 1, valid < 1], + orElse: [ + microcodeRead.en < 1, + microcodeRead.addr < _counter, If( - microcodeRead.valid, + microcodeRead.done, then: [ If( - patternMatch & nzfMatch & zfMatch, + microcodeRead.valid, then: [ - index < pattern['opIndex']!.zeroExtend(index.width), - ...fields.entries.map((entry) => entry.value < 0).toList(), - ...instrTypeMap.entries - .map((entry) => entry.value < 0) - .toList(), - Case(pattern['type']!, [ - for (final e in instrTypeMap.entries.indexed) - CaseItem( - Const(e.$1, width: instrTypeMap.length.bitLength), - [ - e.$2.value < 1, - done < 1, - valid < 1, - ...microcode.typeStructs[e.$2.key]!.mapping.entries - .where((entry) => entry.key != 'imm') - .map((entry) { - final fieldName = entry.key; - final fieldOutput = fields[fieldName]!; - final range = entry.value; - final value = input - .slice(range.end, range.start) - .zeroExtend(fieldOutput.width) - .named(fieldName); - return fieldOutput < value; - }) - .toList(), - fields['imm']! < decodeImm(e.$2.key, input), - ], - ), - ]), + If( + patternMatch & nzfMatch & zfMatch, + then: [ + _held < 1, + index < pattern['opIndex']!.zeroExtend(index.width), + ...fields.entries.map((entry) => entry.value < 0), + ...instrTypeMap.entries.map((entry) => entry.value < 0), + Case(pattern['type']!, [ + for (final e in instrTypeMap.entries.indexed) + CaseItem( + Const(e.$1, width: instrTypeMap.length.bitLength), + [ + e.$2.value < 1, + done < 1, + valid < 1, + ...microcode.typeStructs[e.$2.key]!.fields.entries + .where((entry) => entry.key != 'imm') + .map((entry) { + final fieldName = entry.key; + final fieldOutput = fields[fieldName]!; + final range = entry.value; + final extracted = instr.slice( + range.end, + range.start, + ); + final value = + extracted.width <= fieldOutput.width + ? extracted.zeroExtend( + fieldOutput.width, + ) + : extracted.slice( + fieldOutput.width - 1, + 0, + ); + return fieldOutput < value.named(fieldName); + }), + fields['imm']! < decodeImm(e.$2.key, instr), + ], + ), + ]), + // Per-op override: apply implicit fixed registers and the RVC + // immediate descramble for compressed ops (the type-based + // extraction above is blind to op.fixedRs1 etc. and op.immKind). + // Keyed on the matched opIndex, later in the list so it wins. + if (overrideOps.isNotEmpty) + Case(pattern['opIndex']!, [ + for (final e in overrideOps) + CaseItem(Const(e.key, width: opIdxWidth), [ + fields['rd']! < compReg(e.value, instr, 'rd'), + fields['rs1']! < compReg(e.value, instr, 'rs1'), + fields['rs2']! < compReg(e.value, instr, 'rs2'), + fields['imm']! < immFor(e.value, instr), + ]), + ]), + ], + orElse: [ + _counter < (_counter + 1), + done < 0, + valid < 0, + index < 0, + ...instrTypeMap.entries.map((entry) => entry.value < 0), + ...fields.entries.map((entry) => entry.value < 0), + ], + ), ], orElse: [ - _counter < (_counter + 1), - done < 0, + done < 1, valid < 0, index < 0, - ...instrTypeMap.entries - .map((entry) => entry.value < 0) - .toList(), - ...fields.entries.map((entry) => entry.value < 0).toList(), + ...instrTypeMap.entries.map((entry) => entry.value < 0), + ...fields.entries.map((entry) => entry.value < 0), ], ), ], orElse: [ - done < 1, + done < 0, valid < 0, index < 0, - ...instrTypeMap.entries.map((entry) => entry.value < 0).toList(), - ...fields.entries.map((entry) => entry.value < 0).toList(), + ...instrTypeMap.entries.map((entry) => entry.value < 0), + ...fields.entries.map((entry) => entry.value < 0), ], ), ], - orElse: [ - done < 0, - valid < 0, - index < 0, - ...instrTypeMap.entries.map((entry) => entry.value < 0).toList(), - ...fields.entries.map((entry) => entry.value < 0).toList(), - ], ), ]; } @@ -339,61 +500,52 @@ class StaticInstructionDecoder extends InstructionDecoder { required super.mxlen, super.staticInstructions, super.counterWidth = 32, + super.pcIn, super.name = 'river_static_instruction_decoder', }); - List decode(Logic input) { - final decodeMap = lookupDecode(input); + @override + List decode(Logic instr) { + final decodeMap = lookupDecode(instr); return [ If.block([ - ...decodeMap.entries - .map( - (entry) => Iff(entry.value, [ - valid < 1, - index < Const(entry.key.opIndex, width: index.width), - ...fields.entries.map((entry) => entry.value < 0).toList(), - ...instrTypeMap.entries - .map((entry) => entry.value < 0) - .toList(), - instrTypeMap[Microcode.instrType( - microcode.execLookup[entry.key.opIndex]!, - )]! < - 1, - ...microcode - .execLookup[entry.key.opIndex]! - .struct - .mapping - .entries - .where((entry) => entry.key != 'imm') - .map((entry) { - final fieldName = entry.key; - final fieldOutput = fields[fieldName]!; - final range = entry.value; - final value = input - .getRange(range.start, range.end + 1) - .zeroExtend(fieldOutput.width) - .named(fieldName); - return fieldOutput < value; - }) - .toList(), - fields['imm']! < - decodeImm( - Microcode.instrType( - microcode.execLookup[entry.key.opIndex]!, - ), - input, - ), - done < 1, - ]), - ) - .toList(), + ...decodeMap.entries.map((mapEntry) { + final op = microcode.execLookup[mapEntry.key.opIndex]!; + final isComp = (op.opcode & 0x3) != 0x3; + return Iff(mapEntry.value, [ + valid < 1, + index < Const(mapEntry.key.opIndex, width: index.width), + ...fields.entries.map((e) => e.value < 0), + ...instrTypeMap.entries.map((e) => e.value < 0), + instrTypeMap[MicrocodeRom.instrType(op)]! < 1, + ...op.format.fields.entries.where((e) => e.key != 'imm').map((e) { + final fieldOutput = fields[e.key]!; + final range = e.value; + final extracted = instr.getRange(range.start, range.end + 1); + final value = extracted.width <= fieldOutput.width + ? extracted.zeroExtend(fieldOutput.width) + : extracted.slice(fieldOutput.width - 1, 0); + return fieldOutput < value.named(e.key); + }), + // Compressed register mapping: translate prime (x8-x15), rd_rs1 + // aliasing, and implicit (fixed) registers into rd/rs1/rs2 that the + // pipeline reads. Mirrors the emulator's DecodedInstruction logic. + if (isComp) ...[ + fields['rd']! < compReg(op, instr, 'rd'), + fields['rs1']! < compReg(op, instr, 'rs1'), + fields['rs2']! < compReg(op, instr, 'rs2'), + ], + fields['imm']! < immFor(op, instr), + done < 1, + ]); + }), Else([ valid < 0, index < 0, done < 1, - ...instrTypeMap.entries.map((entry) => entry.value < 0).toList(), - ...fields.entries.map((entry) => entry.value < 0).toList(), + ...instrTypeMap.entries.map((entry) => entry.value < 0), + ...fields.entries.map((entry) => entry.value < 0), ]), ]), ]; diff --git a/packages/river_hdl/lib/src/core/exec.dart b/packages/river_hdl/lib/src/core/exec.dart index 35468e3..3d075ff 100644 --- a/packages/river_hdl/lib/src/core/exec.dart +++ b/packages/river_hdl/lib/src/core/exec.dart @@ -1,12 +1,130 @@ import 'package:rohd/rohd.dart'; -import 'package:rohd_hcl/rohd_hcl.dart'; -import 'package:riscv/riscv.dart'; +import 'package:rohd_hcl/rohd_hcl.dart' hide DataPortInterface, DataPortGroup; +import 'package:river/river.dart'; +import '../data_port.dart'; +import '../compat.dart'; +import '../microcode_rom.dart'; +import 'alu_ops.dart'; +import 'iterative_divider.dart'; +import 'iterative_multiplier.dart'; +import 'microcode_alu.dart'; + +/// Div/rem functs routed to the shared [IterativeDivider] instead of a +/// combinational `/`/`%`. Whole RV32M/RV64M div+rem set (signed/unsigned, full+word). +const _kIterativeDivRem = { + RiscVAluFunct.div, + RiscVAluFunct.divu, + RiscVAluFunct.divw, + RiscVAluFunct.divuw, + RiscVAluFunct.rem, + RiscVAluFunct.remu, + RiscVAluFunct.remw, + RiscVAluFunct.remuw, +}; + +/// Manual IEEE-754 compare of two same-width float bit patterns [a],[b] +/// (ROHD-HCL has no FP comparator). Returns less-than / equal / ordered +/// (neither operand is NaN) as 1-bit Logics; handles +0==-0 and NaN-unordered. +/// [width] is the total bit width, [expBits] the exponent field width. +({Logic lt, Logic eq, Logic ordered}) fpCompare( + Logic a, + Logic b, + int width, + int expBits, +) { + final manBits = width - 1 - expBits; + final sa = a[width - 1]; + final sb = b[width - 1]; + final expA = a.slice(width - 2, manBits); + final expB = b.slice(width - 2, manBits); + final manA = a.slice(manBits - 1, 0); + final manB = b.slice(manBits - 1, 0); + final magA = a.slice(width - 2, 0); // exp:mantissa magnitude + final magB = b.slice(width - 2, 0); + final allOnes = Const((1 << expBits) - 1, width: expBits); + final aNaN = expA.eq(allOnes) & manA.neq(0); + final bNaN = expB.eq(allOnes) & manB.neq(0); + final bothZero = magA.eq(0) & magB.eq(0); + final sameSign = sa.eq(sb); + final ltMag = mux(sa, magA.gt(magB), magA.lt(magB)); // negative => reversed + final lt = mux(sameSign, ltMag, sa & ~bothZero); // diff sign: a microcode.isa.extensions.any((e) => e.name == 'Zvfh'); final List staticInstructions; late final Logic clk; @@ -19,6 +137,121 @@ abstract class ExecutionUnit extends Module { late final Logic? medeleg; late final Logic? mtvec; late final Logic? stvec; + late final Logic? + virtIn; // V-bit: VS-mode access to an HS-only CSR -> cause 22 + // Smstateen SE0 bits, for the VS-mode state-enable virtual-instruction nuance. + late final Logic? mstateen0Se0; + late final Logic? hstateen0Se0; + late final Logic? memFaultGuest; // dport fault was in the G-stage -> guest PF + + // LR/SC reservation (A extension): a single address reservation set by + // load-reserved and consumed/cleared by store-conditional. + late final Logic reservationValid; + late final Logic reservationAddr; + // AMO scratch: holds the loaded ("old") value across the dynamic-microcode + // read -> modify -> write phases of a single RiscVAtomicMemory micro-op, so + // the destination register gets the pre-modification value on completion. + late final Logic amoOld; + + // Floating-point (F/D) register file, internal to the in-order unit. Present + // only when the configured ISA uses FP regs (detected from op resources). + // FP reads/writes are routed here when an op's RfResource marks the field FP. + DataPortInterface? fprs1Read; + DataPortInterface? fprs2Read; + DataPortInterface? fprdWrite; + HarborRegisterFile? fpRegfile; + + // Vector register file (32 x VLEN), present when the ISA has the V extension. + DataPortInterface? vrs1Read; + DataPortInterface? vrs2Read; + DataPortInterface? vrdWrite; + HarborRegisterFile? vRegfile; + // Vector config state, written by vsetvli, read by vector ops: _vtype holds + // vtypei (vsew[5:3]/vlmul[2:0]); _vl holds the active element count. _vtmp + // holds an arith result across the read-modify-write for vl/tail masking. + Logic? _vtype; + Logic? _vl; + Logic? _vtmp; + // LMUL grouping: the register index (0..LMUL-1) within the destination group + // currently being processed by a vector arith op. + Logic? _vregIdx; + + // Single-precision FP arithmetic results, combinationally computed from the + // rs1/rs2 operand latches by ROHD-HCL units (present when hasFloat). + Logic? _fpAddS; + Logic? _fpSubS; + Logic? _fpMulS; + Logic? _fpSqrtS; + Logic? _fpAddD; + Logic? _fpSubD; + Logic? _fpMulD; + Logic? _fpSqrtD; + // Fused multiply-add results: rd = +-(rs1*rs2) +- rs3. Built by reusing the FP + // multiplier and adding 4 adders per precision (one per sign combination). + Logic? _fmaddS; + Logic? _fmsubS; + Logic? _fnmsubS; + Logic? _fnmaddS; + Logic? _fmaddD; + Logic? _fmsubD; + Logic? _fnmsubD; + Logic? _fnmaddD; + // The rs3 operand latch (instance field so cycle()'s readField/writeField can + // reach it without threading a new param through every cycle variant). + Logic? _rs3Latch; + // fp->int rounding+saturation support: |operand| converted losslessly to a + // Q64.N fixed (N = full mantissa width, so no rounding loss). cycle() extracts + // integer/round/sticky from these and applies the per-rm rounding + signed/ + // unsigned saturation. `_cvtOvf*` flags |operand| >= 2^64. + Logic? _cvtMagS; // Q64.24 magnitude of the f32 operand (89 bits) + Logic? _cvtOvfS; + Logic? _cvtMagD; // Q64.53 magnitude of the f64 operand (118 bits) + Logic? _cvtOvfD; + // fcvt int<->fp results. fp->int (W/L, signed/unsigned) is handled by the + // unified roundSatFpToInt in cycle(); only int->fp + precision converts are + // pre-built here. + Logic? _fcvtSW; // int32 -> f32 + Logic? _fcvtDW; // int32 -> f64 + Logic? _fcvtSD; // f64 -> f32 (narrow) + Logic? _fcvtDS; // f32 -> f64 (widen) + Logic? _fcvtSL; // int64 -> f32 + Logic? _fcvtDL; // int64 -> f64 + // Unsigned int->fp (rs2 bit0): s.wu/s.lu / d.wu/d.lu. + Logic? _fcvtSWu; // uint32 -> f32 + Logic? _fcvtSLu; // uint64 -> f32 + Logic? _fcvtDWu; // uint32 -> f64 + Logic? _fcvtDLu; // uint64 -> f64 + // Multi-cycle Newton-Raphson divider state (shared across precisions; only + // one fdiv runs at a time in-order). _divStep sequences the FSM; _recip holds + // the reciprocal estimate x; _divT holds the intermediate b*x. The reused + // multiplier/adder outputs are _divMulOut{S,D}; seeds are _divSeed{S,D}. + Logic? _divStep; + Logic? _recip; + Logic? _divT; + Logic? _divSeedS; + Logic? _divSeedD; + Logic? _divMulOutS; + Logic? _divMulOutD; + // Shared multi-cycle integer divider (M-extension div/rem), present when the + // ISA has M. One instance replaces the eight combinational div/rem trees that + // otherwise dominate the static execution unit's LUTs. The div/rem mop holds + // [_idivStart] high while resident and reads back the divider outputs; see + // StaticExecutionUnit.cycle and iterative_divider.dart. + IterativeDivider? _idiv; + Logic? _idivStart; + Logic? _idivDividend; + Logic? _idivDivisor; + + // Shared multi-cycle iterative multiplier (M mul family), present when the ISA + // has M. Replaces the single-cycle 64x64 partial-product tree (a large LUT4 + // cost on ECP5 25F): one chunk-multiply reused per cycle accumulates the 2*XLEN + // unsigned product. A mul/mulh* mop holds [_imulStart] while resident and reads + // back IterativeMultiplier.product; signed-high flavors apply the same two + // sign-correction subtracts as the single-cycle path. See iterative_multiplier.dart. + IterativeMultiplier? _imul; + Logic? _imulStart; + Logic? _imulA; + Logic? _imulB; Logic get done => output('done'); Logic get valid => output('valid'); @@ -28,6 +261,10 @@ abstract class ExecutionUnit extends Module { Logic get trap => output('trap'); Logic get trapCause => output('trapCause'); Logic get trapTval => output('trapTval'); + Logic get trapEpc => output('trapEpc'); + Logic get isReturn => output('isReturn'); + Logic get returnLevel => output('returnLevel'); + Logic get memGuest => output('memGuest'); Logic get fence => output('fence'); Logic get interruptHold => output('interruptHold'); Logic get counter => output('counter'); @@ -52,18 +289,27 @@ abstract class ExecutionUnit extends Module { DataPortInterface? microcodeRead, this.hasSupervisor = false, this.hasUser = false, + this.useIterativeMul = true, required this.microcode, required this.mxlen, + this.vlen = 128, Logic? mideleg, Logic? medeleg, Logic? mtvec, Logic? stvec, + Logic? virtIn, + Logic? mstateen0Se0, + Logic? hstateen0Se0, + Logic? memFaultGuest, + // Asserted when the instruction at currentPc could not be fetched because + // its translation faulted. The cycle raises instructionPageFault instead of + // executing (there is no instruction). + Logic? fetchFault, int counterWidth = 32, this.staticInstructions = const [], super.name = 'river_execution_unit', }) { - clk = addInput('clk', clk); - this.clk = clk; + this.clk = clk = addInput('clk', clk); reset = addInput('reset', reset); enable = addInput('enable', enable); @@ -77,6 +323,10 @@ abstract class ExecutionUnit extends Module { this.currentMode = addInput('currentMode', currentMode, width: 3); currentMode = this.currentMode; + final fetchFaultIn = fetchFault == null + ? Const(0) + : addInput('fetchFault', fetchFault); + instrIndex = addInput( 'instrIndex', instrIndex, @@ -85,8 +335,7 @@ abstract class ExecutionUnit extends Module { instrTypeMap = Map.fromEntries( instrTypeMap.entries.map( - (entry) => - MapEntry(entry.key, addInput(entry.value.name!, entry.value)), + (entry) => MapEntry(entry.key, addInput(entry.value.name, entry.value)), ), ); @@ -94,16 +343,16 @@ abstract class ExecutionUnit extends Module { fields.entries.map( (entry) => MapEntry( entry.key, - addInput(entry.value.name!, entry.value, width: entry.value.width), + addInput(entry.value.name, entry.value, width: entry.value.width), ), ), ); if (csrRead != null) { - this.csrRead = csrRead!.clone() + this.csrRead = csrRead.clone() ..connectIO( this, - csrRead!, + csrRead, outputTags: {DataPortGroup.control}, inputTags: {DataPortGroup.data, DataPortGroup.integrity}, uniquify: (og) => 'csrRead_$og', @@ -114,10 +363,10 @@ abstract class ExecutionUnit extends Module { } if (csrWrite != null) { - this.csrWrite = csrWrite!.clone() + this.csrWrite = csrWrite.clone() ..connectIO( this, - csrWrite!, + csrWrite, outputTags: {DataPortGroup.control, DataPortGroup.data}, inputTags: {DataPortGroup.integrity}, uniquify: (og) => 'csrWrite_$og', @@ -170,32 +419,52 @@ abstract class ExecutionUnit extends Module { ); if (microcodeRead != null) { - microcodeRead = microcodeRead!.clone() + microcodeRead = microcodeRead.clone() ..connectIO( this, - microcodeRead!, + microcodeRead, outputTags: {DataPortGroup.control}, inputTags: {DataPortGroup.data, DataPortGroup.integrity}, uniquify: (og) => 'microcodeRead_$og', ); } - if (mideleg != null) + if (mideleg != null) { this.mideleg = addInput('mideleg', mideleg, width: mxlen.size); - else + } else { this.mideleg = null; - if (medeleg != null) + } + if (medeleg != null) { this.medeleg = addInput('medeleg', medeleg, width: mxlen.size); - else + } else { this.medeleg = null; - if (mtvec != null) + } + if (mtvec != null) { this.mtvec = addInput('mtvec', mtvec, width: mxlen.size); - else + } else { this.mtvec = null; - if (stvec != null) + } + if (stvec != null) { this.stvec = addInput('stvec', stvec, width: mxlen.size); - else + } else { this.stvec = null; + } + if (virtIn != null) { + this.virtIn = addInput('virtIn', virtIn); + } else { + this.virtIn = null; + } + this.mstateen0Se0 = mstateen0Se0 == null + ? null + : addInput('mstateen0Se0', mstateen0Se0); + this.hstateen0Se0 = hstateen0Se0 == null + ? null + : addInput('hstateen0Se0', hstateen0Se0); + if (memFaultGuest != null) { + this.memFaultGuest = addInput('memFaultGuest', memFaultGuest); + } else { + this.memFaultGuest = null; + } addOutput('done'); addOutput('valid'); @@ -205,12 +474,24 @@ abstract class ExecutionUnit extends Module { addOutput('trap'); addOutput('trapCause', width: 6); addOutput('trapTval', width: mxlen.size); + // PC of the trapping instruction → {m,s}epc. Captured here (not from the + // core's live pc register, which has already advanced to tvec by the time + // the registered trap pulse reaches core). + addOutput('trapEpc', width: mxlen.size); + // xRET (MRET/SRET): isReturn pulses on the retire cycle; returnLevel is the + // privilege level being returned FROM (3=MRET, 1=SRET). core.dart restores + // PC/mode from {m,s}epc/{m,s}status on this pulse. + addOutput('isReturn'); + addOutput('returnLevel', width: 3); + // Asserted for the duration of an HLV/HSV (hypervisor virtual) memory access + // so the MMU translates it through the guest two-stage tables even from + // HS-mode (virt=0). Held while memRead/memWrite.en is held (same registered + // timing), so the multi-cycle walk sees it throughout. + addOutput('memGuest'); addOutput('fence'); addOutput('interruptHold'); addOutput('counter', width: counterWidth); - final opIndices = microcode.opIndices; - final maxLen = microcode.microOpSequences.values .map((s) => s.ops.length * 2) .fold(0, (a, b) => a > b ? a : b); @@ -220,9 +501,364 @@ abstract class ExecutionUnit extends Module { final alu = Logic(name: 'aluState', width: mxlen.size); final rs1 = Logic(name: 'rs1State', width: mxlen.size); final rs2 = Logic(name: 'rs2State', width: mxlen.size); + // Third source latch, used by the fused multiply-add ops (rs3). Its FP read + // reuses fprs1Read (reads are sequential), so no extra regfile port is needed. + final rs3 = Logic(name: 'rs3State', width: mxlen.size); + _rs3Latch = rs3; final rd = Logic(name: 'rdState', width: mxlen.size); final imm = Logic(name: 'immState', width: mxlen.size); + reservationValid = Logic(name: 'reservationValid'); + reservationAddr = Logic(name: 'reservationAddr', width: mxlen.size); + amoOld = Logic(name: 'amoOld', width: mxlen.size); + + // Floating-point register file (F/D). Instantiated only when some handled + // op reads/writes an FP register (RfResource with RiscVFloatRegFile). The + // FP regfile is 64 bits wide (holds D; F values are NaN-boxed/low-32). + final hasFloat = microcode.execLookup.values.any( + (op) => op.resources.any( + (r) => r is RfResource && r.regfile is RiscVFloatRegFile, + ), + ); + if (hasFloat) { + final fp1 = DataPortInterface(64, 5); + final fp2 = DataPortInterface(64, 5); + final fpw = DataPortInterface(64, 5); + final fpRegs = HarborRegisterFile( + numEntries: 32, + dataWidth: 64, + name: 'fp_regfile', + ); + fpRegs.input('clk').srcConnection! <= clk; + fpRegs.input('reset').srcConnection! <= reset; + fpRegs.input('rd0_addr').srcConnection! <= fp1.addr; + fpRegs.input('rd1_addr').srcConnection! <= fp2.addr; + fpRegs.input('wr_en').srcConnection! <= fpw.en; + fpRegs.input('wr_addr').srcConnection! <= fpw.addr; + fpRegs.input('wr_data').srcConnection! <= fpw.data; + fp1.data <= fpRegs.rd0Data; + fp2.data <= fpRegs.rd1Data; + fp1.done <= fp1.en; + fp1.valid <= fp1.en; + fp2.done <= fp2.en; + fp2.valid <= fp2.en; + fpw.done <= fpw.en; + fpw.valid <= fpw.en; + fprs1Read = fp1; + fprs2Read = fp2; + fprdWrite = fpw; + fpRegfile = fpRegs; + + // Single-precision FP arithmetic (combinational ROHD-HCL units wired to + // the operand latches). fsub = fadd with b's sign flipped. + final fa = FloatingPoint32(); + fa <= rs1.slice(31, 0); + final fb = FloatingPoint32(); + fb <= rs2.slice(31, 0); + final fnegb = FloatingPoint32(); + fnegb <= rs2.slice(31, 0) ^ (Const(1, width: 32) << 31); + Logic packed(FloatingPoint f) => + [f.sign, f.exponent, f.mantissa].swizzle(); + final add = FloatingPointAdderSinglePath(fa, fb); + final sub = FloatingPointAdderSinglePath(fa, fnegb); + final mul = FloatingPointMultiplierSimple(fa, fb); + final sqrt = FloatingPointSqrtSimple(fa); + _fpAddS = packed(add.sum); + _fpSubS = packed(sub.sum); + _fpMulS = packed(mul.product); + _fpSqrtS = packed(sqrt.sqrt); + + // Fused multiply-add (single): reuse the product (rs1*rs2) and add +-rs3. + // Negation flips the sign bit. fmadd=+p+c, fmsub=+p-c, fnmsub=-p+c, + // fnmadd=-p-c. Four adders feed the four functs (selected in the switch). + final fmaNegProdS = FloatingPoint32(); + fmaNegProdS <= packed(mul.product) ^ (Const(1, width: 32) << 31); + final fmaCS = FloatingPoint32(); + fmaCS <= rs3.slice(31, 0); + final fmaNegCS = FloatingPoint32(); + fmaNegCS <= rs3.slice(31, 0) ^ (Const(1, width: 32) << 31); + _fmaddS = packed(FloatingPointAdderSinglePath(mul.product, fmaCS).sum); + _fmsubS = packed(FloatingPointAdderSinglePath(mul.product, fmaNegCS).sum); + _fnmsubS = packed(FloatingPointAdderSinglePath(fmaNegProdS, fmaCS).sum); + _fnmaddS = packed( + FloatingPointAdderSinglePath(fmaNegProdS, fmaNegCS).sum, + ); + + // fcvt int<->float (single). The emulator truncates toward zero and + // ignores rm; FixedToFloat/FloatToFixed do the same, so this matches the + // golden model. fcvt.s.w: signed int32 -> f32. fcvt.w.s: f32 -> int32 + // (RTZ), sign-extended to xlen. + // FixedToFloat rejects fractionWidth==0 (it computes log2Ceil(0) = -inf), + // so use Q31.1 with the int pre-shifted left by 1: value = bits/2 == N. + final intIn = FixedPoint( + signed: true, + integerWidth: 31, + fractionWidth: 1, + ); + intIn <= (rs1.slice(31, 0).signExtend(33) << 1); + final outSW = FloatingPoint32(); + FixedToFloat(intIn, outSW); + _fcvtSW = packed(outSW); + + // int64->f32: FixedToFloat rejects fractionWidth==0, so use Q64.1 with the + // 64-bit signed integer pre-shifted left by 1 (value = bits/2 == N); the + // extra integer bit preserves the full 64-bit magnitude (no top-bit loss). + final intInL = FixedPoint( + signed: true, + integerWidth: 64, + fractionWidth: 1, + ); + intInL <= (rs1.signExtend(66) << 1); + final outSL = FloatingPoint32(); + FixedToFloat(intInL, outSL); + _fcvtSL = packed(outSL); + + // Unsigned single-precision int->fp conversions (rs2 bit0 set). uint->fp + // uses an unsigned FixedPoint (Q.1 pre-shift, like the signed path) so + // FixedToFloat treats the source as magnitude-only. (fp->uint is handled by + // the unified roundSatFpToInt in cycle().) + final uInW = FixedPoint( + signed: false, + integerWidth: 32, + fractionWidth: 1, + ); + uInW <= (rs1.slice(31, 0).zeroExtend(33) << 1); + final outSWu = FloatingPoint32(); + FixedToFloat(uInW, outSWu); + _fcvtSWu = packed(outSWu); + final uInL = FixedPoint( + signed: false, + integerWidth: 64, + fractionWidth: 1, + ); + uInL <= (rs1.zeroExtend(65) << 1); + final outSLu = FloatingPoint32(); + FixedToFloat(uInL, outSLu); + _fcvtSLu = packed(outSLu); + + // Magnitude of the f32 operand as a lossless Q64.24 fixed (24 fraction + // bits = full f32 mantissa). cycle() reads integer=[87:24], round=[23], + // sticky=|[22:0] from this for per-rm rounding + saturation. checkOverflow + // flags |f| >= 2^64. + final absFaS = FloatingPoint32(); + absFaS <= (rs1.slice(31, 0) & Const(0x7FFFFFFF, width: 32)); + final f2magS = FloatToFixed( + absFaS, + integerWidth: 64, + fractionWidth: 24, + checkOverflow: true, + ); + _cvtMagS = f2magS.fixed.packed; + _cvtOvfS = f2magS.overflow ?? Const(0); + + // fdiv: multi-cycle Newton-Raphson reusing ONE multiplier + adder per + // precision (sequenced by _divStep in the FpuOp handler), keeps + // elaboration cheap vs. unrolling ~14 FP units. Reciprocal seed + // x0 = (2*bias< ~56-bit, full f32/f64). + _divStep = Logic(name: 'divStep', width: 4); + _recip = Logic(name: 'recipEst', width: 64); + _divT = Logic(name: 'divT', width: 64); + final divIsFinal = _divStep!.eq(9); + final divIsX = ~_divStep![0] & ~_divStep!.eq(0); // even, !=0 => x*(2-t) + + _divSeedS = + Const(BigInt.from(2 * 127) << 23, width: 32) - rs2.slice(31, 0); + final divTwoS = FloatingPoint32(); + divTwoS <= Const(0x40000000, width: 32); // 2.0f + final divNegTS = FloatingPoint32(); + divNegTS <= _divT!.slice(31, 0) ^ (Const(1, width: 32) << 31); + final divUS = packed(FloatingPointAdderSinglePath(divTwoS, divNegTS).sum); + final divMulInAS = FloatingPoint32(); + divMulInAS <= + mux( + divIsFinal, + rs1.slice(31, 0), + mux(divIsX, _recip!.slice(31, 0), rs2.slice(31, 0)), + ); + final divMulInBS = FloatingPoint32(); + divMulInBS <= mux(divIsX, divUS, _recip!.slice(31, 0)); + _divMulOutS = packed( + FloatingPointMultiplierSimple(divMulInAS, divMulInBS).product, + ); + + // Double-precision arithmetic (only when the ISA uses 64-bit FP regs). + final hasDouble = microcode.execLookup.values.any( + (op) => op.resources.any( + (r) => + r is RfResource && + r.regfile is RiscVFloatRegFile && + (r.regfile as RiscVFloatRegFile).width == 64, + ), + ); + if (hasDouble) { + final da = FloatingPoint64(); + da <= rs1; + final db = FloatingPoint64(); + db <= rs2; + final dnegb = FloatingPoint64(); + dnegb <= rs2 ^ (Const(1, width: 64) << 63); + final dadd = FloatingPointAdderSinglePath(da, db); + final dsub = FloatingPointAdderSinglePath(da, dnegb); + final dmul = FloatingPointMultiplierSimple(da, db); + final dsqrt = FloatingPointSqrtSimple(da); + _fpAddD = packed(dadd.sum); + _fpSubD = packed(dsub.sum); + _fpMulD = packed(dmul.product); + _fpSqrtD = packed(dsqrt.sqrt); + + // Fused multiply-add (double): mirrors the single path with FP64 units. + final fmaNegProdD = FloatingPoint64(); + fmaNegProdD <= packed(dmul.product) ^ (Const(1, width: 64) << 63); + final fmaCD = FloatingPoint64(); + fmaCD <= rs3; + final fmaNegCD = FloatingPoint64(); + fmaNegCD <= rs3 ^ (Const(1, width: 64) << 63); + _fmaddD = packed(FloatingPointAdderSinglePath(dmul.product, fmaCD).sum); + _fmsubD = packed( + FloatingPointAdderSinglePath(dmul.product, fmaNegCD).sum, + ); + _fnmsubD = packed(FloatingPointAdderSinglePath(fmaNegProdD, fmaCD).sum); + _fnmaddD = packed( + FloatingPointAdderSinglePath(fmaNegProdD, fmaNegCD).sum, + ); + + // fcvt for double: int32<->f64 and f32<->f64 precision converts. + final outDW = FloatingPoint64(); + FixedToFloat(intIn, outDW); // signed int32 -> f64 + _fcvtDW = packed(outDW); + // int64 -> f64 (fcvt.d.l); fp->int for double is handled by the unified + // roundSatFpToInt in cycle(). + final outDL = FloatingPoint64(); + FixedToFloat(intInL, outDL); // int64 -> f64 (Q64.1 fixed from above) + _fcvtDL = packed(outDL); + + // Unsigned double int->fp conversions (rs2 bit0); the unsigned FixedPoint + // inputs (uInW/uInL) are reused with f64 outputs. + final outDWu = FloatingPoint64(); + FixedToFloat(uInW, outDWu); + _fcvtDWu = packed(outDWu); + final outDLu = FloatingPoint64(); + FixedToFloat(uInL, outDLu); + _fcvtDLu = packed(outDLu); + + // Magnitude of the f64 operand as a lossless Q64.53 fixed (53 fraction + // bits = full f64 mantissa). Same role as _cvtMagS for the single path. + final absDaD = FloatingPoint64(); + absDaD <= + (rs1 & + Const(BigInt.parse('7FFFFFFFFFFFFFFF', radix: 16), width: 64)); + final f2magD = FloatToFixed( + absDaD, + integerWidth: 64, + fractionWidth: 53, + checkOverflow: true, + ); + _cvtMagD = f2magD.fixed.packed; + _cvtOvfD = f2magD.overflow ?? Const(0); + + // f64 -> f32 (narrow): zero-extend into the 64-bit latch. + final outSD = FloatingPoint32(); + FloatingPointConverter(da, outSD); + _fcvtSD = packed(outSD).zeroExtend(mxlen.size); + // f32 -> f64 (widen): take the low 32 bits as the source float. + final outDS = FloatingPoint64(); + FloatingPointConverter(fa, outDS); + _fcvtDS = packed(outDS); + + // fdiv.d reuses the same _divStep FSM (divIsFinal/divIsX) with FP64 + // units and the full 64-bit recip/T registers. + _divSeedD = Const(BigInt.from(2 * 1023) << 52, width: 64) - rs2; + final divTwoD = FloatingPoint64(); + divTwoD <= Const(BigInt.from(0x4000000000000000), width: 64); // 2.0d + final divNegTD = FloatingPoint64(); + divNegTD <= _divT! ^ (Const(1, width: 64) << 63); + final divUD = packed( + FloatingPointAdderSinglePath(divTwoD, divNegTD).sum, + ); + final divMulInAD = FloatingPoint64(); + divMulInAD <= mux(divIsFinal, rs1, mux(divIsX, _recip!, rs2)); + final divMulInBD = FloatingPoint64(); + divMulInBD <= mux(divIsX, divUD, _recip!); + _divMulOutD = packed( + FloatingPointMultiplierSimple(divMulInAD, divMulInBD).product, + ); + } + } + + // Vector register file (32 x VLEN). Present when any handled op has a + // VectorResource. Zero-latency, ROHD auto-detects the submodule. + final hasVector = microcode.execLookup.values.any( + (op) => op.resources.any((r) => r is VectorResource), + ); + if (hasVector) { + final v1 = DataPortInterface(vlen, 5); + final v2 = DataPortInterface(vlen, 5); + final vw = DataPortInterface(vlen, 5); + final vregs = HarborRegisterFile( + numEntries: 32, + dataWidth: vlen, + name: 'v_regfile', + ); + vregs.input('clk').srcConnection! <= clk; + vregs.input('reset').srcConnection! <= reset; + vregs.input('rd0_addr').srcConnection! <= v1.addr; + vregs.input('rd1_addr').srcConnection! <= v2.addr; + vregs.input('wr_en').srcConnection! <= vw.en; + vregs.input('wr_addr').srcConnection! <= vw.addr; + vregs.input('wr_data').srcConnection! <= vw.data; + v1.data <= vregs.rd0Data; + v2.data <= vregs.rd1Data; + v1.done <= v1.en; + v1.valid <= v1.en; + v2.done <= v2.en; + v2.valid <= v2.en; + vw.done <= vw.en; + vw.valid <= vw.en; + vrs1Read = v1; + vrs2Read = v2; + vrdWrite = vw; + vRegfile = vregs; + _vtype = Logic(name: 'vtypeState', width: 11); + _vl = Logic(name: 'vlState', width: mxlen.size); + _vtmp = Logic(name: 'vtmpState', width: vlen); + _vregIdx = Logic(name: 'vregIdxState', width: 4); + } + + // One shared multi-cycle integer divider for the whole div/rem family + // (built when the ISA has M). Its control register [_idivStart] is driven + // and reset alongside the other multi-cycle state in the Sequential below; + // the operand nets carry unsigned magnitudes selected by the resident + // div/rem mop (StaticExecutionUnit.cycle). Unused (start tied low) on the + // microcode/OoO paths, where synthesis prunes it. + if (microcode.isa.extensions.any((e) => e.name == 'M')) { + _idivStart = Logic(name: 'idivStart'); + _idivDividend = Logic(name: 'idivDividend', width: mxlen.size); + _idivDivisor = Logic(name: 'idivDivisor', width: mxlen.size); + _idiv = IterativeDivider( + clk, + reset, + _idivStart!, + _idivDividend!, + _idivDivisor!, + width: mxlen.size, + ); + if (useIterativeMul) { + _imulStart = Logic(name: 'imulStart'); + _imulA = Logic(name: 'imulA', width: mxlen.size); + _imulB = Logic(name: 'imulB', width: mxlen.size); + _imul = IterativeMultiplier( + clk, + reset, + _imulStart!, + _imulA!, + _imulB!, + width: mxlen.size, + ); + } + } + Sequential(clk, [ If( reset, @@ -230,6 +866,31 @@ abstract class ExecutionUnit extends Module { alu < 0, mopStep < 0, done < 0, + output('trap') < 0, + output('trapEpc') < currentPc, + output('isReturn') < 0, + output('returnLevel') < 0, + output('memGuest') < 0, + reservationValid < 0, + amoOld < 0, + if (_divStep != null) _divStep! < 0, + if (_idivStart != null) ...[ + _idivStart! < 0, + _idivDividend! < 0, + _idivDivisor! < 0, + ], + if (_imulStart != null) ...[ + _imulStart! < 0, + _imulA! < 0, + _imulB! < 0, + ], + // Pragmatic power-on vector config (e32, vl=VLMAX) so ops work before + // an explicit vsetvli; real code sets vtype/vl first. (RVV proper + // would reset vill; this convenience keeps non-vsetvli tests valid.) + if (_vtype != null) _vtype! < Const(0x10, width: 11), + if (_vl != null) _vl! < Const(vlen ~/ 32, width: mxlen.size), + if (_vtmp != null) _vtmp! < 0, + if (_vregIdx != null) _vregIdx! < 0, rs1Read.en < 0, rs1Read.addr < 0, rs2Read.en < 0, @@ -259,6 +920,7 @@ abstract class ExecutionUnit extends Module { interruptHold < 0, nextPc < currentPc, nextSp < currentSp, + nextMode < Const(PrivilegeMode.machine.id, width: 3), counter < 0, ], orElse: [ @@ -266,38 +928,52 @@ abstract class ExecutionUnit extends Module { enable, then: [ counter < (counter + 1), - ...(microcodeRead != null - ? cycleMicrocode( - instrIndex, - mopStep, - microcodeRead!, - alu: alu, - rs1: rs1, - rs2: rs2, - rd: rd, - imm: imm, - fields: fields, - memRead: memRead, - memWrite: memWrite, - rs1Read: rs1Read, - rs2Read: rs2Read, - rdWrite: rdWrite, - ) - : cycle( - instrIndex, - mopStep, - alu: alu, - rs1: rs1, - rs2: rs2, - rd: rd, - imm: imm, - fields: fields, - memRead: memRead, - memWrite: memWrite, - rs1Read: rs1Read, - rs2Read: rs2Read, - rdWrite: rdWrite, - )), + // Default: privilege is unchanged and no trap. doTrap/MRET/SRET + // override these later in the same Sequential, taking precedence. + nextMode < currentMode, + output('trap') < 0, + output('trapEpc') < currentPc, + output('isReturn') < 0, + output('returnLevel') < 0, + output('memGuest') < 0, + // A fetch fault means there is no instruction to run: raise an + // instruction page fault at currentPc (the faulting PC) instead. + If( + fetchFaultIn, + then: doTrap(Trap.instructionPageFault, currentPc), + orElse: microcodeRead != null + ? cycleMicrocode( + instrIndex, + mopStep, + microcodeRead, + alu: alu, + rs1: rs1, + rs2: rs2, + rd: rd, + imm: imm, + fields: fields, + memRead: memRead, + memWrite: memWrite, + rs1Read: rs1Read, + rs2Read: rs2Read, + rdWrite: rdWrite, + ) + : cycle( + instrIndex, + mopStep, + alu: alu, + rs1: rs1, + rs2: rs2, + rd: rd, + imm: imm, + fields: fields, + memRead: memRead, + memWrite: memWrite, + rs1Read: rs1Read, + rs2Read: rs2Read, + rdWrite: rdWrite, + ), + ), ], orElse: [ alu < 0, @@ -332,6 +1008,12 @@ abstract class ExecutionUnit extends Module { interruptHold < 0, nextPc < currentPc, nextSp < currentSp, + nextMode < currentMode, + output('trap') < 0, + output('trapEpc') < currentPc, + output('isReturn') < 0, + output('returnLevel') < 0, + output('memGuest') < 0, ], ), ], @@ -382,34 +1064,15 @@ abstract class ExecutionUnit extends Module { Logic? mideleg, Logic? medeleg, { String? suffix, - }) { - suffix ??= ''; - - final machine = Const(PrivilegeMode.machine.id, width: 3); - if (csrRead == null || csrWrite == null) return machine; - - final supervisor = Const(PrivilegeMode.supervisor.id, width: 3); - - final isMachine = mode.eq(machine); - final noSup = ~Const(hasSupervisor ? 1 : 0); - - final delegatedInterrupt = mideleg == null ? Const(0) : mideleg[causeCode]; - final delegatedException = medeleg == null ? Const(0) : medeleg[causeCode]; - - final goesToSupervisor = mux( - trapInterrupt, - delegatedInterrupt, - delegatedException, - ); - - final notMachineAndHasSup = ~isMachine & Const(hasSupervisor ? 1 : 0); - - return mux( - notMachineAndHasSup, - mux(goesToSupervisor, supervisor, machine), - machine, - ); - } + }) => selectTrapTargetModeTop( + trapInterrupt, + causeCode, + mode, + mideleg, + medeleg, + hasCsr: csrRead != null && csrWrite != null, + hasSupervisor: hasSupervisor, + ); Logic encodeCause(Logic trapInterrupt, Logic causeCode) => (trapInterrupt.zeroExtend(mxlen.size) << (mxlen.size - 1)) | @@ -420,25 +1083,13 @@ abstract class ExecutionUnit extends Module { Logic causeCode, Logic trapInterrupt, { String? suffix, - }) { - suffix ??= ''; - final base = (tvec & Const(~0x3, width: mxlen.size)).named( - 'trapBase$suffix', - ); - final mode = tvec.slice(1, 0).named('trapMode$suffix'); - - final isVectored = mode.eq(Const(1, width: 2)).named('isVectored$suffix'); - - final vecOffset = (causeCode << 2) - .zeroExtend(mxlen.size) - .named('tvecOffset$suffix'); - - return mux( - isVectored & trapInterrupt, - base + vecOffset, - base, - ).named('tvecPc$suffix'); - } + }) => computeTrapVectorPcTop( + tvec, + causeCode, + trapInterrupt, + mxlen, + suffix: suffix, + ); List rawTrap( Logic trapInterrupt, @@ -452,6 +1103,7 @@ abstract class ExecutionUnit extends Module { return [ trapCause < encodeCause(trapInterrupt, causeCode).slice(5, 0), trapTval < (tval ?? Const(0, width: mxlen.size)), + output('trapEpc') < currentPc, output('trap') < 1, done < 1, valid < 1, @@ -477,6 +1129,7 @@ abstract class ExecutionUnit extends Module { causeCode, ).slice(5, 0).named('cause$suffix'), trapTval < (tval ?? Const(0, width: mxlen.size)), + output('trapEpc') < currentPc, tvec < ((stvec != null) @@ -509,71 +1162,63 @@ abstract class ExecutionUnit extends Module { List doTrap(Trap t, [Logic? tval, String? suffix]) { final trapInterrupt = Const(t.interrupt ? 1 : 0); - final causeCode = Const(t.mcauseCode, width: 6); + final causeCode = Const(t.causeCode, width: 6); return rawTrap(trapInterrupt, causeCode, tval, suffix); } + + /// VS-mode state-enable virtual-instruction: a guest sstateen (0x10C-0x10F) + /// access that mstateen0.SE0 permits but hstateen0.SE0 blocks. (An + /// mstateen-blocked access is illegal, raised by the CSR legality path.) + /// Const(0) for a core without stateen + hypervisor support. + Logic _stateenVsViol(Logic addr12) { + final mse0 = mstateen0Se0; + final hse0 = hstateen0Se0; + if (mse0 == null || hse0 == null) return Const(0); + return (virtIn ?? Const(0)) & + addr12.gte(Const(0x10C, width: 12)) & + addr12.lte(Const(0x10F, width: 12)) & + mse0 & + ~hse0; + } } class DynamicExecutionUnit extends ExecutionUnit { DynamicExecutionUnit( - Logic clk, - Logic reset, - Logic enable, - Logic currentSp, - Logic currentPc, - Logic currentMode, - Logic instrIndex, - Map instrTypeMap, - Map fields, - DataPortInterface? csrRead, - DataPortInterface? csrWrite, - DataPortInterface memRead, - DataPortInterface memWrite, - DataPortInterface rs1Read, - DataPortInterface rs2Read, - DataPortInterface rdWrite, + super.clk, + super.reset, + super.enable, + super.currentSp, + super.currentPc, + super.currentMode, + super.instrIndex, + super.instrTypeMap, + super.fields, + super.csrRead, + super.csrWrite, + super.memRead, + super.memWrite, + super.rs1Read, + super.rs2Read, + super.rdWrite, DataPortInterface microcodeRead, { - bool hasSupervisor = false, - bool hasUser = false, - required Microcode microcode, - required Mxlen mxlen, - Logic? mideleg, - Logic? medeleg, - Logic? mtvec, - Logic? stvec, - int counterWidth = 32, - List staticInstructions = const [], - String name = 'river_dynamic_execution_unit', - }) : super( - clk, - reset, - enable, - currentSp, - currentPc, - currentMode, - instrIndex, - instrTypeMap, - fields, - csrRead, - csrWrite, - memRead, - memWrite, - rs1Read, - rs2Read, - rdWrite, - microcodeRead: microcodeRead, - hasSupervisor: hasSupervisor, - hasUser: hasUser, - microcode: microcode, - mxlen: mxlen, - mideleg: mideleg, - medeleg: medeleg, - mtvec: mtvec, - stvec: stvec, - counterWidth: counterWidth, - staticInstructions: staticInstructions, - name: name, - ); + super.hasSupervisor, + super.hasUser, + required super.microcode, + required super.mxlen, + super.vlen = 128, + super.mideleg, + super.medeleg, + super.mtvec, + super.stvec, + super.virtIn, + super.mstateen0Se0, + super.hstateen0Se0, + super.memFaultGuest, + super.fetchFault, + super.counterWidth, + super.staticInstructions, + super.name = 'river_dynamic_execution_unit', + }) : super(microcodeRead: microcodeRead); @override List cycleMicrocode( @@ -597,16 +1242,26 @@ class DynamicExecutionUnit extends ExecutionUnit { final mopCount = Logic(name: 'mopCount', width: mopStep.width); + // Micro-op funct codes this config's ROM actually emits. A funct-Case arm + // whose funct is never emitted is dead logic (the ROM can never produce it), + // so drop it and its operand datapath. Derived from the ROM alone, so each + // config keeps exactly its arms. rc1-s (RV64IMAC) e.g. never emits + // TlbFence/TlbInvalidate/InterruptHold/FpuOp. + final emittedFuncts = microcode.emittedFuncts; + bool functEmitted(int f) => emittedFuncts.contains(f); + final mopTable = Map.fromEntries( kMicroOpTable .where((mop) { - if (mop.funct == ReadCsrMicroOp.funct && csrRead == null) + if (mop.funct == ReadCsrMicroOp.funct && csrRead == null) { return false; - if (mop.funct == WriteCsrMicroOp.funct && csrWrite == null) + } + if (mop.funct == WriteCsrMicroOp.funct && csrWrite == null) { return false; + } return true; }) - .map((mop) => MapEntry(Microcode.mopType(mop), mop)), + .map((mop) => MapEntry(MicrocodeRom.mopType(mop), mop)), ); final mop = mopTable.map( @@ -630,23 +1285,19 @@ class DynamicExecutionUnit extends ExecutionUnit { .named('mopFunct'); Logic readSource(Logic source) => mux( - source.eq(Const(MicroOpSource.imm.value, width: MicroOpSource.width)), + source.eq(Const(MicroOpSource.imm, width: MicroOpSource.width)), imm, mux( - source.eq(Const(MicroOpSource.alu.value, width: MicroOpSource.width)), + source.eq(Const(MicroOpSource.alu, width: MicroOpSource.width)), alu, mux( - source.eq(Const(MicroOpSource.rs1.value, width: MicroOpSource.width)), + source.eq(Const(MicroOpSource.rs1, width: MicroOpSource.width)), rs1, mux( - source.eq( - Const(MicroOpSource.rs2.value, width: MicroOpSource.width), - ), + source.eq(Const(MicroOpSource.rs2, width: MicroOpSource.width)), rs2, mux( - source.eq( - Const(MicroOpSource.rd.value, width: MicroOpSource.width), - ), + source.eq(Const(MicroOpSource.rd, width: MicroOpSource.width)), rd, nextPc, ), @@ -656,19 +1307,19 @@ class DynamicExecutionUnit extends ExecutionUnit { ); Logic readField(Logic field, {bool register = true}) => mux( - field.eq(Const(MicroOpField.rd.value, width: MicroOpField.width)), + field.eq(Const(MicroOpField.rd, width: MicroOpField.width)), (register ? rd : fields['rd']!).zeroExtend(mxlen.size), mux( - field.eq(Const(MicroOpField.rs1.value, width: MicroOpField.width)), + field.eq(Const(MicroOpField.rs1, width: MicroOpField.width)), (register ? rs1 : fields['rs1']!).zeroExtend(mxlen.size), mux( - field.eq(Const(MicroOpField.rs2.value, width: MicroOpField.width)), + field.eq(Const(MicroOpField.rs2, width: MicroOpField.width)), (register ? rs2 : fields['rs2']!).zeroExtend(mxlen.size), mux( - field.eq(Const(MicroOpField.imm.value, width: MicroOpField.width)), + field.eq(Const(MicroOpField.imm, width: MicroOpField.width)), register ? imm : fields['imm']!, mux( - field.eq(Const(MicroOpField.pc.value, width: MicroOpField.width)), + field.eq(Const(MicroOpField.pc, width: MicroOpField.width)), nextPc, nextSp, ), @@ -677,22 +1328,288 @@ class DynamicExecutionUnit extends ExecutionUnit { ), ); + // Shared microcode-ALU operands: hoisted out of the ~19-arm funct Case so + // synth infers ONE operand mux per side instead of one per arm (mux-bound). + final aluA = readField(mop['Alu']!['a']!); + final aluB = readField(mop['Alu']!['b']!); + + // Shared single-cycle integer ALU: ONE control-driven unit for all 18 + // single-cycle funct arms (add/sub/logic/shift/compare/word/zicond). mul + // (iterative _imul) and div/rem (IterativeDivider) stay multi-cycle and + // explicit; everything else falls through to this result. + final microcodeAlu = MicrocodeAlu( + aluA, + aluB, + mop['Alu']!['alu']!, + mxlen: mxlen, + ).result; + + // Atomics (AMO/LR/SC) exist ONLY at word and doubleword width (RISC-V has no + // sub-word atomic; the ROM never emits a byte/half atomic size, see harbor + // rv_a.dart). Restricting the atomic size Cases to these widths drops the + // unreachable byte/half arms (each a full operand-read + combine). The AMO + // combine (amoNewVal, a 9-way afunct mux) per size is the biggest mux source + // in the unit (~22% of all muxes at byte+word widths). + bool atomicSize(RiscVMemSize s) => + (s.bytes == 4 || s.bytes == 8) && s.bytes <= mxlen.width; + + // Shared memory-address base operand: the base read is the SAME 6:1 operand + // mux in all five memory handlers (MemLoad/MemStore/LoadReserved/ + // StoreConditional/AtomicMemory), differing only in which 3-bit ROM field + // selects it. Mux the cheap selector by the active micro-op so ONE wide + // readField serves them all instead of five (mux-bound). + Logic functIs(int f) => funct.eq(Const(f, width: funct.width)); + final opBase = readField( + mux( + functIs(MemLoadMicroOp.funct), + mop['MemLoad']!['base']!, + mux( + functIs(MemStoreMicroOp.funct), + mop['MemStore']!['base']!, + mux( + functIs(LoadReservedMicroOp.funct), + mop['LoadReserved']!['base']!, + mux( + functIs(StoreConditionalMicroOp.funct), + mop['StoreConditional']!['base']!, + mop['AtomicMemory']!['base']!, + ), + ), + ), + ), + ); + + // Shared store-data operand: MemStore and StoreConditional both read a `src` + // field (mutually-exclusive funct arms, both drive memWrite.data). Mux the + // 3-bit selector by funct so ONE readField serves both (mux-bound). + final opStoreSrc = readField( + mux( + functIs(MemStoreMicroOp.funct), + mop['MemStore']!['src']!, + mop['StoreConditional']!['src']!, + ), + ); + + // Shared operand-source read. WriteRegister, ModifyLatch, MoveToField and + // WriteCsr each read a MicroOpSource operand in mutually-exclusive funct + // arms; muxing the 3-bit source selector by funct lets ONE readSource serve + // them all (mux-bound). Only folds in micro-ops present in this ROM. + Logic srcSel = mop['WriteRegister']!['source']!; + if (mop.containsKey('ModifyLatch')) { + srcSel = mux( + functIs(ModifyLatchMicroOp.funct), + mop['ModifyLatch']!['source']!, + srcSel, + ); + } + if (mop.containsKey('MoveToField')) { + srcSel = mux( + functIs(SetFieldMicroOpFunct.funct), + mop['MoveToField']!['src']!, + srcSel, + ); + } + if (csrWrite != null && mop.containsKey('WriteCsr')) { + srcSel = mux( + functIs(WriteCsrMicroOp.funct), + mop['WriteCsr']!['source']!, + srcSel, + ); + } + if (mop.containsKey('UpdatePC')) { + srcSel = mux( + functIs(UpdatePCMicroOp.funct), + mop['UpdatePC']!['offsetSource']!, + srcSel, + ); + } + final sharedSourceVal = readSource(srcSel); + + // Shared operand-field read for the mutually-exclusive UpdatePC and + // CopyField arms (both readField(...) a micro-op field with the default + // register variant); one shared 6:1 operand mux instead of two. + Logic? sharedFieldVal; + if (mop.containsKey('UpdatePC') && mop.containsKey('CopyField')) { + sharedFieldVal = readField( + mux( + functIs(UpdatePCMicroOp.funct), + mop['UpdatePC']!['offsetField']!, + mop['CopyField']!['src']!, + ), + ); + } + + // Shared CSR address read. ReadCsr and WriteCsr are mutually-exclusive funct + // arms that both derive the 12-bit CSR index from a micro-op field via + // readField(...).slice(11,0); muxing the field selector by funct shares that + // single readField operand mux. Built only when a CSR port exists. + Logic? csrAddr; + if (csrRead != null || csrWrite != null) { + var csrAddrSel = mop['ReadCsr']!['source']!; + if (csrWrite != null) { + csrAddrSel = mux( + functIs(WriteCsrMicroOp.funct), + mop['WriteCsr']!['field']!, + csrAddrSel, + ); + } + csrAddr = readField(csrAddrSel).slice(11, 0); + } + + // AMO read-modify-write: combine the loaded ("old") value with src per the + // 4-bit afunct selector (RiscVAtomicFunct.index). All operands are [bits] + // wide; the result is [bits] wide. Mirrors the static RiscVAtomicMemory arm. + // cas (Zacas) needs rd's value as the compare operand and is handled by the + // static path only; plain rvA never emits it, so it falls through to src. + Logic amoNewVal(Logic afunct, Logic old, Logic src, int bits) { + Logic sel(int v) => + afunct.eq(Const(v, width: AtomicMemoryMicroOp.functWidth)); + return mux( + sel(0), + old + src, // add + mux( + sel(1), + src, // swap + mux( + sel(2), + old ^ src, // xor + mux( + sel(3), + old & src, // and + mux( + sel(4), + old | src, // or + mux( + sel(5), + mux(bmSignedLt(old, src, bits), old, src), // min + mux( + sel(6), + mux(bmSignedLt(old, src, bits), src, old), // max + mux( + sel(7), + mux(old.lt(src), old, src), // minu + mux( + sel(8), + mux(old.lt(src), src, old), // maxu + src, // cas fallthrough (static path only) + ), + ), + ), + ), + ), + ), + ), + ), + ); + } + + // AMO read-modify-write combine, computed ONCE at XLEN instead of a 9-way + // amoNewVal per size. `amoSizeMux` selects an XLEN value by atomic size + // (word/dword); old and src are sign-extended to XLEN. Signed min/max and + // unsigned minu/maxu stay correct (32->64 sign-extension is monotonic for + // both orderings); add/xor/and/or/swap only need correct low bits. The mem + // port writes only `amoBytes` bytes, so high bits are don't-care. + Logic amoSizeMux(Logic Function(RiscVMemSize) f) { + final sizes = MicroOpMemSize.values.where(atomicSize).toList(); + var acc = f(sizes.first); + for (final s in sizes.skip(1)) { + acc = mux( + mop['AtomicMemory']!['size']!.eq( + Const(s.value, width: MicroOpMemSize.width), + ), + f(s), + acc, + ); + } + return acc; + } + + final amoOldX = amoSizeMux( + (s) => memRead.data.slice(s.bits - 1, 0).signExtend(mxlen.size), + ); + final amoNewX = amoNewVal( + mop['AtomicMemory']!['afunct']!, + amoOldX, + amoSizeMux( + (s) => readField( + mop['AtomicMemory']!['src']!, + ).slice(s.bits - 1, 0).signExtend(mxlen.size), + ), + mxlen.size, + ); + final amoBytes = amoSizeMux((s) => Const(s.bytes, width: 7)); + // Stored value: the combine's low size.bits, ZERO-extended to XLEN (the + // combine is sign-extended for correct min/max, but the store wrote zero + // high bits before this fold, and the mem model keeps those high bytes). + final amoStoreVal = amoSizeMux( + (s) => amoNewX.slice(s.bits - 1, 0).zeroExtend(mxlen.size), + ); + + // MemLoad result: the loaded memRead.data extended to XLEN per the access + // size ([sizeField]) and signedness ([unsignedField]). Computed once as a + // size-driven data mux so the MemLoad-completion arm does a single + // writeField instead of replicating the dest demux per byte/half/word/dword. + Logic loadSizeMux(Logic sizeField, Logic unsignedField) { + final sizes = MicroOpMemSize.values + .where((s) => s.bytes <= mxlen.width) + .toList(); + Logic ext(RiscVMemSize s) => mux( + unsignedField, + memRead.data.slice(s.bits - 1, 0).zeroExtend(mxlen.size), + memRead.data.slice(s.bits - 1, 0).signExtend(mxlen.size), + ); + var acc = ext(sizes.first); + for (final s in sizes.skip(1)) { + acc = mux( + sizeField.eq(Const(s.value, width: MicroOpMemSize.width)), + ext(s), + acc, + ); + } + return acc; + } + + // Shared rd-commit dest selector. LoadReserved, AMO-write and SC-write all + // finish with the SAME "commit rd (or advance on x0)" datapath, reading a + // dest field via readField(dest, register: false).slice(4,0). Mutually + // exclusive by funct, so muxing the 3-bit dest selector by funct shares ONE + // readField(dest) cone (mux-bound). Every micro-op type is in the mop table + // (filtered only by CSR presence), so no key guards needed. + var commitDest = mop['LoadReserved']!['dest']! as Logic; + commitDest = mux( + funct.eq(Const(StoreConditionalMicroOp.funct, width: funct.width)), + mop['StoreConditional']!['dest']!, + commitDest, + ); + commitDest = mux( + funct.eq(Const(AtomicMemoryMicroOp.funct, width: funct.width)), + mop['AtomicMemory']!['dest']!, + commitDest, + ); + // AMO writes the old memory value, SC writes zero (LR uses the loaded value, + // handled at its own site since the width/extension differs). + final scAmoVal = mux( + funct.eq(Const(AtomicMemoryMicroOp.funct, width: funct.width)), + amoOld, + Const(0, width: mxlen.size), + ); + Conditional writeField(Logic field, Logic value) => Case( field, [ - CaseItem(Const(MicroOpField.rd.value, width: MicroOpField.width), [ + CaseItem(Const(MicroOpField.rd, width: MicroOpField.width), [ rd < value.zeroExtend(mxlen.size), ]), - CaseItem(Const(MicroOpField.rs1.value, width: MicroOpField.width), [ + CaseItem(Const(MicroOpField.rs1, width: MicroOpField.width), [ rs1 < value.zeroExtend(mxlen.size), ]), - CaseItem(Const(MicroOpField.rs2.value, width: MicroOpField.width), [ + CaseItem(Const(MicroOpField.rs2, width: MicroOpField.width), [ rs2 < value.zeroExtend(mxlen.size), ]), - CaseItem(Const(MicroOpField.imm.value, width: MicroOpField.width), [ + CaseItem(Const(MicroOpField.imm, width: MicroOpField.width), [ imm < value.zeroExtend(mxlen.size), ]), - CaseItem(Const(MicroOpField.sp.value, width: MicroOpField.width), [ + CaseItem(Const(MicroOpField.sp, width: MicroOpField.width), [ nextSp < value.zeroExtend(mxlen.size), ]), ], @@ -702,6 +1619,123 @@ class DynamicExecutionUnit extends ExecutionUnit { Conditional clearField(Logic field) => writeField(field, readField(field, register: false)); + // Iterative multiplier for the mul family. The shared [IterativeMultiplier] + // computes the full 2*XLEN unsigned product over a few cycles (one chunk- + // multiply reused per cycle) instead of a single-cycle partial-product tree. + // A mul/mulh* mop holds [_imulStart] while resident (operands stable, mopStep + // frozen) and reads back the product. mul/mulw/mulh* flavors derive from that + // registered product: a slice for low/word/high-unsigned, plus the two + // sign-correction subtracts for signed-high. Mirrors idivArm's handshake. + final mulA = aluA; + final mulB = aluB; + // mul family present whenever the ISA has M. With useIterativeMul the product + // comes from _imul; otherwise a single-cycle combinational unsigned product. + // mulw/mulh* flavors derive identically from the 2w-bit product either way. + final hasMul = microcode.isa.extensions.any((e) => e.name == 'M'); + Logic? mulLowR, mulwR, mulhSSR, mulhSUR, mulhUUR; + if (hasMul) { + final w = mxlen.size; + final z = Const(0, width: w); + final prod = _imul != null + ? _imul! + .product // 2w-bit unsigned product (multi-cycle) + : (mulA.zeroExtend(w * 2) * + mulB.zeroExtend(w * 2)); // single-cycle unsigned product + mulLowR = prod.slice(w - 1, 0); + mulwR = mulLowR.slice(31, 0).signExtend(w); + mulhUUR = prod.slice(w * 2 - 1, w); + // Signed-high corrections: MULHSU treats a as signed, b as unsigned; if a + // is negative subtract b from the high word. MULH treats both signed; the + // extra correction for b negative subtracts a. + mulhSUR = mulhUUR - mux(mulA[w - 1], mulB, z); + mulhSSR = mulhSUR - mux(mulB[w - 1], mulA, z); + } + + // One mul-family arm: route to the shared IterativeMultiplier exactly like + // idivArm routes div/rem. Hold start while resident (operands held stable + // since mopStep does not advance), and on done commit the selected flavor of + // the unsigned product and advance. Stub when no M. + List imulArm(Logic? result) { + if (!hasMul) { + // No M extension: unreachable stub (the Case is fully elaborated). + return [ + alu < Const(0, width: mxlen.size), + mopStep < mopStep + 1, + microcodeRead.en < 0, + ]; + } + if (_imul == null) { + // Single-cycle mul: result is combinational, commit and advance now. + return [alu < result!, mopStep < mopStep + 1, microcodeRead.en < 0]; + } + return [ + _imulStart! < 1, + _imulA! < mulA, + _imulB! < mulB, + If( + _imul!.done, + then: [ + alu < result!, + _imulStart! < 0, + mopStep < mopStep + 1, + microcodeRead.en < 0, + ], + ), + ]; + } + + // Routes a div/rem micro-op to the shared multi-cycle IterativeDivider: + // hold start while resident, feed unsigned magnitudes (divisor forced + // non-zero), and on done commit the sign/word/div-by-zero/overflow-fixed + // result and advance. Reproduces the static unit's semantics. When the ISA + // has no M extension the divider is absent and these arms are unreachable + // stubs (still elaborated as part of the full funct Case). + List idivArm({ + required bool isW, + required bool isRem, + required bool isSigned, + }) { + if (_idiv == null) { + return [ + alu < Const(0, width: mxlen.size), + mopStep < mopStep + 1, + microcodeRead.en < 0, + ]; + } + final w = isW ? 32 : mxlen.size; + final aOp = isW ? mulA.slice(31, 0) : mulA; + final bOp = isW ? mulB.slice(31, 0) : mulB; + final aMag = isSigned ? bmAbs(aOp, w) : aOp; + final bMag = isSigned ? bmAbs(bOp, w) : bOp; + final zw = Const(0, width: w); + final dividend = aMag.zeroExtend(mxlen.size); + final divisor = mux( + bMag.eq(zw), + Const(1, width: w), + bMag, + ).zeroExtend(mxlen.size); + final q = _idiv!.quotient.slice(w - 1, 0); + final r = _idiv!.remainder.slice(w - 1, 0); + final resW = isRem + ? (isSigned ? remFixupS(aOp, bOp, r, w) : remFixupU(aOp, bOp, r, w)) + : (isSigned ? divFixupS(aOp, bOp, q, w) : divFixupU(aOp, bOp, q, w)); + final result = isW ? resW.signExtend(mxlen.size) : resW; + return [ + _idivStart! < 1, + _idivDividend! < dividend, + _idivDivisor! < divisor, + If( + _idiv!.done, + then: [ + alu < result, + _idivStart! < 0, + mopStep < mopStep + 1, + microcodeRead.en < 0, + ], + ), + ]; + } + return [ If.block([ Iff(mopStep.eq(0), [ @@ -767,70 +1801,103 @@ class DynamicExecutionUnit extends ExecutionUnit { ]), ]), Iff(rdWrite.en, [ + If( + rdWrite.done & rdWrite.valid, + then: [mopStep < mopStep + 1, microcodeRead.en < 0, rdWrite.en < 0], + ), + ]), + Iff(memRead.en, [ Case(funct, [ - CaseItem(Const(WriteRegisterMicroOp.funct, width: funct.width), [ + CaseItem(Const(MemLoadMicroOp.funct, width: funct.width), [ If( - rdWrite.done & rdWrite.valid, + memRead.done & memRead.valid, then: [ + // Sign/zero-extend the loaded value by size ONCE via a size- + // driven data mux, then a SINGLE writeField, instead of a per- + // size Case replicating the wide writeField dest-demux for each + // of byte/half/word/dword (mux-bound). Result equals the old + // per-size value exactly (each arm was the same extend of the + // same slice). + writeField( + mop['MemLoad']!['dest']!, + loadSizeMux( + mop['MemLoad']!['size']!, + mop['MemLoad']!['unsigned']!, + ), + ), mopStep < mopStep + 1, microcodeRead.en < 0, - rdWrite.en < 0, + memRead.en < 0, ], ), + If( + memRead.done & ~memRead.valid, + then: doTrap(Trap.loadPageFault, opBase + imm), + ), ]), - ]), - ]), - Iff(memRead.en, [ - Case( - funct, - [ - CaseItem(Const(MemLoadMicroOp.funct, width: funct.width), [ - If( - memRead.done & memRead.valid, - then: [ - Case(mop['MemLoad']!['size']!, [ - for (final size in MicroOpMemSize.values.where( - (s) => s.bytes <= mxlen.width, - )) - CaseItem( - Const(size.value, width: MicroOpMemSize.width), - [ - writeField( - mop['MemLoad']!['dest']!, - mux( - mop['MemLoad']!['unsigned']!, - memRead.data - .slice(size.bits - 1, 0) - .zeroExtend(mxlen.size), + // Load-reserved: commit rd = sign-extended loaded value, arm the + // reservation, then advance (via the rdWrite wrapper, or directly + // when rd == x0). + CaseItem(Const(LoadReservedMicroOp.funct, width: funct.width), [ + If( + memRead.done & memRead.valid, + then: [ + reservationValid < 1, + reservationAddr < memRead.addr, + memRead.en < 0, + Case(mop['LoadReserved']!['size']!, [ + for (final size in MicroOpMemSize.values.where(atomicSize)) + CaseItem(Const(size.value, width: MicroOpMemSize.width), [ + If( + readField( + commitDest, + register: false, + ).slice(4, 0).gt(0), + then: [ + rdWrite.addr < + readField( + commitDest, + register: false, + ).slice(4, 0), + rdWrite.data < memRead.data .slice(size.bits - 1, 0) .signExtend(mxlen.size), - ), - ), - mopStep < mopStep + 1, - microcodeRead.en < 0, - memRead.en < 0, + rdWrite.en < 1, ], + orElse: [mopStep < mopStep + 1, microcodeRead.en < 0], ), - ]), - ], - ), - If( - memRead.done & ~memRead.valid, - then: doTrap( - Trap.loadAccess, - readField(mop['MemLoad']!['base']!) + imm, - ), - ), - ]), - ], - defaultItem: [ - microcodeRead.en < 1, - microcodeRead.addr < - (instrIndex.zeroExtend(microcodeRead.addr.width) + - mopStep.zeroExtend(microcodeRead.addr.width)), - ], - ), + ]), + ]), + ], + ), + If( + memRead.done & ~memRead.valid, + then: [memRead.en < 0, ...doTrap(Trap.loadPageFault, opBase)], + ), + ]), + // AMO read phase: latch the (sign-extended) old value, compute the + // new value, and issue the write. rd + advance happen in the + // memWrite-completion wrapper. + CaseItem(Const(AtomicMemoryMicroOp.funct, width: funct.width), [ + If( + memRead.done & memRead.valid, + then: [ + // Shared combine (amoNewX) + size-driven byte count; no + // per-size Case. The mem port writes only amoBytes bytes. + amoOld < amoOldX, + memWrite.en < 1, + memWrite.addr < memRead.addr, + memWrite.data < [amoBytes, amoStoreVal].swizzle(), + memRead.en < 0, + ], + ), + If( + memRead.done & ~memRead.valid, + then: [memRead.en < 0, ...doTrap(Trap.loadPageFault, opBase)], + ), + ]), + ]), ]), Iff(memWrite.en, [ Case(funct, [ @@ -847,47 +1914,105 @@ class DynamicExecutionUnit extends ExecutionUnit { memWrite.done & ~memWrite.valid, then: [ memWrite.en < 0, - ...doTrap( - Trap.storeAccess, - readField(mop['MemStore']!['base']!) + imm, + ...doTrap(Trap.storePageFault, opBase + imm), + ], + ), + ]), + // AMO write phase: commit rd = old value, then advance (rdWrite + // wrapper, or directly when rd == x0). + CaseItem(Const(AtomicMemoryMicroOp.funct, width: funct.width), [ + If( + memWrite.done & memWrite.valid, + then: [ + memWrite.en < 0, + If( + readField(commitDest, register: false).slice(4, 0).gt(0), + then: [ + rdWrite.addr < + readField(commitDest, register: false).slice(4, 0), + rdWrite.data < scAmoVal, + rdWrite.en < 1, + ], + orElse: [mopStep < mopStep + 1, microcodeRead.en < 0], + ), + ], + ), + If( + memWrite.done & ~memWrite.valid, + then: [memWrite.en < 0, ...doTrap(Trap.storePageFault, opBase)], + ), + ]), + // SC hit: the store succeeded -> rd = 0, then advance. + CaseItem(Const(StoreConditionalMicroOp.funct, width: funct.width), [ + If( + memWrite.done & memWrite.valid, + then: [ + memWrite.en < 0, + If( + readField(commitDest, register: false).slice(4, 0).gt(0), + then: [ + rdWrite.addr < + readField(commitDest, register: false).slice(4, 0), + rdWrite.data < scAmoVal, + rdWrite.en < 1, + ], + orElse: [mopStep < mopStep + 1, microcodeRead.en < 0], ), ], ), + If( + memWrite.done & ~memWrite.valid, + then: [memWrite.en < 0, ...doTrap(Trap.storePageFault, opBase)], + ), ]), ]), ]), if (csrRead != null) Iff(csrRead.en, [ - Case(funct, [ - CaseItem(Const(ReadCsrMicroOp.funct, width: funct.width), [ - If( - csrRead.done & csrRead.valid, - then: [ - writeField(mop['ReadCsr']!['source']!, csrRead.data), - mopStep < mopStep + 1, - microcodeRead.en < 0, - csrRead.en < 0, - ], - ), - If(csrRead.done & ~csrRead.valid, then: doTrap(Trap.illegal)), - ]), - ]), + If( + csrRead.done & csrRead.valid, + then: [ + writeField(mop['ReadCsr']!['source']!, csrRead.data), + mopStep < mopStep + 1, + microcodeRead.en < 0, + csrRead.en < 0, + ], + ), + If(csrRead.done & ~csrRead.valid, then: doTrap(Trap.illegal)), ]), if (csrWrite != null) Iff(csrWrite.en, [ - Case(funct, [ - CaseItem(Const(WriteCsrMicroOp.funct, width: funct.width), [ - If( - csrWrite.done & csrWrite.valid, - then: [ - mopStep < mopStep + 1, - microcodeRead.en < 0, - csrWrite.en < 0, - ], - ), - If(csrWrite.done & ~csrWrite.valid, then: doTrap(Trap.illegal)), - ]), - ]), + If( + csrWrite.done & csrWrite.valid, + then: [ + mopStep < mopStep + 1, + microcodeRead.en < 0, + csrWrite.en < 0, + ], + ), + // csrrs/csrrc rs1=x0 (csrr*i uimm=0) reading a read-only CSR: the + // write is illegal (valid=0) but the spec says these forms do not + // write and must not trap. funct3[1] marks set/clear; instr[19:15] + // (rs1/uimm field) == 0 is the no-write case. Suppress the trap and + // complete (rd already has the old value from the read step). + If( + csrWrite.done & + ~csrWrite.valid & + fields['funct3']![1] & + fields['rs1']!.eq(Const(0, width: fields['rs1']!.width)), + then: [ + mopStep < mopStep + 1, + microcodeRead.en < 0, + csrWrite.en < 0, + ], + ), + If( + csrWrite.done & + ~csrWrite.valid & + ~(fields['funct3']![1] & + fields['rs1']!.eq(Const(0, width: fields['rs1']!.width))), + then: doTrap(Trap.illegal), + ), ]), Iff((mopStep - 1).lt(mopCount), [ If( @@ -929,7 +2054,7 @@ class DynamicExecutionUnit extends ExecutionUnit { If( mop['ReadRegister']!['source']!.eq( Const( - MicroOpSource.rs2.value, + MicroOpSource.rs2, width: MicroOpSource.width, ), ), @@ -938,6 +2063,7 @@ class DynamicExecutionUnit extends ExecutionUnit { rs2Read.addr < (readField( mop['ReadRegister']!['source']!, + register: false, ).zeroExtend(mxlen.size) + mop['ReadRegister']!['offset']!) .slice(4, 0), @@ -947,6 +2073,7 @@ class DynamicExecutionUnit extends ExecutionUnit { rs1Read.addr < (readField( mop['ReadRegister']!['source']!, + register: false, ).zeroExtend(mxlen.size) + mop['ReadRegister']!['offset']!) .slice(4, 0), @@ -956,357 +2083,156 @@ class DynamicExecutionUnit extends ExecutionUnit { ]), ], ), - CaseItem( - Const(WriteRegisterMicroOp.funct, width: funct.width), - [ - If( - (readField( - mop['WriteRegister']!['field']!, - ).zeroExtend(mxlen.size) + - mop['WriteRegister']!['offset']!) - .slice(4, 0) - .eq(Const(Register.x0.value, width: 5)), - then: [mopStep < mopStep + 1, microcodeRead.en < 0], - orElse: [ - If( + CaseItem(Const(WriteRegisterMicroOp.funct, width: funct.width), [ + If( + (readField( + mop['WriteRegister']!['field']!, + register: false, + ).zeroExtend(mxlen.size) + + mop['WriteRegister']!['offset']!) + .slice(4, 0) + .eq(Const(Register.x0.value, width: 5)), + then: [mopStep < mopStep + 1, microcodeRead.en < 0], + orElse: [ + // Mirror x2 (sp) writes to the fast-path nextSp, but x2 + // is a real GPR too: it must ALSO take the normal + // regfile write below (whose rdWrite handshake advances + // mopStep). Setting nextSp alone left no mopStep advance + // and hung the core on any x2 write. + If( + (readField( + mop['WriteRegister']!['field']!, + register: false, + ).zeroExtend(mxlen.size) + + mop['WriteRegister']!['offset']!) + .slice(4, 0) + .eq(Const(Register.x2.value, width: 5)), + then: [ + nextSp < + (sharedSourceVal + + mop['WriteRegister']!['valueOffset']!), + ], + ), + rdWrite.en < 1, + rdWrite.addr < (readField( mop['WriteRegister']!['field']!, + register: false, ).zeroExtend(mxlen.size) + mop['WriteRegister']!['offset']!) - .slice(4, 0) - .eq(Const(Register.x2.value, width: 5)), - then: [ - nextSp < - (readSource( - mop['WriteRegister']!['source']!, - ) + - mop['WriteRegister']!['valueOffset']!), - microcodeRead.en < 0, - ], - orElse: [ - rdWrite.en < 1, - rdWrite.addr < - (readField( - mop['WriteRegister']!['field']!, - ).zeroExtend(mxlen.size) + - mop['WriteRegister']!['offset']!) - .slice(4, 0), - rdWrite.data < - (readSource( - mop['WriteRegister']!['source']!, - ) + - mop['WriteRegister']!['valueOffset']!), - ], - ), - ], - ), - ], - ), + .slice(4, 0), + rdWrite.data < + (sharedSourceVal + + mop['WriteRegister']!['valueOffset']!), + ], + ), + ]), CaseItem(Const(AluMicroOp.funct, width: funct.width), [ - Case(mop['Alu']!['alu']!, [ - CaseItem( - Const( - MicroOpAluFunct.add.value, - width: MicroOpAluFunct.width, - ), - [ - alu < - (readField(mop['Alu']!['a']!) + - readField(mop['Alu']!['b']!)), - mopStep < mopStep + 1, - microcodeRead.en < 0, - ], - ), - CaseItem( - Const( - MicroOpAluFunct.sub.value, - width: MicroOpAluFunct.width, - ), - [ - alu < - (readField(mop['Alu']!['a']!) - - readField(mop['Alu']!['b']!)), - mopStep < mopStep + 1, - microcodeRead.en < 0, - ], - ), - CaseItem( - Const( - MicroOpAluFunct.and.value, - width: MicroOpAluFunct.width, - ), - [ - alu < - (readField(mop['Alu']!['a']!) & - readField(mop['Alu']!['b']!)), - mopStep < mopStep + 1, - microcodeRead.en < 0, - ], - ), - CaseItem( - Const( - MicroOpAluFunct.or.value, - width: MicroOpAluFunct.width, - ), - [ - alu < - (readField(mop['Alu']!['a']!) | - readField(mop['Alu']!['b']!)), - mopStep < mopStep + 1, - microcodeRead.en < 0, - ], - ), - CaseItem( - Const( - MicroOpAluFunct.xor.value, - width: MicroOpAluFunct.width, - ), - [ - alu < - (readField(mop['Alu']!['a']!) ^ - readField(mop['Alu']!['b']!)), - mopStep < mopStep + 1, - microcodeRead.en < 0, - ], - ), - CaseItem( - Const( - MicroOpAluFunct.sll.value, - width: MicroOpAluFunct.width, - ), - [ - alu < - (readField(mop['Alu']!['a']!) << - readField(mop['Alu']!['b']!)), - mopStep < mopStep + 1, - microcodeRead.en < 0, - ], - ), - CaseItem( - Const( - MicroOpAluFunct.srl.value, - width: MicroOpAluFunct.width, - ), - [ - alu < - (readField(mop['Alu']!['a']!) >> - readField(mop['Alu']!['b']!)), - mopStep < mopStep + 1, - microcodeRead.en < 0, - ], - ), - CaseItem( - Const( - MicroOpAluFunct.sra.value, - width: MicroOpAluFunct.width, - ), - [ - alu < - (readField(mop['Alu']!['a']!) >> - readField(mop['Alu']!['b']!)), - mopStep < mopStep + 1, - microcodeRead.en < 0, - ], - ), - CaseItem( - Const( - MicroOpAluFunct.slt.value, - width: MicroOpAluFunct.width, - ), - [ - alu < - readField(mop['Alu']!['a']!) - .lte(readField(mop['Alu']!['b']!)) - .zeroExtend(mxlen.size), - mopStep < mopStep + 1, - microcodeRead.en < 0, - ], - ), - CaseItem( - Const( - MicroOpAluFunct.sltu.value, - width: MicroOpAluFunct.width, - ), - [ - alu < - (readField(mop['Alu']!['a']!) - - readField(mop['Alu']!['b']!))[mxlen.size - - 1] - .zeroExtend(mxlen.size), - mopStep < mopStep + 1, - microcodeRead.en < 0, - ], - ), - CaseItem( - Const( - MicroOpAluFunct.masked.value, - width: MicroOpAluFunct.width, + Case( + mop['Alu']!['alu']!, + [ + CaseItem( + Const( + MicroOpAluFunct.mul, + width: MicroOpAluFunct.width, + ), + imulArm(mulLowR), ), - [ - alu < - (readField(mop['Alu']!['a']!) & - ~readField(mop['Alu']!['b']!)), - mopStep < mopStep + 1, - microcodeRead.en < 0, - ], - ), - CaseItem( - Const( - MicroOpAluFunct.mul.value, - width: MicroOpAluFunct.width, + CaseItem( + Const( + MicroOpAluFunct.mulw, + width: MicroOpAluFunct.width, + ), + imulArm(mulwR), ), - [ - alu < - (readField(mop['Alu']!['a']!) * - readField(mop['Alu']!['b']!)), - mopStep < mopStep + 1, - microcodeRead.en < 0, - ], - ), - CaseItem( - Const( - MicroOpAluFunct.mulw.value, - width: MicroOpAluFunct.width, + CaseItem( + Const( + MicroOpAluFunct.mulh, + width: MicroOpAluFunct.width, + ), + imulArm(mulhSSR), ), - [ - alu < - (readField(mop['Alu']!['a']!) * - readField(mop['Alu']!['b']!)), - mopStep < mopStep + 1, - microcodeRead.en < 0, - ], - ), - CaseItem( - Const( - MicroOpAluFunct.mulh.value, - width: MicroOpAluFunct.width, + CaseItem( + Const( + MicroOpAluFunct.mulhsu, + width: MicroOpAluFunct.width, + ), + imulArm(mulhSUR), ), - [ - alu < - (readField(mop['Alu']!['a']!) * - readField(mop['Alu']!['b']!)), - mopStep < mopStep + 1, - microcodeRead.en < 0, - ], - ), - CaseItem( - Const( - MicroOpAluFunct.mulhsu.value, - width: MicroOpAluFunct.width, + CaseItem( + Const( + MicroOpAluFunct.mulhu, + width: MicroOpAluFunct.width, + ), + imulArm(mulhUUR), ), - [ - alu < - (readField(mop['Alu']!['a']!) * - readField(mop['Alu']!['b']!)), - mopStep < mopStep + 1, - microcodeRead.en < 0, - ], - ), - CaseItem( - Const( - MicroOpAluFunct.mulhu.value, - width: MicroOpAluFunct.width, + CaseItem( + Const( + MicroOpAluFunct.div, + width: MicroOpAluFunct.width, + ), + idivArm(isW: false, isRem: false, isSigned: true), ), - [ - alu < - (readField(mop['Alu']!['a']!) * - readField(mop['Alu']!['b']!)), - mopStep < mopStep + 1, - microcodeRead.en < 0, - ], - ), - CaseItem( - Const( - MicroOpAluFunct.div.value, - width: MicroOpAluFunct.width, + CaseItem( + Const( + MicroOpAluFunct.divu, + width: MicroOpAluFunct.width, + ), + idivArm(isW: false, isRem: false, isSigned: false), ), - [ - alu < - (readField(mop['Alu']!['a']!) / - readField(mop['Alu']!['b']!)), - mopStep < mopStep + 1, - microcodeRead.en < 0, - ], - ), - CaseItem( - Const( - MicroOpAluFunct.divu.value, - width: MicroOpAluFunct.width, + CaseItem( + Const( + MicroOpAluFunct.divuw, + width: MicroOpAluFunct.width, + ), + idivArm(isW: true, isRem: false, isSigned: false), ), - [ - alu < - (readField(mop['Alu']!['a']!) / - readField(mop['Alu']!['b']!)), - mopStep < mopStep + 1, - microcodeRead.en < 0, - ], - ), - CaseItem( - Const( - MicroOpAluFunct.divuw.value, - width: MicroOpAluFunct.width, + CaseItem( + Const( + MicroOpAluFunct.divw, + width: MicroOpAluFunct.width, + ), + idivArm(isW: true, isRem: false, isSigned: true), ), - [ - alu < - (readField(mop['Alu']!['a']!) / - readField(mop['Alu']!['b']!)), - mopStep < mopStep + 1, - microcodeRead.en < 0, - ], - ), - CaseItem( - Const( - MicroOpAluFunct.divw.value, - width: MicroOpAluFunct.width, + CaseItem( + Const( + MicroOpAluFunct.rem, + width: MicroOpAluFunct.width, + ), + idivArm(isW: false, isRem: true, isSigned: true), ), - [ - alu < - (readField(mop['Alu']!['a']!) / - readField(mop['Alu']!['b']!)), - mopStep < mopStep + 1, - microcodeRead.en < 0, - ], - ), - CaseItem( - Const( - MicroOpAluFunct.rem.value, - width: MicroOpAluFunct.width, + CaseItem( + Const( + MicroOpAluFunct.remu, + width: MicroOpAluFunct.width, + ), + idivArm(isW: false, isRem: true, isSigned: false), ), - [ - alu < - (readField(mop['Alu']!['a']!) % - readField(mop['Alu']!['b']!)), - mopStep < mopStep + 1, - microcodeRead.en < 0, - ], - ), - CaseItem( - Const( - MicroOpAluFunct.remuw.value, - width: MicroOpAluFunct.width, + CaseItem( + Const( + MicroOpAluFunct.remuw, + width: MicroOpAluFunct.width, + ), + idivArm(isW: true, isRem: true, isSigned: false), ), - [ - alu < - (readField(mop['Alu']!['a']!) % - readField(mop['Alu']!['b']!)), - mopStep < mopStep + 1, - microcodeRead.en < 0, - ], - ), - CaseItem( - Const( - MicroOpAluFunct.remw.value, - width: MicroOpAluFunct.width, + CaseItem( + Const( + MicroOpAluFunct.remw, + width: MicroOpAluFunct.width, + ), + idivArm(isW: true, isRem: true, isSigned: true), ), - [ - alu < - (readField(mop['Alu']!['a']!) % - readField(mop['Alu']!['b']!)), - mopStep < mopStep + 1, - microcodeRead.en < 0, - ], - ), - ]), + ], + defaultItem: [ + // All single-cycle ALU functs (add/sub/logic/shift/ + // compare/word/zicond) route to the shared MicrocodeAlu; + // only the multi-cycle mul (_imul) and div/rem + // (IterativeDivider) arms above are explicit. + alu < microcodeAlu, + mopStep < mopStep + 1, + microcodeRead.en < 0, + ], + ), ]), CaseItem(Const(UpdatePCMicroOp.funct, width: funct.width), [ nextPc < @@ -1317,12 +2243,10 @@ class DynamicExecutionUnit extends ExecutionUnit { ) + mux( mop['UpdatePC']!['hasField']!, - readField(mop['UpdatePC']!['offsetField']!), + sharedFieldVal!, mux( mop['UpdatePC']!['hasSource']!, - readSource( - mop['UpdatePC']!['offsetSource']!, - ), + sharedSourceVal, mop['UpdatePC']!['offset']!, ), )) & @@ -1343,17 +2267,13 @@ class DynamicExecutionUnit extends ExecutionUnit { Const(size.value, width: MicroOpMemSize.width), [ If( - ((readField(mop['MemLoad']!['base']!) + imm) & + ((opBase + imm) & Const(size.bytes - 1, width: mxlen.size)) .neq(0), - then: doTrap( - Trap.misalignedLoad, - readField(mop['MemLoad']!['base']!) + imm, - ), + then: doTrap(Trap.misalignedLoad, opBase + imm), orElse: [ memRead.en < 1, - memRead.addr < - (readField(mop['MemLoad']!['base']!) + imm), + memRead.addr < (opBase + imm), ], ), ], @@ -1369,23 +2289,18 @@ class DynamicExecutionUnit extends ExecutionUnit { Const(size.value, width: MicroOpMemSize.width), [ If( - ((readField(mop['MemStore']!['base']!) + imm) & + ((opBase + imm) & Const(size.bytes - 1, width: mxlen.size)) .neq(0), - then: doTrap( - Trap.misalignedStore, - readField(mop['MemStore']!['base']!) + imm, - ), + then: doTrap(Trap.misalignedStore, opBase + imm), orElse: [ memWrite.en < 1, - memWrite.addr < - (readField(mop['MemStore']!['base']!) + - imm), + memWrite.addr < (opBase + imm), memWrite.data < [ (Const(1, width: 7) << - mop['MemLoad']!['size']!), - readField(mop['MemStore']!['src']!), + mop['MemStore']!['size']!), + opStoreSrc, ].swizzle(), ], ), @@ -1393,175 +2308,172 @@ class DynamicExecutionUnit extends ExecutionUnit { ), ]), ]), - CaseItem(Const(TrapMicroOp.funct, width: funct.width), [ - Case(currentMode, [ - for (final mode in PrivilegeMode.values) - CaseItem(Const(mode.id, width: 3), [ - Case(mop['Trap']![mode.name]!, [ - for (final trap in Trap.values) - CaseItem( - Const( - trap.index, - width: Trap.values.length.bitLength, - ), - doTrap(trap), + // Load-reserved: issue the read (the memRead-completion wrapper + // writes rd, sets the reservation, and advances). + CaseItem( + Const(LoadReservedMicroOp.funct, width: funct.width), + [ + Case(mop['LoadReserved']!['size']!, [ + for (final size in MicroOpMemSize.values.where( + atomicSize, + )) + CaseItem( + Const(size.value, width: MicroOpMemSize.width), + [ + If( + (opBase & + Const( + size.bytes - 1, + width: mxlen.size, + )) + .neq(0), + then: doTrap(Trap.misalignedLoad, opBase), + orElse: [memRead.en < 1, memRead.addr < opBase], ), - ]), - ]), - ]), - ]), - CaseItem(Const(BranchIfMicroOp.funct, width: funct.width), [ - Case(mop['BranchIf']!['condition']!, [ - CaseItem( - Const( - MicroOpCondition.eq.value, - width: MicroOpCondition.width, - ), - [ - If( - readSource(mop['BranchIf']!['target']!).eq(0), - then: [ - nextPc < - mux( - mop['BranchIf']!['hasField']!, - readField(mop['BranchIf']!['offsetField']!), - mop['BranchIf']!['offset']!, - ), - done < 1, - valid < 1, - ], - orElse: [ - mopStep < mopStep + 1, - microcodeRead.en < 0, ], ), - ], - ), - CaseItem( - Const( - MicroOpCondition.ne.value, - width: MicroOpCondition.width, - ), - [ - If( - readSource(mop['BranchIf']!['target']!).neq(0), - then: [ - nextPc < - mux( - mop['BranchIf']!['hasField']!, - readField(mop['BranchIf']!['offsetField']!), - mop['BranchIf']!['offset']!, + ]), + ], + ), + // Store-conditional: on a reservation HIT, issue the write (the + // memWrite-completion wrapper writes rd=0 and advances); on a + // MISS, write rd=1 and complete here. Always clears the + // reservation. + CaseItem( + Const(StoreConditionalMicroOp.funct, width: funct.width), + [ + Case(mop['StoreConditional']!['size']!, [ + for (final size in MicroOpMemSize.values.where( + atomicSize, + )) + CaseItem( + Const(size.value, width: MicroOpMemSize.width), + [ + If( + (opBase & + Const( + size.bytes - 1, + width: mxlen.size, + )) + .neq(0), + then: doTrap(Trap.misalignedStore, opBase), + orElse: [ + reservationValid < 0, + If( + reservationValid & + reservationAddr.eq(opBase), + then: [ + memWrite.en < 1, + // opBase IS readField(SC base) here (funct + // selects StoreConditional), so reuse the + // shared base read instead of two more. + memWrite.addr < opBase, + memWrite.data < + [ + Const(size.bytes, width: 7), + opStoreSrc, + ].swizzle(), + ], + orElse: [ + // Miss: rd = 1 (fail), complete now. + If( + readField( + mop['StoreConditional']!['dest']!, + register: false, + ).slice(4, 0).gt(0), + then: [ + rdWrite.addr < + readField( + mop['StoreConditional']!['dest']!, + register: false, + ).slice(4, 0), + rdWrite.data < + Const(1, width: mxlen.size), + rdWrite.en < 1, + ], + orElse: [ + mopStep < mopStep + 1, + microcodeRead.en < 0, + ], + ), + ], ), - done < 1, - valid < 1, - ], - orElse: [ - mopStep < mopStep + 1, - microcodeRead.en < 0, + ], + ), ], ), - ], - ), - CaseItem( - Const( - MicroOpCondition.lt.value, - width: MicroOpCondition.width, - ), - [ - If( - readSource(mop['BranchIf']!['target']!).lt(0), - then: [ - nextPc < - mux( - mop['BranchIf']!['hasField']!, - readField(mop['BranchIf']!['offsetField']!), - mop['BranchIf']!['offset']!, - ), - done < 1, - valid < 1, - ], - orElse: [ - mopStep < mopStep + 1, - microcodeRead.en < 0, - ], - ), - ], - ), - CaseItem( - Const( - MicroOpCondition.gt.value, - width: MicroOpCondition.width, - ), - [ - If( - readSource(mop['BranchIf']!['target']!).gt(0), - then: [ - nextPc < - mux( - mop['BranchIf']!['hasField']!, - readField(mop['BranchIf']!['offsetField']!), - mop['BranchIf']!['offset']!, - ), - done < 1, - valid < 1, - ], - orElse: [ - mopStep < mopStep + 1, - microcodeRead.en < 0, + ]), + ], + ), + // AMO: issue the read; the memRead-completion wrapper latches + // the old value, computes the new value and issues the write, + // and the memWrite-completion wrapper writes rd and advances. + CaseItem( + Const(AtomicMemoryMicroOp.funct, width: funct.width), + [ + Case(mop['AtomicMemory']!['size']!, [ + for (final size in MicroOpMemSize.values.where( + atomicSize, + )) + CaseItem( + Const(size.value, width: MicroOpMemSize.width), + [ + If( + (opBase & + Const( + size.bytes - 1, + width: mxlen.size, + )) + .neq(0), + then: doTrap(Trap.misalignedStore, opBase), + orElse: [memRead.en < 1, memRead.addr < opBase], + ), ], ), - ], - ), - CaseItem( - Const( - MicroOpCondition.ge.value, - width: MicroOpCondition.width, + ]), + ], + ), + CaseItem(Const(TrapMicroOp.funct, width: funct.width), [ + ...rawTrap( + mop['Trap']!['isInterrupt']!, + mop['Trap']!['causeCode']!, + ), + ]), + CaseItem(Const(BranchIfMicroOp.funct, width: funct.width), [ + // Compare the latched rs1/rs2 values DIRECTLY (the branch + // microcode reads both before this step). Testing the sign of + // the rs1-rs2 difference can't express unsigned bltu/bgeu and + // is wrong for signed blt/bge on overflow. Mirrors the static + // RiscVBranch path + fu_branch.dart. + Case(mop['BranchIf']!['condition']!, [ + for (final cond in [ + (MicroOpCondition.eq, rs1.eq(rs2)), + (MicroOpCondition.ne, rs1.neq(rs2)), + (MicroOpCondition.lt, bmSignedLt(rs1, rs2, mxlen.size)), + ( + MicroOpCondition.ge, + ~bmSignedLt(rs1, rs2, mxlen.size), ), - [ - If( - readSource(mop['BranchIf']!['target']!).gte(0), - then: [ - nextPc < - mux( - mop['BranchIf']!['hasField']!, - readField(mop['BranchIf']!['offsetField']!), - mop['BranchIf']!['offset']!, - ), - done < 1, - valid < 1, - ], - orElse: [ - mopStep < mopStep + 1, - microcodeRead.en < 0, - ], - ), - ], - ), - CaseItem( - Const( - MicroOpCondition.le.value, - width: MicroOpCondition.width, + (MicroOpCondition.ltu, rs1.lt(rs2)), + (MicroOpCondition.geu, ~rs1.lt(rs2)), + ]) + CaseItem( + Const(cond.$1, width: MicroOpCondition.width), + [ + If( + cond.$2, + then: [ + nextPc < (currentPc + imm), + done < 1, + valid < 1, + ], + orElse: [ + mopStep < mopStep + 1, + microcodeRead.en < 0, + ], + ), + ], ), - [ - If( - readSource(mop['BranchIf']!['target']!).lte(0), - then: [ - nextPc < - mux( - mop['BranchIf']!['hasField']!, - readField(mop['BranchIf']!['offsetField']!), - mop['BranchIf']!['offset']!, - ), - done < 1, - valid < 1, - ], - orElse: [ - mopStep < mopStep + 1, - microcodeRead.en < 0, - ], - ), - ], - ), ]), ]), CaseItem( @@ -1605,6 +2517,14 @@ class DynamicExecutionUnit extends ExecutionUnit { (nextPc + mop['WriteLinkRegister']!['pcOffset']!), ], + // rd == x0: a no-link jump (`tail`/`jr`). No write + // issues, so the rdWrite.done handshake that + // advances mopStep never fires; advance directly + // here or the FSM hangs on the jump. + orElse: [ + mopStep < mopStep + 1, + microcodeRead.en < 0, + ], ), ]), ]), @@ -1622,170 +2542,189 @@ class DynamicExecutionUnit extends ExecutionUnit { mopStep < mopStep + 1, microcodeRead.en < 0, ]), - CaseItem( - Const(ValidateFieldMicroOp.funct, width: funct.width), - [ - Case(mop['ValidateField']!['condition']!, [ - CaseItem( - Const( - MicroOpCondition.eq.value, - width: MicroOpCondition.width, + if (mop.containsKey('ValidateField')) + CaseItem( + Const(ValidateFieldMicroOp.funct, width: funct.width), + [ + Case(mop['ValidateField']!['condition']!, [ + CaseItem( + Const( + MicroOpCondition.eq, + width: MicroOpCondition.width, + ), + [ + If( + readField( + mop['ValidateField']!['field']!, + ).eq(mop['ValidateField']!['value']!), + then: [ + mopStep < mopStep + 1, + microcodeRead.en < 0, + ], + orElse: doTrap(Trap.illegal), + ), + ], ), - [ - If( - readField( - mop['ValidateField']!['field']!, - ).eq(mop['ValidateField']!['value']!), - then: [ - mopStep < mopStep + 1, - microcodeRead.en < 0, - ], - orElse: doTrap(Trap.illegal), + CaseItem( + Const( + MicroOpCondition.ne, + width: MicroOpCondition.width, ), - ], - ), - CaseItem( - Const( - MicroOpCondition.ne.value, - width: MicroOpCondition.width, + [ + If( + readField( + mop['ValidateField']!['field']!, + ).neq(mop['ValidateField']!['value']!), + then: [ + mopStep < mopStep + 1, + microcodeRead.en < 0, + ], + orElse: doTrap(Trap.illegal), + ), + ], ), - [ - If( - readField( - mop['ValidateField']!['field']!, - ).neq(mop['ValidateField']!['value']!), - then: [ - mopStep < mopStep + 1, - microcodeRead.en < 0, - ], - orElse: doTrap(Trap.illegal), + CaseItem( + Const( + MicroOpCondition.lt, + width: MicroOpCondition.width, ), - ], - ), - CaseItem( - Const( - MicroOpCondition.lt.value, - width: MicroOpCondition.width, + [ + If( + readField( + mop['ValidateField']!['field']!, + ).lt(mop['ValidateField']!['value']!), + then: [ + mopStep < mopStep + 1, + microcodeRead.en < 0, + ], + orElse: doTrap(Trap.illegal), + ), + ], ), - [ - If( - readField( - mop['ValidateField']!['field']!, - ).lt(mop['ValidateField']!['value']!), - then: [ - mopStep < mopStep + 1, - microcodeRead.en < 0, - ], - orElse: doTrap(Trap.illegal), + CaseItem( + Const( + MicroOpCondition.gt, + width: MicroOpCondition.width, ), - ], - ), - CaseItem( - Const( - MicroOpCondition.gt.value, - width: MicroOpCondition.width, + [ + If( + readField( + mop['ValidateField']!['field']!, + ).gt(mop['ValidateField']!['value']!), + then: [ + mopStep < mopStep + 1, + microcodeRead.en < 0, + ], + orElse: doTrap(Trap.illegal), + ), + ], ), - [ - If( - readField( - mop['ValidateField']!['field']!, - ).gt(mop['ValidateField']!['value']!), - then: [ - mopStep < mopStep + 1, - microcodeRead.en < 0, - ], - orElse: doTrap(Trap.illegal), + CaseItem( + Const( + MicroOpCondition.ge, + width: MicroOpCondition.width, ), - ], - ), - CaseItem( - Const( - MicroOpCondition.ge.value, - width: MicroOpCondition.width, + [ + If( + readField( + mop['ValidateField']!['field']!, + ).gte(mop['ValidateField']!['value']!), + then: [ + mopStep < mopStep + 1, + microcodeRead.en < 0, + ], + orElse: doTrap(Trap.illegal), + ), + ], ), - [ - If( - readField( - mop['ValidateField']!['field']!, - ).gte(mop['ValidateField']!['value']!), - then: [ - mopStep < mopStep + 1, - microcodeRead.en < 0, - ], - orElse: doTrap(Trap.illegal), + CaseItem( + Const( + MicroOpCondition.le, + width: MicroOpCondition.width, ), - ], - ), - CaseItem( - Const( - MicroOpCondition.le.value, - width: MicroOpCondition.width, + [ + If( + readField( + mop['ValidateField']!['field']!, + ).lte(mop['ValidateField']!['value']!), + then: [ + mopStep < mopStep + 1, + microcodeRead.en < 0, + ], + orElse: doTrap(Trap.illegal), + ), + ], ), - [ - If( - readField( - mop['ValidateField']!['field']!, - ).lte(mop['ValidateField']!['value']!), - then: [ - mopStep < mopStep + 1, - microcodeRead.en < 0, - ], - orElse: doTrap(Trap.illegal), + ]), + ], + ), + if (mop.containsKey('ModifyLatch')) + CaseItem( + Const(ModifyLatchMicroOp.funct, width: funct.width), + [ + If( + mop['ModifyLatch']!['replace']!, + then: [ + writeField( + mop['ModifyLatch']!['field']!, + sharedSourceVal, ), + mopStep < mopStep + 1, + microcodeRead.en < 0, + ], + orElse: [ + clearField(mop['ModifyLatch']!['field']!), + mopStep < mopStep + 1, + microcodeRead.en < 0, ], ), - ]), - ], - ), - CaseItem( - Const(ModifyLatchMicroOp.funct, width: funct.width), - [ - If( - mop['ModifyLatch']!['replace']!, - then: [ - writeField( - mop['ModifyLatch']!['field']!, - readSource(mop['ModifyLatch']!['source']!), - ), - mopStep < mopStep + 1, - microcodeRead.en < 0, - ], - orElse: [ - clearField(mop['ModifyLatch']!['field']!), - mopStep < mopStep + 1, - microcodeRead.en < 0, - ], - ), - ], - ), - CaseItem(Const(SetFieldMicroOp.funct, width: funct.width), [ - writeField( - mop['SetField']!['field']!, - mop['SetField']!['value']!, + ], ), - mopStep < mopStep + 1, - microcodeRead.en < 0, - ]), - CaseItem( - Const(InterruptHoldMicroOp.funct, width: funct.width), - [ - interruptHold < 1, + if (mop.containsKey('SetField')) + CaseItem(Const(SetFieldMicroOp.funct, width: funct.width), [ + writeField( + mop['SetField']!['field']!, + mop['SetField']!['value']!, + ), mopStep < mopStep + 1, microcodeRead.en < 0, - ], - ), + ]), + if (functEmitted(InterruptHoldMicroOp.funct)) + CaseItem( + Const(InterruptHoldMicroOp.funct, width: funct.width), + [ + interruptHold < 1, + mopStep < mopStep + 1, + microcodeRead.en < 0, + ], + ), + if (mop.containsKey('CopyField')) + CaseItem( + Const(CopyFieldMicroOp.funct, width: funct.width), + [ + writeField(mop['CopyField']!['dest']!, sharedFieldVal!), + mopStep < mopStep + 1, + microcodeRead.en < 0, + ], + ), + if (mop.containsKey('MoveToField')) + CaseItem( + Const(SetFieldMicroOpFunct.funct, width: funct.width), + [ + writeField( + mop['MoveToField']!['dest']!, + sharedSourceVal, + ), + mopStep < mopStep + 1, + microcodeRead.en < 0, + ], + ), if (csrRead != null) CaseItem(Const(ReadCsrMicroOp.funct, width: funct.width), [ If( currentMode.eq(Const(PrivilegeMode.user.id, width: 3)), then: doTrap(Trap.illegal), - orElse: [ - csrRead.en < 1, - csrRead.addr < - readField( - mop['ReadCsr']!['source']!, - ).slice(11, 0), - ], + orElse: [csrRead.en < 1, csrRead.addr < csrAddr!], ), ]), if (csrWrite != null) @@ -1795,27 +2734,48 @@ class DynamicExecutionUnit extends ExecutionUnit { then: doTrap(Trap.illegal), orElse: [ csrWrite.en < 1, - csrWrite.addr < - readField( - mop['WriteCsr']!['field']!, - ).slice(11, 0), - csrWrite.data < - readSource(mop['WriteCsr']!['source']!), + csrWrite.addr < csrAddr!, + csrWrite.data < sharedSourceVal, ], ), ]), - CaseItem(Const(TlbFenceMicroOp.funct, width: funct.width), [ - // TODO: once MMU has a TLB - mopStep < mopStep + 1, - microcodeRead.en < 0, - ]), - CaseItem( - Const(TlbInvalidateMicroOp.funct, width: funct.width), - [ - // TODO: once MMU has a TLB + if (functEmitted(TlbFenceMicroOp.funct)) + CaseItem(Const(TlbFenceMicroOp.funct, width: funct.width), [ + // sfence.vma: pulse fence, which the core routes to the MMU + // fetch-TLB flush (it also harmlessly over-flushes the icache). + fence < 1, mopStep < mopStep + 1, microcodeRead.en < 0, - ], + ]), + if (functEmitted(TlbInvalidateMicroOp.funct)) + CaseItem( + Const(TlbInvalidateMicroOp.funct, width: funct.width), + [ + // TODO: once MMU has a TLB + mopStep < mopStep + 1, + microcodeRead.en < 0, + ], + ), + // MRET/SRET. Terminal single-step: signal the return and target + // privilege; core.dart restores PC<-{m,s}epc, mode<-{m,s}status.xPP + // and pops the status stack. privilegeLevel from the micro-op + // (3=M, 1=S). Mirrors the static RiscVReturnOp path. Missing here + // once, so mret looped forever (the creek trap-return hang). + CaseItem(Const(ReturnMicroOp.funct, width: funct.width), [ + output('isReturn') < 1, + output('returnLevel') < + mop['Return']!['privilegeLevel']!.zeroExtend( + output('returnLevel').width, + ), + done < 1, + valid < 1, + ]), + // wfi: treat the wait as a NOP hint and advance to the next + // micro-op (its microcode's UpdatePc retires at pc+4). Without + // this arm wfi hit the default case and stalled the core. + CaseItem( + Const(WaitForInterruptMicroOp.funct, width: funct.width), + [mopStep < mopStep + 1, microcodeRead.en < 0], ), CaseItem(Const(0, width: funct.width), []), ], @@ -1844,6 +2804,16 @@ class DynamicExecutionUnit extends ExecutionUnit { } class StaticExecutionUnit extends ExecutionUnit { + /// One [BmMulSet] per distinct operand FIELD pair: every mul-family + /// micro-op shares a single multiplier array instead of elaborating its + /// own (the static per-arm switch otherwise builds one per opcode). Keyed + /// by the field enums because readField mints a fresh wire per call; the + /// underlying field latches are the same signals across micro-ops. + final _mulSets = {}; + + BmMulSet _mulSetFor(Object key, Logic a, Logic b, int w) => + _mulSets.putIfAbsent(key, () => BmMulSet(a, b, w)); + StaticExecutionUnit( super.clk, super.reset, @@ -1865,10 +2835,16 @@ class StaticExecutionUnit extends ExecutionUnit { super.hasUser = false, required super.microcode, required super.mxlen, + super.vlen = 128, super.mideleg, super.medeleg, super.mtvec, super.stvec, + super.virtIn, + super.mstateen0Se0, + super.hstateen0Se0, + super.memFaultGuest, + super.fetchFault, super.staticInstructions = const [], super.counterWidth = 32, super.name = 'river_static_execution_unit', @@ -1897,66 +2873,59 @@ class StaticExecutionUnit extends ExecutionUnit { .map((s) => s.ops.length * 2) .fold(0, (a, b) => a > b ? a : b); - Logic readSource(MicroOpSource source) { + Logic readSource(RiscVMicroOpSource source) { switch (source) { - case MicroOpSource.imm: + case RiscVMicroOpSource.imm: return imm; - case MicroOpSource.alu: + case RiscVMicroOpSource.alu: return alu; - case MicroOpSource.rs1: + case RiscVMicroOpSource.rs1: return rs1; - case MicroOpSource.rs2: + case RiscVMicroOpSource.rs2: return rs2; - case MicroOpSource.rd: + case RiscVMicroOpSource.rd: return rd; - case MicroOpSource.pc: + case RiscVMicroOpSource.pc: return nextPc; - default: - throw 'Invalid source $source'; } } - Logic readField(MicroOpField field, {bool register = true}) { + Logic readField(RiscVMicroOpField field, {bool register = true}) { switch (field) { - case MicroOpField.rd: + case RiscVMicroOpField.rd: return (register ? rd : fields['rd']!).zeroExtend(mxlen.size); - case MicroOpField.rs1: + case RiscVMicroOpField.rs1: return (register ? rs1 : fields['rs1']!).zeroExtend(mxlen.size); - case MicroOpField.rs2: + case RiscVMicroOpField.rs2: return (register ? rs2 : fields['rs2']!).zeroExtend(mxlen.size); - case MicroOpField.imm: + case RiscVMicroOpField.imm: return register ? imm : fields['imm']!; - case MicroOpField.pc: + case RiscVMicroOpField.pc: return nextPc; - case MicroOpField.sp: - return nextSp; - default: - throw 'Invalid field $field'; + case RiscVMicroOpField.rs3: + return (register ? _rs3Latch! : fields['rs3']!).zeroExtend( + mxlen.size, + ); } } - Conditional writeField(MicroOpField field, Logic value) { + Conditional writeField(RiscVMicroOpField field, Logic value) { switch (field) { - case MicroOpField.rd: + case RiscVMicroOpField.rd: return rd < value.zeroExtend(mxlen.size); - case MicroOpField.rs1: + case RiscVMicroOpField.rs1: return rs1 < value.zeroExtend(mxlen.size); - case MicroOpField.rs2: + case RiscVMicroOpField.rs2: return rs2 < value.zeroExtend(mxlen.size); - case MicroOpField.imm: + case RiscVMicroOpField.imm: return imm < value.zeroExtend(mxlen.size); - case MicroOpField.sp: + case RiscVMicroOpField.pc: return nextPc < value.zeroExtend(mxlen.size); - case MicroOpField.sp: - return nextSp < value.zeroExtend(mxlen.size); - default: - throw 'Invalid field $field'; + case RiscVMicroOpField.rs3: + return _rs3Latch! < value.zeroExtend(mxlen.size); } } - Conditional clearField(MicroOpField field) => - writeField(field, fields[field.name]!.zeroExtend(mxlen.size)); - return [ Case( instrIndex, @@ -1970,28 +2939,1483 @@ class StaticExecutionUnit extends ExecutionUnit { final op = entry.value; final steps = []; - for (final mop in op.indexedMicrocode.values) { - final i = steps.length + 1; + // Which micro-op fields name FP registers for this op (from its + // RfResource declarations). ReadRegister/WriteRegister of these + // fields route to the FP register file rather than the integer one. + final fpFields = {}; + for (final r in op.resources) { + if (r is RfResource && r.regfile is RiscVFloatRegFile) { + final a = r.access; + if (a is RfRead) { + if (a.name == 'RS1') fpFields.add(RiscVMicroOpField.rs1); + if (a.name == 'RS2') fpFields.add(RiscVMicroOpField.rs2); + if (a.name == 'RS3') fpFields.add(RiscVMicroOpField.rs3); + } else if (a is RfWrite && a.name == 'RD') { + fpFields.add(RiscVMicroOpField.rd); + } + } + } + + // Vector vsetvli: vl = min(AVL, VLMAX), VLMAX = vlen*LMUL/SEW. + // Special-cased (its only microcode is RiscVUpdatePc): read AVL + // from rs1, compute vl from the vtypei immediate (zimm_rs2 = + // bits[30:20]: vsew[5:3], vlmul[2:0]), write rd=vl, advance PC. + // VLMAX = base<>(8-vlmul) + // for fractional LMUL (vlmul 5/6/7 = mf8/mf4/mf2), base = vlen>>(3+vsew). + // rs1==x0 is special: with rd!=x0 it sets vl=VLMAX; with rd==x0 it + // keeps the current vl (vtype still updates). The micro-op loop + // below is skipped for vsetvli. + final isVsetvli = op.mnemonic == 'vsetvli'; + final isVle = op.mnemonic == 'vle32.v'; + final isVse = op.mnemonic == 'vse32.v'; + // OPIVV/OPIVX/OPIVI integer arithmetic. The decoder collides all + // ops within a funct3 group, so these mnemonics are the collided + // entries (.vv/.vx/.vi); the actual op is the runtime funct6, and + // the second operand is a vreg (.vv) / scalar broadcast (.vx) / + // immediate broadcast (.vi). + final isVArithVV = op.mnemonic == 'vadd.vv'; + final isVArithVX = op.mnemonic == 'vadd.vx'; + final isVArithVI = op.mnemonic == 'vadd.vi'; + final isVArith = isVArithVV || isVArithVX || isVArithVI; + // OPFVV FP arithmetic collides like the integer ops; vfadd/vfmul + // are distinguished by the runtime funct6 (add=0x00, mul=0x24). + final isVFloat = op.mnemonic == 'vfadd.vv'; + final isVecHandled = + isVsetvli || isVle || isVse || isVArith || isVFloat; + if (isVsetvli) { + final vtypei = fields['zimm_rs2']!; + final vsew = vtypei.slice(5, 3); + final vlmul = vtypei.slice(2, 0); + final avlIdx = fields['rs1_uimm']!.slice(4, 0); + final rdIdx = fields['rd']!.slice(4, 0); + final shiftAmt = Const(3, width: 6) + vsew.zeroExtend(6); + final base = Const(vlen, width: mxlen.size) >> shiftAmt; + // Integer LMUL (vlmul 0-3): base<>(8-vlmul). + final vlmaxInt = base << vlmul.zeroExtend(mxlen.size); + final vlmaxFrac = + base >> (Const(8, width: 6) - vlmul.zeroExtend(6)); + final vlmax = mux(vlmul[2], vlmaxFrac, vlmaxInt); + final rs1IsX0 = avlIdx.eq(Const(0, width: 5)); + final rdIsX0 = rdIdx.eq(Const(0, width: 5)); + final minAvl = mux(rs1Read.data.lt(vlmax), rs1Read.data, vlmax); + // rs1!=x0: min(x[rs1], VLMAX). rs1=x0: VLMAX, or keep vl if rd=x0. + final vl = mux(rs1IsX0, mux(rdIsX0, _vl!, vlmax), minAvl); + steps.add( + CaseItem(Const(1, width: maxLen.bitLength), [ + rs1Read.addr < avlIdx, + rs1Read.en < 1, + mopStep < mopStep + 1, + ]), + ); + steps.add( + CaseItem(Const(2, width: maxLen.bitLength), [ + If( + rs1Read.done & rs1Read.valid, + then: [ + rdWrite.addr < rdIdx, + rdWrite.data < vl, + rdWrite.en < rdIdx.neq(Const(0, width: 5)), + // Commit vector config state for subsequent ops. + _vtype! < vtypei, + _vl! < vl, + // nextPc holds into the auto-done step (steps.length+1). + nextPc < (currentPc + Const(4, width: mxlen.size)), + mopStep < mopStep + 1, + ], + ), + ]), + ); + } else if (isVle) { + // vle32.v vd, (rs1): unit-stride load of the full VLEN-wide vreg + // from x[rs1], as VLEN/mxlen mxlen-wide chunks. For VLEN=128 / + // rv64 that's 2 chunks: base is captured in `alu`, chunk 0 in + // `rs1`, and the final step assembles vd = {chunk1, chunk0}. + // (vl1. Holding en high and + // only changing the address streams stale data (the k>0 + // load otherwise consumed the previous register's chunk). + memRead.en < 0, + If( + (kL.zeroExtend(5) + Const(1, width: 5)).lt(lmaxL), + then: [ + // Loop to step 1 (re-read base): re-reading the GPR + // base is idempotent and lets _vregIdx settle before + // the address recomputes. + _vregIdx! < (kL + Const(1, width: 4)), + mopStep < Const(1, width: maxLen.bitLength), + ], + orElse: [ + _vregIdx! < Const(0, width: 4), + nextPc < (currentPc + Const(4, width: mxlen.size)), + mopStep < mopStep + 1, + ], + ), + ], + ), + ]), + ); + } else if (isVse) { + // vse32.v vs3, (rs1): store the full VLEN-wide vreg to x[rs1] as + // VLEN/mxlen sized dword chunks (2 for VLEN=128/rv64). Base in + // `alu`; vs3 held in vrs1Read across the chunk writes. + final chunkBytes = mxlen.size ~/ 8; + final regStride = vlen ~/ 8; // bytes per vreg + final baseIdx = fields['rs1']!.slice(4, 0); + final vs3Idx = fields['vd_vs3']!.slice(4, 0); + // sized-store data {size=8 (dword), value} for a vreg slice. + Logic stData(Logic v) => [Const(8, width: 7), v].swizzle(); + // LMUL grouping: store L=1< + (base.zeroExtend(6) + k.zeroExtend(6)).slice(4, 0); + final vs2Reg = regAddr(vs2Idx); + final vs1Reg = regAddr(src1Idx); + final vdReg = regAddr(vdIdx); + // Elements per register at the live SEW (= VLEN / SEW). + final epr = + (Const(vlen, width: 16) >> + (Const(3, width: 4) + vsew.zeroExtend(4))) + .zeroExtend(_vl!.width); + Logic seg( + int laneW, + Logic a, + Logic b, + Logic Function(Logic, Logic) f, + ) { + final lanes = []; + for (var lo = 0; lo + laneW <= vlen; lo += laneW) { + lanes.add( + f( + a.slice(lo + laneW - 1, lo), + b.slice(lo + laneW - 1, lo), + ), + ); + } + return lanes.reversed.toList().swizzle(); + } + + // Select lane width from the live vsew (default 32). + Logic segSew( + Logic a, + Logic b, + Logic Function(Logic, Logic) f, + ) => mux( + vsew.eq(Const(0, width: 3)), + seg(8, a, b, f), + mux( + vsew.eq(Const(1, width: 3)), + seg(16, a, b, f), + mux( + vsew.eq(Const(3, width: 3)), + seg(64, a, b, f), + seg(32, a, b, f), + ), + ), + ); + + // Op from the runtime funct6 (the collided mnemonic is always + // 'vadd.*'). a = vs2, b = the second operand. funct6: add=0x00, + // sub=0x02, and=0x09, or=0x0A, xor=0x0B. and/or/xor are + // SEW-independent (full-width bitwise). + final f6 = fields['funct6']!; + Logic f6eq(int v) => f6.eq(Const(v, width: f6.width)); + // Per-lane shift amount = low log2(SEW) bits of b (SEW = x.width). + Logic sll(Logic x, Logic y) => + x << y.slice(x.width.bitLength - 2, 0); + Logic srl(Logic x, Logic y) => + x >>> y.slice(x.width.bitLength - 2, 0); + Logic arith(Logic a, Logic b) => mux( + f6eq(0x02), + segSew(a, b, (x, y) => x - y), // vsub + mux( + f6eq(0x09), + a & b, // vand (SEW-independent) + mux( + f6eq(0x0A), + a | b, // vor + mux( + f6eq(0x0B), + a ^ b, // vxor + mux( + f6eq(0x04), + segSew(a, b, (x, y) => mux(x.lt(y), x, y)), // vminu + mux( + f6eq(0x05), + segSew( + a, + b, + (x, y) => mux(bmSignedLt(x, y, x.width), x, y), + ), + mux( + f6eq(0x06), + segSew( + a, + b, + (x, y) => mux(x.lt(y), y, x), + ), // vmaxu + mux( + f6eq(0x07), + segSew( + a, + b, + (x, y) => + mux(bmSignedLt(x, y, x.width), y, x), + ), + mux( + f6eq(0x25), + segSew(a, b, sll), // vsll + mux( + f6eq(0x28), + segSew(a, b, srl), // vsrl + segSew( + a, + b, + (x, y) => x + y, + ), // 0x00 = vadd + ), + ), + ), + ), + ), + ), + ), + ), + ), + ); + + // Broadcast a 32-bit scalar to every SEW=32 lane. + Logic bcast(Logic s32) => + List.filled(vlen ~/ 32, s32).swizzle(); + // .vi immediate: imm5 in the vs1 field, sign-extended to 32. + final immB = bcast(fields['vs1']!.slice(4, 0).signExtend(32)); + + steps.add( + CaseItem(Const(1, width: maxLen.bitLength), [ + vrs2Read!.addr < vs2Reg, + vrs2Read!.en < 1, + if (isVArithVV) ...[ + vrs1Read!.addr < vs1Reg, + vrs1Read!.en < 1, + ], + if (isVArithVX) ...[rs1Read.addr < src1Idx, rs1Read.en < 1], + mopStep < mopStep + 1, + ]), + ); + final src1Ready = isVArithVV + ? (vrs1Read!.done & vrs1Read!.valid) + : isVArithVX + ? (rs1Read.done & rs1Read.valid) + : Const(1); // .vi: immediate, no read + final b = isVArithVV + ? vrs1Read!.data + : isVArithVX + ? bcast(rs1Read.data.slice(31, 0)) + : immB; + // Step 2: capture the full-width result. Step 3 reads the old vd + // and merges: active lanes (low vl*SEW bits) take the result, + // tail bits stay undisturbed (matches the emulator). + steps.add( + CaseItem(Const(2, width: maxLen.bitLength), [ + If( + vrs2Read!.done & vrs2Read!.valid & src1Ready, + then: [ + _vtmp! < arith(vrs2Read!.data, b), + // Re-point a read port to old vd; its data (the vreg + // read has 1-cycle latency) is consumed at step 3. + vrs2Read!.addr < vdReg, + vrs2Read!.en < 1, + mopStep < mopStep + 1, + ], + ), + ]), + ); + // Per-register vl/tail mask for register k: the active elements + // are the global indices [k*EPR, (k+1)*EPR) that are below vl, so + // localVl = clamp(vl - k*EPR, 0, EPR), and the mask is the low + // (localVl * SEW) bits. Register k beyond vl gets localVl=0 (mask + // 0 -> vd undisturbed); a fully-active register gets the full mask. + final kEpr = (k.zeroExtend(_vl!.width) * epr).slice( + _vl!.width - 1, + 0, + ); + final remVl = mux( + _vl!.gt(kEpr), + _vl! - kEpr, + Const(0, width: _vl!.width), + ); + final localVl = mux(remVl.gt(epr), epr, remVl); + final shiftAmt = + localVl << (Const(3, width: 4) + vsew.zeroExtend(4)); + final ones = Const(1, width: vlen + 1); + final mask = ((ones << shiftAmt) - ones).slice(vlen - 1, 0); + steps.add( + CaseItem(Const(3, width: maxLen.bitLength), [ + // vrs2Read.data is now old vd (addr set at step 2). Merge: + // active lanes = result, tail = undisturbed. + vrdWrite!.addr < vdReg, + vrdWrite!.data < + ((_vtmp! & mask) | (vrs2Read!.data & ~mask)), + vrdWrite!.en < 1, + If( + (k.zeroExtend(5) + Const(1, width: 5)).lt(lmax), + then: [ + // More registers in the group: advance k and restart the + // 3-step FSM at step 1 (mopStep holds the PC unchanged). + _vregIdx! < (k + Const(1, width: 4)), + mopStep < Const(1, width: maxLen.bitLength), + ], + orElse: [ + _vregIdx! < Const(0, width: 4), + nextPc < (currentPc + Const(4, width: mxlen.size)), + mopStep < mopStep + 1, + ], + ), + ]), + ); + } else if (isVFloat) { + // OPFVV vfadd.vv / vfmul.vv: per-lane FP add or multiply via + // ROHD-HCL units, selected by funct6 (add=0x00, mul=0x24). The + // lane width is SEW-generic from the live vtype.vsew: SEW=32 + // (FP32) and SEW=64 (FP64) always, plus SEW=16 (FP16) when Zvfh + // is configured (see fpLanes below). + final vs1Idx = fields['vs1']!.slice(4, 0); + final vs2Idx = fields['vs2']!.slice(4, 0); + final vdIdx = fields['vd']!.slice(4, 0); + final f6 = fields['funct6']!; + // LMUL grouping (mirrors the integer path): the op spans + // L=1< + (base.zeroExtend(6) + k.zeroExtend(6)).slice(4, 0); + final vs2Reg = regAddr(vs2Idx); + final vs1Reg = regAddr(vs1Idx); + final vdReg = regAddr(vdIdx); + // Elements per register at the live SEW (= VLEN / SEW). + final epr = + (Const(vlen, width: 16) >> + (Const(3, width: 4) + + _vtype!.slice(5, 3).zeroExtend(4))) + .zeroExtend(_vl!.width); + // Per-lane FP add/mul for a given lane width (16, 32 or 64). All + // widths are built and muxed on vsew (16->vsew==1, 32->2, 64->3), + // since ROHD elaborates statically. FloatingPointAdder/Multiplier + // are width-generic over FloatingPoint16/32/64 (Zvfh = SEW=16). + Logic fpLanesW(Logic a, Logic b, bool mul, int laneW) { + final lanes = []; + for (var lo = 0; lo + laneW <= vlen; lo += laneW) { + FloatingPoint mk() => switch (laneW) { + 16 => FloatingPoint16(), + 64 => FloatingPoint64(), + _ => FloatingPoint32(), + }; + final fa = mk(); + fa <= a.slice(lo + laneW - 1, lo); + final fb = mk(); + fb <= b.slice(lo + laneW - 1, lo); + final r = mul + ? FloatingPointMultiplierSimple(fa, fb).product + : FloatingPointAdderSinglePath(fa, fb).sum; + lanes.add([r.sign, r.exponent, r.mantissa].swizzle()); + } + return lanes.reversed.toList().swizzle(); + } + + final vsewF = _vtype!.slice(5, 3); + Logic fpLanes(Logic a, Logic b, bool mul) { + // SEW=32 (single) / SEW=64 (double) are always built. + final base = mux( + vsewF.eq(Const(3, width: 3)), // SEW=64 (double) + fpLanesW(a, b, mul, 64), + fpLanesW(a, b, mul, 32), // default SEW=32 (single) + ); + // SEW=16 (half) lanes only when Zvfh is configured: this is a + // Dart-level gate, so a non-Zvfh core never elaborates the FP16 + // units. Without Zvfh a SEW=16 vfadd falls through to `base` + // (the SEW=32 datapath), which the spec never reaches anyway. + if (!hasZvfh) return base; + return mux( + vsewF.eq( + Const(1, width: 3), + ), // SEW=16 (Zvfh half-precision) + fpLanesW(a, b, mul, 16), + base, + ); + } + + steps.add( + CaseItem(Const(1, width: maxLen.bitLength), [ + vrs1Read!.addr < vs1Reg, + vrs1Read!.en < 1, + vrs2Read!.addr < vs2Reg, + vrs2Read!.en < 1, + mopStep < mopStep + 1, + ]), + ); + final fadd = fpLanes(vrs2Read!.data, vrs1Read!.data, false); + final fmul = fpLanes(vrs2Read!.data, vrs1Read!.data, true); + // Same vl/tail read-modify-write as the integer path: capture + // the FP result, re-read old vd, merge active vs tail. + steps.add( + CaseItem(Const(2, width: maxLen.bitLength), [ + If( + vrs1Read!.done & + vrs1Read!.valid & + vrs2Read!.done & + vrs2Read!.valid, + then: [ + _vtmp! < + mux( + f6.eq(Const(0x24, width: f6.width)), + fmul, + fadd, + ), + vrs2Read!.addr < vdReg, // old vd (1-cycle latency) + vrs2Read!.en < 1, + mopStep < mopStep + 1, + ], + ), + ]), + ); + final fpVsew = _vtype!.slice(5, 3); + // Per-register tail mask: localVl = clamp(vl - k*EPR, 0, EPR). + final fpKEpr = (k.zeroExtend(_vl!.width) * epr).slice( + _vl!.width - 1, + 0, + ); + final fpRemVl = mux( + _vl!.gt(fpKEpr), + _vl! - fpKEpr, + Const(0, width: _vl!.width), + ); + final fpLocalVl = mux(fpRemVl.gt(epr), epr, fpRemVl); + final fpShift = + fpLocalVl << (Const(3, width: 4) + fpVsew.zeroExtend(4)); + final fpOnes = Const(1, width: vlen + 1); + final fpMask = ((fpOnes << fpShift) - fpOnes).slice( + vlen - 1, + 0, + ); + steps.add( + CaseItem(Const(3, width: maxLen.bitLength), [ + vrdWrite!.addr < vdReg, + vrdWrite!.data < + ((_vtmp! & fpMask) | (vrs2Read!.data & ~fpMask)), + vrdWrite!.en < 1, + If( + (k.zeroExtend(5) + Const(1, width: 5)).lt(lmax), + then: [ + _vregIdx! < (k + Const(1, width: 4)), + mopStep < Const(1, width: maxLen.bitLength), + ], + orElse: [ + _vregIdx! < Const(0, width: 4), + nextPc < (currentPc + Const(4, width: mxlen.size)), + mopStep < mopStep + 1, + ], + ), + ]), + ); + } + + for (final mop + in (isVecHandled + ? [] + : op.indexedMicrocode.values)) { + final i = steps.length + 1; + + if (mop is RiscVReadRegister) { + final isFp = fpFields.contains(mop.source); + final addr = + (readField(mop.source, register: false) + + Const(mop.offset, width: mxlen.size)) + .slice(4, 0); + final port = isFp + ? (mop.source == RiscVMicroOpField.rs2 + ? fprs2Read! + : fprs1Read!) + : (mop.source == RiscVMicroOpField.rs2 + ? rs2Read + : rs1Read); + steps.add( + CaseItem(Const(i, width: maxLen.bitLength), [ + // x2/sp shortcut only applies to the integer register + // file; FP reads always go through the port. + if (isFp) ...[ + port.addr < addr, + port.en < 1, + mopStep < mopStep + 1, + ] else + If( + addr.eq(Const(Register.x2.value, width: 5)), + then: [ + writeField(mop.source, currentSp), + mopStep < mopStep + 2, + ], + orElse: [ + port.addr < addr, + port.en < 1, + mopStep < mopStep + 1, + ], + ), + ]), + ); + + // FP read port is FLEN(64)-wide; take the low mxlen bits for + // the mxlen-wide intermediate (no-op on rv64; rv32 F's f32 is + // in the low 32). #71. + final readData = isFp + ? port.data.getRange(0, mxlen.size) + : port.data; + steps.add( + CaseItem(Const(i + 1, width: maxLen.bitLength), [ + writeField( + mop.source, + readData + Const(mop.offset, width: mxlen.size), + ), + If(port.done & port.valid, then: [mopStep < mopStep + 1]), + ]), + ); + } else if (mop is RiscVWriteRegister) { + final isFp = fpFields.contains(mop.dest); + final addr = + (readField(mop.dest, register: false) + + Const(mop.valueOffset, width: mxlen.size)) + .slice(4, 0); + + final value = + (readSource(mop.source) + + Const(mop.valueOffset, width: mxlen.size)); + + final wport = isFp ? fprdWrite! : rdWrite; + // The FP regfile is FLEN(64)-wide but values flow through the + // mxlen-wide intermediate; resize to the write port's width at + // the boundary (no-op on rv64 where mxlen==64). #71. + final wData = isFp ? value.zeroExtend(64) : value; + steps.add( + CaseItem(Const(i, width: maxLen.bitLength), [ + // Mirror sp into nextSp only for integer x2 writes. + if (!isFp) + If( + addr.eq(Const(Register.x2.value, width: 5)), + then: [nextSp < value], + ), + wport.addr < addr, + wport.data < wData, + // FP f0 is a real register (not hardwired zero), so FP + // writes always enable; integer x0 writes are dropped. + wport.en < (isFp ? Const(1) : addr.gt(0)), + mopStep < mopStep + 1, + ]), + ); + } else if (mop is RiscVAlu && + _kIterativeDivRem.contains(mop.funct)) { + // Multi-cycle integer divide/remainder. Hold the shared + // IterativeDivider's start high while this mop is resident, + // feeding it unsigned magnitudes, and commit the sign/edge- + // fixed result when it reports done. This is what removes the + // eight combinational div/rem trees (the static unit's biggest + // LUT cost). div and rem share the same iteration; signed and + // word-width variants differ only in the pre/post fixup here. + final f = mop.funct; + final isW = + f == RiscVAluFunct.divw || + f == RiscVAluFunct.divuw || + f == RiscVAluFunct.remw || + f == RiscVAluFunct.remuw; + final isRem = + f == RiscVAluFunct.rem || + f == RiscVAluFunct.remu || + f == RiscVAluFunct.remw || + f == RiscVAluFunct.remuw; + final isSigned = + f == RiscVAluFunct.div || + f == RiscVAluFunct.divw || + f == RiscVAluFunct.rem || + f == RiscVAluFunct.remw; + final w = isW ? 32 : mxlen.size; + final aOp = isW + ? readField(mop.a).slice(31, 0) + : readField(mop.a); + final bOp = isW + ? readField(mop.b).slice(31, 0) + : readField(mop.b); + // Feed unsigned magnitudes; force the divisor non-zero so the + // core never divides by zero (the fixup overrides the result + // when the original divisor is zero anyway). + final aMag = isSigned ? bmAbs(aOp, w) : aOp; + final bMag = isSigned ? bmAbs(bOp, w) : bOp; + final zw = Const(0, width: w); + final dividend = aMag.zeroExtend(mxlen.size); + final divisor = mux( + bMag.eq(zw), + Const(1, width: w), + bMag, + ).zeroExtend(mxlen.size); + final q = _idiv!.quotient.slice(w - 1, 0); + final r = _idiv!.remainder.slice(w - 1, 0); + final resW = isRem + ? (isSigned + ? remFixupS(aOp, bOp, r, w) + : remFixupU(aOp, bOp, r, w)) + : (isSigned + ? divFixupS(aOp, bOp, q, w) + : divFixupU(aOp, bOp, q, w)); + final result = isW ? resW.signExtend(mxlen.size) : resW; + steps.add( + CaseItem(Const(i, width: maxLen.bitLength), [ + _idivStart! < 1, + _idivDividend! < dividend, + _idivDivisor! < divisor, + If( + _idiv!.done, + then: [ + alu < result, + _idivStart! < 0, + mopStep < mopStep + 1, + ], + ), + ]), + ); + } else if (mop is RiscVAlu) { + steps.add( + CaseItem(Const(i, width: maxLen.bitLength), [ + alu < + (switch (mop.funct) { + RiscVAluFunct.add => + readField(mop.a) + readField(mop.b), + RiscVAluFunct.sub => + readField(mop.a) - readField(mop.b), + RiscVAluFunct.and_ => + readField(mop.a) & readField(mop.b), + RiscVAluFunct.or_ => + readField(mop.a) | readField(mop.b), + RiscVAluFunct.xor_ => + readField(mop.a) ^ readField(mop.b), + // Shift amount is masked to log2(XLEN) bits (so a + // 6-bit RV64 shamt / a shift-imm whose funct6 bits + // leak into the imm field don't over-shift), and srl + // is a *logical* (>>>) right shift. + RiscVAluFunct.sll => + readField(mop.a) << + (readField(mop.b) & + Const(mxlen.size - 1, width: mxlen.size)), + RiscVAluFunct.srl => + readField(mop.a) >>> + (readField(mop.b) & + Const(mxlen.size - 1, width: mxlen.size)), + RiscVAluFunct.sra => + readField(mop.a) >> + (readField(mop.b) & + Const(mxlen.size - 1, width: mxlen.size)), + RiscVAluFunct.slt => bmSignedLt( + readField(mop.a), + readField(mop.b), + mxlen.size, + ).zeroExtend(mxlen.size), + RiscVAluFunct.sltu => readField( + mop.a, + ).lt(readField(mop.b)).zeroExtend(mxlen.size), + // The whole mul family shares one multiplier per + // operand pair (see BmMulSet for the identity). + RiscVAluFunct.mul => _mulSetFor( + (mop.a, mop.b), + readField(mop.a), + readField(mop.b), + mxlen.size, + ).low, + RiscVAluFunct.mulw => _mulSetFor( + (mop.a, mop.b), + readField(mop.a), + readField(mop.b), + mxlen.size, + ).low.slice(31, 0).signExtend(mxlen.size), + RiscVAluFunct.mulh => _mulSetFor( + (mop.a, mop.b), + readField(mop.a), + readField(mop.b), + mxlen.size, + ).highSS, + RiscVAluFunct.mulhsu => _mulSetFor( + (mop.a, mop.b), + readField(mop.a), + readField(mop.b), + mxlen.size, + ).highSU, + RiscVAluFunct.mulhu => _mulSetFor( + (mop.a, mop.b), + readField(mop.a), + readField(mop.b), + mxlen.size, + ).highUU, + // div/rem are handled by the multi-cycle + // IterativeDivider in the branch above + // (_kIterativeDivRem), never this combinational + // switch, so no `/`/`%` tree is elaborated here. + RiscVAluFunct.div || + RiscVAluFunct.divu || + RiscVAluFunct.divw || + RiscVAluFunct.divuw || + RiscVAluFunct.rem || + RiscVAluFunct.remu || + RiscVAluFunct.remw || + RiscVAluFunct.remuw => throw StateError( + 'div/rem (${mop.funct.name}) must use the ' + 'iterative divider path, not the combinational ' + 'ALU switch', + ), + RiscVAluFunct.addw => + (readField(mop.a) + readField(mop.b)) + .slice(31, 0) + .signExtend(mxlen.size), + RiscVAluFunct.subw => + (readField(mop.a) - readField(mop.b)) + .slice(31, 0) + .signExtend(mxlen.size), + RiscVAluFunct.sllw => + (readField(mop.a) << readField(mop.b).slice(4, 0)) + .slice(31, 0) + .signExtend(mxlen.size), + RiscVAluFunct.srlw => + (readField(mop.a).slice(31, 0) >>> + readField(mop.b).slice(4, 0)) + .signExtend(mxlen.size), + RiscVAluFunct.sraw => + (readField(mop.a).slice(31, 0) >> + readField(mop.b).slice(4, 0)) + .signExtend(mxlen.size), + // Zbb/Zba/Zbs/Zicond/Zcb: full set, matching the + // emulator. (w = mxlen.size; helpers above build the + // min/max, rotate, clz/ctz/cpop, orc.b, rev8 HW.) + RiscVAluFunct.andn => + readField(mop.a) & ~readField(mop.b), + RiscVAluFunct.orn => + readField(mop.a) | ~readField(mop.b), + RiscVAluFunct.xnor => + ~(readField(mop.a) ^ readField(mop.b)), + RiscVAluFunct.sextb => readField( + mop.a, + ).slice(7, 0).signExtend(mxlen.size), + RiscVAluFunct.sexth => readField( + mop.a, + ).slice(15, 0).signExtend(mxlen.size), + RiscVAluFunct.zexth => readField( + mop.a, + ).slice(15, 0).zeroExtend(mxlen.size), + RiscVAluFunct.zextb => readField( + mop.a, + ).slice(7, 0).zeroExtend(mxlen.size), + RiscVAluFunct.zextw => readField( + mop.a, + ).slice(31, 0).zeroExtend(mxlen.size), + RiscVAluFunct.notOp => ~readField(mop.a), + RiscVAluFunct.sh1add => + (readField(mop.a) << 1) + readField(mop.b), + RiscVAluFunct.sh2add => + (readField(mop.a) << 2) + readField(mop.b), + RiscVAluFunct.sh3add => + (readField(mop.a) << 3) + readField(mop.b), + // min/max (signed and unsigned) + RiscVAluFunct.minOp => mux( + bmSignedLt( + readField(mop.a), + readField(mop.b), + mxlen.size, + ), + readField(mop.a), + readField(mop.b), + ), + RiscVAluFunct.maxOp => mux( + bmSignedLt( + readField(mop.a), + readField(mop.b), + mxlen.size, + ), + readField(mop.b), + readField(mop.a), + ), + RiscVAluFunct.minuOp => mux( + readField(mop.a).lt(readField(mop.b)), + readField(mop.a), + readField(mop.b), + ), + RiscVAluFunct.maxuOp => mux( + readField(mop.a).lt(readField(mop.b)), + readField(mop.b), + readField(mop.a), + ), + // rotates + RiscVAluFunct.rol => bmRotl( + readField(mop.a), + readField(mop.b), + mxlen.size, + ), + RiscVAluFunct.ror => bmRotr( + readField(mop.a), + readField(mop.b), + mxlen.size, + ), + RiscVAluFunct.rolw => bmRotl( + readField(mop.a).slice(31, 0), + readField(mop.b).slice(31, 0), + 32, + ).signExtend(mxlen.size), + RiscVAluFunct.rorw => bmRotr( + readField(mop.a).slice(31, 0), + readField(mop.b).slice(31, 0), + 32, + ).signExtend(mxlen.size), + // counts + RiscVAluFunct.clz => bmClz( + readField(mop.a), + mxlen.size, + ), + RiscVAluFunct.ctz => bmCtz( + readField(mop.a), + mxlen.size, + ), + RiscVAluFunct.cpop => bmPopcount( + readField(mop.a), + mxlen.size, + ), + RiscVAluFunct.clzw => bmClz( + readField(mop.a).slice(31, 0), + 32, + ).zeroExtend(mxlen.size), + RiscVAluFunct.ctzw => bmCtz( + readField(mop.a).slice(31, 0), + 32, + ).zeroExtend(mxlen.size), + RiscVAluFunct.cpopw => bmPopcount( + readField(mop.a).slice(31, 0), + 32, + ).zeroExtend(mxlen.size), + // byte ops + RiscVAluFunct.orcb => bmOrcb( + readField(mop.a), + mxlen.size, + ), + RiscVAluFunct.rev8 => bmRev8( + readField(mop.a), + mxlen.size, + ), + // Zba unsigned-word shift-add + RiscVAluFunct.adduw => + readField( + mop.a, + ).slice(31, 0).zeroExtend(mxlen.size) + + readField(mop.b), + RiscVAluFunct.sh1adduw => + (readField( + mop.a, + ).slice(31, 0).zeroExtend(mxlen.size) << + 1) + + readField(mop.b), + RiscVAluFunct.sh2adduw => + (readField( + mop.a, + ).slice(31, 0).zeroExtend(mxlen.size) << + 2) + + readField(mop.b), + RiscVAluFunct.sh3adduw => + (readField( + mop.a, + ).slice(31, 0).zeroExtend(mxlen.size) << + 3) + + readField(mop.b), + // Zbs single-bit (shift amount masked to width) + RiscVAluFunct.bset => + readField(mop.a) | + (Const(1, width: mxlen.size) << + (readField(mop.b) & + Const( + mxlen.size - 1, + width: mxlen.size, + ))), + RiscVAluFunct.bclr => + readField(mop.a) & + ~(Const(1, width: mxlen.size) << + (readField(mop.b) & + Const( + mxlen.size - 1, + width: mxlen.size, + ))), + RiscVAluFunct.binv => + readField(mop.a) ^ + (Const(1, width: mxlen.size) << + (readField(mop.b) & + Const( + mxlen.size - 1, + width: mxlen.size, + ))), + RiscVAluFunct.bext => + (readField(mop.a) >>> + (readField(mop.b) & + Const( + mxlen.size - 1, + width: mxlen.size, + ))) & + Const(1, width: mxlen.size), + // Zicond + RiscVAluFunct.czeroEqz => mux( + readField(mop.b).eq(Const(0, width: mxlen.size)), + Const(0, width: mxlen.size), + readField(mop.a), + ), + RiscVAluFunct.czeroNez => mux( + readField(mop.b).eq(Const(0, width: mxlen.size)), + readField(mop.a), + Const(0, width: mxlen.size), + ), + }).named( + 'alu_${op.mnemonic}_${mop.funct.name}_${mop.a.name}_${mop.b.name}', + ), + mopStep < mopStep + 1, + ]), + ); + } else if (mop is RiscVUpdatePc) { + Logic value = Const(mop.offset, width: mxlen.size); + if (mop.offsetField != null) { + value = readField(mop.offsetField!); + } + if (mop.offsetSource != null) { + value = readSource(mop.offsetSource!); + } + if (mop.align) value &= ~Const(1, width: mxlen.size); + + steps.add( + CaseItem(Const(i, width: maxLen.bitLength), [ + nextPc < (mop.absolute ? value : (currentPc + value)), + mopStep < mopStep + 1, + ]), + ); + } else if (mop is RiscVMemLoad) { + final base = readField(mop.base); + final addr = base + imm; + + final unaligned = + (addr & Const(mop.size.bytes - 1, width: mxlen.size)).neq( + 0, + ); + + // Sub-word loads: the memory returns the aligned bus-word, so + // select the addressed lane by shifting right by the byte + // offset before slicing (lb/lbu/lh/lhu and Zcb c.lbu/lhu/lh). + final busBytes = mxlen.size ~/ 8; + final alignedAddr = + addr & ~Const(busBytes - 1, width: mxlen.size); + final byteOff = addr & Const(busBytes - 1, width: mxlen.size); + final shifted = + memRead.data >> (byteOff * Const(8, width: mxlen.size)); + final raw = shifted.slice(mop.size.bits - 1, 0); + + steps.add( + CaseItem(Const(i, width: maxLen.bitLength), [ + If( + unaligned, + then: doTrap( + Trap.misalignedLoad, + addr, + '_${op.mnemonic}', + ), + orElse: [ + memRead.en < 1, + memRead.addr < alignedAddr, + mopStep < mopStep + 1, + ], + ), + ]), + ); + + steps.add( + CaseItem(Const(i + 1, width: maxLen.bitLength), [ + If( + memRead.en & memRead.done & memRead.valid, + then: [ + writeField( + mop.dest, + mop.unsigned + ? raw.zeroExtend(mxlen.size) + : raw.signExtend(mxlen.size), + ), + memRead.en < 0, + mopStep < mopStep + 1, + ], + ), + // dport done & ~valid means the MMU walk faulted, the + // only ~valid source (PMP/physical access faults aren't + // modeled), so it is always a page fault (cause 13/15), + // matching the emulator's mmu.dart. + If( + memRead.en & memRead.done & ~memRead.valid, + then: [ + memRead.en < 0, + // G-stage walk fault -> guest load page fault (21); + // VS/single-stage -> regular load page fault (13). + If( + memFaultGuest ?? Const(0), + then: doTrap( + Trap.loadGuestPageFault, + addr, + '_${op.mnemonic}', + ), + orElse: doTrap( + Trap.loadPageFault, + addr, + '_${op.mnemonic}', + ), + ), + ], + ), + ]), + ); + } else if (mop is RiscVMemStore) { + final base = readField(mop.base); + final value = readField(mop.src); + final addr = base + imm; + + final unaligned = + (addr & Const(mop.size.bytes - 1, width: mxlen.size)).neq( + 0, + ); + + steps.add( + CaseItem(Const(i, width: maxLen.bitLength), [ + If( + unaligned, + then: doTrap( + Trap.misalignedStore, + addr, + '_${op.mnemonic}', + ), + orElse: [ + memWrite.en < 1, + memWrite.addr < addr, + // Size prefix is the byte count (1<> (byteOff * Const(8, width: mxlen.size)); + final raw = shifted.slice(mop.size.bits - 1, 0); + steps.add( + CaseItem(Const(i, width: maxLen.bitLength), [ + If( + unaligned, + then: doTrap( + Trap.misalignedLoad, + addr, + '_${op.mnemonic}', + ), + orElse: [ + memRead.en < 1, + memRead.addr < alignedAddr, + output('memGuest') < 1, + mopStep < mopStep + 1, + ], + ), + ]), + ); + steps.add( + CaseItem(Const(i + 1, width: maxLen.bitLength), [ + output('memGuest') < 1, // hold across the walk + If( + memRead.en & memRead.done & memRead.valid, + then: [ + // HLV's microcode has no trailing WriteRegister, so + // commit the loaded value directly to rd (like AMO). + rdWrite.en < 1, + rdWrite.addr < readField(mop.dest).slice(4, 0), + rdWrite.data < + (mop.unsigned + ? raw.zeroExtend(mxlen.size) + : raw.signExtend(mxlen.size)), + memRead.en < 0, + mopStep < mopStep + 1, + ], + ), + If( + memRead.en & memRead.done & ~memRead.valid, + then: [ + memRead.en < 0, + If( + memFaultGuest ?? Const(0), + then: doTrap( + Trap.loadGuestPageFault, + addr, + '_${op.mnemonic}', + ), + orElse: doTrap( + Trap.loadPageFault, + addr, + '_${op.mnemonic}', + ), + ), + ], + ), + ]), + ); + } else { + final value = readField(mop.dest); // rs2 = store data + steps.add( + CaseItem(Const(i, width: maxLen.bitLength), [ + If( + unaligned, + then: doTrap( + Trap.misalignedStore, + addr, + '_${op.mnemonic}', + ), + orElse: [ + memWrite.en < 1, + memWrite.addr < addr, + memWrite.data < + [ + Const(mop.size.bytes, width: 7), + value, + ].swizzle(), + output('memGuest') < 1, + If( + memWrite.done & memWrite.valid, + then: [memWrite.en < 0, mopStep < mopStep + 1], + ), + If( + memWrite.done & ~memWrite.valid, + then: [ + memWrite.en < 0, + If( + memFaultGuest ?? Const(0), + then: doTrap( + Trap.storeGuestPageFault, + addr, + '_${op.mnemonic}', + ), + orElse: doTrap( + Trap.storePageFault, + addr, + '_${op.mnemonic}', + ), + ), + ], + ), + ], + ), + ]), + ); + } + } else if (mop is RiscVAtomicMemory) { + // AMO: read-modify-write. base=rs1 (addr, no imm), src=rs2, + // dest=rd (gets the sign-extended old value). Three steps: + // issue read, compute+issue write, complete. + final addr = readField(mop.base); + final bits = mop.size.bits; + final raw = memRead.data.slice(bits - 1, 0); + final src = readField(mop.src).slice(bits - 1, 0); + final newVal = (switch (mop.funct) { + RiscVAtomicFunct.add => raw + src, + RiscVAtomicFunct.swap => src, + RiscVAtomicFunct.xor_ => raw ^ src, + RiscVAtomicFunct.and_ => raw & src, + RiscVAtomicFunct.or_ => raw | src, + RiscVAtomicFunct.min => mux( + bmSignedLt(raw, src, bits), + raw, + src, + ), + RiscVAtomicFunct.max => mux( + bmSignedLt(raw, src, bits), + src, + raw, + ), + RiscVAtomicFunct.minu => mux(raw.lt(src), raw, src), + RiscVAtomicFunct.maxu => mux(raw.lt(src), src, raw), + // Zacas amocas: store src (rs2) iff the loaded value equals + // rd's current value; otherwise leave memory unchanged (store + // the loaded value back). rd still receives the loaded value. + // The compare operand is rd's VALUE, not its index: the rd + // latch holds the index (loaded at setup, never read back + // because the shared AMO microcode has no ReadRegister(rd)), + // so source the value over the otherwise-idle rs1 read port + // (its address is the latched rs1, not the port), driven for + // cas below. + RiscVAtomicFunct.cas => mux( + raw.eq(rs1Read.data.slice(bits - 1, 0)), + src, + raw, + ), + }).named('amo_${mop.funct.name}'); + final unaligned = + (addr & Const(mop.size.bytes - 1, width: mxlen.size)).neq( + 0, + ); - if (mop is ReadRegisterMicroOp) { - final addr = - (readField(mop.source) + - Const(mop.offset, width: mxlen.size)) - .slice(4, 0); - final port = mop.source == MicroOpSource.rs2 - ? rs2Read - : rs1Read; steps.add( CaseItem(Const(i, width: maxLen.bitLength), [ If( - addr.eq(Const(Register.x2.value, width: 5)), - then: [ - writeField(mop.source, currentSp), - mopStep < mopStep + 2, - ], + unaligned, + then: doTrap( + Trap.misalignedStore, + addr, + '_${op.mnemonic}', + ), orElse: [ - port.addr < addr, - port.en < 1, + memRead.en < 1, + memRead.addr < addr, + // cas needs rd's VALUE as the compare operand: read it + // over the idle rs1 port (held through the compute step + // below). Harmless for other AMOs, so gate on cas. + if (mop.funct == RiscVAtomicFunct.cas) ...[ + rs1Read.en < 1, + rs1Read.addr < + readField( + mop.dest, + register: false, + ).slice(4, 0), + ], mopStep < mopStep + 1, ], ), @@ -2000,123 +4424,98 @@ class StaticExecutionUnit extends ExecutionUnit { steps.add( CaseItem(Const(i + 1, width: maxLen.bitLength), [ - writeField( - mop.source, - port.data + Const(mop.valueOffset, width: mxlen.size), + If( + memRead.en & memRead.done & memRead.valid, + then: [ + memRead.en < 0, + // Commit the (sign-extended) old value to rd, the AMO + // microcode has no trailing WriteRegister, so drive the + // regfile write port directly (as WriteRegister does). + rdWrite.addr < + readField(mop.dest, register: false).slice(4, 0), + rdWrite.data < raw.signExtend(mxlen.size), + rdWrite.en < + readField( + mop.dest, + register: false, + ).slice(4, 0).gt(0), + // Issue the modified-value store. + memWrite.en < 1, + memWrite.addr < addr, + memWrite.data < + [ + Const(mop.size.bytes, width: 7), + newVal.zeroExtend(mxlen.size), + ].swizzle(), + mopStep < mopStep + 1, + ], + ), + If( + memRead.en & memRead.done & ~memRead.valid, + then: [ + memRead.en < 0, + // G-stage walk fault -> guest load page fault (21); + // VS/single-stage -> regular load page fault (13). + If( + memFaultGuest ?? Const(0), + then: doTrap( + Trap.loadGuestPageFault, + addr, + '_${op.mnemonic}', + ), + orElse: doTrap( + Trap.loadPageFault, + addr, + '_${op.mnemonic}', + ), + ), + ], ), - If(port.done & port.valid, then: [mopStep < mopStep + 1]), ]), ); - } else if (mop is WriteRegisterMicroOp) { - final addr = - (readField(mop.field) + - Const(mop.offset, width: mxlen.size)) - .slice(4, 0); - - final value = - (readSource(mop.source) + - Const(mop.valueOffset, width: mxlen.size)); steps.add( - CaseItem(Const(i, width: maxLen.bitLength), [ + CaseItem(Const(i + 2, width: maxLen.bitLength), [ If( - addr.eq(Const(Register.x2.value, width: 5)), - then: [nextSp < value], + memWrite.done & memWrite.valid, + then: [memWrite.en < 0, mopStep < mopStep + 1], ), - rdWrite.addr < addr, - rdWrite.data < value, - rdWrite.en < addr.gt(0), - mopStep < mopStep + 1, - ]), - ); - } else if (mop is AluMicroOp) { - steps.add( - CaseItem(Const(i, width: maxLen.bitLength), [ - alu < - (switch (mop.alu) { - MicroOpAluFunct.add => - readField(mop.a) + readField(mop.b), - MicroOpAluFunct.sub => - readField(mop.a) - readField(mop.b), - MicroOpAluFunct.and => - readField(mop.a) & readField(mop.b), - MicroOpAluFunct.or => - readField(mop.a) | readField(mop.b), - MicroOpAluFunct.xor => - readField(mop.a) ^ readField(mop.b), - MicroOpAluFunct.sll => - readField(mop.a) << readField(mop.b), - MicroOpAluFunct.srl => - readField(mop.a) >> readField(mop.b), - MicroOpAluFunct.sra => - readField(mop.a) >> readField(mop.b), - MicroOpAluFunct.slt => readField( - mop.a, - ).lte(readField(mop.b)).zeroExtend(mxlen.size), - MicroOpAluFunct.sltu => - (readField(mop.a) - readField(mop.b))[mxlen.size - - 1] - .zeroExtend(mxlen.size), - MicroOpAluFunct.masked => - readField(mop.a) & ~readField(mop.b), - MicroOpAluFunct.mul => - readField(mop.a) * readField(mop.b), - MicroOpAluFunct.mulw => - readField(mop.a) * readField(mop.b), - MicroOpAluFunct.mulh => - readField(mop.a) * readField(mop.b), - MicroOpAluFunct.mulhsu => - readField(mop.a) * readField(mop.b), - MicroOpAluFunct.mulhu => - readField(mop.a) * readField(mop.b), - MicroOpAluFunct.div => - readField(mop.a) / readField(mop.b), - MicroOpAluFunct.divu => - readField(mop.a) / readField(mop.b), - MicroOpAluFunct.divuw => - readField(mop.a) / readField(mop.b), - MicroOpAluFunct.divw => - readField(mop.a) / readField(mop.b), - MicroOpAluFunct.rem => - readField(mop.a) % readField(mop.b), - MicroOpAluFunct.remu => - readField(mop.a) % readField(mop.b), - MicroOpAluFunct.remuw => - readField(mop.a) % readField(mop.b), - MicroOpAluFunct.remw => - readField(mop.a) % readField(mop.b), - _ => throw 'Invalid ALU function ${mop.alu}', - }).named( - 'alu_${op.mnemonic}_${mop.alu.name}_${mop.a.name}_${mop.b.name}', + If( + memWrite.done & ~memWrite.valid, + then: [ + memWrite.en < 0, + // G-stage walk fault -> guest store page fault (23); + // VS/single-stage -> regular store page fault (15). + If( + memFaultGuest ?? Const(0), + then: doTrap( + Trap.storeGuestPageFault, + addr, + '_${op.mnemonic}', + ), + orElse: doTrap( + Trap.storePageFault, + addr, + '_${op.mnemonic}', + ), ), - mopStep < mopStep + 1, - ]), - ); - } else if (mop is UpdatePCMicroOp) { - Logic value = Const(mop.offset, width: mxlen.size); - if (mop.offsetField != null) - value = readField(mop.offsetField!); - if (mop.offsetSource != null) - value = readSource(mop.offsetSource!); - if (mop.align) value &= ~Const(1, width: mxlen.size); - - steps.add( - CaseItem(Const(i, width: maxLen.bitLength), [ - nextPc < (mop.absolute ? value : (currentPc + value)), - mopStep < mopStep + 1, + ], + ), ]), ); - } else if (mop is MemLoadMicroOp) { - final base = readField(mop.base); - final addr = base + imm; - + } else if (mop is RiscVLoadReserved) { + // LR: load + set the address reservation. + final addr = readField(mop.base); + final bits = mop.size.bits; + final raw = memRead.data.slice(bits - 1, 0); + final rdIdx = readField( + mop.dest, + register: false, + ).slice(4, 0); final unaligned = (addr & Const(mop.size.bytes - 1, width: mxlen.size)).neq( 0, ); - - final raw = memRead.data.slice(mop.size.bits - 1, 0); - steps.add( CaseItem(Const(i, width: maxLen.bitLength), [ If( @@ -2134,37 +4533,57 @@ class StaticExecutionUnit extends ExecutionUnit { ), ]), ); - steps.add( CaseItem(Const(i + 1, width: maxLen.bitLength), [ If( memRead.en & memRead.done & memRead.valid, then: [ - writeField( - mop.dest, - mop.unsigned - ? raw.zeroExtend(mxlen.size) - : raw.signExtend(mxlen.size), - ), + memRead.en < 0, + rdWrite.addr < rdIdx, + rdWrite.data < raw.signExtend(mxlen.size), + rdWrite.en < rdIdx.gt(0), + reservationValid < 1, + reservationAddr < addr, mopStep < mopStep + 1, ], ), If( memRead.en & memRead.done & ~memRead.valid, - then: doTrap(Trap.loadAccess, addr, '_${op.mnemonic}'), + then: [ + memRead.en < 0, + // G-stage walk fault -> guest load page fault (21); + // VS/single-stage -> regular load page fault (13). + If( + memFaultGuest ?? Const(0), + then: doTrap( + Trap.loadGuestPageFault, + addr, + '_${op.mnemonic}', + ), + orElse: doTrap( + Trap.loadPageFault, + addr, + '_${op.mnemonic}', + ), + ), + ], ), ]), ); - } else if (mop is MemStoreMicroOp) { - final base = readField(mop.base); + } else if (mop is RiscVStoreConditional) { + // SC: store iff the reservation is still valid for this addr; + // rd=0 on success, 1 on failure. Always clears the reservation. + final addr = readField(mop.base); final value = readField(mop.src); - final addr = base + imm; - + final rdIdx = readField( + mop.dest, + register: false, + ).slice(4, 0); final unaligned = (addr & Const(mop.size.bytes - 1, width: mxlen.size)).neq( 0, ); - + final hit = reservationValid & reservationAddr.eq(addr); steps.add( CaseItem(Const(i, width: maxLen.bitLength), [ If( @@ -2175,126 +4594,483 @@ class StaticExecutionUnit extends ExecutionUnit { '_${op.mnemonic}', ), orElse: [ - memWrite.en < 1, - memWrite.addr < addr, - memWrite.data < - [Const(mop.size.bits, width: 7), value].swizzle(), - If( - memWrite.done & memWrite.valid, - then: [memWrite.en < 0, mopStep < mopStep + 1], - ), + reservationValid < 0, If( - memWrite.done & ~memWrite.valid, + hit, then: [ - memWrite.en < 0, - ...doTrap( - Trap.storeAccess, - addr, - '_${op.mnemonic}', - ), + memWrite.en < 1, + memWrite.addr < addr, + // Byte-count size prefix (see RiscVMemStore). + memWrite.data < + [ + Const(mop.size.bytes, width: 7), + value, + ].swizzle(), + mopStep < mopStep + 1, + ], + orElse: [ + rdWrite.addr < rdIdx, + rdWrite.data < Const(1, width: mxlen.size), + rdWrite.en < rdIdx.gt(0), + mopStep < mopStep + 2, ], ), ], ), ]), ); - } else if (mop is TrapMicroOp) { - final kindMachine = mop.kindMachine; - final kindSupervisor = mop.kindSupervisor ?? kindMachine; - final kindUser = mop.kindUser ?? kindSupervisor; - - Logic computeKind( - PrivilegeMode expectedMode, - Logic a, - Logic b, [ - Logic? fallback, - ]) { - final value = a == b - ? a - : mux( - currentMode.eq(Const(expectedMode.id, width: 3)), - a, - b, - ); - return switch (expectedMode) { - PrivilegeMode.machine => value, - PrivilegeMode.supervisor => - hasSupervisor ? value : (fallback ?? b), - PrivilegeMode.user => hasUser ? value : (fallback ?? b), - }; - } - steps.add( - CaseItem( - Const(i, width: maxLen.bitLength), - rawTrap( - computeKind( - PrivilegeMode.machine, - Const(kindMachine.interrupt), - computeKind( - PrivilegeMode.supervisor, - Const(kindSupervisor.interrupt), - computeKind( - PrivilegeMode.user, - Const(kindUser.interrupt), - Const(kindMachine.interrupt), + CaseItem(Const(i + 1, width: maxLen.bitLength), [ + If( + memWrite.done & memWrite.valid, + then: [ + memWrite.en < 0, + rdWrite.addr < rdIdx, + rdWrite.data < Const(0, width: mxlen.size), + rdWrite.en < rdIdx.gt(0), + mopStep < mopStep + 1, + ], + ), + If( + memWrite.done & ~memWrite.valid, + then: [ + memWrite.en < 0, + // G-stage walk fault -> guest store page fault (23); + // VS/single-stage -> regular store page fault (15). + If( + memFaultGuest ?? Const(0), + then: doTrap( + Trap.storeGuestPageFault, + addr, + '_${op.mnemonic}', + ), + orElse: doTrap( + Trap.storePageFault, + addr, + '_${op.mnemonic}', ), - Const(kindMachine.interrupt), + ), + ], + ), + ]), + ); + } else if (mop is RiscVFpuOp) { + // FP compute. Operands are in the rs1/rs2 latches (read + // FP-routed); the trailing WriteRegister commits rd per + // fpFields. fadd/sub/mul/sqrt use ROHD-HCL units; fcvt uses + // FixedToFloat/FloatToFixed/FloatingPointConverter; feq/flt/fle + // a manual comparator; fdiv a multi-cycle Newton-Raphson FSM. + if (mop.funct == RiscVFpuFunct.fdiv) { + // Multi-cycle Newton-Raphson divide: stay resident at this + // mopStep, sequencing _divStep 0..9 (seed, 4 iters of two + // phases, final a*x), then write a/b and advance. The reused + // multiplier/adder are selected combinationally by _divStep. + final dp = mop.doublePrecision; + final seed = dp ? _divSeedD! : _divSeedS!.zeroExtend(64); + final mulOut = dp + ? _divMulOutD! + : _divMulOutS!.zeroExtend(64); + final resultBits = dp + ? _divMulOutD! + : _divMulOutS!.zeroExtend(mxlen.size); + steps.add( + CaseItem(Const(i, width: maxLen.bitLength), [ + Case(_divStep!, [ + CaseItem(Const(0, width: 4), [ + _recip! < seed, + _divStep! < Const(1, width: 4), + ]), + for (var sIdx = 1; sIdx <= 8; sIdx++) + CaseItem(Const(sIdx, width: 4), [ + (sIdx.isOdd ? _divT! : _recip!) < mulOut, + _divStep! < Const(sIdx + 1, width: 4), + ]), + CaseItem(Const(9, width: 4), [ + writeField(mop.dest, resultBits), + _divStep! < Const(0, width: 4), + mopStep < mopStep + 1, + ]), + ]), + ]), + ); + } else { + // FP compares (feq/flt/fle) write a 0/1 to an integer reg; + // computed manually since ROHD-HCL has no FP comparator. + final aOp = mop.doublePrecision ? rs1 : rs1.slice(31, 0); + final bOp = mop.doublePrecision ? rs2 : rs2.slice(31, 0); + final cmp = fpCompare( + aOp, + bOp, + mop.doublePrecision ? 64 : 32, + mop.doublePrecision ? 11 : 8, + ); + final cmpEq = (cmp.ordered & cmp.eq).zeroExtend(mxlen.size); + final cmpLt = (cmp.ordered & cmp.lt).zeroExtend(mxlen.size); + final cmpLe = (cmp.ordered & (cmp.lt | cmp.eq)).zeroExtend( + mxlen.size, + ); + + // Bit-level FP ops (sign-inject, min/max, classify), + // combinational, matching the emulator's RiscVFpuFunct + // semantics. min/max select the raw bit pattern using the + // same ordered compare the emulator's `ab` uses + // (NaN compares false → returns the second operand). + final w = mop.doublePrecision ? 64 : 32; + final manBits = mop.doublePrecision ? 52 : 23; + final aF = rs1.slice(w - 1, 0); + final bF = rs2.slice(w - 1, 0); + final signF = Const(1, width: w) << (w - 1); + final magMask = ~signF; + final fsgnj = (aF & magMask) | (bF & signF); + final fsgnjn = (aF & magMask) | ((~bF) & signF); + final fsgnjx = (aF & magMask) | ((aF ^ bF) & signF); + final ltOrdered = cmp.ordered & cmp.lt; + final gtOrdered = cmp.ordered & ~(cmp.lt | cmp.eq); + final fmin = mux(ltOrdered, aF, bF); + final fmax = mux(gtOrdered, aF, bF); + // fclass: 10-bit classification of operand a. + final expF = aF.slice(w - 2, manBits); + final manF = aF.slice(manBits - 1, 0); + final signBit = aF[w - 1]; + final expAll1 = expF.eq( + Const( + (1 << (w - 1 - manBits)) - 1, + width: w - 1 - manBits, + ), + ); + final exp0 = ~expF.or(); + final man0 = ~manF.or(); + final isInf = expAll1 & man0; + final isNaN = expAll1 & ~man0; + final isQNaN = isNaN & manF[manBits - 1]; + final isSNaN = isNaN & ~manF[manBits - 1]; + final isZero = exp0 & man0; + final isSub = exp0 & ~man0; + final isNorm = ~expAll1 & ~exp0; + // fcvt width/sign select: rs2 bit1 = 64-bit (L) vs 32-bit + // (W), rs2 bit0 = unsigned vs signed (decoder ignores rs2 + // otherwise). cvtSel picks among {w, wu, l, lu}. + final cvtIsL = fields['rs2']![1]; + final cvtUns = fields['rs2']![0]; + Logic cvtSel(Logic wv, Logic wu, Logic lv, Logic lu) => + mux(cvtIsL, mux(cvtUns, lu, lv), mux(cvtUns, wu, wv)); + // fp -> int with per-rm rounding + RISC-V saturation. magP is + // the Q64.fracW magnitude of |operand| (lossless); ovf flags + // |operand| >= 2^64. Reads rs2 (W/L, signed/unsigned) and + // funct3 (rm; DYN=7 -> RNE, matching the emulator). Replaces + // the per-variant cvtSel for fp->int. + final ones64 = Const( + BigInt.parse('FFFFFFFFFFFFFFFF', radix: 16), + width: 64, + ); + Logic roundSatFpToInt(Logic magP, Logic ovf, int fracW) { + final intMag = magP.slice(fracW + 63, fracW); + final roundBit = magP[fracW - 1]; + final sticky = magP.slice(fracW - 2, 0).or(); + final rm = fields['funct3']!; + final rne = roundBit & (sticky | intMag[0]); + final rdn = signBit & (roundBit | sticky); + final rup = ~signBit & (roundBit | sticky); + final roundUp = mux( + rm.eq(Const(1, width: 3)), // RTZ + Const(0), + mux( + rm.eq(Const(2, width: 3)), // RDN + rdn, + mux( + rm.eq(Const(3, width: 3)), // RUP + rup, + mux(rm.eq(Const(4, width: 3)), roundBit, rne), ), ), - computeKind( - PrivilegeMode.machine, - Const(kindMachine.mcauseCode, width: 6), - computeKind( - PrivilegeMode.supervisor, - Const(kindSupervisor.mcauseCode, width: 6), - computeKind( - PrivilegeMode.user, - Const(kindUser.mcauseCode, width: 6), - Const(kindMachine.mcauseCode, width: 6), - ), - Const(kindMachine.mcauseCode, width: 6), + ); + final rounded = + (intMag.zeroExtend(65) + roundUp.zeroExtend(65)) + .slice(64, 0); + final magOvf = ovf | rounded[64]; + final rMag = rounded.slice(63, 0); + final neg = (~rMag + Const(1, width: 64)).slice(63, 0); + final isL = fields['rs2']![1]; + final uns = fields['rs2']![0]; + final special = isNaN | isInf; + // W signed (sign-extended to xlen) + final wsPos = mux( + magOvf | rMag.gt(Const(0x7FFFFFFF, width: 64)), + Const(0x7FFFFFFF, width: 32), + rMag.slice(31, 0), + ); + final wsNeg = mux( + magOvf | rMag.gt(Const(0x80000000, width: 64)), + Const(0x80000000, width: 32), + neg.slice(31, 0), + ); + final ws = mux( + special, + mux( + isNaN, + Const(0x7FFFFFFF, width: 32), + mux( + signBit, + Const(0x80000000, width: 32), + Const(0x7FFFFFFF, width: 32), ), ), + mux(signBit, wsNeg, wsPos), + ).signExtend(mxlen.size); + // W unsigned (sign-extended to xlen) + final wuPos = mux( + magOvf | rMag.gt(Const(0xFFFFFFFF, width: 64)), + Const(0xFFFFFFFF, width: 32), + rMag.slice(31, 0), + ); + final wu = mux( + special, + mux( + isNaN | (isInf & ~signBit), + Const(0xFFFFFFFF, width: 32), + Const(0, width: 32), + ), + mux(signBit, Const(0, width: 32), wuPos), + ).signExtend(mxlen.size); + // L signed + final c63 = Const( + BigInt.parse('7FFFFFFFFFFFFFFF', radix: 16), + width: 64, + ); + final c63n = Const( + BigInt.parse('8000000000000000', radix: 16), + width: 64, + ); + final lsPos = mux(magOvf | rMag.gt(c63), c63, rMag); + final lsNeg = mux(magOvf | rMag.gt(c63n), c63n, neg); + final ls = mux( + special, + mux(isNaN, c63, mux(signBit, c63n, c63)), + mux(signBit, lsNeg, lsPos), + ); + // L unsigned + final lu = mux( + special, + mux( + isNaN | (isInf & ~signBit), + ones64, + Const(0, width: 64), + ), + mux( + signBit, + Const(0, width: 64), + mux(magOvf, ones64, rMag), + ), + ); + // ws/wu are mxlen-wide; ls/lu are 64 (the L=fcvt.l.* form + // is rv64-only, dead on rv32). Coerce the L side to mxlen so + // the W/L mux is uniform width (no-op on rv64). #71. + return mux( + isL, + mux(uns, lu, ls).getRange(0, mxlen.size), + mux(uns, wu, ws), + ); + } + + final fclassBits = [ + isQNaN, + isSNaN, + ~signBit & isInf, + ~signBit & isNorm, + ~signBit & isSub, + ~signBit & isZero, + signBit & isZero, + signBit & isSub, + signBit & isNorm, + signBit & isInf, + ].swizzle().zeroExtend(mxlen.size); + + // Coerce a result arm to mxlen so the switch builds with a + // uniform width. The double-conversion arms produce FLEN=64 + // values that are DEAD in the single-precision path (a single + // op never has those functs) but still elaborate; on rv32 that + // 64-bit width clashed with the 32-bit single arms (#71). + Logic fitM(Logic x) => x.width == mxlen.size + ? x + : (x.width > mxlen.size + ? x.getRange(0, mxlen.size) + : x.zeroExtend(mxlen.size)); + final Logic result; + if (!mop.doublePrecision) { + result = switch (mop.funct) { + RiscVFpuFunct.fadd => _fpAddS!.zeroExtend(mxlen.size), + RiscVFpuFunct.fsub => _fpSubS!.zeroExtend(mxlen.size), + RiscVFpuFunct.fmul => _fpMulS!.zeroExtend(mxlen.size), + RiscVFpuFunct.fsqrt => _fpSqrtS!.zeroExtend(mxlen.size), + RiscVFpuFunct.fmadd => _fmaddS!.zeroExtend(mxlen.size), + RiscVFpuFunct.fmsub => _fmsubS!.zeroExtend(mxlen.size), + RiscVFpuFunct.fnmsub => _fnmsubS!.zeroExtend( + mxlen.size, + ), + RiscVFpuFunct.fnmadd => _fnmaddS!.zeroExtend( + mxlen.size, + ), + RiscVFpuFunct.feq => fitM(cmpEq), + RiscVFpuFunct.flt => fitM(cmpLt), + RiscVFpuFunct.fle => fitM(cmpLe), + RiscVFpuFunct.fcvtWS => fitM( + roundSatFpToInt(_cvtMagS!, _cvtOvfS!, 24), + ), + RiscVFpuFunct.fcvtSW => cvtSel( + _fcvtSW!.zeroExtend(mxlen.size), + _fcvtSWu!.zeroExtend(mxlen.size), + _fcvtSL!.zeroExtend(mxlen.size), + _fcvtSLu!.zeroExtend(mxlen.size), + ), + RiscVFpuFunct.fcvtWD => fitM( + roundSatFpToInt(_cvtMagD!, _cvtOvfD!, 53), + ), + RiscVFpuFunct.fcvtDW => fitM( + cvtSel(_fcvtDW!, _fcvtDWu!, _fcvtDL!, _fcvtDLu!), + ), + RiscVFpuFunct.fcvtSD => fitM(_fcvtSD!), + RiscVFpuFunct.fcvtDS => fitM(_fcvtDS!), + RiscVFpuFunct.fsgnj => fsgnj.zeroExtend(mxlen.size), + RiscVFpuFunct.fsgnjn => fsgnjn.zeroExtend(mxlen.size), + RiscVFpuFunct.fsgnjx => fsgnjx.zeroExtend(mxlen.size), + RiscVFpuFunct.fmin => fmin.zeroExtend(mxlen.size), + RiscVFpuFunct.fmax => fmax.zeroExtend(mxlen.size), + RiscVFpuFunct.fclass => fclassBits, + _ => readField(mop.a), + }; + } else { + result = switch (mop.funct) { + RiscVFpuFunct.fadd => _fpAddD!, + RiscVFpuFunct.fsub => _fpSubD!, + RiscVFpuFunct.fmul => _fpMulD!, + RiscVFpuFunct.fsqrt => _fpSqrtD!, + RiscVFpuFunct.fmadd => _fmaddD!, + RiscVFpuFunct.fmsub => _fmsubD!, + RiscVFpuFunct.fnmsub => _fnmsubD!, + RiscVFpuFunct.fnmadd => _fnmaddD!, + RiscVFpuFunct.feq => cmpEq, + RiscVFpuFunct.flt => cmpLt, + RiscVFpuFunct.fle => cmpLe, + RiscVFpuFunct.fcvtWS => roundSatFpToInt( + _cvtMagS!, + _cvtOvfS!, + 24, + ), + RiscVFpuFunct.fcvtSW => cvtSel( + _fcvtSW!.zeroExtend(mxlen.size), + _fcvtSWu!.zeroExtend(mxlen.size), + _fcvtSL!.zeroExtend(mxlen.size), + _fcvtSLu!.zeroExtend(mxlen.size), + ), + RiscVFpuFunct.fcvtWD => roundSatFpToInt( + _cvtMagD!, + _cvtOvfD!, + 53, + ), + RiscVFpuFunct.fcvtDW => cvtSel( + _fcvtDW!, + _fcvtDWu!, + _fcvtDL!, + _fcvtDLu!, + ), + RiscVFpuFunct.fcvtSD => _fcvtSD!, + RiscVFpuFunct.fcvtDS => _fcvtDS!, + RiscVFpuFunct.fsgnj => fsgnj, + RiscVFpuFunct.fsgnjn => fsgnjn, + RiscVFpuFunct.fsgnjx => fsgnjx, + RiscVFpuFunct.fmin => fmin, + RiscVFpuFunct.fmax => fmax, + RiscVFpuFunct.fclass => fclassBits, + _ => readField(mop.a), + }; + } + steps.add( + CaseItem(Const(i, width: maxLen.bitLength), [ + writeField(mop.dest, result), + mopStep < mopStep + 1, + ]), + ); + } + } else if (mop is RiscVTrapOp) { + // ECALL's cause depends on the originating privilege/virt: + // U/VU=8, HS=9, VS=10, M=11. (ebreak and the rest keep their + // fixed cause.) Harbor's microcode hardcodes 8. + final isEcall = !mop.isInterrupt && mop.causeCode == 8; + final causeCode = isEcall + ? mux( + currentMode.eq( + Const(PrivilegeMode.machine.id, width: 3), + ), + Const(11, width: 6), + mux( + currentMode.eq( + Const(PrivilegeMode.supervisor.id, width: 3), + ), + mux( + virtIn ?? Const(0), + Const(10, width: 6), + Const(9, width: 6), + ), + Const(8, width: 6), + ), + ) + : Const(mop.causeCode, width: 6); + steps.add( + CaseItem( + Const(i, width: maxLen.bitLength), + rawTrap( + Const(mop.isInterrupt ? 1 : 0), + causeCode, null, '_${op.mnemonic}', ), ), ); - } else if (mop is BranchIfMicroOp) { - final target = readSource(mop.target); - + } else if (mop is RiscVBranch) { final value = mop.offsetField != null ? readField(mop.offsetField!) : Const(mop.offset, width: mxlen.size); + // Compare the two source registers directly. ROHD `.lt`/`.gte` + // are UNSIGNED, so the old sign-of-difference test (target.lt(0)) + // was always false and broke blt/bge/bltu/bgeu. Signed needs + // bmSignedLt; unsigned needs a real unsigned compare. Mirrors + // fu_branch.dart. + final lhs = readField(RiscVMicroOpField.rs1); + final rhs = readField(RiscVMicroOpField.rs2); final condition = switch (mop.condition) { - MicroOpCondition.eq => target.eq(0), - MicroOpCondition.ne => target.neq(0), - MicroOpCondition.lt => target.lt(0), - MicroOpCondition.gt => target.gt(0), - MicroOpCondition.ge => target.gte(0), - MicroOpCondition.le => target.lte(0), + RiscVBranchCondition.eq => lhs.eq(rhs), + RiscVBranchCondition.ne => lhs.neq(rhs), + RiscVBranchCondition.lt => bmSignedLt(lhs, rhs, mxlen.size), + RiscVBranchCondition.ge => ~bmSignedLt( + lhs, + rhs, + mxlen.size, + ), + RiscVBranchCondition.ltu => lhs.lt(rhs), + RiscVBranchCondition.geu => ~lhs.lt(rhs), }; steps.add( CaseItem(Const(i, width: maxLen.bitLength), [ If( condition, - then: [nextPc < value, done < 1, valid < 1], + // Taken: target is PC-RELATIVE (pc + offset). `value` is + // the offset alone; omitting `currentPc +` collapsed the + // target to the offset (the in-order taken-branch wedge, + // #69). Jumps already do currentPc + value. + then: [ + nextPc < (currentPc + value), + done < 1, + valid < 1, + ], orElse: [mopStep < mopStep + 1], ), ]), ); - } else if (mop is WriteLinkRegisterMicroOp) { + } else if (mop is RiscVWriteLinkRegister) { final value = nextPc + Const(mop.pcOffset, width: mxlen.size); - - Logic reg = Const(Register.x0.value, width: 5); - if (mop.link.reg != null) { - reg = Const(mop.link.reg!.value, width: 5); - } else if (mop.link.source != null) { - reg = readSource(mop.link.source!); - } + final reg = readField(mop.dest).slice(4, 0); steps.add( CaseItem(Const(i, width: maxLen.bitLength), [ @@ -2309,7 +5085,7 @@ class StaticExecutionUnit extends ExecutionUnit { mopStep < mopStep + 1, ]), ); - } else if (mop is FenceMicroOp) { + } else if (mop is RiscVFenceOp) { steps.add( CaseItem(Const(i, width: maxLen.bitLength), [ rs1Read.en < 0, @@ -2323,66 +5099,59 @@ class StaticExecutionUnit extends ExecutionUnit { mopStep < mopStep + 1, ]), ); - } else if (mop is ValidateFieldMicroOp) { - final field = readField(mop.field); - final value = Const(mop.value, width: mxlen.size); - - final condition = switch (mop.condition) { - MicroOpCondition.eq => field.eq(value), - MicroOpCondition.ne => field.neq(value), - MicroOpCondition.lt => field.lt(value), - MicroOpCondition.gt => field.gt(value), - MicroOpCondition.ge => field.gte(value), - MicroOpCondition.le => field.lte(value), - _ => throw 'Invalid condition: ${mop.condition}', - }; - - steps.add( - CaseItem(Const(i, width: maxLen.bitLength), [ - If( - condition, - then: [mopStep < mopStep + 1], - orElse: doTrap(Trap.illegal, null, '_${op.mnemonic}'), - ), - ]), - ); - } else if (mop is ModifyLatchMicroOp) { + } else if (mop is RiscVInterruptHold) { steps.add( CaseItem(Const(i, width: maxLen.bitLength), [ - if (mop.replace) - writeField(mop.field, readSource(mop.source)) - else - clearField(mop.field), + interruptHold < 1, mopStep < mopStep + 1, ]), ); - } else if (mop is SetFieldMicroOp) { + } else if (mop is RiscVCopyField) { steps.add( CaseItem(Const(i, width: maxLen.bitLength), [ - writeField( - mop.field, - Const(mop.value, width: mxlen.size), - ), + writeField(mop.dest, readField(mop.src)), mopStep < mopStep + 1, ]), ); - } else if (mop is InterruptHoldMicroOp) { + } else if (mop is RiscVSetField) { steps.add( CaseItem(Const(i, width: maxLen.bitLength), [ - interruptHold < 1, + writeField(mop.dest, readSource(mop.src)), mopStep < mopStep + 1, ]), ); - } else if (mop is ReadCsrMicroOp && csrRead != null) { + } else if (mop is RiscVReadCsr && csrRead != null) { + final rdCsrAddr = readField(mop.source).slice(11, 0); + // VS-mode access to an HS-only hypervisor CSR (addr[11:8]==0x6, + // the 0x6xx range), OR a VS-mode sstateen access that mstateen + // allows but hstateen0.SE0 blocks, raises a virtual-instruction + // exception (mstateen-blocked is illegal, handled by the CSR + // legality path). + final rdVViol = + ((virtIn ?? Const(0)) & + rdCsrAddr.slice(11, 8).eq(Const(0x6, width: 4))) | + _stateenVsViol(rdCsrAddr); steps.add( CaseItem(Const(i, width: maxLen.bitLength), [ If( - currentMode.eq(Const(PrivilegeMode.user.id, width: 3)), - then: doTrap(Trap.illegal, null, '_${op.mnemonic}'), + rdVViol, + then: doTrap( + Trap.virtualInstruction, + null, + '_${op.mnemonic}', + ), orElse: [ - csrRead.en < 1, - csrRead.addr < readField(mop.source).slice(11, 0), - mopStep < mopStep + 1, + If( + currentMode.eq( + Const(PrivilegeMode.user.id, width: 3), + ), + then: doTrap(Trap.illegal, null, '_${op.mnemonic}'), + orElse: [ + csrRead.en < 1, + csrRead.addr < rdCsrAddr, + mopStep < mopStep + 1, + ], + ), ], ), ]), @@ -2402,17 +5171,46 @@ class StaticExecutionUnit extends ExecutionUnit { ]), ]), ); - } else if (mop is WriteCsrMicroOp && csrWrite != null) { + } else if (mop is RiscVWriteCsr && csrWrite != null) { + final wrCsrAddr = readField(mop.dest).slice(11, 0); + // csrrs/csrrc with rs1=x0 (and csrr*i with uimm=0) must NOT + // write the CSR and must NOT trap on a read-only CSR. funct3[1] + // marks the set/clear forms (RS/RC/RSI/RCI); instr[19:15] (the + // rs1 / uimm field) == 0 is the no-write case. The write still + // fires harmlessly on a writable CSR (unchanged value); only + // the read-only trap (valid=0) must be suppressed. + final csrNoWrite = + (fields['funct3']![1] & + fields['rs1']!.eq( + Const(0, width: fields['rs1']!.width), + )) + .named('csrNoWrite_${op.mnemonic}'); + final wrVViol = + ((virtIn ?? Const(0)) & + wrCsrAddr.slice(11, 8).eq(Const(0x6, width: 4))) | + _stateenVsViol(wrCsrAddr); steps.add( CaseItem(Const(i, width: maxLen.bitLength), [ If( - currentMode.eq(Const(PrivilegeMode.user.id, width: 3)), - then: doTrap(Trap.illegal, null, '_${op.mnemonic}'), + wrVViol, + then: doTrap( + Trap.virtualInstruction, + null, + '_${op.mnemonic}', + ), orElse: [ - csrWrite.en < 1, - csrWrite.addr < readField(mop.field).slice(11, 0), - csrWrite.data < readSource(mop.source), - mopStep < mopStep + 1, + If( + currentMode.eq( + Const(PrivilegeMode.user.id, width: 3), + ), + then: doTrap(Trap.illegal, null, '_${op.mnemonic}'), + orElse: [ + csrWrite.en < 1, + csrWrite.addr < wrCsrAddr, + csrWrite.data < readSource(mop.source), + mopStep < mopStep + 1, + ], + ), ], ), ]), @@ -2424,19 +5222,56 @@ class StaticExecutionUnit extends ExecutionUnit { Iff(csrWrite.en & csrWrite.done & csrWrite.valid, [ mopStep < mopStep + 1, ]), + // Read-only CSR via csrrs/csrrc x0 (csrr*i 0): no trap, + // just complete (the read already delivered rd). + Iff( + csrWrite.en & + csrWrite.done & + ~csrWrite.valid & + csrNoWrite, + [mopStep < mopStep + 1], + ), Iff( - csrWrite.en & csrWrite.done & ~csrWrite.valid, + csrWrite.en & + csrWrite.done & + ~csrWrite.valid & + ~csrNoWrite, doTrap(Trap.illegal, null, '_${op.mnemonic}'), ), ]), ]), ); - } else if (mop is TlbFenceMicroOp) { - // TODO: once MMU has a TLB - } else if (mop is TlbInvalidateMicroOp) { + } else if (mop is RiscVReturnOp) { + // MRET (privilegeLevel 3) / SRET (1). Terminal single-step: + // signal the return; core.dart restores PC←{m,s}epc and + // mode←{m,s}status.xPP and pops the status stack. + steps.add( + CaseItem(Const(i, width: maxLen.bitLength), [ + output('isReturn') < 1, + output('returnLevel') < + Const(mop.privilegeLevel, width: 3), + done < 1, + valid < 1, + ]), + ); + } else if (mop is RiscVTlbFenceOp) { + // sfence.vma: pulse fence -> MMU fetch-TLB flush (see static + // path). Over-flushes the icache harmlessly. + steps.add( + CaseItem(Const(i, width: maxLen.bitLength), [ + fence < 1, + mopStep < mopStep + 1, + ]), + ); + } else if (mop is RiscVTlbInvalidateOp) { // TODO: once MMU has a TLB } else { - print(mop); + // Unhandled micro-op, generate a no-op step that advances + steps.add( + CaseItem(Const(steps.length + 1, width: maxLen.bitLength), [ + mopStep < mopStep + 1, + ]), + ); } } diff --git a/packages/river_hdl/lib/src/core/fetcher.dart b/packages/river_hdl/lib/src/core/fetcher.dart index a4a7a9d..3006996 100644 --- a/packages/river_hdl/lib/src/core/fetcher.dart +++ b/packages/river_hdl/lib/src/core/fetcher.dart @@ -1,6 +1,20 @@ import 'package:rohd/rohd.dart'; -import 'package:rohd_hcl/rohd_hcl.dart'; +import '../data_port.dart'; +/// Fetches one instruction from memory, transparently handling the RISC-V "C" +/// (compressed) extension for both 32-bit and 64-bit memory interfaces. +/// +/// An aligned memory word holds `dataWidth/16` instruction halfwords. The PC may +/// point at any 2-byte halfword within (or, for a 32-bit instruction, spanning) +/// that word, so the unit: +/// * selects the halfword at the PC's offset (`pc[log2(words)-1:1]`), +/// * treats it as a 16-bit instruction when `bits[1:0] != 0b11`, otherwise +/// * forms a 32-bit instruction from this halfword and the next one, issuing +/// a second aligned read when the 32-bit instruction straddles the word +/// boundary (its upper half lives in the following memory word). +/// +/// This is width-general: 32-bit memory has 2 halfwords/word (straddle when the +/// PC is at the high halfword), 64-bit memory has 4 (straddle at the top one). class FetchUnit extends Module { final bool hasCompressed; @@ -9,6 +23,16 @@ class FetchUnit extends Module { Logic get compressed => output('compressed'); Logic get result => output('result'); + /// PC of the instruction currently being delivered (the latched fetch PC). + /// In speculative mode this is the fetcher's self-sequenced PC, which the + /// front-end uses as the instruction's PC instead of the (commit-paced) arch + /// PC. + Logic get pcOut => output('pc_out'); + + /// Asserted with done & ~valid when the delivered fetch faulted (instruction + /// page fault). The pipeline traps to instructionPageFault at [pcOut]. + Logic get fetchFault => output('fetch_fault'); + FetchUnit( Logic clk, Logic reset, @@ -16,6 +40,14 @@ class FetchUnit extends Module { Logic pc, DataPortInterface memRead, { this.hasCompressed = false, + Logic? advance, + Logic? redirect, + Logic? redirectPc, + Logic? stride, + // The fetch port's page-fault signal (asserted with done & ~valid when an + // instruction-fetch translation faults). When wired, a faulting read is + // delivered as done & ~valid with `fetch_fault` set instead of retried. + Logic? fault, super.name = 'river_fetch_unit', }) { clk = addInput('clk', clk); @@ -23,6 +55,27 @@ class FetchUnit extends Module { enable = addInput('enable', enable); pc = addInput('pc', pc, width: pc.width); + // Speculative-fetch controls (default tied off → classic lockstep fetch, + // where the unit holds the fetched instruction until `enable` toggles). + // `advance`: the delivered instruction was accepted downstream, so self- + // sequence to the next PC (pcLatch += instruction size) and fetch it. + // `redirect`/`redirectPc`: squash the in-flight fetch and restart at the + // given PC (branch/exception recovery). + advance = addInput('advance', advance ?? Const(0)); + redirect = addInput('redirect', redirect ?? Const(0)); + redirectPc = addInput( + 'redirect_pc', + redirectPc ?? Const(0, width: pc.width), + width: pc.width, + ); + // Self-sequencing stride on `advance`. Defaults to the instruction size + // (single-fetch). Dual-dispatch drives it to the bundle stride (8 when both + // lanes accept, else 4) so the two fetchers step over each other's lanes. + final strideIn = stride != null + ? addInput('stride', stride, width: pc.width) + : null; + final faultIn = fault == null ? Const(0) : addInput('fault', fault); + memRead = memRead.clone() ..connectIO( this, @@ -36,40 +89,110 @@ class FetchUnit extends Module { addOutput('valid'); if (hasCompressed) addOutput('compressed'); addOutput('result', width: 32); + addOutput('pc_out', width: pc.width); + addOutput('fetch_fault'); - final halfwordMask = Const(0xFFFF, width: 32); - - final fetchAlignBits = switch (memRead.data.width) { + final dataW = memRead.data.width; + final fetchAlignBits = switch (dataW) { 32 => 2, 64 => 3, - _ => throw 'Unsupported XLEN=${pc.width}', + _ => throw 'Unsupported memory data width=$dataW', }; + final wordBytes = dataW ~/ 8; // bytes per aligned memory word (4 or 8) + final nHalves = dataW ~/ 16; // instruction halfwords per word (2 or 4) + final lastOff = nHalves - 1; + // Bits of pc that index the halfword within a word: pc[offBits:1]. + final offBits = (nHalves - 1).bitLength; // 1 for 32-bit, 2 for 64-bit final alignment = Const(~((1 << fetchAlignBits) - 1), width: pc.width); + final wordStep = Const(wordBytes, width: pc.width); final enableRead = Logic(name: 'enableRead'); memRead.en <= enableRead; - final halfSelect = Logic(name: 'halfSelect'); - final readData = Logic(name: 'readData', width: memRead.data.width); - + final readData = Logic(name: 'readData', width: dataW); + final secondData = Logic(name: 'secondData', width: dataW); final complete = Logic(name: 'complete'); + final phase2 = Logic(name: 'phase2'); // second read in flight (straddle) + // A speculative redirect can hit while a memory read is in flight. The + // memory will still return data for the pre-redirect address; if accepted, + // that stale instruction would be delivered paired with the post-redirect + // pcOut (a one-instruction skew). `discardResp` marks that the next read + // response belongs to the squashed pre-redirect fetch and must be dropped. + final discardResp = Logic(name: 'discardResp'); final pcLatch = Logic(name: 'pcLatch', width: pc.width); + // Latched when a fetch read returns a page fault; delivered alongside the + // (held) done & ~valid so the pipeline can raise an instruction page fault. + final faulted = Logic(name: 'faulted'); + + // The halfword offset of the (latched) PC within an aligned word. + final hwOff = pcLatch.slice(offBits, 1).named('hwOff'); + + // Split a memory word into its halfwords (index 0 = lowest address). + List halvesOf(Logic data) => [ + for (var i = 0; i < nHalves; i++) data.slice(16 * i + 15, 16 * i), + ]; - final instr32 = Logic(name: 'instr32', width: 32); + // Select item `[off]` from a list via a mux chain (off is offBits wide). + Logic selByOff(Logic off, List items) { + var r = items[0]; + for (var i = 1; i < items.length; i++) { + r = mux(off.eq(i), items[i], r); + } + return r; + } - instr32 <= - ((memRead.data.width == 32) - ? memRead.data.slice(31, 0) - : mux( - halfSelect, - memRead.data.slice(63, 32), - memRead.data.slice(31, 0), - )); + // Low halfword of the instruction (and whether it is a 16-bit instruction) + // computed from a given word source at the latched offset. + Logic loHalfOf(Logic data) => selByOff(hwOff, halvesOf(data)); + Logic isCompOf(Logic data) => loHalfOf(data).slice(1, 0).neq(0x3); - final isCompressed = Logic(name: 'isCompressed'); - isCompressed <= - (((instr32 & halfwordMask) & Const(0x3, width: 32)).neq(0x3)); + // From the latched first word: low halfword, compressed flag, and the + // upper halfword that lives within the same word (valid unless straddling). + final loHalf = loHalfOf(readData).named('loHalf'); + final isComp = isCompOf(readData).named('isComp'); + // hiSameWord[off] = halves[off+1]; the top slot is unused (straddle covers). + final halves = halvesOf(readData); + final hiSameWord = selByOff(hwOff, [ + for (var i = 1; i < nHalves; i++) halves[i], + halves[lastOff], + ]).named('hiSameWord'); + final straddle = (~isComp & hwOff.eq(lastOff)).named('straddle'); + final hiHalf = mux( + straddle, + secondData.slice(15, 0), + hiSameWord, + ).named('hiHalf'); + // With C: a 16-bit instruction occupies the low half, otherwise the 32-bit + // instruction is assembled from this halfword and the next. Without C the + // unit is a plain 32-bit fetch, none of the compressed logic above is used. + final instrResult = + (hasCompressed + ? mux(isComp, loHalf.zeroExtend(32), [hiHalf, loHalf].swizzle()) + : [hiSameWord, loHalf].swizzle()) + .named('instrResult'); + + // Straddle decision at first-read latch time uses the fresh bus data, since + // `readData` only updates on the same clock edge. + final straddleFresh = + (hasCompressed + ? (~isCompOf(memRead.data) & hwOff.eq(lastOff)) + : Const(0)) + .named('straddleFresh'); + + // Size of the delivered instruction, for speculative self-sequencing. + final instrSizeBytes = + (hasCompressed + ? mux( + isComp, + Const(2, width: pc.width), + Const(4, width: pc.width), + ) + : Const(4, width: pc.width)) + .named('instrSizeBytes'); + final nextLatch = (pcLatch + (strideIn ?? instrSizeBytes)).named( + 'nextLatch', + ); Sequential(clk, [ If( @@ -81,9 +204,13 @@ class FetchUnit extends Module { done < 0, valid < 0, result < 0, + pcOut < 0, complete < 0, + phase2 < 0, + discardResp < 0, readData < 0, - if (memRead.data.width == 64) halfSelect < 0, + secondData < 0, + faulted < 0, if (hasCompressed) compressed < 0, ], orElse: [ @@ -91,41 +218,166 @@ class FetchUnit extends Module { valid < 0, result < 0, If.block([ - Iff(enable & ~complete & ~enableRead, [ + // Speculative redirect (highest priority): squash the in-flight + // fetch and restart at redirectPc. A read may already be in flight + // for the old address, flag its response for discard so it is not + // delivered with the new pcOut. + Iff(redirect, [ + pcLatch < redirectPc, + complete < 0, + phase2 < 0, + faulted < 0, + discardResp < 1, + enableRead < 1, + memRead.addr < (redirectPc & alignment), + ]), + // Discard the stale pre-redirect read response (one in flight), then + // re-issue at the redirected pcLatch. Higher priority than the + // first/second-read latch branches so the stale data is never + // accepted. If no response was actually in flight this costs one + // extra cycle but stays correct (the read is simply re-issued). + Iff(discardResp & memRead.done, [ + discardResp < 0, + complete < 0, + phase2 < 0, + enableRead < 1, + memRead.addr < (pcLatch & alignment), + ]), + // Issue the first (aligned) read. + Iff(enable & ~complete & ~phase2 & ~enableRead, [ pcLatch < pc, - if (memRead.data.width == 64) halfSelect < pc[2], enableRead < 1, memRead.addr < (pc & alignment), ]), - Iff(enable & ~complete & ~memRead.done, [ + // Awaiting the first read. + Iff(enable & ~complete & ~phase2 & enableRead & ~memRead.done, [ enableRead < 1, memRead.addr < (pcLatch & alignment), ]), - Iff(enable & ~complete & memRead.done, [ + // First read returned data. + Iff( + enable & + ~complete & + ~phase2 & + enableRead & + memRead.done & + memRead.valid, + [ + readData < memRead.data, + // Freeze the instruction's PC with its data (pcLatch keeps + // advancing as the fetch moves on), so pcOut corresponds to the + // delivered `result` and stays paired through the decoder. + pcOut < pcLatch, + If( + straddleFresh, + then: [ + // Upper half is in the next word: issue a second read. + phase2 < 1, + enableRead < 1, + memRead.addr < ((pcLatch & alignment) + wordStep), + ], + orElse: [ + complete < 1, + enableRead < 1, + memRead.addr < (pcLatch & alignment), + ], + ), + ], + ), + // First read returned invalid. A page fault (faultIn) is delivered + // as a held done & ~valid; otherwise it is a transient miss, retry. + Iff( + enable & + ~complete & + ~phase2 & + enableRead & + memRead.done & + ~memRead.valid, + [ + If( + faultIn, + then: [ + complete < 1, + faulted < 1, + pcOut < pcLatch, + enableRead < 1, + memRead.addr < (pcLatch & alignment), + ], + orElse: [ + enableRead < 1, + memRead.addr < (pcLatch & alignment), + ], + ), + ], + ), + // Awaiting the straddle second read. + Iff(enable & ~complete & phase2 & ~memRead.done, [ + enableRead < 1, + memRead.addr < ((pcLatch & alignment) + wordStep), + ]), + // Second read returned data. + Iff(enable & ~complete & phase2 & memRead.done & memRead.valid, [ + secondData < memRead.data, + complete < 1, + phase2 < 0, enableRead < 1, memRead.addr < (pcLatch & alignment), + ]), + // Second (straddle) read returned invalid: a page fault means the + // instruction crosses into an unmapped page, deliver the fault. + Iff(enable & ~complete & phase2 & memRead.done & ~memRead.valid, [ If( - memRead.valid, - then: [complete < 1, readData < memRead.data, result < 0], - orElse: [done < 1, valid < 0, enableRead < 0], + faultIn, + then: [ + complete < 1, + faulted < 1, + phase2 < 0, + pcOut < pcLatch, + enableRead < 1, + memRead.addr < (pcLatch & alignment), + ], + orElse: [ + enableRead < 1, + memRead.addr < ((pcLatch & alignment) + wordStep), + ], ), ]), + // Accepted downstream (speculative): the instruction was delivered + // and taken this cycle, so self-sequence to the next PC and fetch + // it. `done` falls (default above), this instruction is consumed. + Iff(enable & complete & advance, [ + pcLatch < nextLatch, + complete < 0, + phase2 < 0, + faulted < 0, + enableRead < 1, + memRead.addr < (nextLatch & alignment), + ]), + // Deliver the instruction (held until accepted/redirected). pcOut + // is registered alongside result so the two correspond (result is + // registered, pcLatch is not, using pcLatch directly would run the + // PC one instruction ahead of the decoded instruction). A fetch fault + // is delivered as a valid instruction with `fetch_fault` set so the + // pipeline flows normally and the exec stage overrides it with an + // instruction page fault (the result is don't-care, it never writes + // back). pcOut already holds the faulting PC. Iff(enable & complete, [ done < 1, valid < 1, - enableRead < 1, + // The instruction is already captured, so do NOT re-issue the read + // while holding it. A redundant re-read is harmless for physical + // memory but, through the MMU, re-walks the page table every cycle + // and starves the data port (a translated load would never run). + enableRead < 0, memRead.addr < (pcLatch & alignment), - if (hasCompressed) ...[ - compressed < isCompressed, - result < mux(isCompressed, (instr32 & halfwordMask), instr32), - ] else ...[ - result < instr32, - ], + result < instrResult, + if (hasCompressed) compressed < isComp, ]), + // Disabled: drop transient state. Iff(~enable, [ complete < 0, + phase2 < 0, pcLatch < pc, - if (memRead.data.width == 64) halfSelect < 0, if (hasCompressed) compressed < 0, enableRead < 0, memRead.addr < 0, @@ -134,5 +386,8 @@ class FetchUnit extends Module { ], ), ]); + + // The fault is signalled with the held done & ~valid delivery. + output('fetch_fault') <= done & faulted; } } diff --git a/packages/river_hdl/lib/src/core/fu_alu.dart b/packages/river_hdl/lib/src/core/fu_alu.dart new file mode 100644 index 0000000..90f19f2 --- /dev/null +++ b/packages/river_hdl/lib/src/core/fu_alu.dart @@ -0,0 +1,403 @@ +import 'package:rohd/rohd.dart'; +import 'package:harbor/harbor.dart' hide PrivilegeMode; +import 'alu_ops.dart'; + +/// ALU functional unit. +/// +/// Combinational ALU with 1-cycle latency for basic operations. +/// Mul/div use a multi-cycle state machine. +/// Supports dual instantiation for 2-wide issue. +class AluUnit extends Module { + final int xlen; + + /// Cycles from issue to result for mul/div (>= 2). Their datapath is held + /// between operand and result registers across this window, a clean + /// multi-cycle path for ASIC timing closure (constrain it in SDC). + final int mulDivLatency; + + Logic get resultValid => output('result_valid'); + Logic get resultTag => output('result_tag'); + Logic get resultData => output('result_data'); + Logic get resultException => output('result_exception'); + Logic get resultCause => output('result_cause'); + Logic get busy => output('busy'); + + AluUnit( + Logic clk, + Logic reset, { + required Logic issueValid, + required Logic issueTag, + required Logic issueSrc1, + required Logic issueSrc2, + required Logic issueImm, + required Logic issueFunct, + required Logic issueUseImm, + required Logic issuePc, + required Logic flush, + this.xlen = 64, + int robTagBits = 7, + this.mulDivLatency = 4, + super.name = 'alu_unit', + }) : assert(mulDivLatency >= 2, 'mul/div multi-cycle latency must be >= 2'), + super(definitionName: 'AluUnit') { + clk = addInput('clk', clk); + reset = addInput('reset', reset); + + // Issue interface + issueValid = addInput('issue_valid', issueValid); + issueTag = addInput('issue_tag', issueTag, width: robTagBits); + issueSrc1 = addInput('issue_src1', issueSrc1, width: xlen); + issueSrc2 = addInput('issue_src2', issueSrc2, width: xlen); + issueImm = addInput('issue_imm', issueImm, width: xlen); + issueFunct = addInput('issue_funct', issueFunct, width: 7); + issueUseImm = addInput('issue_use_imm', issueUseImm); + issuePc = addInput('issue_pc', issuePc, width: xlen); + + // Flush + flush = addInput('flush', flush); + + // Result interface + addOutput('result_valid'); + addOutput('result_tag', width: robTagBits); + addOutput('result_data', width: xlen); + addOutput('result_exception'); + addOutput('result_cause', width: 6); + addOutput('busy'); + + final operand2 = mux(issueUseImm, issueImm, issueSrc2); + + // Single-cycle ALU operations + final aluResult = Logic(name: 'alu_result', width: xlen); + + // Single-cycle ALU op set, matching the in-order ALU (exec.dart) so both + // datapaths agree. funct is 7 bits (RiscVAluFunct has >32 values). + // Bitmanip uses the shared alu_ops helpers. The mul/div family is NOT in + // this Case: it executes on the latched multi-cycle path below. + CaseItem ci(RiscVAluFunct f, Logic result) => + CaseItem(Const(f.index, width: 7), [aluResult < result]); + final mask = Const(xlen - 1, width: xlen); + Logic bit1(Logic shamt) => Const(1, width: xlen) << (shamt & mask); + + Combinational([ + Case( + issueFunct, + [ + ci(RiscVAluFunct.add, issueSrc1 + operand2), + ci(RiscVAluFunct.sub, issueSrc1 - operand2), + ci(RiscVAluFunct.and_, issueSrc1 & operand2), + ci(RiscVAluFunct.or_, issueSrc1 | operand2), + ci(RiscVAluFunct.xor_, issueSrc1 ^ operand2), + ci(RiscVAluFunct.sll, issueSrc1 << operand2.slice(5, 0)), + ci(RiscVAluFunct.srl, issueSrc1 >>> operand2.slice(5, 0)), + ci(RiscVAluFunct.sra, issueSrc1 >> operand2.slice(5, 0)), + ci( + RiscVAluFunct.slt, + bmSignedLt(issueSrc1, operand2, xlen).zeroExtend(xlen), + ), + ci(RiscVAluFunct.sltu, issueSrc1.lt(operand2).zeroExtend(xlen)), + // 32-bit word variants + ci( + RiscVAluFunct.addw, + (issueSrc1 + operand2).slice(31, 0).signExtend(xlen), + ), + ci( + RiscVAluFunct.subw, + (issueSrc1 - operand2).slice(31, 0).signExtend(xlen), + ), + ci( + RiscVAluFunct.sllw, + (issueSrc1.slice(31, 0) << operand2.slice(4, 0)).signExtend(xlen), + ), + ci( + RiscVAluFunct.srlw, + (issueSrc1.slice(31, 0) >>> operand2.slice(4, 0)).signExtend(xlen), + ), + ci( + RiscVAluFunct.sraw, + (issueSrc1.slice(31, 0) >> operand2.slice(4, 0)).signExtend(xlen), + ), + // M extension (mul/div) is handled by the multi-cycle path below, + // not this single-cycle Case, so its heavy datapath is registered. + // Zbb logical-with-negate + extends + ci(RiscVAluFunct.andn, issueSrc1 & ~operand2), + ci(RiscVAluFunct.orn, issueSrc1 | ~operand2), + ci(RiscVAluFunct.xnor, ~(issueSrc1 ^ operand2)), + ci(RiscVAluFunct.sextb, issueSrc1.slice(7, 0).signExtend(xlen)), + ci(RiscVAluFunct.sexth, issueSrc1.slice(15, 0).signExtend(xlen)), + ci(RiscVAluFunct.zexth, issueSrc1.slice(15, 0).zeroExtend(xlen)), + ci(RiscVAluFunct.zextb, issueSrc1.slice(7, 0).zeroExtend(xlen)), + ci(RiscVAluFunct.zextw, issueSrc1.slice(31, 0).zeroExtend(xlen)), + ci(RiscVAluFunct.notOp, ~issueSrc1), + // Zbb min/max + ci( + RiscVAluFunct.minOp, + mux(bmSignedLt(issueSrc1, operand2, xlen), issueSrc1, operand2), + ), + ci( + RiscVAluFunct.maxOp, + mux(bmSignedLt(issueSrc1, operand2, xlen), operand2, issueSrc1), + ), + ci( + RiscVAluFunct.minuOp, + mux(issueSrc1.lt(operand2), issueSrc1, operand2), + ), + ci( + RiscVAluFunct.maxuOp, + mux(issueSrc1.lt(operand2), operand2, issueSrc1), + ), + // Zbb rotates + ci(RiscVAluFunct.rol, bmRotl(issueSrc1, operand2, xlen)), + ci(RiscVAluFunct.ror, bmRotr(issueSrc1, operand2, xlen)), + ci( + RiscVAluFunct.rolw, + bmRotl( + issueSrc1.slice(31, 0), + operand2.slice(31, 0), + 32, + ).signExtend(xlen), + ), + ci( + RiscVAluFunct.rorw, + bmRotr( + issueSrc1.slice(31, 0), + operand2.slice(31, 0), + 32, + ).signExtend(xlen), + ), + // Zbb counts + ci(RiscVAluFunct.clz, bmClz(issueSrc1, xlen)), + ci(RiscVAluFunct.ctz, bmCtz(issueSrc1, xlen)), + ci(RiscVAluFunct.cpop, bmPopcount(issueSrc1, xlen)), + ci( + RiscVAluFunct.clzw, + bmClz(issueSrc1.slice(31, 0), 32).zeroExtend(xlen), + ), + ci( + RiscVAluFunct.ctzw, + bmCtz(issueSrc1.slice(31, 0), 32).zeroExtend(xlen), + ), + ci( + RiscVAluFunct.cpopw, + bmPopcount(issueSrc1.slice(31, 0), 32).zeroExtend(xlen), + ), + // Zbb byte ops + ci(RiscVAluFunct.orcb, bmOrcb(issueSrc1, xlen)), + ci(RiscVAluFunct.rev8, bmRev8(issueSrc1, xlen)), + // Zba shift-add (and unsigned-word forms) + ci(RiscVAluFunct.sh1add, (issueSrc1 << 1) + operand2), + ci(RiscVAluFunct.sh2add, (issueSrc1 << 2) + operand2), + ci(RiscVAluFunct.sh3add, (issueSrc1 << 3) + operand2), + ci( + RiscVAluFunct.adduw, + issueSrc1.slice(31, 0).zeroExtend(xlen) + operand2, + ), + ci( + RiscVAluFunct.sh1adduw, + (issueSrc1.slice(31, 0).zeroExtend(xlen) << 1) + operand2, + ), + ci( + RiscVAluFunct.sh2adduw, + (issueSrc1.slice(31, 0).zeroExtend(xlen) << 2) + operand2, + ), + ci( + RiscVAluFunct.sh3adduw, + (issueSrc1.slice(31, 0).zeroExtend(xlen) << 3) + operand2, + ), + // Zbs single-bit + ci(RiscVAluFunct.bset, issueSrc1 | bit1(operand2)), + ci(RiscVAluFunct.bclr, issueSrc1 & ~bit1(operand2)), + ci(RiscVAluFunct.binv, issueSrc1 ^ bit1(operand2)), + ci( + RiscVAluFunct.bext, + (issueSrc1 >>> (operand2 & mask)) & Const(1, width: xlen), + ), + // Zicond + ci( + RiscVAluFunct.czeroEqz, + mux( + operand2.eq(Const(0, width: xlen)), + Const(0, width: xlen), + issueSrc1, + ), + ), + ci( + RiscVAluFunct.czeroNez, + mux( + operand2.eq(Const(0, width: xlen)), + issueSrc1, + Const(0, width: xlen), + ), + ), + ], + defaultItem: [aluResult < Const(0, width: xlen)], + ), + ]); + + // mul/div: multi-cycle, functionally exact. + // mul/div are combinationally heavy (a 2*XLEN product / XLEN-wide divide). + // Instead of completing them in the single-cycle path, latch the operands, + // raise `busy` (the scheduler then holds off issuing to this unit), and + // present the result after `mulDivLatency` cycles. The heavy datapath then + // lives only between the latched-operand and result registers - a clean + // multi-cycle path to constrain in SDC. Products come from the shared + // BmMulSet and div/rem from the bmDiv*/bmRem* helpers, the same engines + // the in-order ALU uses, so both datapaths are functionally exact. + const mdOps = [ + RiscVAluFunct.mul, RiscVAluFunct.mulw, RiscVAluFunct.mulh, + RiscVAluFunct.mulhsu, RiscVAluFunct.mulhu, // + RiscVAluFunct.div, RiscVAluFunct.divu, RiscVAluFunct.divw, + RiscVAluFunct.divuw, RiscVAluFunct.rem, RiscVAluFunct.remu, + RiscVAluFunct.remw, RiscVAluFunct.remuw, + ]; + final isMulDiv = mdOps + .map((f) => issueFunct.eq(Const(f.index, width: 7))) + .reduce((a, b) => a | b); + + // Latched operands + control for the in-flight mul/div. + final mdSrc1 = Logic(name: 'md_src1', width: xlen); + final mdSrc2 = Logic(name: 'md_src2', width: xlen); + final mdFunct = Logic(name: 'md_funct', width: 7); + final mdTag = Logic(name: 'md_tag', width: robTagBits); + final mdActive = Logic(name: 'md_active'); + final cntBits = mulDivLatency.bitLength; + final mdCount = Logic(name: 'md_count', width: cntBits); + + // Combinational mul/div result from the LATCHED operands. The whole mul + // family shares one multiplier (see BmMulSet for the identity). + final mdResult = Logic(name: 'md_result', width: xlen); + final mdMul = BmMulSet(mdSrc1, mdSrc2, xlen); + CaseItem ciMd(RiscVAluFunct f, Logic result) => + CaseItem(Const(f.index, width: 7), [mdResult < result]); + Combinational([ + Case( + mdFunct, + [ + ciMd(RiscVAluFunct.mul, mdMul.low), + ciMd(RiscVAluFunct.mulw, mdMul.low.slice(31, 0).signExtend(xlen)), + ciMd(RiscVAluFunct.mulh, mdMul.highSS), + ciMd(RiscVAluFunct.mulhsu, mdMul.highSU), + ciMd(RiscVAluFunct.mulhu, mdMul.highUU), + ciMd(RiscVAluFunct.div, bmDivS(mdSrc1, mdSrc2, xlen)), + ciMd(RiscVAluFunct.divu, bmDivU(mdSrc1, mdSrc2, xlen)), + ciMd( + RiscVAluFunct.divw, + bmDivS( + mdSrc1.slice(31, 0), + mdSrc2.slice(31, 0), + 32, + ).signExtend(xlen), + ), + ciMd( + RiscVAluFunct.divuw, + bmDivU( + mdSrc1.slice(31, 0), + mdSrc2.slice(31, 0), + 32, + ).signExtend(xlen), + ), + ciMd(RiscVAluFunct.rem, bmRemS(mdSrc1, mdSrc2, xlen)), + ciMd(RiscVAluFunct.remu, bmRemU(mdSrc1, mdSrc2, xlen)), + ciMd( + RiscVAluFunct.remw, + bmRemS( + mdSrc1.slice(31, 0), + mdSrc2.slice(31, 0), + 32, + ).signExtend(xlen), + ), + ciMd( + RiscVAluFunct.remuw, + bmRemU( + mdSrc1.slice(31, 0), + mdSrc2.slice(31, 0), + 32, + ).signExtend(xlen), + ), + ], + defaultItem: [mdResult < Const(0, width: xlen)], + ), + ]); + + // Count is loaded with latency-1 at issue and completes when it reaches 1, + // so result_valid rises exactly `mulDivLatency` cycles after issue. + final mdLoad = Const(mulDivLatency - 1, width: cntBits); + final one = Const(1, width: cntBits); + + Sequential(clk, [ + If( + reset | flush, + then: [ + resultValid < 0, + resultTag < 0, + resultData < 0, + resultException < 0, + resultCause < 0, + busy < 0, + mdActive < 0, + mdCount < 0, + mdSrc1 < 0, + mdSrc2 < 0, + mdFunct < 0, + mdTag < 0, + ], + orElse: [ + If( + mdActive, + then: [ + // In-flight mul/div: count down, complete when it reaches 1. + If( + mdCount.eq(one), + then: [ + resultValid < 1, + resultTag < mdTag, + resultData < mdResult, + resultException < 0, + resultCause < 0, + mdActive < 0, + busy < 0, + ], + orElse: [mdCount < mdCount - one, resultValid < 0, busy < 1], + ), + ], + orElse: [ + If( + issueValid & isMulDiv, + then: [ + // Start a multi-cycle mul/div: latch operands, raise busy. + mdActive < 1, + busy < 1, + mdCount < mdLoad, + mdTag < issueTag, + mdFunct < issueFunct, + mdSrc1 < issueSrc1, + mdSrc2 < operand2, + resultValid < 0, + ], + orElse: [ + If( + issueValid, + then: [ + // Single-cycle ALU op. + resultValid < 1, + resultTag < issueTag, + resultData < aluResult, + resultException < 0, + resultCause < 0, + busy < 0, + ], + orElse: [ + resultValid < 0, + resultTag < 0, + resultData < 0, + busy < 0, + ], + ), + ], + ), + ], + ), + ], + ), + ]); + } +} diff --git a/packages/river_hdl/lib/src/core/fu_branch.dart b/packages/river_hdl/lib/src/core/fu_branch.dart new file mode 100644 index 0000000..08c7224 --- /dev/null +++ b/packages/river_hdl/lib/src/core/fu_branch.dart @@ -0,0 +1,173 @@ +import 'package:rohd/rohd.dart'; + +import 'alu_ops.dart'; + +/// Branch functional unit. +/// +/// Resolves conditional branches (BEQ, BNE, BLT, BGE, BLTU, BGEU) +/// and jumps (JAL, JALR). Single-cycle resolution. +/// Produces a redirect signal when a branch is mispredicted. +class BranchUnit extends Module { + final int xlen; + + Logic get resultValid => output('result_valid'); + Logic get resultTag => output('result_tag'); + Logic get resultData => output('result_data'); + Logic get resultException => output('result_exception'); + Logic get resultCause => output('result_cause'); + + /// Whether a redirect (misprediction recovery) is needed. + Logic get redirect => output('redirect'); + + /// The corrected PC after branch resolution. + Logic get redirectPc => output('redirect_pc'); + + Logic get busy => output('busy'); + + BranchUnit( + Logic clk, + Logic reset, { + required Logic issueValid, + required Logic issueTag, + required Logic issueSrc1, + required Logic issueSrc2, + required Logic issueImm, + required Logic issuePc, + required Logic issueCondition, + required Logic issueIsJump, + required Logic issueIsJalr, + required Logic issuePredictedTaken, + required Logic flush, + this.xlen = 64, + int robTagBits = 7, + super.name = 'branch_unit', + }) : super(definitionName: 'BranchUnit') { + clk = addInput('clk', clk); + reset = addInput('reset', reset); + + // Issue interface + issueValid = addInput('issue_valid', issueValid); + issueTag = addInput('issue_tag', issueTag, width: robTagBits); + issueSrc1 = addInput('issue_src1', issueSrc1, width: xlen); + issueSrc2 = addInput('issue_src2', issueSrc2, width: xlen); + issueImm = addInput('issue_imm', issueImm, width: xlen); + issuePc = addInput('issue_pc', issuePc, width: xlen); + + /// Branch condition (funct3 encoding): + /// 0=BEQ, 1=BNE, 4=BLT, 5=BGE, 6=BLTU, 7=BGEU + issueCondition = addInput('issue_condition', issueCondition, width: 3); + + /// Whether this is an unconditional jump (JAL/JALR). + issueIsJump = addInput('issue_is_jump', issueIsJump); + + /// Whether this is JALR (target = rs1 + imm, not pc + imm). + issueIsJalr = addInput('issue_is_jalr', issueIsJalr); + + /// Predicted taken (from front-end, for detecting mispredictions). + issuePredictedTaken = addInput( + 'issue_predicted_taken', + issuePredictedTaken, + ); + + // Flush + flush = addInput('flush', flush); + + // Result interface + addOutput('result_valid'); + addOutput('result_tag', width: robTagBits); + addOutput('result_data', width: xlen); // link address for JAL/JALR + addOutput('result_exception'); + addOutput('result_cause', width: 6); + addOutput('redirect'); + addOutput('redirect_pc', width: xlen); + addOutput('busy'); + + // Branch condition evaluation (combinational) + final branchTaken = Logic(name: 'branch_taken'); + + Combinational([ + Case( + issueCondition, + [ + CaseItem(Const(0, width: 3), [ + // BEQ + branchTaken < issueSrc1.eq(issueSrc2), + ]), + CaseItem(Const(1, width: 3), [ + // BNE + branchTaken < issueSrc1.neq(issueSrc2), + ]), + CaseItem(Const(4, width: 3), [ + // BLT (signed): .lt is unsigned, so use the signed-compare helper. + branchTaken < bmSignedLt(issueSrc1, issueSrc2, xlen), + ]), + CaseItem(Const(5, width: 3), [ + // BGE (signed): not-less-than (signed). + branchTaken < ~bmSignedLt(issueSrc1, issueSrc2, xlen), + ]), + CaseItem(Const(6, width: 3), [ + // BLTU (unsigned) + branchTaken < issueSrc1.lt(issueSrc2), + ]), + CaseItem(Const(7, width: 3), [ + // BGEU (unsigned) + branchTaken < issueSrc1.gte(issueSrc2), + ]), + ], + defaultItem: [branchTaken < Const(0)], + ), + ]); + + // Target computation + final branchTarget = mux( + issueIsJalr, + issueSrc1 + issueImm, + issuePc + issueImm, + ).named('branch_target'); + + // Next sequential PC (for not-taken branches and link address) + final nextPc = (issuePc + Const(4, width: xlen)).named('next_pc'); + + // Actual taken: unconditional jumps are always taken + final actualTaken = (issueIsJump | branchTaken).named('actual_taken'); + + // Misprediction detection + final mispredicted = (actualTaken ^ issuePredictedTaken).named( + 'mispredicted', + ); + + // Single-cycle: all branch ops complete immediately + Sequential(clk, [ + If( + reset, + then: [ + resultValid < 0, + resultTag < 0, + resultData < 0, + resultException < 0, + resultCause < 0, + redirect < 0, + redirectPc < 0, + busy < 0, + ], + orElse: [ + If( + issueValid, + then: [ + resultValid < 1, + resultTag < issueTag, + // Link address for JAL/JALR (rd = PC+4) + resultData < nextPc, + resultException < 0, + resultCause < 0, + redirect < mispredicted, + redirectPc < mux(actualTaken, branchTarget, nextPc), + busy < 0, + ], + orElse: [resultValid < 0, redirect < 0, busy < 0], + ), + ], + ), + ]); + } +} diff --git a/packages/river_hdl/lib/src/core/fu_csr.dart b/packages/river_hdl/lib/src/core/fu_csr.dart new file mode 100644 index 0000000..ea43898 --- /dev/null +++ b/packages/river_hdl/lib/src/core/fu_csr.dart @@ -0,0 +1,238 @@ +import 'package:rohd/rohd.dart'; +import '../data_port.dart'; + +/// CSR functional unit. +/// +/// Handles CSR read/write/set/clear operations. +/// Serialised: only one CSR op in flight at a time (no OoO for CSRs). +/// Multi-cycle: cycle 1 reads CSR, cycle 2 writes new value. +class CsrUnit extends Module { + final int xlen; + + Logic get resultValid => output('result_valid'); + Logic get resultTag => output('result_tag'); + Logic get resultData => output('result_data'); + Logic get resultException => output('result_exception'); + Logic get resultCause => output('result_cause'); + Logic get busy => output('busy'); + + CsrUnit( + Logic clk, + Logic reset, + DataPortInterface csrRead, + DataPortInterface csrWrite, { + required Logic issueValid, + required Logic issueTag, + required Logic issueSrc1, + required Logic issueImm, + required Logic issueOp, + required Logic issueCsrAddr, + required Logic flush, + this.xlen = 64, + int robTagBits = 7, + super.name = 'csr_unit', + }) : super(definitionName: 'CsrUnit') { + clk = addInput('clk', clk); + reset = addInput('reset', reset); + + // Issue interface + issueValid = addInput('issue_valid', issueValid); + issueTag = addInput('issue_tag', issueTag, width: robTagBits); + issueSrc1 = addInput('issue_src1', issueSrc1, width: xlen); + issueImm = addInput('issue_imm', issueImm, width: xlen); + issueOp = addInput('issue_op', issueOp, width: 3); + issueCsrAddr = addInput('issue_csr_addr', issueCsrAddr, width: 12); + + // Flush + flush = addInput('flush', flush); + + // CSR port connections + csrRead = csrRead.clone() + ..connectIO( + this, + csrRead, + outputTags: {DataPortGroup.control}, + inputTags: {DataPortGroup.data, DataPortGroup.integrity}, + uniquify: (og) => 'csrRead_$og', + ); + + csrWrite = csrWrite.clone() + ..connectIO( + this, + csrWrite, + outputTags: {DataPortGroup.control, DataPortGroup.data}, + inputTags: {DataPortGroup.integrity}, + uniquify: (og) => 'csrWrite_$og', + ); + + // Result interface + addOutput('result_valid'); + addOutput('result_tag', width: robTagBits); + addOutput('result_data', width: xlen); + addOutput('result_exception'); + addOutput('result_cause', width: 6); + addOutput('busy'); + + // FSM: IDLE → READ → WRITE → DONE + final stateIdle = Const(0, width: 2); + final stateRead = Const(1, width: 2); + final stateWrite = Const(2, width: 2); + + final state = Logic(name: 'csr_state', width: 2); + final savedTag = Logic(name: 'saved_tag', width: robTagBits); + final savedOp = Logic(name: 'saved_op', width: 3); + final savedSrc = Logic(name: 'saved_src', width: xlen); + final savedAddr = Logic(name: 'saved_addr', width: 12); + final readValue = Logic(name: 'read_value', width: xlen); + + // Computed new CSR value (combinational; valid in stateRead where csrRead.data + // holds the old value). Mirrors the write-value Case below. + final newCsrVal = Logic(name: 'new_csr_val', width: xlen); + Combinational([ + Case( + savedOp.slice(1, 0), + [ + CaseItem(Const(1, width: 2), [newCsrVal < savedSrc]), // RW + CaseItem(Const(2, width: 2), [ + newCsrVal < (csrRead.data | savedSrc), // RS + ]), + CaseItem(Const(3, width: 2), [ + newCsrVal < (csrRead.data & ~savedSrc), // RC + ]), + ], + defaultItem: [newCsrVal < savedSrc], + ), + ]); + // A SET/CLEAR (RS/RC, funct3[1]=1) write that does not change the CSR is + // suppressed entirely (no frontdoor write, no legality check) - this is how + // csrrs/csrrc rs1=x0 (and csrr*i uimm=0) read a READ-ONLY CSR without taking + // a write-to-RO illegal trap. csrrw (RW, funct3[1]=0) must ALWAYS write per + // spec, even when the value is unchanged, so it is never suppressed. + final writeIsNoOp = (savedOp[1] & newCsrVal.eq(csrRead.data)).named( + 'csrWriteNoOp', + ); + + Sequential(clk, [ + If( + reset | flush, + then: [ + state < stateIdle, + savedTag < 0, + savedOp < 0, + savedSrc < 0, + savedAddr < 0, + readValue < 0, + resultValid < 0, + resultTag < 0, + resultData < 0, + resultException < 0, + resultCause < 0, + busy < 0, + csrRead.en < 0, + csrRead.addr < 0, + csrWrite.en < 0, + csrWrite.addr < 0, + csrWrite.data < 0, + ], + orElse: [ + Case( + state, + [ + // IDLE + CaseItem(stateIdle, [ + resultValid < 0, + If( + issueValid, + then: [ + state < stateRead, + savedTag < issueTag, + savedOp < issueOp, + // Immediate variants are csrrwi/csrrsi/csrrci (funct3 5/6/7), + // distinguished by BIT 2 - not funct3>=3, which wrongly + // flagged csrrc (funct3 3, a register form). + savedSrc < + mux(issueOp[2], issueImm.zeroExtend(xlen), issueSrc1), + savedAddr < issueCsrAddr, + busy < 1, + // Start CSR read + csrRead.en < 1, + csrRead.addr < issueCsrAddr, + csrWrite.en < 0, + ], + orElse: [busy < 0, csrRead.en < 0, csrWrite.en < 0], + ), + ]), + // READ: wait for CSR read response + CaseItem(stateRead, [ + If( + csrRead.done, + then: [ + If( + csrRead.valid, + then: [ + readValue < csrRead.data, + csrRead.en < 0, + If( + writeIsNoOp, + // No actual write (csrrs/csrrc x0, csrr*i 0, or any + // value-preserving write): skip stateWrite so a + // read-only CSR is not hit with a write-to-RO trap. + // Complete now with the read value as rd. + then: [ + state < stateIdle, + busy < 0, + csrWrite.en < 0, + resultValid < 1, + resultTag < savedTag, + resultData < csrRead.data, + resultException < 0, + resultCause < 0, + ], + orElse: [ + state < stateWrite, + csrWrite.en < 1, + csrWrite.addr < savedAddr, + csrWrite.data < newCsrVal, + ], + ), + ], + orElse: [ + // CSR read failed: illegal CSR + state < stateIdle, + busy < 0, + csrRead.en < 0, + csrWrite.en < 0, + resultValid < 1, + resultTag < savedTag, + resultData < 0, + resultException < 1, + resultCause < Const(2, width: 6), // illegal instruction + ], + ), + ], + ), + ]), + // WRITE: wait for CSR write response + CaseItem(stateWrite, [ + If( + csrWrite.done, + then: [ + state < stateIdle, + busy < 0, + csrWrite.en < 0, + resultValid < 1, + resultTag < savedTag, + resultData < readValue, + resultException < 0, + resultCause < 0, + ], + ), + ]), + ], + defaultItem: [state < stateIdle], + ), + ], + ), + ]); + } +} diff --git a/packages/river_hdl/lib/src/core/fu_mem.dart b/packages/river_hdl/lib/src/core/fu_mem.dart new file mode 100644 index 0000000..b67fd5a --- /dev/null +++ b/packages/river_hdl/lib/src/core/fu_mem.dart @@ -0,0 +1,440 @@ +import 'package:rohd/rohd.dart'; + +/// Load/store functional unit. +/// +/// Handles memory loads, stores, and atomic operations. +/// Multi-cycle: issues address on cycle 1, waits for memory response. +/// Connects to the bus fabric via Wishbone master port. +/// +/// With a load-store queue configured ([lsqStores] true), stores do NOT drive +/// the bus here, they push their address/data into the store queue (via the +/// `store_fill_*` outputs) and complete in one cycle; the architectural write +/// happens later at commit. Loads can also be held: while [loadStall] is high +/// (an older store has not yet drained) an accepted load waits before issuing +/// its bus read, so it observes the older store's value. +class MemoryUnit extends Module { + final int xlen; + + /// Whether stores are routed into a store queue instead of the bus. + final bool lsqStores; + + Logic get resultValid => output('result_valid'); + Logic get resultTag => output('result_tag'); + Logic get resultData => output('result_data'); + Logic get resultException => output('result_exception'); + Logic get resultCause => output('result_cause'); + Logic get busy => output('busy'); + + // Speculative LSQ: a store that violated load ordering (a younger load already + // read its address) redirects to re-fetch from after the store. + Logic get resultRedirect => output('result_redirect'); + Logic get resultTarget => output('result_target'); + // The completing op's access info, for the load-queue (push on a load) and + // the store-queue CAM. + Logic get resultIsStore => output('result_is_store'); + Logic get resultAddr => output('result_addr'); + Logic get resultSize => output('result_size'); + + // Store-queue fill (only meaningful when [lsqStores]). Asserted the cycle a + // store is accepted; carries the address/data/size to push into the queue. + Logic get storeFillValid => output('store_fill_valid'); + Logic get storeFillTag => output('store_fill_tag'); + Logic get storeFillAddr => output('store_fill_addr'); + Logic get storeFillData => output('store_fill_data'); + Logic get storeFillSize => output('store_fill_size'); + + // Wishbone master port signals + Logic get wbCyc => output('wb_cyc'); + Logic get wbStb => output('wb_stb'); + Logic get wbWe => output('wb_we'); + Logic get wbAdr => output('wb_adr'); + Logic get wbDatMosi => output('wb_dat_mosi'); + Logic get wbSel => output('wb_sel'); + + /// Access byte count (1/2/4/8) of the in-flight request, for consumers that + /// pack a sized store data word. + Logic get wbSize => output('wb_size'); + + MemoryUnit( + Logic clk, + Logic reset, { + required Logic issueValid, + required Logic issueTag, + required Logic issueSrc1, + required Logic issueSrc2, + required Logic issueImm, + required Logic issueIsStore, + required Logic issueSize, + required Logic issueSignExtend, + required Logic flush, + required Logic wbAck, + required Logic wbDatMiso, + required Logic wbErr, + // High when an accepted load must wait for the store queue to drain before + // reading the bus. Tied to 0 when no LSQ is configured. + Logic? loadStall, + // Store→load forwarding (forwarding mode): when an accepted load's address + // is satisfied by an in-queue store, take the value directly and skip the + // bus. Tied to 0 when forwarding is not configured. + Logic? fwdHit, + Logic? fwdData, + // The dispatching op's PC (for the store-violation replay target) and a + // store→load ordering violation flag from the load queue (speculative mode). + Logic? issuePc, + Logic? camViolation, + // MMU page-fault for the in-flight access (dport `done & ~valid`). When high + // during the bus request the access traps with a load/store page fault + // instead of completing or hanging. [memFaultGuest] selects the guest + // (G-stage) page-fault cause. Both tie to 0 when no MMU faults are wired. + Logic? memFault, + Logic? memFaultGuest, + this.lsqStores = false, + this.xlen = 64, + int robTagBits = 7, + super.name = 'memory_unit', + }) : super(definitionName: 'MemoryUnit') { + clk = addInput('clk', clk); + reset = addInput('reset', reset); + + // Issue interface + issueValid = addInput('issue_valid', issueValid); + issueTag = addInput('issue_tag', issueTag, width: robTagBits); + issueSrc1 = addInput('issue_src1', issueSrc1, width: xlen); + issueSrc2 = addInput('issue_src2', issueSrc2, width: xlen); + issueImm = addInput('issue_imm', issueImm, width: xlen); + issueIsStore = addInput('issue_is_store', issueIsStore); + issueSize = addInput('issue_size', issueSize, width: 3); // bytes: 1,2,4,8 + issueSignExtend = addInput('issue_sign_extend', issueSignExtend); + loadStall = addInput('load_stall', loadStall ?? Const(0)); + fwdHit = addInput('fwd_hit', fwdHit ?? Const(0)); + fwdData = addInput( + 'fwd_data', + fwdData ?? Const(0, width: xlen), + width: xlen, + ); + issuePc = addInput( + 'issue_pc', + issuePc ?? Const(0, width: xlen), + width: xlen, + ); + camViolation = addInput('cam_violation', camViolation ?? Const(0)); + memFault = addInput('mem_fault', memFault ?? Const(0)); + memFaultGuest = addInput('mem_fault_guest', memFaultGuest ?? Const(0)); + + // Flush + flush = addInput('flush', flush); + + // Wishbone slave response (from bus fabric) + wbAck = addInput('wb_ack', wbAck); + wbDatMiso = addInput('wb_dat_miso', wbDatMiso, width: xlen); + wbErr = addInput('wb_err', wbErr); + + // Result interface + addOutput('result_valid'); + addOutput('result_tag', width: robTagBits); + addOutput('result_data', width: xlen); + addOutput('result_exception'); + addOutput('result_cause', width: 6); + addOutput('busy'); + addOutput('result_redirect'); + addOutput('result_target', width: xlen); + addOutput('result_is_store'); + addOutput('result_addr', width: xlen); + addOutput('result_size', width: 3); + + // Store-queue fill outputs + addOutput('store_fill_valid'); + addOutput('store_fill_tag', width: robTagBits); + addOutput('store_fill_addr', width: xlen); + addOutput('store_fill_data', width: xlen); + addOutput('store_fill_size', width: 3); + + // Wishbone master outputs + addOutput('wb_cyc'); + addOutput('wb_stb'); + addOutput('wb_we'); + addOutput('wb_adr', width: xlen); + addOutput('wb_dat_mosi', width: xlen); + addOutput('wb_sel', width: xlen ~/ 8); + addOutput('wb_size', width: 3); + + // Address generation + final effectiveAddr = (issueSrc1 + issueImm).named('effective_addr'); + + // Byte select mask from a size in bytes. + Logic selFromSize(Logic size) { + final sel = Logic(name: 'sel_tmp', width: xlen ~/ 8); + Combinational([ + Case( + size, + [ + CaseItem(Const(1, width: 3), [sel < Const(0x01, width: xlen ~/ 8)]), + CaseItem(Const(2, width: 3), [sel < Const(0x03, width: xlen ~/ 8)]), + CaseItem(Const(4, width: 3), [sel < Const(0x0F, width: xlen ~/ 8)]), + CaseItem(Const(8, width: 3), [sel < Const(0xFF, width: xlen ~/ 8)]), + ], + defaultItem: [sel < Const(0x0F, width: xlen ~/ 8)], + ), + ]); + return sel; + } + + final byteSel = selFromSize(issueSize).named('byte_sel'); + + // FSM states + final stateIdle = Const(0, width: 3); + final stateRequest = Const(1, width: 3); + final stateWait = Const(2, width: 3); // load waiting for the SQ to drain + final stateStoreDone = Const(3, width: 3); // LSQ store: complete next cycle + final stateForward = Const( + 4, + width: 3, + ); // forwarded load: complete next cyc + + final state = Logic(name: 'mem_state', width: 3); + final savedTag = Logic(name: 'saved_tag', width: robTagBits); + final savedIsStore = Logic(name: 'saved_is_store'); + final savedSize = Logic(name: 'saved_size', width: 3); + final savedSignExtend = Logic(name: 'saved_sign_extend'); + final savedAddr = Logic(name: 'saved_addr', width: xlen); + final savedSel = Logic(name: 'saved_sel', width: xlen ~/ 8); + final savedFwdData = Logic(name: 'saved_fwd_data', width: xlen); + final savedPc = Logic(name: 'saved_pc', width: xlen); + final savedViolation = Logic(name: 'saved_violation'); + + // Combinational result info (valid alongside result_valid for the LSQ). + output('result_is_store') <= savedIsStore; + output('result_addr') <= savedAddr; + output('result_size') <= savedSize; + + // An LSQ store accepted this cycle (pushed into the queue, no bus access). + final isLsqStore = issueIsStore & (lsqStores ? Const(1) : Const(0)); + final acceptLsqStore = issueValid & isLsqStore; + // A load whose value is forwarded from the store queue (no bus access). + final acceptForward = issueValid & ~issueIsStore & fwdHit; + // A load that must wait for the store queue before reading the bus. + final acceptWaitLoad = issueValid & ~issueIsStore & loadStall; + + // Store-fill: expose the pushed store's fields the cycle it is accepted. + storeFillValid <= state.eq(stateIdle) & acceptLsqStore; + storeFillTag <= issueTag; + storeFillAddr <= effectiveAddr; + storeFillData <= issueSrc2; + storeFillSize <= issueSize; + + Sequential(clk, [ + If( + reset | flush, + then: [ + state < stateIdle, + savedTag < 0, + savedIsStore < 0, + savedSize < 0, + savedSignExtend < 0, + savedAddr < 0, + savedSel < 0, + savedFwdData < 0, + savedPc < 0, + savedViolation < 0, + resultValid < 0, + resultTag < 0, + resultData < 0, + resultException < 0, + resultCause < 0, + resultRedirect < 0, + resultTarget < 0, + busy < 0, + wbCyc < 0, + wbStb < 0, + wbWe < 0, + wbAdr < 0, + wbDatMosi < 0, + wbSel < 0, + ], + orElse: [ + Case( + state, + [ + // IDLE: accept new request + CaseItem(stateIdle, [ + resultValid < 0, + resultRedirect < 0, + If( + issueValid, + then: [ + savedTag < issueTag, + savedIsStore < issueIsStore, + savedSize < issueSize, + savedSignExtend < issueSignExtend, + savedAddr < effectiveAddr, + savedSel < byteSel, + savedPc < issuePc, + savedViolation < camViolation, + busy < 1, + If( + acceptLsqStore, + // LSQ store: pushed to the queue (combinationally), no bus + // cycle; complete next cycle. + then: [state < stateStoreDone, wbCyc < 0, wbStb < 0], + orElse: [ + If( + acceptForward, + // Load satisfied by an in-queue store: forward, no bus. + then: [ + state < stateForward, + savedFwdData < fwdData, + wbCyc < 0, + wbStb < 0, + ], + orElse: [ + If( + acceptWaitLoad, + // Load blocked by an undrained store: hold, no bus yet. + then: [state < stateWait, wbCyc < 0, wbStb < 0], + orElse: [ + // Load (clear) or legacy store: start the bus cycle. + state < stateRequest, + wbCyc < 1, + wbStb < 1, + wbWe < issueIsStore, + wbAdr < effectiveAddr, + wbDatMosi < issueSrc2, + wbSel < byteSel, + ], + ), + ], + ), + ], + ), + ], + orElse: [busy < 0, wbCyc < 0, wbStb < 0], + ), + ]), + // STORE_DONE: LSQ store retires its execution (no bus). If it + // violated load ordering, redirect to re-fetch from after it. + CaseItem(stateStoreDone, [ + state < stateIdle, + busy < 0, + resultValid < 1, + resultTag < savedTag, + resultData < 0, + resultException < 0, + resultCause < 0, + resultRedirect < savedViolation, + resultTarget < (savedPc + Const(4, width: xlen)), + ]), + // FORWARD: load completes with the store-queue-forwarded value. + CaseItem(stateForward, [ + state < stateIdle, + busy < 0, + resultValid < 1, + resultTag < savedTag, + resultData < savedFwdData, + resultException < 0, + resultCause < 0, + ]), + // WAIT: load held until the store queue drains. + CaseItem(stateWait, [ + If( + ~loadStall, + then: [ + // SQ drained: now issue the bus read from saved fields. + state < stateRequest, + wbCyc < 1, + wbStb < 1, + wbWe < 0, + wbAdr < savedAddr, + wbDatMosi < 0, + wbSel < savedSel, + ], + ), + ]), + // REQUEST: waiting for ack + CaseItem(stateRequest, [ + If( + wbAck, + then: [ + state < stateIdle, + busy < 0, + wbCyc < 0, + wbStb < 0, + resultValid < 1, + resultTag < savedTag, + resultException < 0, + resultCause < 0, + If( + savedIsStore, + then: [resultData < 0], + orElse: [ + // Load: extract and sign-extend based on size + resultData < wbDatMiso, + ], + ), + ], + orElse: [ + If( + memFault, + then: [ + // MMU page fault (dport done & ~valid). Guest (G-stage) + // = store 23 / load 21; single-stage = store 15 / 13. + state < stateIdle, + busy < 0, + wbCyc < 0, + wbStb < 0, + resultValid < 1, + resultTag < savedTag, + resultData < 0, + resultException < 1, + resultCause < + mux( + memFaultGuest, + mux( + savedIsStore, + Const(23, width: 6), + Const(21, width: 6), + ), + mux( + savedIsStore, + Const(15, width: 6), + Const(13, width: 6), + ), + ), + ], + orElse: [ + If( + wbErr, + then: [ + // Bus error → access fault + state < stateIdle, + busy < 0, + wbCyc < 0, + wbStb < 0, + resultValid < 1, + resultTag < savedTag, + resultData < 0, + resultException < 1, + // Load access fault = 5, Store access fault = 7 + resultCause < + mux( + savedIsStore, + Const(7, width: 6), + Const(5, width: 6), + ), + ], + ), + ], + ), + ], + ), + ]), + ], + defaultItem: [state < stateIdle, busy < 0], + ), + ], + ), + ]); + + // Expose the in-flight access byte count (held in savedSize during REQUEST). + output('wb_size') <= savedSize; + } +} diff --git a/packages/river_hdl/lib/src/core/icache.dart b/packages/river_hdl/lib/src/core/icache.dart new file mode 100644 index 0000000..0086215 --- /dev/null +++ b/packages/river_hdl/lib/src/core/icache.dart @@ -0,0 +1,314 @@ +import 'package:rohd/rohd.dart'; +import 'package:rohd_bridge/rohd_bridge.dart'; +import 'package:harbor/harbor.dart'; + +/// Direct-mapped instruction cache between the fetch unit(s) and the MMU ifetch +/// port. Hit serves one cycle after the address is presented; miss fills the +/// whole line from the MMU one word at a time. Two lookup ports serve both +/// dual-dispatch fetch lanes when their addresses land in the same line. +/// +/// Virtually addressed (pre-translation), so flush on fence.i / satp write. Bare +/// mode is vaddr==paddr, no flush needed. +/// +/// Storage split so it fits a 25F: wide per-line DATA in a [HarborRegisterFile] +/// maps to a block RAM (ECP5 DP16KD) instead of a flop array indexed at runtime +/// (N-way mux + N-way write decoder). Narrow VALID/TAG stay in flops: valid must +/// clear in one cycle for fence.i (a block RAM cannot), tag compare is a few LUTs. +/// +/// Block-RAM read is registered ([HarborRegisterFile.readLatency] forced to 1 so +/// the sim flop model matches the DP16KD). Hit detection compares against a +/// one-cycle-delayed request address ([_addrQ]): the fetcher holds its address +/// until `done`, so last cycle's lookup answers this cycle. `done` is suppressed +/// during a fill and one cycle after commit, so no read crosses a +/// read-after-write to the same block-RAM entry. +class RiverICache extends BridgeModule { + final int xlen; + final int lineWords; // words per cache line + final int numLines; // number of (direct-mapped) lines + final bool dualPort; // second lookup port for dual-dispatch + + // Port 0 response. + Logic get done0 => output('done0'); + Logic get valid0 => output('valid0'); + Logic get rdata0 => output('rdata0'); + // Port 1 response (dual only). + Logic get done1 => output('done1'); + Logic get valid1 => output('valid1'); + Logic get rdata1 => output('rdata1'); + // Downstream MMU ifetch request (misses). + Logic get memEn => output('mem_en'); + Logic get memAddr => output('mem_addr'); + + RiverICache( + Logic clk, + Logic reset, { + required Logic req0En, + required Logic req0Addr, + Logic? req1En, + Logic? req1Addr, + required Logic memDone, + required Logic memValid, + required Logic memRdata, + required Logic flush, + this.xlen = 64, + this.lineWords = 4, + this.numLines = 16, + this.dualPort = false, + // Physical address bits the fetch stream can present. Sizes the tag store + // and compares instead of [xlen], so a tiny cache over a <=32-bit map does + // not pay for a 58-bit tag (upper bits are constant 0 but yosys cannot prove + // the stored tag is zero-extended). Null = xlen. MUST cover every fetchable + // address. + int? physAddrBits, + // FPGA/ASIC target for the data block RAM. Null (sim / std-cell) uses the + // flop backend at the same forced read latency, verifying the registered + // read without the EBR blackbox. + HarborDeviceTarget? target, + String name = 'river_icache', + }) : super('RiverICache', name: name) { + clk = addInput('clk', clk); + reset = addInput('reset', reset); + req0En = addInput('req0_en', req0En); + req0Addr = addInput('req0_addr', req0Addr, width: xlen); + if (dualPort) { + req1En = addInput('req1_en', req1En!); + req1Addr = addInput('req1_addr', req1Addr!, width: xlen); + } + memDone = addInput('mem_done', memDone); + memValid = addInput('mem_valid', memValid); + memRdata = addInput('mem_rdata', memRdata, width: xlen); + flush = addInput('flush', flush); + + addOutput('done0'); + addOutput('valid0'); + addOutput('rdata0', width: xlen); + if (dualPort) { + addOutput('done1'); + addOutput('valid1'); + addOutput('rdata1', width: xlen); + } + addOutput('mem_en'); + addOutput('mem_addr', width: xlen); + + final wordBytes = xlen ~/ 8; + final offBits = (lineWords - 1).bitLength; // bits to index word in line + final idxBits = (numLines - 1).bitLength; // bits to index line + final byteBits = (wordBytes - 1).bitLength; // bits within a word + final tagLo = byteBits + offBits + idxBits; + // Tag spans [paBits-1 : tagLo]. paBits <= xlen; addresses above paBits are + // guaranteed 0 by the memory map, so ignoring them cannot alias. + final reqPa = physAddrBits ?? xlen; + final paBits = reqPa > xlen ? xlen : reqPa; + final tagBits = paBits - tagLo; + + Logic idxOf(Logic addr) => idxBits == 0 + ? Const(0, width: 1) + : addr.slice(byteBits + offBits + idxBits - 1, byteBits + offBits); + Logic tagOf(Logic addr) => addr.slice(paBits - 1, tagLo); + // Combined {line, word} index into the flat data RAM (the whole in-line + // address field, aligned to a word). offBits+idxBits wide. + Logic dataEntryOf(Logic addr) => (offBits + idxBits) == 0 + ? Const(0, width: 1) + : addr.slice(byteBits + offBits + idxBits - 1, byteBits); + + // Per-line VALID + TAG kept in flops: valid must reset/flush in one cycle, + // and the tag compare is cheap. Read combinationally at the (registered) + // index. + final lineValid = List.generate(numLines, (i) => Logic(name: 'valid_$i')); + final lineTag = List.generate( + numLines, + (i) => Logic(name: 'tag_$i', width: tagBits), + ); + + // N-way read of a flop array by line index. + Logic muxLine(List arr, Logic idx) { + var r = arr[0]; + for (var i = 1; i < numLines; i++) { + r = mux(idx.eq(i), arr[i], r); + } + return r; + } + + // Per-line DATA in a block RAM (one read port per lookup port, one shared + // write port for fills). readLatency forced to 1 so the sim flop model + // behaves exactly like the ECP5 DP16KD registered read. + final nEntries = numLines * lineWords; + final dataRam = HarborRegisterFile( + numEntries: nEntries, + dataWidth: xlen, + numReadPorts: dualPort ? 2 : 1, + numWritePorts: 1, + reservedZero: false, + target: target, + forceReadLatency: 1, + name: 'icache_data', + ); + addSubModule(dataRam); + dataRam.input('clk').srcConnection! <= clk; + dataRam.input('reset').srcConnection! <= reset; + dataRam.input('rd0_addr').srcConnection! <= dataEntryOf(req0Addr); + if (dualPort) { + dataRam.input('rd1_addr').srcConnection! <= dataEntryOf(req1Addr!); + } + + // Miss/fill FSM state. + final filling = Logic(name: 'filling'); + // High for one cycle after a fill commits: the just-written line's block-RAM + // entry was the read-during-write target, so its registered read is only + // trustworthy the cycle after. Gates `done` off for that settling cycle. + final fillSettle = Logic(name: 'fillSettle'); + final fillIdx = Logic(name: 'fillIdx', width: idxBits == 0 ? 1 : idxBits); + final fillTag = Logic(name: 'fillTag', width: tagBits); + final fillBase = Logic(name: 'fillBase', width: xlen); + final fillWord = Logic( + name: 'fillWord', + width: (offBits == 0 ? 1 : offBits) + 1, + ); + + // One-cycle-delayed copy of each port's request address: last cycle's + // block-RAM read answers this cycle, so hit detection compares against this. + // req==addrQ means the answer is for the wanted address; req!=addrQ + // suppresses a stale hit and the new lookup answers next cycle. + final addr0Q = Logic(name: 'addr0Q', width: xlen); + final addr1Q = dualPort ? Logic(name: 'addr1Q', width: xlen) : null; + + // A fill or its one-cycle settle blocks any hit response. + final blockHit = (filling | fillSettle).named('blockHit'); + + Logic committedHit(Logic addrQ) => + muxLine(lineValid, idxOf(addrQ)) & + muxLine(lineTag, idxOf(addrQ)).eq(tagOf(addrQ)); + + // A port is "answered" this cycle when its held address matches the one the + // block RAM just looked up. Hit = answered & committed & not blocked. + Logic answered(Logic en, Logic addr, Logic addrQ) => en & addr.eq(addrQ); + + final ans0 = answered(req0En, req0Addr, addr0Q).named('ans0'); + final hit0 = (ans0 & committedHit(addr0Q) & ~blockHit).named('hit0'); + final ans1 = dualPort + ? answered(req1En!, req1Addr!, addr1Q!).named('ans1') + : Const(0); + final hit1 = dualPort + ? (ans1 & committedHit(addr1Q!) & ~blockHit).named('hit1') + : Const(0); + + // A port misses when its lookup is answered but not a hit (and we are idle, + // so the block-RAM read is clean). Port 0 has priority for starting a fill. + final miss0 = (ans0 & ~committedHit(addr0Q) & ~blockHit).named('miss0'); + final miss1 = dualPort + ? (ans1 & ~committedHit(addr1Q!) & ~blockHit).named('miss1') + : Const(0); + final wantFill = miss0 | miss1; + // Fill from the registered (stable, held) address of the missing port. + final fillAddr = mux(miss0, addr0Q, dualPort ? addr1Q! : addr0Q); + + // Line base address (aligned to the line) for the chosen fill addr. + final lineMask = Const( + ((BigInt.one << (byteBits + offBits)) - BigInt.one), + width: xlen, + ); + final fillLineBase = fillAddr & ~lineMask; + + // Drive the MMU request during a fill. + final memEnR = Logic(name: 'memEnR'); + final memAddrR = Logic(name: 'memAddrR', width: xlen); + memEn <= memEnR; + memAddr <= memAddrR; + + // Responses. `done`/`data` are aligned: done from the flop tag compare on + // addrQ, data from the block-RAM read that answers addrQ this cycle. + done0 <= hit0; + valid0 <= hit0; + rdata0 <= dataRam.readData(0); + if (dualPort) { + done1 <= hit1; + valid1 <= hit1; + rdata1 <= dataRam.readData(1); + } + + // Data block-RAM write port: one fill word per MMU response. + final fillWrEn = (filling & memDone & memValid).named('fillWrEn'); + // Write entry = {fillIdx, low offBits of fillWord}. + final Logic fillEntry; + if (offBits == 0) { + fillEntry = fillIdx; + } else if (idxBits == 0) { + fillEntry = fillWord.slice(offBits - 1, 0); + } else { + fillEntry = [fillIdx, fillWord.slice(offBits - 1, 0)].swizzle(); + } + dataRam.input('wr_en').srcConnection! <= fillWrEn; + dataRam.input('wr_addr').srcConnection! <= fillEntry; + dataRam.input('wr_data').srcConnection! <= memRdata; + + final lastWord = Const(lineWords - 1, width: fillWord.width); + + Sequential(clk, [ + // Track the delayed request addresses for the read-latency alignment. + addr0Q < req0Addr, + if (dualPort) addr1Q! < req1Addr!, + If( + reset | flush, + then: [ + ...List.generate(numLines, (i) => lineValid[i] < 0), + filling < 0, + fillSettle < 0, + memEnR < 0, + ], + orElse: [ + fillSettle < 0, + If( + filling, + then: [ + // Awaiting a fill word from the MMU (the write port captures it). + If( + memDone & memValid, + then: [ + If( + fillWord.eq(lastWord), + then: [ + // Last word written this edge: commit the line and finish. + memEnR < 0, + filling < 0, + fillSettle < 1, + ...List.generate( + numLines, + (l) => If( + fillIdx.eq(l), + then: [lineValid[l] < 1, lineTag[l] < fillTag], + ), + ), + ], + orElse: [ + // Next word. + fillWord < fillWord + 1, + memAddrR < + (fillBase + + ((fillWord + 1).zeroExtend(xlen) * + Const(wordBytes, width: xlen))), + ], + ), + ], + ), + ], + orElse: [ + // Idle: start a fill for the highest-priority missing port. + If( + wantFill, + then: [ + filling < 1, + fillIdx < idxOf(fillAddr), + fillTag < tagOf(fillAddr), + fillBase < fillLineBase, + fillWord < 0, + memEnR < 1, + memAddrR < fillLineBase, + ], + ), + ], + ), + ], + ), + ]); + } +} diff --git a/packages/river_hdl/lib/src/core/instruction_aligner.dart b/packages/river_hdl/lib/src/core/instruction_aligner.dart new file mode 100644 index 0000000..adac069 --- /dev/null +++ b/packages/river_hdl/lib/src/core/instruction_aligner.dart @@ -0,0 +1,115 @@ +import 'package:rohd/rohd.dart'; + +/// Variable-length instruction aligner. Extracts up to two instructions per +/// cycle from a halfword window of the instruction stream, handling the RISC-V +/// "C" (compressed) extension where instructions are 2 or 4 bytes. +/// +/// This is the core of a superscalar compressed front-end. Fixed-width dual +/// fetch assumes lane1.pc == lane0.pc + 4. With compressed code lane1.pc is +/// lane0.pc + lane0.size, and the size is only known after decoding lane0's +/// first halfword. The aligner resolves both instruction boundaries +/// combinationally from one buffered window, so each decode lane gets a +/// correctly sized instruction at the right PC. +/// +/// Window model: `halves` is a little-endian pack of [laneCount] 16-bit +/// halfwords, halfword 0 being the lowest address (the current 2-byte-aligned +/// fetch PC). `validHalves` is how many of them hold real stream bytes (the rest +/// are past the fetched or redirect boundary). A 32-bit instruction takes two +/// consecutive halfwords, a compressed one takes one. Resolving two back-to-back +/// 4-byte instructions needs 4 halfwords, so [laneCount] must be >= 4. +class InstructionAligner extends Module { + /// First (lane-0) instruction, its size in HALFWORDS (1=compressed, 2=32-bit), + /// whether it is compressed, and whether it is fully present in the window. + Logic get instr0 => output('instr0'); + Logic get size0 => output('size0'); // 1 or 2 (halfwords) + Logic get compressed0 => output('compressed0'); + Logic get valid0 => output('valid0'); + + /// Second (lane-1) instruction, the one starting at PC + size0*2. + Logic get instr1 => output('instr1'); + Logic get size1 => output('size1'); + Logic get compressed1 => output('compressed1'); + Logic get valid1 => output('valid1'); + + final int laneCount; + + InstructionAligner( + Logic halves, + Logic validHalves, { + this.laneCount = 4, + super.name = 'instruction_aligner', + }) : super(definitionName: 'InstructionAligner') { + assert( + laneCount >= 4, + 'aligner needs >= 4 halfwords to resolve two 32-bit ' + 'instructions (got $laneCount)', + ); + final cntW = validHalves.width; + halves = addInput('halves', halves, width: laneCount * 16); + validHalves = addInput('valid_halves', validHalves, width: cntW); + + addOutput('instr0', width: 32); + addOutput('size0', width: 2); + addOutput('compressed0'); + addOutput('valid0'); + addOutput('instr1', width: 32); + addOutput('size1', width: 2); + addOutput('compressed1'); + addOutput('valid1'); + + // Split the window into halfwords (hw[0] = lowest address). + final hw = [ + for (var i = 0; i < laneCount; i++) halves.slice(16 * i + 15, 16 * i), + ]; + + Logic isComp(Logic half) => half.slice(1, 0).neq(0x3); + // Select halfword[idx] from the window by a small constant-or-dynamic index. + Logic hwAt(Logic idx) { + Logic r = hw[0]; + for (var i = 1; i < laneCount; i++) { + r = mux(idx.eq(Const(i, width: idx.width)), hw[i], r); + } + return r; + } + + // Lane 0 starts at halfword 0. hasHw0 gates the size/compressed decode: with + // no valid halfword, hw[0] is unfetched (X) so comp0/s0 are X. AND-ing the + // guard first keeps v0 a clean 0 (0 & X == 0), never X, which matters because + // v0 feeds a pipeline register that an X would poison. + final hasHw0 = validHalves.gte(Const(1, width: cntW)).named('hasHw0'); + final comp0 = isComp(hw[0]).named('comp0'); + final i0 = mux( + comp0, + hw[0].zeroExtend(32), + [hw[1], hw[0]].swizzle(), + ).named('i0'); + final s0 = mux(comp0, Const(1, width: 2), Const(2, width: 2)).named('s0'); + // Fully present iff the first halfword is valid AND the window holds >= s0. + final v0 = (hasHw0 & s0.zeroExtend(cntW).lte(validHalves)).named('v0'); + + // Lane 1 starts at halfword s0 (1 or 2). + final base1 = s0 + .zeroExtend(cntW) + .named('base1'); // halfword index of instr1 + final lo1 = hwAt(base1).named('lo1'); + final hi1 = hwAt((base1 + 1).named('base1p1')).named('hi1'); + final comp1 = isComp(lo1).named('comp1'); + final i1 = mux(comp1, lo1.zeroExtend(32), [hi1, lo1].swizzle()).named('i1'); + final s1 = mux(comp1, Const(1, width: 2), Const(2, width: 2)).named('s1'); + // hasLo1 gates lane-1 decode the same way: comp1/s1 are only meaningful when + // instr1's first halfword is inside the valid window (base1 < validHalves). + // With lane 0 present and that guard, v1 stays a clean 0 when short. + final hasLo1 = (v0 & base1.lt(validHalves)).named('hasLo1'); + final need1 = (base1 + s1.zeroExtend(cntW)).named('need1'); + final v1 = (hasLo1 & need1.lte(validHalves)).named('v1'); + + instr0 <= i0; + size0 <= s0; + compressed0 <= comp0; + valid0 <= v0; + instr1 <= i1; + size1 <= s1; + compressed1 <= comp1; + valid1 <= v1; + } +} diff --git a/packages/river_hdl/lib/src/core/int.dart b/packages/river_hdl/lib/src/core/int.dart index d166656..66c9b30 100644 --- a/packages/river_hdl/lib/src/core/int.dart +++ b/packages/river_hdl/lib/src/core/int.dart @@ -54,7 +54,6 @@ class RiscVInterruptController extends Module { static const int _prioBase = 0x0000; static const int _pendBase = 0x1000; - static const int _enBase = 0x2000; static const int _ctxBase = 0x3000; static const int _ctxStride = 0x100; diff --git a/packages/river_hdl/lib/src/core/issue.dart b/packages/river_hdl/lib/src/core/issue.dart new file mode 100644 index 0000000..891937e --- /dev/null +++ b/packages/river_hdl/lib/src/core/issue.dart @@ -0,0 +1,1013 @@ +import 'package:rohd/rohd.dart'; + +/// Functional unit type classification for dispatch. +enum FuType { alu, memory, branch, csr } + +/// Issue queue entry width decomposition. +class IssueEntry { + final int xlen; + final int robTagBits; + + const IssueEntry({required this.xlen, this.robTagBits = 7}); + + // Packed fields (LSB-first): + // robTag [robTagBits] + // psrc1 [7] + // psrc2 [7] + // pdst [7] + // src1Ready [1] + // src2Ready [1] + // src1Value [xlen] + // src2Value [xlen] + // imm [xlen] + // pc [xlen] + // funct [5] + // fuType [2] + // isStore [1] + // memSize [3] + // branchCond [3] + // isJump [1] + // isJalr [1] + // useImm [1] + // writesRd [1] + // csrOp [3] + // csrAddr [12] + // signExtend [1] + // valid [1] + + int get width => + robTagBits + + 7 + + 7 + + 7 + + 1 + + 1 + + xlen * 4 + + 5 + + 2 + + 1 + + 3 + + 3 + + 1 + + 1 + + 1 + + 1 + + 3 + + 12 + + 1 + + 1; +} + +/// Issue queue with wake-up and select logic for dual-issue dispatch. +/// +/// Accepts up to 2 instructions per cycle from the rename stage. +/// Dispatches up to 2 instructions per cycle to functional units when +/// all source operands are ready (via register read or result bypass). +class IssueQueue extends Module { + /// Number of issue queue entries. + final int depth; + + /// XLEN of the core. + final int xlen; + + /// Physical register index width. + final int physRegBits; + + /// ROB tag width. + final int robTagBits; + + /// Whether memory ops dispatch strictly in program order (LSQ mode). + final bool inOrderMem; + + /// Whether loads may speculatively dispatch ahead of not-ready older stores. + final bool speculativeMem; + + // -- Enqueue output -- + + Logic get enqReady => output('enq_ready'); + + // -- Dispatch ports (to functional units) -- + + /// ALU dispatch slot 0. + Logic get dispatchAluValid0 => output('dispatch_alu_valid_0'); + Logic get dispatchAluTag0 => output('dispatch_alu_tag_0'); + Logic get dispatchAluSrc10 => output('dispatch_alu_src1_0'); + Logic get dispatchAluSrc20 => output('dispatch_alu_src2_0'); + Logic get dispatchAluImm0 => output('dispatch_alu_imm_0'); + Logic get dispatchAluFunct0 => output('dispatch_alu_funct_0'); + Logic get dispatchAluUseImm0 => output('dispatch_alu_use_imm_0'); + Logic get dispatchAluPc0 => output('dispatch_alu_pc_0'); + + /// ALU dispatch slot 1 (dual-issue: second ALU). + Logic get dispatchAluValid1 => output('dispatch_alu_valid_1'); + Logic get dispatchAluTag1 => output('dispatch_alu_tag_1'); + Logic get dispatchAluSrc11 => output('dispatch_alu_src1_1'); + Logic get dispatchAluSrc21 => output('dispatch_alu_src2_1'); + Logic get dispatchAluImm1 => output('dispatch_alu_imm_1'); + Logic get dispatchAluFunct1 => output('dispatch_alu_funct_1'); + Logic get dispatchAluUseImm1 => output('dispatch_alu_use_imm_1'); + Logic get dispatchAluPc1 => output('dispatch_alu_pc_1'); + + /// Memory dispatch. + Logic get dispatchMemValid => output('dispatch_mem_valid'); + Logic get dispatchMemTag => output('dispatch_mem_tag'); + Logic get dispatchMemSrc1 => output('dispatch_mem_src1'); + Logic get dispatchMemSrc2 => output('dispatch_mem_src2'); + Logic get dispatchMemImm => output('dispatch_mem_imm'); + Logic get dispatchMemIsStore => output('dispatch_mem_is_store'); + Logic get dispatchMemSize => output('dispatch_mem_size'); + Logic get dispatchMemSignExtend => output('dispatch_mem_sign_extend'); + Logic get dispatchMemPc => output('dispatch_mem_pc'); + + /// Branch dispatch. + Logic get dispatchBranchValid => output('dispatch_branch_valid'); + Logic get dispatchBranchTag => output('dispatch_branch_tag'); + Logic get dispatchBranchSrc1 => output('dispatch_branch_src1'); + Logic get dispatchBranchSrc2 => output('dispatch_branch_src2'); + Logic get dispatchBranchImm => output('dispatch_branch_imm'); + Logic get dispatchBranchPc => output('dispatch_branch_pc'); + Logic get dispatchBranchCondition => output('dispatch_branch_condition'); + Logic get dispatchBranchIsJump => output('dispatch_branch_is_jump'); + Logic get dispatchBranchIsJalr => output('dispatch_branch_is_jalr'); + + /// CSR dispatch. + Logic get dispatchCsrValid => output('dispatch_csr_valid'); + Logic get dispatchCsrTag => output('dispatch_csr_tag'); + Logic get dispatchCsrSrc1 => output('dispatch_csr_src1'); + Logic get dispatchCsrImm => output('dispatch_csr_imm'); + Logic get dispatchCsrOp => output('dispatch_csr_op'); + Logic get dispatchCsrAddr => output('dispatch_csr_addr'); + + IssueQueue( + Logic clk, + Logic reset, { + // Enqueue slot 0 + required Logic enqValid0, + required Logic enqTag0, + required Logic enqPsrc10, + required Logic enqPsrc20, + required Logic enqPdst0, + required Logic enqImm0, + required Logic enqPc0, + required Logic enqFunct0, + required Logic enqFuType0, + required Logic enqWritesRd0, + required Logic enqIsStore0, + required Logic enqMemSize0, + required Logic enqBranchCond0, + required Logic enqIsJump0, + required Logic enqIsJalr0, + required Logic enqUseImm0, + required Logic enqCsrOp0, + required Logic enqCsrAddr0, + required Logic enqSignExtend0, + // Enqueue slot 1 + required Logic enqValid1, + required Logic enqTag1, + required Logic enqPsrc11, + required Logic enqPsrc21, + required Logic enqPdst1, + required Logic enqImm1, + required Logic enqPc1, + required Logic enqFunct1, + required Logic enqFuType1, + required Logic enqWritesRd1, + required Logic enqIsStore1, + required Logic enqMemSize1, + required Logic enqBranchCond1, + required Logic enqIsJump1, + required Logic enqIsJalr1, + required Logic enqUseImm1, + required Logic enqCsrOp1, + required Logic enqCsrAddr1, + required Logic enqSignExtend1, + // Operand values from physical register file + required Logic enqSrc1Value0, + required Logic enqSrc2Value0, + required Logic enqSrc1Ready0, + required Logic enqSrc2Ready0, + required Logic enqSrc1Value1, + required Logic enqSrc2Value1, + required Logic enqSrc1Ready1, + required Logic enqSrc2Ready1, + // Wakeup signals + required Logic wakeupValid0, + required Logic wakeupTag0, + required Logic wakeupValue0, + required Logic wakeupValid1, + required Logic wakeupTag1, + required Logic wakeupValue1, + // Optional 3rd wakeup port (dual-dispatch: ALU1 and the branch/CSR unit can + // otherwise complete the same cycle and collide on a shared port, dropping a + // wakeup → a waiting dependent never fires → deadlock). + Logic? wakeupValid2, + Logic? wakeupTag2, + Logic? wakeupValue2, + // FU busy signals + required Logic aluBusy0, + required Logic aluBusy1, + required Logic memBusy, + required Logic branchBusy, + required Logic csrBusy, + // Flush + required Logic flush, + // When true, memory ops dispatch in program order (oldest ready memory op + // first), required by the store queue so its entries are always older than + // any executing load. A store is held when [sqFull]. + this.inOrderMem = false, + // When true (speculative LSQ), a load may dispatch ahead of a not-ready + // older store (stores still dispatch in program order; loads are ordered + // only against older loads). Takes precedence over [inOrderMem]. + this.speculativeMem = false, + Logic? sqFull, + this.depth = 16, + this.xlen = 64, + this.physRegBits = 7, + this.robTagBits = 7, + super.name = 'issue_queue', + }) : super(definitionName: 'IssueQueue') { + clk = addInput('clk', clk); + reset = addInput('reset', reset); + + // Enqueue inputs (dual-issue from rename), slot 0 + enqValid0 = addInput('enq_valid_0', enqValid0); + enqTag0 = addInput('enq_tag_0', enqTag0, width: robTagBits); + enqPsrc10 = addInput('enq_psrc1_0', enqPsrc10, width: physRegBits); + enqPsrc20 = addInput('enq_psrc2_0', enqPsrc20, width: physRegBits); + enqPdst0 = addInput('enq_pdst_0', enqPdst0, width: physRegBits); + enqImm0 = addInput('enq_imm_0', enqImm0, width: xlen); + enqPc0 = addInput('enq_pc_0', enqPc0, width: xlen); + enqFunct0 = addInput('enq_funct_0', enqFunct0, width: 7); + enqFuType0 = addInput('enq_fu_type_0', enqFuType0, width: 2); + enqWritesRd0 = addInput('enq_writes_rd_0', enqWritesRd0); + enqIsStore0 = addInput('enq_is_store_0', enqIsStore0); + enqMemSize0 = addInput('enq_mem_size_0', enqMemSize0, width: 3); + enqBranchCond0 = addInput('enq_branch_cond_0', enqBranchCond0, width: 3); + enqIsJump0 = addInput('enq_is_jump_0', enqIsJump0); + enqIsJalr0 = addInput('enq_is_jalr_0', enqIsJalr0); + enqUseImm0 = addInput('enq_use_imm_0', enqUseImm0); + enqCsrOp0 = addInput('enq_csr_op_0', enqCsrOp0, width: 3); + enqCsrAddr0 = addInput('enq_csr_addr_0', enqCsrAddr0, width: 12); + enqSignExtend0 = addInput('enq_sign_extend_0', enqSignExtend0); + + // Enqueue inputs, slot 1 + enqValid1 = addInput('enq_valid_1', enqValid1); + enqTag1 = addInput('enq_tag_1', enqTag1, width: robTagBits); + enqPsrc11 = addInput('enq_psrc1_1', enqPsrc11, width: physRegBits); + enqPsrc21 = addInput('enq_psrc2_1', enqPsrc21, width: physRegBits); + enqPdst1 = addInput('enq_pdst_1', enqPdst1, width: physRegBits); + enqImm1 = addInput('enq_imm_1', enqImm1, width: xlen); + enqPc1 = addInput('enq_pc_1', enqPc1, width: xlen); + enqFunct1 = addInput('enq_funct_1', enqFunct1, width: 7); + enqFuType1 = addInput('enq_fu_type_1', enqFuType1, width: 2); + enqWritesRd1 = addInput('enq_writes_rd_1', enqWritesRd1); + enqIsStore1 = addInput('enq_is_store_1', enqIsStore1); + enqMemSize1 = addInput('enq_mem_size_1', enqMemSize1, width: 3); + enqBranchCond1 = addInput('enq_branch_cond_1', enqBranchCond1, width: 3); + enqIsJump1 = addInput('enq_is_jump_1', enqIsJump1); + enqIsJalr1 = addInput('enq_is_jalr_1', enqIsJalr1); + enqUseImm1 = addInput('enq_use_imm_1', enqUseImm1); + enqCsrOp1 = addInput('enq_csr_op_1', enqCsrOp1, width: 3); + enqCsrAddr1 = addInput('enq_csr_addr_1', enqCsrAddr1, width: 12); + enqSignExtend1 = addInput('enq_sign_extend_1', enqSignExtend1); + + // Operand values from physical register file + enqSrc1Value0 = addInput('enq_src1_value_0', enqSrc1Value0, width: xlen); + enqSrc2Value0 = addInput('enq_src2_value_0', enqSrc2Value0, width: xlen); + enqSrc1Ready0 = addInput('enq_src1_ready_0', enqSrc1Ready0); + enqSrc2Ready0 = addInput('enq_src2_ready_0', enqSrc2Ready0); + + enqSrc1Value1 = addInput('enq_src1_value_1', enqSrc1Value1, width: xlen); + enqSrc2Value1 = addInput('enq_src2_value_1', enqSrc2Value1, width: xlen); + enqSrc1Ready1 = addInput('enq_src1_ready_1', enqSrc1Ready1); + enqSrc2Ready1 = addInput('enq_src2_ready_1', enqSrc2Ready1); + + // Wake-up broadcast from functional unit results (for in-flight entries) + wakeupValid0 = addInput('wakeup_valid_0', wakeupValid0); + wakeupTag0 = addInput('wakeup_tag_0', wakeupTag0, width: physRegBits); + wakeupValue0 = addInput('wakeup_value_0', wakeupValue0, width: xlen); + + wakeupValid1 = addInput('wakeup_valid_1', wakeupValid1); + wakeupTag1 = addInput('wakeup_tag_1', wakeupTag1, width: physRegBits); + wakeupValue1 = addInput('wakeup_value_1', wakeupValue1, width: xlen); + final wuV2 = addInput('wakeup_valid_2', wakeupValid2 ?? Const(0)); + final wuT2 = addInput( + 'wakeup_tag_2', + wakeupTag2 ?? Const(0, width: physRegBits), + width: physRegBits, + ); + final wuVal2 = addInput( + 'wakeup_value_2', + wakeupValue2 ?? Const(0, width: xlen), + width: xlen, + ); + + // FU busy signals + aluBusy0 = addInput('alu_busy_0', aluBusy0); + aluBusy1 = addInput('alu_busy_1', aluBusy1); + memBusy = addInput('mem_busy', memBusy); + branchBusy = addInput('branch_busy', branchBusy); + csrBusy = addInput('csr_busy', csrBusy); + final sqFullIn = addInput('sq_full', sqFull ?? Const(0)); + + // Flush + flush = addInput('flush', flush); + + // Enqueue ready output + addOutput('enq_ready'); + + // Dispatch outputs, ALU slot 0 + addOutput('dispatch_alu_valid_0'); + addOutput('dispatch_alu_tag_0', width: robTagBits); + addOutput('dispatch_alu_src1_0', width: xlen); + addOutput('dispatch_alu_src2_0', width: xlen); + addOutput('dispatch_alu_imm_0', width: xlen); + addOutput('dispatch_alu_funct_0', width: 7); + addOutput('dispatch_alu_use_imm_0'); + addOutput('dispatch_alu_pc_0', width: xlen); + + // Dispatch outputs, ALU slot 1 + addOutput('dispatch_alu_valid_1'); + addOutput('dispatch_alu_tag_1', width: robTagBits); + addOutput('dispatch_alu_src1_1', width: xlen); + addOutput('dispatch_alu_src2_1', width: xlen); + addOutput('dispatch_alu_imm_1', width: xlen); + addOutput('dispatch_alu_funct_1', width: 7); + addOutput('dispatch_alu_use_imm_1'); + addOutput('dispatch_alu_pc_1', width: xlen); + + // Dispatch outputs, Memory + addOutput('dispatch_mem_valid'); + addOutput('dispatch_mem_tag', width: robTagBits); + addOutput('dispatch_mem_src1', width: xlen); + addOutput('dispatch_mem_src2', width: xlen); + addOutput('dispatch_mem_imm', width: xlen); + addOutput('dispatch_mem_is_store'); + addOutput('dispatch_mem_size', width: 3); + addOutput('dispatch_mem_sign_extend'); + addOutput('dispatch_mem_pc', width: xlen); + + // Dispatch outputs, Branch + addOutput('dispatch_branch_valid'); + addOutput('dispatch_branch_tag', width: robTagBits); + addOutput('dispatch_branch_src1', width: xlen); + addOutput('dispatch_branch_src2', width: xlen); + addOutput('dispatch_branch_imm', width: xlen); + addOutput('dispatch_branch_pc', width: xlen); + addOutput('dispatch_branch_condition', width: 3); + addOutput('dispatch_branch_is_jump'); + addOutput('dispatch_branch_is_jalr'); + + // Dispatch outputs, CSR + addOutput('dispatch_csr_valid'); + addOutput('dispatch_csr_tag', width: robTagBits); + addOutput('dispatch_csr_src1', width: xlen); + addOutput('dispatch_csr_imm', width: xlen); + addOutput('dispatch_csr_op', width: 3); + addOutput('dispatch_csr_addr', width: 12); + + // -- Internal storage -- + // Simplified: use per-field arrays instead of packed entries for readability. + + final entryValid = List.generate(depth, (i) => Logic(name: 'iq_valid_$i')); + final entryTag = List.generate( + depth, + (i) => Logic(name: 'iq_tag_$i', width: robTagBits), + ); + final entryFuType = List.generate( + depth, + (i) => Logic(name: 'iq_futype_$i', width: 2), + ); + final entrySrc1Ready = List.generate( + depth, + (i) => Logic(name: 'iq_s1rdy_$i'), + ); + final entrySrc2Ready = List.generate( + depth, + (i) => Logic(name: 'iq_s2rdy_$i'), + ); + final entrySrc1Value = List.generate( + depth, + (i) => Logic(name: 'iq_s1val_$i', width: xlen), + ); + final entrySrc2Value = List.generate( + depth, + (i) => Logic(name: 'iq_s2val_$i', width: xlen), + ); + final entryPsrc1 = List.generate( + depth, + (i) => Logic(name: 'iq_psrc1_$i', width: physRegBits), + ); + final entryPsrc2 = List.generate( + depth, + (i) => Logic(name: 'iq_psrc2_$i', width: physRegBits), + ); + final entryImm = List.generate( + depth, + (i) => Logic(name: 'iq_imm_$i', width: xlen), + ); + final entryPc = List.generate( + depth, + (i) => Logic(name: 'iq_pc_$i', width: xlen), + ); + final entryFunct = List.generate( + depth, + (i) => Logic(name: 'iq_funct_$i', width: 7), + ); + final entryIsStore = List.generate( + depth, + (i) => Logic(name: 'iq_isstore_$i'), + ); + final entryMemSize = List.generate( + depth, + (i) => Logic(name: 'iq_memsize_$i', width: 3), + ); + final entryBranchCond = List.generate( + depth, + (i) => Logic(name: 'iq_brcond_$i', width: 3), + ); + final entryIsJump = List.generate( + depth, + (i) => Logic(name: 'iq_isjump_$i'), + ); + final entryIsJalr = List.generate( + depth, + (i) => Logic(name: 'iq_isjalr_$i'), + ); + final entryUseImm = List.generate( + depth, + (i) => Logic(name: 'iq_useimm_$i'), + ); + final entryCsrOp = List.generate( + depth, + (i) => Logic(name: 'iq_csrop_$i', width: 3), + ); + final entryCsrAddr = List.generate( + depth, + (i) => Logic(name: 'iq_csraddr_$i', width: 12), + ); + final entrySignExtend = List.generate( + depth, + (i) => Logic(name: 'iq_signext_$i'), + ); + // Per-entry program-order sequence number (LSQ in-order mem dispatch). An + // 8-bit counter assigned at enqueue; the in-flight window (<= depth) is far + // below 128, so a signed difference orders any two entries unambiguously. + final entrySeq = List.generate( + depth, + (i) => Logic(name: 'iq_seq_$i', width: 8), + ); + final seqCtr = Logic(name: 'iq_seq_ctr', width: 8); + + // Count of valid entries + final count = Logic(name: 'iq_count', width: (depth + 1).bitLength); + + // Ready: can accept 2 entries + enqReady <= count.lt(Const(depth - 1, width: count.width)); + + // Find free slots for enqueue (first two invalid entries) + final freeSlot0 = Logic(name: 'free_slot_0', width: depth.bitLength); + final freeSlot1 = Logic(name: 'free_slot_1', width: depth.bitLength); + final freeFound0 = Logic(name: 'free_found_0'); + final freeFound1 = Logic(name: 'free_found_1'); + + // Combinational priority encoder for free slots + final freeSlotConds0 = []; + final freeSlotConds1 = []; + + // Build priority chain for slot 0 + freeSlotConds0.add( + Iff(~entryValid[0], [ + freeSlot0 < Const(0, width: depth.bitLength), + freeFound0 < 1, + ]), + ); + for (var i = 1; i < depth; i++) { + freeSlotConds0.add( + ElseIf(~entryValid[i], [ + freeSlot0 < Const(i, width: depth.bitLength), + freeFound0 < 1, + ]), + ); + } + freeSlotConds0.add(Else([freeSlot0 < 0, freeFound0 < 0])); + + Combinational([If.block(freeSlotConds0)]); + + // Build priority chain for slot 1 (skip slot 0's pick) + // This is simplified: in real hardware, would be a proper second encoder + freeSlotConds1.add(Iff(Const(0), [freeSlot1 < 0, freeFound1 < 0])); + for (var i = 0; i < depth; i++) { + freeSlotConds1.add( + ElseIf( + ~entryValid[i] & ~freeSlot0.eq(Const(i, width: depth.bitLength)), + [freeSlot1 < Const(i, width: depth.bitLength), freeFound1 < 1], + ), + ); + } + freeSlotConds1.add(Else([freeSlot1 < 0, freeFound1 < 0])); + + Combinational([If.block(freeSlotConds1)]); + + // ----------------------------------------------------------------------- + // Combinational dispatch: find oldest ready entry per FU type + // ----------------------------------------------------------------------- + + // An entry is ready to dispatch when valid, both sources ready, and FU free + final entryReady = List.generate( + depth, + (i) => (entryValid[i] & entrySrc1Ready[i] & entrySrc2Ready[i]).named( + 'iq_ready_$i', + ), + ); + + // ALU type = 0 + final aluType = Const(FuType.alu.index, width: 2); + final memType = Const(FuType.memory.index, width: 2); + final branchType = Const(FuType.branch.index, width: 2); + final csrType = Const(FuType.csr.index, width: 2); + + // Dispatch index for each FU (priority encoder: lowest index wins) + final dispAlu0Idx = Logic(name: 'disp_alu0_idx', width: depth.bitLength); + final dispAlu0Found = Logic(name: 'disp_alu0_found'); + final dispAlu1Idx = Logic(name: 'disp_alu1_idx', width: depth.bitLength); + final dispAlu1Found = Logic(name: 'disp_alu1_found'); + final dispMemIdx = Logic(name: 'disp_mem_idx', width: depth.bitLength); + final dispMemFound = Logic(name: 'disp_mem_found'); + final dispBranchIdx = Logic( + name: 'disp_branch_idx', + width: depth.bitLength, + ); + final dispBranchFound = Logic(name: 'disp_branch_found'); + final dispCsrIdx = Logic(name: 'disp_csr_idx', width: depth.bitLength); + final dispCsrFound = Logic(name: 'disp_csr_found'); + + // Priority encoder for ALU slot 0 + final alu0Conds = []; + for (var i = 0; i < depth; i++) { + final cond = entryReady[i] & entryFuType[i].eq(aluType) & ~aluBusy0; + if (i == 0) { + alu0Conds.add( + Iff(cond, [ + dispAlu0Idx < Const(i, width: depth.bitLength), + dispAlu0Found < 1, + ]), + ); + } else { + alu0Conds.add( + ElseIf(cond, [ + dispAlu0Idx < Const(i, width: depth.bitLength), + dispAlu0Found < 1, + ]), + ); + } + } + alu0Conds.add(Else([dispAlu0Idx < 0, dispAlu0Found < 0])); + Combinational([If.block(alu0Conds)]); + + // Priority encoder for ALU slot 1 (skip ALU0's pick) + final alu1Conds = []; + alu1Conds.add(Iff(Const(0), [dispAlu1Idx < 0, dispAlu1Found < 0])); + for (var i = 0; i < depth; i++) { + final cond = + entryReady[i] & + entryFuType[i].eq(aluType) & + ~aluBusy1 & + ~dispAlu0Idx.eq(Const(i, width: depth.bitLength)); + alu1Conds.add( + ElseIf(cond, [ + dispAlu1Idx < Const(i, width: depth.bitLength), + dispAlu1Found < 1, + ]), + ); + } + alu1Conds.add(Else([dispAlu1Idx < 0, dispAlu1Found < 0])); + Combinational([If.block(alu1Conds)]); + + // Memory dispatch select. + if (speculativeMem) { + // Speculative LSQ: a store is eligible only as the oldest undispatched + // store (program-order store↔store) and with queue room; a load is + // eligible as the oldest undispatched load, it may bypass a not-ready + // older store. Among eligible memory ops, dispatch the oldest. + final elig = []; + for (var i = 0; i < depth; i++) { + final isMemI = entryValid[i] & entryFuType[i].eq(memType); + final isStoreI = isMemI & entryIsStore[i]; + final isLoadI = isMemI & ~entryIsStore[i]; + Logic anyOlderStore = Const(0); + Logic anyOlderLoad = Const(0); + for (var j = 0; j < depth; j++) { + if (j == i) continue; + final isMemJ = entryValid[j] & entryFuType[j].eq(memType); + final jOlder = isMemJ & (entrySeq[j] - entrySeq[i])[7]; + anyOlderStore = anyOlderStore | (jOlder & entryIsStore[j]); + anyOlderLoad = anyOlderLoad | (jOlder & ~entryIsStore[j]); + } + final eligStore = isStoreI & ~anyOlderStore & ~sqFullIn; + final eligLoad = isLoadI & ~anyOlderLoad; + elig.add(((eligStore | eligLoad) & entryReady[i]).named('iq_melig_$i')); + } + final memConds = []; + for (var i = 0; i < depth; i++) { + Logic anyOlderElig = Const(0); + for (var j = 0; j < depth; j++) { + if (j == i) continue; + anyOlderElig = + anyOlderElig | (elig[j] & (entrySeq[j] - entrySeq[i])[7]); + } + final cond = elig[i] & ~anyOlderElig & ~memBusy; + memConds.add( + i == 0 + ? Iff(cond, [ + dispMemIdx < Const(i, width: depth.bitLength), + dispMemFound < 1, + ]) + : ElseIf(cond, [ + dispMemIdx < Const(i, width: depth.bitLength), + dispMemFound < 1, + ]), + ); + } + memConds.add(Else([dispMemIdx < 0, dispMemFound < 0])); + Combinational([If.block(memConds)]); + } else if (!inOrderMem) { + // Default: priority encoder by entry index (memory ops may reorder). + final memConds = []; + for (var i = 0; i < depth; i++) { + final cond = entryReady[i] & entryFuType[i].eq(memType) & ~memBusy; + if (i == 0) { + memConds.add( + Iff(cond, [ + dispMemIdx < Const(i, width: depth.bitLength), + dispMemFound < 1, + ]), + ); + } else { + memConds.add( + ElseIf(cond, [ + dispMemIdx < Const(i, width: depth.bitLength), + dispMemFound < 1, + ]), + ); + } + } + memConds.add(Else([dispMemIdx < 0, dispMemFound < 0])); + Combinational([If.block(memConds)]); + } else { + // LSQ mode: dispatch the OLDEST memory op (smallest program-order seq), + // and only when it is ready, a not-ready older memory op blocks younger + // ones. This keeps the store queue holding strictly older stores than any + // executing load, and serializes memory in program order. A store is also + // gated on store-queue room (~sqFull) so it never dispatches with no slot. + // + // Per entry: it is the oldest memory op iff no other valid memory entry + // has an older sequence number. Exactly one valid memory entry satisfies + // this, so a plain OR over (isOldest & ready & ...) selects it. + final memConds = []; + for (var i = 0; i < depth; i++) { + final isMemI = entryValid[i] & entryFuType[i].eq(memType); + // Is any other valid memory entry older (smaller seq) than entry i? + Logic anyOlder = Const(0); + for (var j = 0; j < depth; j++) { + if (j == i) continue; + final isMemJ = entryValid[j] & entryFuType[j].eq(memType); + // j older than i: signed 8-bit (seq[j] - seq[i]) is negative. + final jOlder = isMemJ & (entrySeq[j] - entrySeq[i])[7]; + anyOlder = anyOlder | jOlder; + } + final isOldest = isMemI & ~anyOlder; + final storeOk = ~entryIsStore[i] | ~sqFullIn; + final cond = isOldest & entryReady[i] & ~memBusy & storeOk; + if (i == 0) { + memConds.add( + Iff(cond, [ + dispMemIdx < Const(i, width: depth.bitLength), + dispMemFound < 1, + ]), + ); + } else { + memConds.add( + ElseIf(cond, [ + dispMemIdx < Const(i, width: depth.bitLength), + dispMemFound < 1, + ]), + ); + } + } + memConds.add(Else([dispMemIdx < 0, dispMemFound < 0])); + Combinational([If.block(memConds)]); + } + + // Priority encoder for branch + final branchConds = []; + for (var i = 0; i < depth; i++) { + final cond = entryReady[i] & entryFuType[i].eq(branchType) & ~branchBusy; + if (i == 0) { + branchConds.add( + Iff(cond, [ + dispBranchIdx < Const(i, width: depth.bitLength), + dispBranchFound < 1, + ]), + ); + } else { + branchConds.add( + ElseIf(cond, [ + dispBranchIdx < Const(i, width: depth.bitLength), + dispBranchFound < 1, + ]), + ); + } + } + branchConds.add(Else([dispBranchIdx < 0, dispBranchFound < 0])); + Combinational([If.block(branchConds)]); + + // Priority encoder for CSR + final csrConds = []; + for (var i = 0; i < depth; i++) { + final cond = entryReady[i] & entryFuType[i].eq(csrType) & ~csrBusy; + if (i == 0) { + csrConds.add( + Iff(cond, [ + dispCsrIdx < Const(i, width: depth.bitLength), + dispCsrFound < 1, + ]), + ); + } else { + csrConds.add( + ElseIf(cond, [ + dispCsrIdx < Const(i, width: depth.bitLength), + dispCsrFound < 1, + ]), + ); + } + } + csrConds.add(Else([dispCsrIdx < 0, dispCsrFound < 0])); + Combinational([If.block(csrConds)]); + + // Helper: mux an entry field by dispatch index + Logic muxField(List field, Logic idx) { + Logic result = field[0]; + for (var i = 1; i < depth; i++) { + result = mux( + idx.eq(Const(i, width: depth.bitLength)), + field[i], + result, + ); + } + return result; + } + + // Drive ALU 0 dispatch outputs + dispatchAluValid0 <= dispAlu0Found; + output('dispatch_alu_tag_0') <= muxField(entryTag, dispAlu0Idx); + output('dispatch_alu_src1_0') <= muxField(entrySrc1Value, dispAlu0Idx); + output('dispatch_alu_src2_0') <= muxField(entrySrc2Value, dispAlu0Idx); + output('dispatch_alu_imm_0') <= muxField(entryImm, dispAlu0Idx); + output('dispatch_alu_funct_0') <= muxField(entryFunct, dispAlu0Idx); + output('dispatch_alu_use_imm_0') <= muxField(entryUseImm, dispAlu0Idx); + output('dispatch_alu_pc_0') <= muxField(entryPc, dispAlu0Idx); + + // Drive ALU 1 dispatch outputs + dispatchAluValid1 <= dispAlu1Found; + output('dispatch_alu_tag_1') <= muxField(entryTag, dispAlu1Idx); + output('dispatch_alu_src1_1') <= muxField(entrySrc1Value, dispAlu1Idx); + output('dispatch_alu_src2_1') <= muxField(entrySrc2Value, dispAlu1Idx); + output('dispatch_alu_imm_1') <= muxField(entryImm, dispAlu1Idx); + output('dispatch_alu_funct_1') <= muxField(entryFunct, dispAlu1Idx); + output('dispatch_alu_use_imm_1') <= muxField(entryUseImm, dispAlu1Idx); + output('dispatch_alu_pc_1') <= muxField(entryPc, dispAlu1Idx); + + // Drive memory dispatch outputs + dispatchMemValid <= dispMemFound; + output('dispatch_mem_tag') <= muxField(entryTag, dispMemIdx); + output('dispatch_mem_src1') <= muxField(entrySrc1Value, dispMemIdx); + output('dispatch_mem_src2') <= muxField(entrySrc2Value, dispMemIdx); + output('dispatch_mem_imm') <= muxField(entryImm, dispMemIdx); + output('dispatch_mem_is_store') <= muxField(entryIsStore, dispMemIdx); + output('dispatch_mem_size') <= muxField(entryMemSize, dispMemIdx); + output('dispatch_mem_sign_extend') <= muxField(entrySignExtend, dispMemIdx); + output('dispatch_mem_pc') <= muxField(entryPc, dispMemIdx); + + // Drive branch dispatch outputs + dispatchBranchValid <= dispBranchFound; + output('dispatch_branch_tag') <= muxField(entryTag, dispBranchIdx); + output('dispatch_branch_src1') <= muxField(entrySrc1Value, dispBranchIdx); + output('dispatch_branch_src2') <= muxField(entrySrc2Value, dispBranchIdx); + output('dispatch_branch_imm') <= muxField(entryImm, dispBranchIdx); + output('dispatch_branch_pc') <= muxField(entryPc, dispBranchIdx); + output('dispatch_branch_condition') <= + muxField(entryBranchCond, dispBranchIdx); + output('dispatch_branch_is_jump') <= muxField(entryIsJump, dispBranchIdx); + output('dispatch_branch_is_jalr') <= muxField(entryIsJalr, dispBranchIdx); + + // Drive CSR dispatch outputs + dispatchCsrValid <= dispCsrFound; + output('dispatch_csr_tag') <= muxField(entryTag, dispCsrIdx); + output('dispatch_csr_src1') <= muxField(entrySrc1Value, dispCsrIdx); + output('dispatch_csr_imm') <= muxField(entryImm, dispCsrIdx); + output('dispatch_csr_op') <= muxField(entryCsrOp, dispCsrIdx); + output('dispatch_csr_addr') <= muxField(entryCsrAddr, dispCsrIdx); + + // Program-order sequence numbers assigned to enqueuing instructions. Slot 0 + // is older than slot 1; the counter advances by the number enqueued. + final enq0 = (enqValid0 & freeFound0).named('iq_enq0'); + final enq1 = (enqValid1 & freeFound1).named('iq_enq1'); + final enqSeq0 = seqCtr; + final enqSeq1 = (seqCtr + enq0.zeroExtend(8)).named('iq_enq_seq1'); + + Sequential(clk, [ + If( + reset | flush, + then: [ + count < 0, + seqCtr < 0, + ...List.generate(depth, (i) => entrySeq[i] < 0), + ...List.generate(depth, (i) => entryValid[i] < 0), + ...List.generate(depth, (i) => entryTag[i] < 0), + ...List.generate(depth, (i) => entryFuType[i] < 0), + ...List.generate(depth, (i) => entrySrc1Ready[i] < 0), + ...List.generate(depth, (i) => entrySrc2Ready[i] < 0), + ...List.generate(depth, (i) => entrySrc1Value[i] < 0), + ...List.generate(depth, (i) => entrySrc2Value[i] < 0), + // Reset the remaining payload fields too: the dispatch priority muxes + // read fields across all slots, so an unwritten slot holding X can + // propagate into a dispatched valid/condition and corrupt the core. + ...List.generate(depth, (i) => entryPsrc1[i] < 0), + ...List.generate(depth, (i) => entryPsrc2[i] < 0), + ...List.generate(depth, (i) => entryImm[i] < 0), + ...List.generate(depth, (i) => entryPc[i] < 0), + ...List.generate(depth, (i) => entryFunct[i] < 0), + ...List.generate(depth, (i) => entryIsStore[i] < 0), + ...List.generate(depth, (i) => entryMemSize[i] < 0), + ...List.generate(depth, (i) => entryBranchCond[i] < 0), + ...List.generate(depth, (i) => entryIsJump[i] < 0), + ...List.generate(depth, (i) => entryIsJalr[i] < 0), + ...List.generate(depth, (i) => entryUseImm[i] < 0), + ...List.generate(depth, (i) => entryCsrOp[i] < 0), + ...List.generate(depth, (i) => entryCsrAddr[i] < 0), + ...List.generate(depth, (i) => entrySignExtend[i] < 0), + ], + orElse: [ + // Wake-up: broadcast result to waiting entries + for (var i = 0; i < depth; i++) ...[ + If( + entryValid[i] & + ~entrySrc1Ready[i] & + wakeupValid0 & + entryPsrc1[i].eq(wakeupTag0), + then: [entrySrc1Ready[i] < 1, entrySrc1Value[i] < wakeupValue0], + ), + If( + entryValid[i] & + ~entrySrc2Ready[i] & + wakeupValid0 & + entryPsrc2[i].eq(wakeupTag0), + then: [entrySrc2Ready[i] < 1, entrySrc2Value[i] < wakeupValue0], + ), + If( + entryValid[i] & + ~entrySrc1Ready[i] & + wakeupValid1 & + entryPsrc1[i].eq(wakeupTag1), + then: [entrySrc1Ready[i] < 1, entrySrc1Value[i] < wakeupValue1], + ), + If( + entryValid[i] & + ~entrySrc2Ready[i] & + wakeupValid1 & + entryPsrc2[i].eq(wakeupTag1), + then: [entrySrc2Ready[i] < 1, entrySrc2Value[i] < wakeupValue1], + ), + If( + entryValid[i] & + ~entrySrc1Ready[i] & + wuV2 & + entryPsrc1[i].eq(wuT2), + then: [entrySrc1Ready[i] < 1, entrySrc1Value[i] < wuVal2], + ), + If( + entryValid[i] & + ~entrySrc2Ready[i] & + wuV2 & + entryPsrc2[i].eq(wuT2), + then: [entrySrc2Ready[i] < 1, entrySrc2Value[i] < wuVal2], + ), + ], + + // Enqueue slot 0 + If( + enqValid0 & freeFound0, + then: [ + Case(freeSlot0, [ + for (var i = 0; i < depth; i++) + CaseItem(Const(i, width: depth.bitLength), [ + entryValid[i] < 1, + entryTag[i] < enqTag0, + entryFuType[i] < enqFuType0, + entryPsrc1[i] < enqPsrc10, + entryPsrc2[i] < enqPsrc20, + entrySrc1Ready[i] < enqSrc1Ready0, + entrySrc2Ready[i] < enqSrc2Ready0, + entrySrc1Value[i] < enqSrc1Value0, + entrySrc2Value[i] < enqSrc2Value0, + entryImm[i] < enqImm0, + entryPc[i] < enqPc0, + entryFunct[i] < enqFunct0, + entryIsStore[i] < enqIsStore0, + entryMemSize[i] < enqMemSize0, + entryBranchCond[i] < enqBranchCond0, + entryIsJump[i] < enqIsJump0, + entryIsJalr[i] < enqIsJalr0, + entryUseImm[i] < enqUseImm0, + entryCsrOp[i] < enqCsrOp0, + entryCsrAddr[i] < enqCsrAddr0, + entrySignExtend[i] < enqSignExtend0, + entrySeq[i] < enqSeq0, + ]), + ]), + ], + ), + + // Enqueue slot 1 + If( + enqValid1 & freeFound1, + then: [ + Case(freeSlot1, [ + for (var i = 0; i < depth; i++) + CaseItem(Const(i, width: depth.bitLength), [ + entryValid[i] < 1, + entryTag[i] < enqTag1, + entryFuType[i] < enqFuType1, + entryPsrc1[i] < enqPsrc11, + entryPsrc2[i] < enqPsrc21, + entrySrc1Ready[i] < enqSrc1Ready1, + entrySrc2Ready[i] < enqSrc2Ready1, + entrySrc1Value[i] < enqSrc1Value1, + entrySrc2Value[i] < enqSrc2Value1, + entryImm[i] < enqImm1, + entryPc[i] < enqPc1, + entryFunct[i] < enqFunct1, + entryIsStore[i] < enqIsStore1, + entryMemSize[i] < enqMemSize1, + entryBranchCond[i] < enqBranchCond1, + entryIsJump[i] < enqIsJump1, + entryIsJalr[i] < enqIsJalr1, + entryUseImm[i] < enqUseImm1, + entryCsrOp[i] < enqCsrOp1, + entryCsrAddr[i] < enqCsrAddr1, + entrySignExtend[i] < enqSignExtend1, + entrySeq[i] < enqSeq1, + ]), + ]), + ], + ), + + // Advance the program-order sequence counter past whatever enqueued. + seqCtr < seqCtr + enq0.zeroExtend(8) + enq1.zeroExtend(8), + + // Invalidate dispatched entries + for (var i = 0; i < depth; i++) ...[ + If( + dispAlu0Found & dispAlu0Idx.eq(Const(i, width: depth.bitLength)), + then: [entryValid[i] < 0], + ), + If( + dispAlu1Found & dispAlu1Idx.eq(Const(i, width: depth.bitLength)), + then: [entryValid[i] < 0], + ), + If( + dispMemFound & dispMemIdx.eq(Const(i, width: depth.bitLength)), + then: [entryValid[i] < 0], + ), + If( + dispBranchFound & + dispBranchIdx.eq(Const(i, width: depth.bitLength)), + then: [entryValid[i] < 0], + ), + If( + dispCsrFound & dispCsrIdx.eq(Const(i, width: depth.bitLength)), + then: [entryValid[i] < 0], + ), + ], + + // Occupancy: a SINGLE net update. Enqueue (+) and dispatch (-) can both + // happen in the same cycle (e.g. when allocation runs at 1/cycle), so + // scattered `count < count+1` / `count < count-1` conditionals would + // conflict on `count` (last-write-wins / X) and wedge enqReady. Sum the + // events and apply the delta once. enq{0,1} and disp*Found are all + // single-bit fire flags. + count < + (count + + enq0.zeroExtend(count.width) + + enq1.zeroExtend(count.width) - + dispAlu0Found.zeroExtend(count.width) - + dispAlu1Found.zeroExtend(count.width) - + dispMemFound.zeroExtend(count.width) - + dispBranchFound.zeroExtend(count.width) - + dispCsrFound.zeroExtend(count.width)), + ], + ), + ]); + } +} diff --git a/packages/river_hdl/lib/src/core/iterative_divider.dart b/packages/river_hdl/lib/src/core/iterative_divider.dart new file mode 100644 index 0000000..65565b4 --- /dev/null +++ b/packages/river_hdl/lib/src/core/iterative_divider.dart @@ -0,0 +1,104 @@ +import 'package:rohd/rohd.dart'; + +/// Shared multi-cycle unsigned integer divider (radix-2 restoring). +/// +/// One division in flight at a time, matching the in-order exec unit: a div/rem +/// mop parks the pipeline at its mopStep and waits for [done]. Replaces the eight +/// combinational `/` and `%` trees (one per div/divu/divw/divuw/rem/remu/remw/ +/// remuw), each thousands of LUT4s, with one core costing a few hundred and one +/// shift-subtract per cycle. +/// +/// Signedness, word-width (`*w`), div-by-zero, and the INT_MIN/-1 overflow corner +/// are handled by the caller (this core sees only unsigned magnitudes with a +/// non-zero divisor); see `alu_ops.dart` for the reference semantics. +/// +/// Handshake (level-based): hold [start] high with [dividend]/[divisor] valid; +/// while idle the core latches operands and begins. After [width] cycles [done] +/// rises and [quotient]/[remainder] hold until [start] drops. +class IterativeDivider extends Module { + final int width; + + Logic get busy => output('busy'); + Logic get done => output('done'); + Logic get quotient => output('quotient'); + Logic get remainder => output('remainder'); + + IterativeDivider( + Logic clk, + Logic reset, + Logic start, + Logic dividend, + Logic divisor, { + this.width = 64, + super.name = 'iterative_divider', + }) { + clk = addInput('clk', clk); + reset = addInput('reset', reset); + start = addInput('start', start); + dividend = addInput('dividend', dividend, width: width); + divisor = addInput('divisor', divisor, width: width); + + final busy = addOutput('busy'); + final done = addOutput('done'); + final quotient = addOutput('quotient', width: width); + final remainder = addOutput('remainder', width: width); + + // State machine: 0 = idle, 1 = run, 2 = done. + const sIdle = 0, sRun = 1, sDone = 2; + final state = Logic(name: 'state', width: 2); + // Iterations remaining; counts width down to 0. width fits in bitLength. + final cntWidth = width.bitLength; + final cnt = Logic(name: 'cnt', width: cntWidth); + final rem = Logic(name: 'rem', width: width); + final quot = Logic(name: 'quot', width: width); + final divsr = Logic(name: 'divsr', width: width); + + // One restoring step: shift the running remainder left by 1, pulling in the + // top quotient bit, then conditionally subtract the divisor. remCat is the + // (width+1)-bit shifted remainder (rem*2 + quot[msb]); the post-subtract + // remainder is < divsr <= 2^width-1, so it fits back in width bits. + final remCat = [rem, quot[width - 1]].swizzle(); + final divExt = divsr.zeroExtend(width + 1); + final ge = remCat.gte(divExt); + final remNext = mux(ge, remCat - divExt, remCat).slice(width - 1, 0); + final quotNext = (quot << 1) | ge.zeroExtend(width); + + Sequential(clk, [ + If( + reset, + then: [state < sIdle, cnt < 0, rem < 0, quot < 0, divsr < 0], + orElse: [ + Case(state, [ + CaseItem(Const(sIdle, width: 2), [ + If( + start, + then: [ + rem < 0, + quot < dividend, + divsr < divisor, + cnt < width, + state < sRun, + ], + ), + ]), + CaseItem(Const(sRun, width: 2), [ + rem < remNext, + quot < quotNext, + cnt < cnt - 1, + // cnt == 1 is the width-th (final) iteration this cycle. + If(cnt.eq(1), then: [state < sDone]), + ]), + CaseItem(Const(sDone, width: 2), [ + If(~start, then: [state < sIdle]), + ]), + ]), + ], + ), + ]); + + busy <= state.eq(sRun); + done <= state.eq(sDone); + quotient <= quot; + remainder <= rem; + } +} diff --git a/packages/river_hdl/lib/src/core/iterative_multiplier.dart b/packages/river_hdl/lib/src/core/iterative_multiplier.dart new file mode 100644 index 0000000..d2bfc34 --- /dev/null +++ b/packages/river_hdl/lib/src/core/iterative_multiplier.dart @@ -0,0 +1,167 @@ +import 'package:rohd/rohd.dart'; + +/// Shared multi-cycle unsigned integer multiplier (radix-2^[radix] shift-add). +/// +/// One multiply in flight at a time, matching the in-order exec unit: a mul/mulh* +/// mop parks the pipeline at its mopStep and waits for [done]. Replaces the +/// single-cycle 64x64 multiply whose partial-product reduction tree costs +/// thousands of LUT4s on small FPGAs. Here one small [width]x[radix] multiply (a +/// couple of MULT18X18D tiles) is reused across cycles, leaving one chunk-multiply +/// plus one accumulate-add per cycle. +/// +/// Both operands unsigned; the full 2*[width]-bit product is on [product]. The +/// caller handles signed/MULH/MULHSU/MULHU/MULW via two sign-correction subtracts. +/// +/// Algorithm (radix-2^[radix] right-shifting accumulator shift-add): process +/// multiplier b [radix] bits at a time from the LSB. State is a narrow +/// ([width]+[radix]-bit) accumulator `acc` plus finalized low product bits in +/// `res`. Each step: +/// sum = acc + a * mr[radix-1:0] // ([width]+[radix])-bit add +/// res = {sum[radix-1:0], res} >> radix // finalized radix bits into res top +/// acc = sum >> radix // carry the high part forward +/// mr >>= radix // consume the radix multiplier bits +/// After [width]/[radix] steps the product is {acc[width-1:0], res-bits}. +/// +/// Leaner than a left-shifting multiplicand scheme: accumulator is only +/// [width]+[radix] bits (not 2*[width]) and there is no 2*[width]-bit shifting +/// multiplicand register, so the per-cycle add and state FFs stay narrow. +/// +/// Handshake (level-based, mirrors IterativeDivider): hold [start] high with +/// [a]/[b] valid; while idle the core latches operands and begins. After +/// ceil([width]/[radix]) cycles [done] rises and [product] holds the result until +/// [start] drops. +class IterativeMultiplier extends Module { + final int width; + final int radix; + + Logic get busy => output('busy'); + Logic get done => output('done'); + + /// Full unsigned product, 2*[width] bits. + Logic get product => output('product'); + + IterativeMultiplier( + Logic clk, + Logic reset, + Logic start, + Logic a, + Logic b, { + this.width = 64, + this.radix = 16, + super.name = 'iterative_multiplier', + }) { + if (width % radix != 0) { + throw ArgumentError( + 'width ($width) must be a multiple of radix ($radix)', + ); + } + clk = addInput('clk', clk); + reset = addInput('reset', reset); + start = addInput('start', start); + a = addInput('a', a, width: width); + b = addInput('b', b, width: width); + + final busy = addOutput('busy'); + final done = addOutput('done'); + final pw = width * 2; + final product = addOutput('product', width: pw); + + final steps = width ~/ radix; + + // State machine: 0 = idle, 1 = run, 2 = done. + const sIdle = 0, sRun = 1, sDone = 2; + final state = Logic(name: 'state', width: 2); + final cntWidth = (steps + 1).bitLength; + final cnt = Logic(name: 'cnt', width: cntWidth); + + // md holds the (fixed) multiplicand a. mr is the remaining multiplier b, + // consumed [radix] bits per cycle from the LSB via a right shift. + final md = Logic(name: 'md', width: width); + final mr = Logic(name: 'mr', width: width); + + // Narrow running accumulator holding the high carry across steps. Post-shift + // bound: sum = acc + a*chunk < 2^(width+radix+1), so (sum>>radix) < 2^(width+1), + // fitting width+1 bits. Narrower than the width+radix add keeps state FFs and + // the feedback adder small. + final accw = width + 1; // stored accumulator width (post-shift bound) + final sw = width + radix + 1; // intermediate sum width (no overflow) + final acc = Logic(name: 'acc', width: accw); + // Finalized low product bits, collected radix at a time from the top so the + // first-produced bits end up least significant once all steps are done. + final res = Logic(name: 'res', width: pw); + + // Per-step: chunk = low radix bits of mr; chunkProd = md * chunk, an + // (width+radix)-bit product. sum = acc + chunkProd, computed at sw bits so it + // cannot overflow. The low radix bits of sum are finalized product bits; acc + // carries (sum >> radix) forward, which fits in accw bits (see bound above). + final chunk = mr.slice(radix - 1, 0); // radix-bit multiplier slice + final chunkProd = (md.zeroExtend(sw) * chunk.zeroExtend(sw)); + final sum = acc.zeroExtend(sw) + chunkProd; + // Shift the finalized low radix bits into res from the TOP; res is filled + // top-down over `steps` shifts so the first chunk lands in the lowest bits. + final resNext = [ + sum.slice(radix - 1, 0), + res.slice(pw - 1, radix), + ].swizzle(); + final accNext = sum.slice(sw - 1, radix); // (sw-radix)==accw bits + final mrNext = mr >>> radix; + + // Final product: after `steps` shifts of `res`, the low product bits occupy + // res[pw-1 : pw-width] and `acc` holds the top width bits. Assemble from the + // next-state (accNext/resNext) on the final step so product and `done` align. + final lowBitsFinal = resNext.slice(pw - 1, pw - width); + final finalProductNext = [ + accNext.slice(width - 1, 0), + lowBitsFinal, + ].swizzle(); + + Sequential(clk, [ + If( + reset, + then: [ + state < sIdle, + cnt < 0, + md < 0, + mr < 0, + acc < 0, + res < 0, + product < 0, + ], + orElse: [ + Case(state, [ + CaseItem(Const(sIdle, width: 2), [ + If( + start, + then: [ + acc < 0, + res < 0, + md < a, + mr < b, + cnt < steps, + state < sRun, + ], + ), + ]), + CaseItem(Const(sRun, width: 2), [ + acc < accNext, + res < resNext, + mr < mrNext, + cnt < cnt - 1, + // cnt == 1 is the final (steps-th) accumulate this cycle. Latch the + // assembled product so it is stable while done is held. + If(cnt.eq(1), then: [state < sDone, product < finalProductNext]), + ]), + CaseItem(Const(sDone, width: 2), [ + If(~start, then: [state < sIdle]), + ]), + ]), + ], + ), + ]); + + busy <= state.eq(sRun); + done <= state.eq(sDone); + // product is a registered output, latched on the final accumulate step above + // and held stable while done is asserted (the caller reads it then). + } +} diff --git a/packages/river_hdl/lib/src/core/jtag_bscan_tunnel.dart b/packages/river_hdl/lib/src/core/jtag_bscan_tunnel.dart new file mode 100644 index 0000000..713afbb --- /dev/null +++ b/packages/river_hdl/lib/src/core/jtag_bscan_tunnel.dart @@ -0,0 +1,152 @@ +import 'package:rohd/rohd.dart'; + +/// SiFive-style JTAG BSCAN tunnel (NESTED_TAP variant): lets OpenOCD reach the +/// River debug module over the FPGA config JTAG (ECP5 `JTAGG` ER1 user register, +/// driven by dirtyJtag) instead of a separate GPIO TAP. The inner +/// [RiverDebugModule] keeps its full TAP; this module reconstructs that TAP's +/// `tck/tms/tdi` from a framed ER1 DR scan and returns its `tdo` on `jtdo1`. +/// +/// Frame (one ER1 DR scan, LSB-first), matching riscv-openocd +/// `riscv_add_bscan_tunneled_scan` for `BSCAN_TUNNEL_NESTED_TAP`: +/// [1 bit] sel : 1 = inner DR scan, 0 = inner IR scan +/// [7 bits] width : inner scan length N (NOT N-1), LSB first +/// [N+1] payload: inner TDI; the +1 is the one-TCK in/out skew OpenOCD +/// compensates by right-shifting the captured field +/// [3 bits] idle : zeros; carry the inner TAP Exit1 -> Update -> Run/Idle +/// Total frame = N + 12 bits. +/// +/// OpenOCD selects this tunnel with `riscv use_bscan_tunnel 0` (0 = +/// nested-tap; irwidth = inner DM IR width = 5). +/// +/// The inner TAP is clocked only during the ER1 Shift-DR window (`jce1 & jshift`) +/// so it advances once per frame bit and is frozen between frames. The tunnel +/// synthesizes a full inner-TAP walk inside that window: +/// sel=1 (DR): RTI -> Select-DR -> Capture-DR -> Shift-DR(N+1) -> Exit1 -> Update -> RTI +/// sel=0 (IR): RTI -> Select-DR -> Select-IR -> Capture-IR -> Shift-IR(N+1) -> Exit1 -> Update -> RTI +/// This FSM and the inner DM both rising-edge-detect `tck` in the system clock +/// domain, so they advance in lockstep. +/// +/// HW-validation pending: the TDI/TDO skew (+1 payload bit) and header-to-shift +/// alignment are the parts to confirm against live OpenOCD. Framing + inner-TAP +/// walk are sim-tested against the real DM in jtag_tunnel_dm_test.dart (only the +/// `Ecp5Jtagg` primitive is an unsimulatable blackbox). +class JtagBscanTunnel extends Module { + /// Width of the widest inner scan (the DMI register, ~41 bits). Sizes the + /// payload counter. + final int maxScanBits; + + JtagBscanTunnel({this.maxScanBits = 64, super.name = 'jtag_bscan_tunnel'}) + : super(definitionName: 'JtagBscanTunnel') { + final clk = addInput('clk', Logic()); + final reset = addInput('reset', Logic()); + + // ER1 user-register side (from Ecp5Jtagg). + final jtck = addInput('jtck', Logic()); + final jtdi = addInput('jtdi', Logic()); + final jshift = addInput('jshift', Logic()); + final jupdate = addInput('jupdate', Logic()); + final jce1 = addInput('jce1', Logic()); + final jrstn = addInput('jrstn', Logic()); + final innerTdo = addInput('inner_tdo', Logic()); + + final jtdo1 = addOutput('jtdo1'); + final innerTck = addOutput('inner_tck'); + final innerTms = addOutput('inner_tms'); + final innerTdi = addOutput('inner_tdi'); + final innerTrstN = addOutput('inner_trst_n'); + + final cntW = (maxScanBits + 16).bitLength; + final cnt = Logic(name: 'bit_cnt', width: cntW); // frame bit index + final sel = Logic(name: 'sel'); // 1=DR, 0=IR + final width = Logic(name: 'width', width: 7); // inner scan length N + final jtckPrev = Logic(name: 'jtck_prev'); + final tdoCap = Logic(name: 'tdo_cap'); // registered inner tdo for jtdo1 + + final jtckRise = (jtck & ~jtckPrev).named('jtck_rise'); + final active = (jce1 & jshift).named('tunnel_active'); // shifting ER1 DR + + // Header is 8 bits (sel + 7 width). OpenOCD sends width+1 payload bits but the + // inner TAP shifts exactly N; the extra bit is the one-TCK TDO skew. So the + // inner Shift window is bits 8 .. 8+N-1. + final headerBits = 8; + final shiftStart = Const(headerBits, width: cntW); + final lastShift = + (Const(headerBits, width: cntW) + + width.zeroExtend(cntW) - + Const(1, width: cntW)) + .named('last_shift'); + + // Inner TAP in Shift (driving N real shifts)? + final inShift = (cnt.gte(shiftStart) & cnt.lte(lastShift)).named( + 'in_shift', + ); + final atLastShift = cnt.eq(lastShift).named('at_last_shift'); + + // TMS schedule by frame bit. Inner TAP starts each frame in Run-Test/Idle + // (TLR on first access lands in RTI too, identical walk). + // DR walk: tms=1 at bit 5 (RTI->Sel-DR); bits 6,7 tms=0 (Capture, Shift). + // IR walk: tms=1 at bits 4,5 (Sel-DR, Sel-IR); bits 6,7 tms=0. + // Then N shift bits 8..lastShift (tms=0); last asserts tms=1 (Shift->Exit1), + // bit lastShift+1 tms=1 (Exit1->Update), trailing bits tms=0 (Update->RTI). + final w4 = cnt.eq(Const(4, width: cntW)); + final w5 = cnt.eq(Const(5, width: cntW)); + final exitFirst = cnt.eq(lastShift + Const(1, width: cntW)); + + final tmsDr = w5.named('tms_dr_walk'); + final tmsIr = (w4 | w5).named('tms_ir_walk'); + final tmsVal = mux( + inShift, + atLastShift, // last shift bit exits Shift -> Exit1 + mux( + cnt.gt(lastShift), + exitFirst, // Exit1 -> Update on the first post-shift bit, then RTI + mux(sel, tmsDr, tmsIr), // header walk (DR vs IR) + ), + ).named('inner_tms_val'); + + Sequential(clk, reset: reset, [ + jtckPrev < jtck, + If( + ~jrstn, + then: [cnt < Const(0, width: cntW)], + orElse: [ + If( + jtckRise, + then: [ + If( + active, + then: [ + cnt < cnt + 1, + If(cnt.eq(Const(0, width: cntW)), then: [sel < jtdi]), + // Shift width in LSB-first across bits 1..7. + If( + cnt.gte(Const(1, width: cntW)) & + cnt.lte(Const(7, width: cntW)), + then: [ + width < [jtdi, width.getRange(1, 7)].swizzle(), + ], + ), + // Capture inner tdo while shifting (registered -> the +1 skew). + If(inShift, then: [tdoCap < innerTdo]), + ], + orElse: [ + // Between scans (outer Capture-DR / Update / idle): restart the + // frame index so the next Shift-DR window begins clean. + cnt < Const(0, width: cntW), + ], + ), + ], + ), + ], + ), + ]); + + // Inner TAP drive. Clock the inner TAP ONLY inside the ER1 Shift-DR window + // so it advances once per frame bit; tms/tdi are combinational per bit. + innerTck <= jtck & active; + innerTrstN <= jrstn; + innerTms <= tmsVal; + innerTdi <= mux(inShift, jtdi, Const(0)); + jtdo1 <= tdoCap; + } +} diff --git a/packages/river_hdl/lib/src/core/load_queue.dart b/packages/river_hdl/lib/src/core/load_queue.dart new file mode 100644 index 0000000..bad3aad --- /dev/null +++ b/packages/river_hdl/lib/src/core/load_queue.dart @@ -0,0 +1,151 @@ +import 'package:rohd/rohd.dart'; + +int _log2(int n) { + var bits = 0; + var v = n - 1; + while (v > 0) { + bits++; + v >>= 1; + } + return bits == 0 ? 1 : bits; +} + +/// Load queue for speculative (out-of-order) loads. +/// +/// When a load executes ahead of an older store whose address is not yet known, +/// it records itself here. Later, when that store resolves its address, it CAMs +/// this queue: any *younger* load that already executed to an overlapping +/// address speculated wrong and must be replayed. Program age is the position of +/// a ROB tag relative to the ROB head (`(tag - headIdx) mod robDepth`), so a +/// load is younger than the store when its position is greater. +/// +/// Entries allocate at load execute and free when the load commits (it is then +/// safe, every older store has committed before it). A flush clears all. +class LoadQueue extends Module { + final int depth; + final int xlen; + final int robTagBits; + + /// No free entry to record another speculative load. + Logic get full => output('full'); + + /// The CAMming store (cam_valid) hit a younger overlapping executed load, + /// an ordering violation, so the store must trigger a replay. + Logic get camViolation => output('cam_violation'); + + LoadQueue( + Logic clk, + Logic reset, { + required Logic flush, + // Push: a load executed this cycle, record it. + required Logic pushValid, + required Logic pushTag, + required Logic pushAddr, + required Logic pushSize, + // Free: a load committed this cycle, drop its entry (matched by tag). + required Logic freeValid, + required Logic freeTag, + // ROB head index, for age (position) comparison. + required Logic headIdx, + // CAM: a store resolved its address this cycle, check for violations. + required Logic camValid, + required Logic camTag, + required Logic camAddr, + required Logic camSize, + this.depth = 8, + this.xlen = 64, + this.robTagBits = 6, + super.name = 'load_queue', + }) : super(definitionName: 'LoadQueue') { + clk = addInput('clk', clk); + reset = addInput('reset', reset); + flush = addInput('flush', flush); + pushValid = addInput('push_valid', pushValid); + pushTag = addInput('push_tag', pushTag, width: robTagBits); + pushAddr = addInput('push_addr', pushAddr, width: xlen); + pushSize = addInput('push_size', pushSize, width: 3); + freeValid = addInput('free_valid', freeValid); + freeTag = addInput('free_tag', freeTag, width: robTagBits); + headIdx = addInput('head_idx', headIdx, width: robTagBits); + camValid = addInput('cam_valid', camValid); + camTag = addInput('cam_tag', camTag, width: robTagBits); + camAddr = addInput('cam_addr', camAddr, width: xlen); + camSize = addInput('cam_size', camSize, width: 3); + + final slotBits = _log2(depth); + + final eValid = List.generate(depth, (i) => Logic(name: 'lq_valid_$i')); + final eTag = List.generate( + depth, + (i) => Logic(name: 'lq_tag_$i', width: robTagBits), + ); + final eAddr = List.generate( + depth, + (i) => Logic(name: 'lq_addr_$i', width: xlen), + ); + final eSize = List.generate( + depth, + (i) => Logic(name: 'lq_size_$i', width: 3), + ); + + addOutput('full'); + addOutput('cam_violation'); + + // First free slot. + final freeSlot = Logic(name: 'lq_free_slot', width: slotBits); + final freeFound = Logic(name: 'lq_free_found'); + final slotConds = []; + for (var i = 0; i < depth; i++) { + final c = [freeSlot < Const(i, width: slotBits), freeFound < 1]; + slotConds.add(i == 0 ? Iff(~eValid[i], c) : ElseIf(~eValid[i], c)); + } + slotConds.add(Else([freeSlot < 0, freeFound < 0])); + Combinational([If.block(slotConds)]); + full <= ~freeFound; + + // CAM: any valid YOUNGER load overlapping the store's byte range? + final sEnd = (camAddr + camSize.zeroExtend(xlen)).named('lq_cam_send'); + final storePos = (camTag - headIdx).named('lq_cam_spos'); + Logic anyViol = Const(0); + for (var j = 0; j < depth; j++) { + final loadPos = (eTag[j] - headIdx); + final younger = loadPos.gt(storePos); + final eEnd = (eAddr[j] + eSize[j].zeroExtend(xlen)); + final overlap = camAddr.lt(eEnd) & eAddr[j].lt(sEnd); + anyViol = anyViol | (eValid[j] & younger & overlap); + } + camViolation <= camValid & anyViol; + + Sequential(clk, [ + If( + reset | flush, + then: [...List.generate(depth, (i) => eValid[i] < 0)], + orElse: [ + If( + pushValid & freeFound, + then: [ + for (var i = 0; i < depth; i++) + If( + freeSlot.eq(Const(i, width: slotBits)), + then: [ + eValid[i] < 1, + eTag[i] < pushTag, + eAddr[i] < pushAddr, + eSize[i] < pushSize, + ], + ), + ], + ), + // Free the committed load's entry (matched by tag). + If( + freeValid, + then: [ + for (var i = 0; i < depth; i++) + If(eValid[i] & eTag[i].eq(freeTag), then: [eValid[i] < 0]), + ], + ), + ], + ), + ]); + } +} diff --git a/packages/river_hdl/lib/src/core/lsq.dart b/packages/river_hdl/lib/src/core/lsq.dart new file mode 100644 index 0000000..c5627dc --- /dev/null +++ b/packages/river_hdl/lib/src/core/lsq.dart @@ -0,0 +1,248 @@ +import 'package:rohd/rohd.dart'; + +int _log2(int n) { + var bits = 0; + var v = n - 1; + while (v > 0) { + bits++; + v >>= 1; + } + return bits == 0 ? 1 : bits; +} + +/// Store queue: a FIFO of executed stores awaiting (and undergoing) their write +/// to memory. +/// +/// A store pushes an entry here when it *executes* (address + data known), well +/// before it commits. Three pointers carve the queue into regions: +/// +/// ``` +/// head ............ commitPtr ............ tail +/// | committed, | speculative | +/// | draining | (not yet retired) | +/// ``` +/// +/// * `tail` advances on push (a store executed). +/// * `commitPtr` advances when a store retires (`commitValid`), the store is +/// now architectural and its write may go to memory. +/// * `head` advances on `popValid` (a memory write completed). +/// +/// Entries in `[head, commitPtr)` are committed and drain to memory in program +/// order *in the background*, the store does NOT stall commit waiting for its +/// write, so several stores can be in flight at once. A load waits until the +/// whole queue is empty (every older store has reached memory). A flush drops +/// only the speculative tail (`tail <- commitPtr`); committed entries are +/// architectural and keep draining. +class StoreQueue extends Module { + final int depth; + final int xlen; + final int robTagBits; + + /// No entries in flight (committed or speculative). + Logic get empty => output('empty'); + + /// No room to push another store (execute must stall). + Logic get full => output('full'); + + /// The head (oldest) entry is committed and ready to write to memory. + Logic get headDrainable => output('head_drainable'); + Logic get headAddr => output('head_addr'); + Logic get headData => output('head_data'); + Logic get headSize => output('head_size'); + Logic get headTag => output('head_tag'); + + /// Store→load forwarding for the address/size on `fwd_query_*`: + /// * `fwdHit`, the youngest store overlapping the query EXACTLY matches its + /// address and size; `fwdData` carries its value (forward it, skip the bus). + /// * `fwdStall`, the youngest overlapping store only partially covers the load + /// (different size or a misaligned overlap); the load must wait for the + /// queue to drain that store before reading the bus. + /// * neither, no store overlaps the load; it may read the bus immediately. + Logic get fwdHit => output('fwd_hit'); + Logic get fwdData => output('fwd_data'); + Logic get fwdStall => output('fwd_stall'); + + StoreQueue( + Logic clk, + Logic reset, { + required Logic flush, + // Push (a store executed this cycle): append addr/data/size at the tail. + required Logic pushValid, + required Logic pushTag, + required Logic pushAddr, + required Logic pushData, + required Logic pushSize, + // A store retired this cycle: advance the commit pointer so the oldest + // speculative entry becomes architectural (drainable). + required Logic commitValid, + // A SECOND store retired the same cycle (dual-commit of two stores). When + // high alongside `commitValid`, the commit pointer advances by two. Because + // memory dispatches in program order and dual-commit is in-order, the two + // retiring stores are always the two oldest speculative entries, so jumping + // the pointer by two is always correct. Tied off (single store/cycle) when + // not driven. This lets the pipeline commit store pairs without throttling + // them through one slot, so the queue makes no assumption about the rate at + // which stores arrive at commit. See project_hdl_frontend_perf. + Logic? commitValid2, + // The head store's memory write completed this cycle: remove the head. + required Logic popValid, + // Forwarding query (a load's effective address + byte size). Combinational. + required Logic fwdQueryAddr, + required Logic fwdQuerySize, + this.depth = 8, + this.xlen = 64, + this.robTagBits = 6, + super.name = 'store_queue', + }) : super(definitionName: 'StoreQueue') { + clk = addInput('clk', clk); + reset = addInput('reset', reset); + flush = addInput('flush', flush); + pushValid = addInput('push_valid', pushValid); + pushTag = addInput('push_tag', pushTag, width: robTagBits); + pushAddr = addInput('push_addr', pushAddr, width: xlen); + pushData = addInput('push_data', pushData, width: xlen); + pushSize = addInput('push_size', pushSize, width: 3); + commitValid = addInput('commit_valid', commitValid); + commitValid2 = addInput('commit_valid2', commitValid2 ?? Const(0)); + popValid = addInput('pop_valid', popValid); + fwdQueryAddr = addInput('fwd_query_addr', fwdQueryAddr, width: xlen); + fwdQuerySize = addInput('fwd_query_size', fwdQuerySize, width: 3); + + final ptrBits = _log2(depth); + + // Circular-buffer pointers. The extra MSB disambiguates full from empty. + final head = Logic(name: 'sq_head', width: ptrBits + 1); + final commitPtr = Logic(name: 'sq_commit', width: ptrBits + 1); + final tail = Logic(name: 'sq_tail', width: ptrBits + 1); + + final entryTag = List.generate( + depth, + (i) => Logic(name: 'sq_tag_$i', width: robTagBits), + ); + final entryAddr = List.generate( + depth, + (i) => Logic(name: 'sq_addr_$i', width: xlen), + ); + final entryData = List.generate( + depth, + (i) => Logic(name: 'sq_data_$i', width: xlen), + ); + final entrySize = List.generate( + depth, + (i) => Logic(name: 'sq_size_$i', width: 3), + ); + + final headIdx = head.slice(ptrBits - 1, 0); + final tailIdx = tail.slice(ptrBits - 1, 0); + final isEmpty = head.eq(tail); + final isFull = headIdx.eq(tailIdx) & (head[ptrBits] ^ tail[ptrBits]); + // A committed-but-not-drained entry exists when head has not caught up to + // the commit pointer. + final hasCommitted = ~head.eq(commitPtr); + + addOutput('empty'); + addOutput('full'); + addOutput('head_drainable'); + addOutput('head_addr', width: xlen); + addOutput('head_data', width: xlen); + addOutput('head_size', width: 3); + addOutput('head_tag', width: robTagBits); + addOutput('fwd_hit'); + addOutput('fwd_data', width: xlen); + addOutput('fwd_stall'); + + Logic muxByIdx(List arr, Logic idx) { + Logic result = arr[0]; + for (var i = 1; i < depth; i++) { + result = mux(idx.eq(Const(i, width: ptrBits)), arr[i], result); + } + return result; + } + + empty <= isEmpty; + full <= isFull; + headDrainable <= hasCommitted; + headAddr <= muxByIdx(entryAddr, headIdx); + headData <= muxByIdx(entryData, headIdx); + headSize <= muxByIdx(entrySize, headIdx); + headTag <= muxByIdx(entryTag, headIdx); + + // -- Store→load forwarding -------------------------------------------- + // Every live entry is an OLDER store (memory dispatches in program order), + // so the load forwards from the youngest entry whose byte range overlaps it. + // pos = distance from head (0 = oldest); larger pos = younger. + final liveCount = (tail - head).named('sq_live_count'); + final qEnd = (fwdQueryAddr + fwdQuerySize.zeroExtend(xlen)).named( + 'fwd_q_end', + ); + final pos = []; + final liveOverlap = []; + final exact = []; + for (var j = 0; j < depth; j++) { + final posj = (Const(j, width: ptrBits) - headIdx).named('sq_pos_$j'); + final livej = posj.zeroExtend(ptrBits + 1).lt(liveCount); + final sEndj = (entryAddr[j] + entrySize[j].zeroExtend(xlen)); + final overlapj = fwdQueryAddr.lt(sEndj) & entryAddr[j].lt(qEnd); + pos.add(posj); + liveOverlap.add((livej & overlapj).named('sq_lov_$j')); + exact.add(entryAddr[j].eq(fwdQueryAddr) & entrySize[j].eq(fwdQuerySize)); + } + Logic fwdDataAcc = Const(0, width: xlen); + Logic fwdExactAcc = Const(0); + Logic anyOverlap = Const(0); + for (var j = 0; j < depth; j++) { + Logic anyYounger = Const(0); + for (var k = 0; k < depth; k++) { + if (k == j) continue; + anyYounger = anyYounger | (liveOverlap[k] & pos[k].gt(pos[j])); + } + final isYoungest = liveOverlap[j] & ~anyYounger; + fwdDataAcc = mux(isYoungest, entryData[j], fwdDataAcc); + fwdExactAcc = fwdExactAcc | (isYoungest & exact[j]); + anyOverlap = anyOverlap | liveOverlap[j]; + } + fwdHit <= fwdExactAcc; + fwdData <= fwdDataAcc; + fwdStall <= anyOverlap & ~fwdExactAcc; + + Sequential(clk, [ + If( + reset, + then: [head < 0, commitPtr < 0, tail < 0], + orElse: [ + If( + flush, + // Drop the speculative tail; committed entries keep draining. + then: [tail < commitPtr], + orElse: [ + If( + pushValid, + then: [ + for (var i = 0; i < depth; i++) + If( + tailIdx.eq(Const(i, width: ptrBits)), + then: [ + entryTag[i] < pushTag, + entryAddr[i] < pushAddr, + entryData[i] < pushData, + entrySize[i] < pushSize, + ], + ), + tail < tail + 1, + ], + ), + // Advance by the number of stores retiring this cycle (0/1/2). + commitPtr < + commitPtr + + (commitValid.zeroExtend(ptrBits + 1) + + commitValid2.zeroExtend(ptrBits + 1)), + ], + ), + // A pop can retire a committed entry even on a flush cycle (the + // draining store is architectural and unaffected by the squash). + If(popValid, then: [head < head + 1]), + ], + ), + ]); + } +} diff --git a/packages/river_hdl/lib/src/core/microcode_alu.dart b/packages/river_hdl/lib/src/core/microcode_alu.dart new file mode 100644 index 0000000..8aed21a --- /dev/null +++ b/packages/river_hdl/lib/src/core/microcode_alu.dart @@ -0,0 +1,97 @@ +import 'package:rohd/rohd.dart'; +import 'package:river/river.dart'; + +import '../compat.dart' show MicroOpAluFunct; +import 'alu_ops.dart' show bmSignedLt; + +/// Shared, control-driven integer ALU for the microcode exec datapath. +/// +/// One reusable unit instead of the DynamicExecutionUnit computing every ALU op +/// inline in a ~30-arm Case (separate adders/shifters per arm). [funct] (a +/// [MicroOpAluFunct] value) selects a single [result]. The adder is shared +/// across add/sub/addw/subw via operand-invert (yosys will not merge that on its +/// own). Multiply/divide stay on their own units (BmMulSet / IterativeDivider); +/// this covers single-cycle integer ops only. +class MicrocodeAlu extends Module { + /// The selected ALU result, XLEN wide. + Logic get result => output('result'); + + MicrocodeAlu( + Logic a, + Logic b, + Logic funct, { + required RiscVMxlen mxlen, + super.name = 'microcode_alu', + }) { + final xlen = mxlen.size; + a = addInput('a', a, width: xlen); + b = addInput('b', b, width: xlen); + funct = addInput('funct', funct, width: MicroOpAluFunct.width); + final result = addOutput('result', width: xlen); + + Logic f(int v) => funct.eq(Const(v, width: MicroOpAluFunct.width)); + + // ONE shared adder: add/sub/addw/subw. sub-family inverts b and carries in. + final isSub = f(MicroOpAluFunct.sub) | f(MicroOpAluFunct.subw); + final sum = a + mux(isSub, ~b, b) + isSub.zeroExtend(xlen); + final sumW = sum.slice(31, 0).signExtend(xlen); + + // Bitwise. + final andR = a & b; + final orR = a | b; + final xorR = a ^ b; + final masked = a & ~b; // MicroOpAluFunct.masked (andn-style) + + // 64-bit shifts (shamt masked to log2(XLEN)). + final shamt = b & Const(xlen - 1, width: xlen); + final sll = a << shamt; + final srl = a >>> shamt; + final sra = a >> shamt; // arithmetic + + // 32-bit (W) shifts, sign-extended to XLEN. + final shamtW = b.slice(4, 0); + final sllw = (a << shamtW).slice(31, 0).signExtend(xlen); + final srlw = (a.slice(31, 0) >>> shamtW).signExtend(xlen); + final sraw = (a.slice(31, 0) >> shamtW).signExtend(xlen); + + // Compares. + final slt = bmSignedLt(a, b, xlen).zeroExtend(xlen); + final sltu = a.lt(b).zeroExtend(xlen); + + // Zicond conditional-zero. + final bZero = b.eq(Const(0, width: xlen)); + final czE = mux(bZero, Const(0, width: xlen), a); // czero.eqz + final czN = mux(bZero, a, Const(0, width: xlen)); // czero.nez + + // Result selection: a parallel Case over funct (balanced mux, not a priority + // chain) selecting the precomputed shared-datapath result. + CaseItem item(int fn, Logic value) => + CaseItem(Const(fn, width: MicroOpAluFunct.width), [result < value]); + Combinational([ + Case( + funct, + [ + item(MicroOpAluFunct.add, sum), + item(MicroOpAluFunct.sub, sum), // shared adder (b inverted) + item(MicroOpAluFunct.addw, sumW), + item(MicroOpAluFunct.subw, sumW), + item(MicroOpAluFunct.and, andR), + item(MicroOpAluFunct.or, orR), + item(MicroOpAluFunct.xor, xorR), + item(MicroOpAluFunct.masked, masked), + item(MicroOpAluFunct.sll, sll), + item(MicroOpAluFunct.srl, srl), + item(MicroOpAluFunct.sra, sra), + item(MicroOpAluFunct.sllw, sllw), + item(MicroOpAluFunct.srlw, srlw), + item(MicroOpAluFunct.sraw, sraw), + item(MicroOpAluFunct.slt, slt), + item(MicroOpAluFunct.sltu, sltu), + item(MicroOpAluFunct.czeroEqz, czE), + item(MicroOpAluFunct.czeroNez, czN), + ], + defaultItem: [result < Const(0, width: xlen)], + ), + ]); + } +} diff --git a/packages/river_hdl/lib/src/core/mmu.dart b/packages/river_hdl/lib/src/core/mmu.dart index d216a2c..eb1cb1a 100644 --- a/packages/river_hdl/lib/src/core/mmu.dart +++ b/packages/river_hdl/lib/src/core/mmu.dart @@ -1,719 +1,986 @@ -import 'package:riscv/riscv.dart'; import 'package:river/river.dart'; import 'package:rohd/rohd.dart'; -import 'package:rohd_hcl/rohd_hcl.dart'; -class MmuModule extends Module { - final Mmu config; - - MmuModule( +/// River MMU with Wishbone bus master downstream. +/// +/// Upstream: ifetch (en/addr → done/valid/rdata) and dport (en/addr/we/wdata/size → done/valid/rdata) +/// Downstream: Wishbone master (CYC/STB/WE/ADR/DAT_MOSI/SEL → ACK/DAT_MISO) +/// +/// Internally: priority arbiter (dport > ifetch), Wishbone master FSM. +class RiverMmu extends Module { + final HarborMmuConfig mmuConfig; + final WishboneConfig busConfig; + + // Upstream response outputs + Logic get ifetchDone => output('ifetch_done'); + Logic get ifetchValid => output('ifetch_valid'); + Logic get ifetchRdata => output('ifetch_rdata'); + Logic get dportDone => output('dport_done'); + Logic get dportValid => output('dport_valid'); + Logic get dportRdata => output('dport_rdata'); + Logic get dportFault => output('dport_fault'); + Logic get dportFaultGuest => output('dport_fault_guest'); + Logic get ifetchFault => output('ifetch_fault'); + + // Downstream bus master outputs + Logic get wbCyc => output('dataBus_CYC'); + Logic get wbStb => output('dataBus_STB'); + Logic get wbWe => output('dataBus_WE'); + Logic get wbAdr => output('dataBus_ADR'); + Logic get wbDatMosi => output('dataBus_DAT_MOSI'); + Logic get wbSel => output('dataBus_SEL'); + + RiverMmu( Logic clk, Logic reset, - List<(MemoryAccess, DataPortInterface)> memWritePorts, - List<(MemoryAccess, DataPortInterface)> memReadPorts, { - required this.config, - Logic? privilegeMode, - Logic? enableSum, - Logic? enableMxr, - Logic? pagingMode, - Logic? pageTableAddress, - Logic? fence, - Map devices = - const {}, + Logic ifetchEn, + Logic ifetchAddr, + Logic dportEn, + Logic dportAddr, + Logic dportWe, + Logic dportWdata, + Logic dportSize, + Logic wbAck, + Logic wbDatMiso, { + required this.mmuConfig, + required this.busConfig, + Logic? satpMode, + Logic? satpRoot, + // Hypervisor two-stage: when [virtIn]=1 and [gMode]!=0, the (VS-stage) + // page-table walk addresses, every PTE pointer and the final leaf, are + // themselves G-translated through the hgatp table ([gMode]/[gRoot]) before + // the host bus access. satpMode/satpRoot already carry vsatp when virt=1. + Logic? virtIn, + Logic? gMode, + Logic? gRoot, + Logic? privMode, // current effective privilege (for U-bit/SUM checks) + Logic? sum, // mstatus.SUM (supervisor may access user pages) + Logic? mxr, // mstatus.MXR (loads may read execute-only pages) + // When true, instruction fetches below machine mode are translated through + // the page table (X-permission + U-bit fetch rule, faulting to ifetch_fault). + // Defaults off until the fetch consumer wires ifetch_fault to cause 12. + bool translateFetch = false, + // Pulsed when the core executes sfence.vma (or fence.i, which over-flushes + // harmlessly): invalidates the single-entry fetch TLB so a page-table edit + // that does not change satp is observed by the next fetch. + Logic? tlbFlush, + // DTLBFC (rpipelinectl[3]): when high, also flush the data TLB on every + // privilege-mode change (satp changes already flush). Closes the data-TLB + // residue channel across context switches for paranoid configs. + Logic? dtlbFlushOnPrivChange, super.name = 'river_mmu', }) { + final xlen = mmuConfig.mxlen.size; + clk = addInput('clk', clk); reset = addInput('reset', reset); - - memWritePorts = memWritePorts.indexed - .map( - (e) => ( - e.$2.$1, - e.$2.$2.clone()..connectIO( - this, - e.$2.$2, - outputTags: {DataPortGroup.integrity}, - inputTags: {DataPortGroup.control, DataPortGroup.data}, - uniquify: (og) => 'memWrite${e.$1}_$og', - ), - ), - ) - .toList(); - - memReadPorts = memReadPorts.indexed - .map( - (e) => ( - e.$2.$1, - e.$2.$2.clone()..connectIO( - this, - e.$2.$2, - outputTags: {DataPortGroup.data, DataPortGroup.integrity}, - inputTags: {DataPortGroup.control}, - uniquify: (og) => 'memRead${e.$1}_$og', - ), - ), - ) - .toList(); - - devices = Map.fromEntries( - devices.entries.indexed.map((e) { - final index = e.$1; - final mmap = e.$2.key; - final devReadPort = e.$2.value.$1; - final devWritePort = e.$2.value.$2; - return MapEntry(mmap, ( - devReadPort != null - ? (devReadPort!.clone()..connectIO( - this, - devReadPort!, - outputTags: {DataPortGroup.control}, - inputTags: {DataPortGroup.data, DataPortGroup.integrity}, - uniquify: (og) => 'devRead${index}_$og', - )) - : null, - devWritePort != null - ? (devWritePort!.clone()..connectIO( - this, - devWritePort!, - outputTags: {DataPortGroup.control, DataPortGroup.data}, - inputTags: {DataPortGroup.integrity}, - uniquify: (og) => 'devWrite${index}_$og', - )) - : null, - )); - }), + ifetchEn = addInput('ifetch_en', ifetchEn); + ifetchAddr = addInput('ifetch_addr', ifetchAddr, width: xlen); + dportEn = addInput('dport_en', dportEn); + dportAddr = addInput('dport_addr', dportAddr, width: xlen); + dportWe = addInput('dport_we', dportWe); + dportWdata = addInput('dport_wdata', dportWdata, width: xlen); + dportSize = addInput('dport_size', dportSize, width: 3); + wbAck = addInput('dataBus_ACK', wbAck); + wbDatMiso = addInput( + 'dataBus_DAT_MISO', + wbDatMiso, + width: busConfig.dataWidth, ); - if (privilegeMode != null) - privilegeMode = addInput('privilegeMode', privilegeMode!, width: 3); - - if (fence != null) fence = addInput('fence', fence!); - - if (config.hasSum) { - assert(enableSum != null, 'SUM is enabled in the MMU but not wired up.'); - enableSum = addInput('enableSum', enableSum!); + // satp.MODE (0=bare, 8=Sv39, 9=Sv48) and root PPN. When wired and MODE!=0, + // data accesses are translated by walking the page table over the bus. + final hasPaging = satpMode != null && satpRoot != null; + satpMode = hasPaging ? addInput('satp_mode', satpMode, width: 4) : null; + satpRoot = hasPaging ? addInput('satp_root', satpRoot, width: xlen) : null; + + // Two-stage (hypervisor G-stage) wiring is present only when all three are + // provided AND single-stage paging exists to build on. + final hasTwoStage = + hasPaging && virtIn != null && gMode != null && gRoot != null; + virtIn = hasTwoStage ? addInput('virt', virtIn) : null; + gMode = hasTwoStage ? addInput('g_mode', gMode, width: 4) : null; + gRoot = hasTwoStage ? addInput('g_root', gRoot, width: xlen) : null; + + // Privilege/permission inputs for leaf checks (U-bit, SUM, MXR). When not + // wired, the leaf check falls back to R/W only (the pre-existing behavior). + final priv = privMode == null ? null : addInput('priv', privMode, width: 3); + final sumIn = sum == null ? null : addInput('sum', sum); + final mxrIn = mxr == null ? null : addInput('mxr', mxr); + final tlbFlushIn = tlbFlush == null + ? Const(0) + : addInput('tlbFlush', tlbFlush); + final dtlbFlushOnPrivIn = dtlbFlushOnPrivChange == null + ? Const(0) + : addInput('dtlbFlushOnPriv', dtlbFlushOnPrivChange); + + addOutput('ifetch_done'); + addOutput('ifetch_valid'); + addOutput('ifetch_rdata', width: xlen); + addOutput('dport_done'); + addOutput('dport_valid'); + addOutput('dport_rdata', width: xlen); + addOutput('dport_fault'); + // 1 when the dport fault occurred in the G-stage (second-stage) walk, so the + // consumer can raise a *guest* page-fault cause (20/21/23) vs the regular + // VS-stage cause (12/13/15). + addOutput('dport_fault_guest'); + // Asserted with ifetch_done & ~ifetch_valid when an instruction-fetch walk + // faults (invalid PTE, no X permission, or a U-bit violation). Lets the + // fetch consumer raise an instruction page fault (cause 12). + addOutput('ifetch_fault'); + addOutput('dataBus_CYC'); + addOutput('dataBus_STB'); + addOutput('dataBus_WE'); + addOutput('dataBus_ADR', width: busConfig.addressWidth); + addOutput('dataBus_DAT_MOSI', width: busConfig.dataWidth); + addOutput('dataBus_SEL', width: busConfig.effectiveSelWidth); + + // Internal registers + final arbState = Logic(name: 'arbState', width: 2); + final busActive = Logic(name: 'busActive'); + // Set for one cycle after a transaction completes so arbitration pauses, + // letting the requester (e.g. the fetch unit redirecting to a straddle's + // second word) present its next address before the next grant. Without it + // the arbiter would re-grant the stale address the moment the bus frees. + final justCompleted = Logic(name: 'justCompleted'); + + final ifDoneR = Logic(name: 'ifDoneR'); + final ifValidR = Logic(name: 'ifValidR'); + final ifRdataR = Logic(name: 'ifRdataR', width: xlen); + final dpDoneR = Logic(name: 'dpDoneR'); + final dpValidR = Logic(name: 'dpValidR'); + final dpRdataR = Logic(name: 'dpRdataR', width: xlen); + // Asserted with dpDone & ~dpValid when a page-table walk faults (invalid PTE + // or leaf-permission violation). Lets the dport consumer raise a *page* + // fault rather than the generic access fault. + final dpFaultR = Logic(name: 'dpFaultR'); + final dpFaultGuestR = Logic(name: 'dpFaultGuestR'); + // Asserted when a walk faults for an instruction fetch (routes the fault to + // ifetch_fault instead of dport_fault). + final ifFaultR = Logic(name: 'ifFaultR'); + final cycR = Logic(name: 'cycR'); + final stbR = Logic(name: 'stbR'); + final weR = Logic(name: 'weR'); + final adrR = Logic(name: 'adrR', width: busConfig.addressWidth); + final datMosiR = Logic(name: 'datMosiR', width: busConfig.dataWidth); + final selR = Logic(name: 'selR', width: busConfig.effectiveSelWidth); + + final selW = busConfig.effectiveSelWidth; + + // Page-table-walk state (only used when hasPaging). `walking` = the bus is + // fetching PTEs (vs the final translated access); walkLevel counts down from + // levels-1; the original dport request is held in req*. + final walking = Logic(name: 'walking'); + final walkLevel = Logic(name: 'walkLevel', width: 3); + final reqAddr = Logic(name: 'reqAddr', width: xlen); + final reqWe = Logic(name: 'reqWe'); + final reqWdata = Logic(name: 'reqWdata', width: xlen); + final reqSize = Logic(name: 'reqSize', width: 3); + // Each bus access of the walk is its own Wishbone transaction (cyc/stb drop + // between accesses, mirroring the single-access path). walkArmed = an access + // address is queued; walkAddr = that address; armed accesses are launched by + // a dedicated branch once the bus has gone idle. + final walkArmed = Logic(name: 'walkArmed'); + final walkAddr = Logic(name: 'walkAddr', width: busConfig.addressWidth); + // 1 while the active walk is for an instruction fetch (access type = instr), + // so leaf-permission checks use the X bit and the fetch U-bit rule, and a + // fault/result routes to the ifetch ports rather than the dport ports. + final isFetchWalk = Logic(name: 'isFetchWalk'); + // Svadu hardware A/D update: after a leaf read whose A (or, for a write, D) + // bit needs setting, the walk writes the updated PTE back to memory (an extra + // bus transaction) before the translated access. `adWrite` is 1 while that + // writeback is in flight; `adTransPa` stashes the translated PA to resume. + final adWrite = Logic(name: 'adWrite'); + final adTransPa = Logic(name: 'adTransPa', width: busConfig.addressWidth); + + // Single-entry instruction-fetch TLB. Caches the last walked fetch + // translation so the lockstep front-end (which re-presents the same + // instruction each cycle) does not re-walk per fetch and starve the data + // port. `ftlbPte` holds the leaf so the permission check re-runs per access + // (priv may change). Invalidated on satp change. + final ftlbValid = Logic(name: 'ftlbValid'); + final ftlbVpn = Logic(name: 'ftlbVpn', width: xlen - 12); + final ftlbPte = Logic(name: 'ftlbPte', width: xlen); + // Single-entry data TLB (mirrors the fetch TLB). `dtlbPte` holds the leaf so + // R/W/U re-checks per access. Single-stage only: guest (two-stage) accesses + // always walk (the cached leaf would be guest-physical). Flushed with ftlb. + final dtlbValid = Logic(name: 'dtlbValid'); + final dtlbVpn = Logic(name: 'dtlbVpn', width: xlen - 12); + final dtlbPte = Logic(name: 'dtlbPte', width: xlen); + final satpShadowMode = Logic(name: 'satpShadowMode', width: 4); + final satpShadowRoot = Logic(name: 'satpShadowRoot', width: xlen); + // Shadow of the privilege mode, to detect a context switch for DTLBFC. + final privShadow = Logic(name: 'privShadow', width: 3); + final privChanged = priv == null + ? Const(0) + : priv.neq(privShadow).named('privChanged'); + + // G-stage (hypervisor second-stage) walk state. Under two-stage, every + // VS-stage bus address (`walkAddr`) is guest-physical and must be G-walked + // through hgatp before launch. `gTranslated` marks `walkAddr` as already + // host-physical (launch directly). `gWalking`/`gWalkLevel`/`gWalkArmed`/ + // `gWalkAddr` mirror the VS-walk state for the inner G walk; `gReqAddr` holds + // the guest-physical being translated; `gSave*` preserve the VS access's + // we/data/sel across the G sub-walk so the final store re-launches. + final gWalking = Logic(name: 'gWalking'); + final gWalkLevel = Logic(name: 'gWalkLevel', width: 3); + final gWalkArmed = Logic(name: 'gWalkArmed'); + final gWalkAddr = Logic(name: 'gWalkAddr', width: busConfig.addressWidth); + final gReqAddr = Logic(name: 'gReqAddr', width: xlen); + final gTranslated = Logic(name: 'gTranslated'); + final gSaveWe = Logic(name: 'gSaveWe'); + final gSaveData = Logic(name: 'gSaveData', width: xlen); + final gSaveSel = Logic(name: 'gSaveSel', width: selW); + + // VPN[level] (9 bits): bits [12 + 9*level +: 9]. Each level's field is a + // fixed slice (L0=[20:12], L1=[29:21], L2=[38:30], L3=[47:39]), so select + // with a small 4:1 mux instead of a 64-bit variable barrel shift (big LUT + // saving). + Logic vpnOf(Logic addr, Logic level) { + Logic field(int lvl) => addr.slice(12 + 9 * lvl + 8, 12 + 9 * lvl); + return mux( + level.eq(0), + field(0), + mux(level.eq(1), field(1), mux(level.eq(2), field(2), field(3))), + ); } - if (config.hasMxr) { - assert(enableMxr != null, 'MXR is enabled in the MMU but not wired up.'); - enableMxr = addInput('enableMxr', enableMxr!); + // PTE fields (Sv39/Sv48, 8-byte PTE in the low bus word): V=bit0, R=bit1, + // X=bit3, PPN=bits 53:10. Next page-table base = PPN<<12. + Logic pteLeaf(Logic pte) => pte[1] | pte[3]; + // Page-fault conditions (V=bit0, R=bit1, W=bit2). A PTE is invalid if V=0 + // or the reserved encoding W&&!R. At a leaf, the access is denied if a write + // (reqWe) hits a non-writable page or a read hits a non-readable one. + Logic pteInvalid(Logic pte) => ~pte[0] | (~pte[1] & pte[2]); + // Leaf permission fault: the requested access must be allowed by the PTE. + // A fetch (isFetch) needs the X bit; a write needs W; a read needs R, or X + // when MXR lets a load read an execute-only page. The U bit must also fit the + // privilege: a user access needs U=1, and a supervisor access to a user page + // needs SUM, except a supervisor FETCH from a user page is never allowed + // (SUM does not cover instruction fetch). M-mode and unwired priv fall back + // to the R/W/X check only. + Logic leafPermFault(Logic pte, Logic isFetch, Logic we) { + final dataPerm = mux( + we, + pte[2], // write -> W + pte[1] | ((mxrIn ?? Const(0)) & pte[3]), // read -> R | (MXR & X) + ); + final permOk = mux(isFetch, pte[3], dataPerm); // fetch -> X + if (priv == null) return ~permOk; + final isUser = priv.eq(Const(PrivilegeMode.user.id, width: 3)); + final isSup = priv.eq(Const(PrivilegeMode.supervisor.id, width: 3)); + final u = pte[4]; + // SUM only relaxes supervisor data access to user pages, not fetches. + final supUserOk = (sumIn ?? Const(0)) & ~isFetch; + final uFault = (isUser & ~u) | (isSup & u & ~supUserOk); + return ~permOk | uFault; } - List pagingReset = []; - List pagingCycle = []; - - final devReadBusy = Logic(name: 'devReadBusy'); - final devReadClaim = Logic( - name: 'devReadClaim', - width: (devices.length + 1).bitLength, - ); - final devReadDone = Logic(name: 'devReadDone'); - final devReadValid = Logic(name: 'devReadValid'); - final devReadEnable = Logic(name: 'devReadEnable'); - final devReadAddr = Logic(name: 'devReadAddr', width: config.mxlen.size); - final devReadData = Logic(name: 'devReadData', width: config.mxlen.size); - - final devWriteBusy = Logic(name: 'devWriteBusy'); - final devWriteClaim = Logic( - name: 'devWriteClaim', - width: (devices.length + 1).bitLength, + Logic pteNextBase(Logic pte) => (pte.slice(53, 10) << 12).zeroExtend(xlen); + // Translated physical address for a 4KB leaf: {PTE.PPN, vaddr[11:0]}. + Logic leafPa(Logic pte, Logic vaddr) => + [pte.slice(53, 10), vaddr.slice(11, 0)].swizzle().zeroExtend(xlen); + // First-level (root) PTE byte address. + Logic ptePtr(Logic base, Logic vpn) => base + (vpn.zeroExtend(xlen) << 3); + final fullSel = Const((1 << selW) - 1, width: selW); + // Byte-enable mask for a log2-sized access, unshifted (lane 0); the lane + // shift happens at the bus boundary. Mask covers (1 << size) bytes: + // byte=0b1, half=0b11, word=0b1111. + Logic sizeSel(Logic log2Size) => mux( + log2Size.eq(0), + Const(0x1, width: selW), + mux( + log2Size.eq(1), + Const(0x3, width: selW), + mux(log2Size.eq(2), Const(0xF, width: selW), fullSel), + ), ); - final devWriteDone = Logic(name: 'devWriteDone'); - final devWriteValid = Logic(name: 'devWriteValid'); - final devWriteEnable = Logic(name: 'devWriteEnable'); - final devWriteAddr = Logic(name: 'devWriteAddr', width: config.mxlen.size); - final devWriteData = Logic(name: 'devWriteData', width: config.mxlen.size); - - final ptwEnable = Logic(name: 'ptwEnable'); - final ptwDone = Logic(name: 'ptwDone'); - final ptwValid = Logic(name: 'ptwValid'); - final ptwAccess = Logic(name: 'ptwAccess', width: 3); - final ptwPaddr = Logic(name: 'ptwPaddr', width: config.mxlen.size); - final ptwVaddr = Logic(name: 'ptwVaddr', width: config.mxlen.size); - - Logic needsPageTranslation = Const(0); - - if (config.hasPaging) { - final pagingModes = PagingMode.values.where( - (m) => m.isSupported(config.mxlen), - ); - - final maxPagingLevel = pagingModes - .map((m) => m.levels) - .fold(0, (a, b) => a > b ? a : b); - - final maxModeId = pagingModes - .map((m) => m.id) - .fold(0, (a, b) => a > b ? a : b); - final pagingModeWidth = maxModeId.bitLength == 0 - ? 1 - : maxModeId.bitLength; + // Levels-1 start index: Sv48 (MODE 9) = 3, else (Sv39) = 2. When the MMU has + // no Sv48, satp.MODE can never be 9, so pin startLevel to 2 and drop the + // satpMode==9 compare + Sv48 level (shrinks Sv39-only cores). + final hasSv48 = mmuConfig.pagingModes.contains(RiscVPagingMode.sv48); + final startLevel = (hasPaging && hasSv48) + ? mux(satpMode!.eq(9), Const(3, width: 3), Const(2, width: 3)) + : Const(2, width: 3); + final rootBase = hasPaging + ? (satpRoot! << 12).zeroExtend(xlen) + : Const(0, width: xlen); + final pagingOn = hasPaging ? satpMode!.neq(0) : Const(0); + // Fetch is translated only when paging is on AND below machine mode (MPRV + // only affects loads/stores, never fetch). When priv is unwired, fall back + // to pagingOn. Also bypassed in virtualized mode: a guest fetch needs + // two-stage (VS + G) translation, which the fetch path does not do yet. + final fetchPagingOn = priv == null + ? pagingOn + : (pagingOn & + priv.neq(Const(PrivilegeMode.machine.id, width: 3)) & + (virtIn == null ? Const(1) : ~virtIn)); + + // Fetch-TLB lookup for the requested fetch address. + final satpChanged = hasPaging + ? (satpMode!.neq(satpShadowMode) | satpRoot!.neq(satpShadowRoot)) + : Const(0); + // Gated on hasPaging: leafPa/leafPermFault assume an Sv39/Sv48 (64-bit) PTE + // layout, so they must not elaborate for non-paging (e.g. RV32) configs. + final ftlbHit = hasPaging + ? (ftlbValid & + ~satpChanged & + ifetchAddr.slice(xlen - 1, 12).eq(ftlbVpn)) + : Const(0); + // Re-run the fetch permission check on the cached leaf (priv may have moved) + // and compute the translated physical address from the cached PTE. + final ftlbPermFault = hasPaging + ? leafPermFault(ftlbPte, Const(1), Const(0)) + : Const(0); + final ftlbPa = hasPaging + ? leafPa(ftlbPte, ifetchAddr) + : Const(0, width: xlen); + + // G-stage derived signals. twoStage = guest mode with a non-bare G-stage. + // gRootBase/gStartLevel = hgatp root and top level. NOTE: the Sv39x4 "+2 + // bits at the root index" widening is not applied yet, fine while + // guest-physical addresses stay in the low 2^(9*levels+12) range. + final twoStage = hasTwoStage ? (virtIn! & gMode!.neq(0)) : Const(0); + final gRootBase = hasTwoStage + ? (gRoot! << 12).zeroExtend(xlen) + : Const(0, width: xlen); + final gStartLevel = hasTwoStage + ? mux(gMode!.eq(9), Const(3, width: 3), Const(2, width: 3)) + : Const(2, width: 3); + + // Data-TLB lookup for the requested data address. Disabled under two-stage + // (guest) translation: the cached leaf would be guest-physical, so always + // walk in that case. Mirrors the fetch-TLB combinational lookup above. + final dtlbUsable = hasTwoStage ? ~twoStage : Const(1); + final dtlbHit = hasPaging + ? (dtlbValid & + ~satpChanged & + dtlbUsable & + // A write to a page cached not-yet-dirty (D=0, bit 7) must re-walk + // so the Svadu writeback sets the D bit; reads always hit (A is + // already set on the cached leaf). + ~(dportWe & ~dtlbPte[7]) & + dportAddr.slice(xlen - 1, 12).eq(dtlbVpn)) + : Const(0); + final dtlbPermFault = hasPaging + ? leafPermFault(dtlbPte, Const(0), dportWe) + : Const(0); + // Svadu hardware A/D update (single-stage only; two-stage A/D is deferred). + // After a leaf read, set A (bit 6) and, for a write, D (bit 7); if the bit + // was not already set, write the updated PTE back before the access. + final adABit = Const(1, width: xlen) << 6; + final adDBit = Const(1, width: xlen) << 7; + final pteWithAd = hasPaging + ? wbDatMiso | adABit | mux(reqWe, adDBit, Const(0, width: xlen)) + : Const(0, width: xlen); + final adDoWrite = hasPaging + ? ((~wbDatMiso[6] | (reqWe & ~wbDatMiso[7])) & dtlbUsable) + : Const(0); + final dtlbPa = hasPaging + ? leafPa(dtlbPte, dportAddr) + : Const(0, width: xlen); - assert( - pagingMode != null, - 'Paging is enabled but missing paging mode input', - ); - pagingMode = addInput('pagingMode', pagingMode!, width: pagingModeWidth); - - assert( - pageTableAddress != null, - 'Paging is enabled but missing page table address input', - ); - pageTableAddress = addInput( - 'pageTableAddress', - pageTableAddress!, - width: config.mxlen.size, - ); + Sequential(clk, [ + If( + reset, + then: [ + arbState < 0, + busActive < 0, + justCompleted < 0, + ifDoneR < 0, + ifValidR < 0, + ifRdataR < 0, + dpDoneR < 0, + dpValidR < 0, + dpRdataR < 0, + dpFaultR < 0, + dpFaultGuestR < 0, + ifFaultR < 0, + isFetchWalk < 0, + adWrite < 0, + adTransPa < 0, + ftlbValid < 0, + ftlbVpn < 0, + dtlbValid < 0, + dtlbVpn < 0, + dtlbPte < 0, + ftlbPte < 0, + satpShadowMode < 0, + satpShadowRoot < 0, + privShadow < 0, + cycR < 0, + stbR < 0, + weR < 0, + adrR < 0, + datMosiR < 0, + selR < 0, + walking < 0, + walkArmed < 0, + walkAddr < 0, + walkLevel < 0, + reqAddr < 0, + reqWe < 0, + reqWdata < 0, + reqSize < 0, + if (hasTwoStage) ...[ + gWalking < 0, + gWalkArmed < 0, + gWalkAddr < 0, + gWalkLevel < 0, + gReqAddr < 0, + gTranslated < 0, + gSaveWe < 0, + gSaveData < 0, + gSaveSel < 0, + ], + ], + orElse: [ + ifDoneR < 0, + ifValidR < 0, + dpDoneR < 0, + dpValidR < 0, + dpFaultR < 0, + dpFaultGuestR < 0, + ifFaultR < 0, + justCompleted < 0, + privShadow < (priv ?? Const(0, width: 3)), + // Track satp so the fetch-TLB self-invalidates when it changes, and + // flush it on sfence.vma (tlbFlushIn). + if (hasPaging) ...[ + satpShadowMode < satpMode!, + satpShadowRoot < satpRoot!, + If(satpChanged | tlbFlushIn, then: [ftlbValid < 0, dtlbValid < 0]), + // DTLBFC: also drop the data TLB on a privilege-mode change (satp + // changes already flushed above) so a cached translation never + // survives a context switch on a paranoid config. + If(dtlbFlushOnPrivIn & privChanged, then: [dtlbValid < 0]), + ], - needsPageTranslation = pagingMode! - .gt(Const(PagingMode.bare.id, width: pagingMode!.width)) - .named('needsPageTranslation'); - - final ptwCycle = Logic(name: 'ptwCycle', width: maxPagingLevel.bitLength); - final pteAddress = Logic(name: 'pteAddress', width: config.mxlen.size); - final pte = Logic(name: 'pte', width: config.mxlen.size); - final pteV = Logic(name: 'pteV'); - final pteR = Logic(name: 'pteR'); - final pteW = Logic(name: 'pteW'); - final pteX = Logic(name: 'pteX'); - final pteU = Logic(name: 'pteU'); - - List defineVPN(Logic addr) { - final modes = pagingModes.toList(); - - final maxVpnBits = modes - .map((m) => m.vpnBits) - .fold(0, (a, b) => a > b ? a : b); - - Logic vpnForModeAtLevel(PagingMode m, int level) { - if (level >= m.levels || m.levels == 0) { - return Const(0, width: maxVpnBits); - } - - final shift = 12 + (m.vpnBits * level); - final shifted = addr >> Const(shift, width: addr.width); - - final mask = (1 << m.vpnBits) - 1; - final masked = shifted & Const(mask, width: addr.width); - - final bits = masked.getRange(0, m.vpnBits - 1); - - return (m.vpnBits == maxVpnBits) ? bits : bits.zeroExtend(maxVpnBits); - } - - return List.generate(maxPagingLevel, (i) { - Logic acc = Const(0, width: maxVpnBits); - - for (final m in modes.reversed) { - final isMode = pagingMode!.eq( - Const(m.id, width: pagingMode!.width), - ); - final v = vpnForModeAtLevel(m, i); - acc = mux(isMode, v.zeroExtend(acc.width), acc); - } - - return acc; - }).reversed.toList(); - } - - final pteBytes = pagingModes - .fold(Const(8, width: config.mxlen.size), (acc, m) { - final isMode = pagingMode!.eq( - Const(m.id, width: pagingMode!.width), - ); - - final bytes = Const(m.pteBytes, width: config.mxlen.size); - - return mux(isMode, bytes, acc); - }) - .named('pteBytes'); - - List vpnTop = defineVPN(ptwVaddr); - final vpnBottom = vpnTop.reversed.toList(); - - pagingReset.addAll([ - ptwEnable < 0, - ptwDone < 0, - ptwValid < 0, - ptwAccess < 0, - ptwPaddr < 0, - ptwVaddr < 0, - ptwCycle < 0, - pteAddress < 0, - pte < 0, - ]); - - Logic buildPhys(PagingMode mode, Logic pte) { - final offset = ptwVaddr & Const(0xFFF, width: config.mxlen.size); - Logic phys = Const(0, width: config.mxlen.size); - - for (int i = 0; i < mode.ppnBits.length; i++) { - final fromVpn = ptwCycle.lt(mode.levels - 1 - i); - final value = mux( - fromVpn, - vpnBottom[i].zeroExtend(config.mxlen.size), - ((pte >> mode.ppnShift(i)) & - Const((1 << mode.ppnBits[i]) - 1, width: config.mxlen.size)) - .zeroExtend(config.mxlen.size), - ); - - phys |= value << mode.ppnPhysShift(i); - } - - return phys | offset; - } - - pagingCycle.addAll([ - If( - ptwEnable, - then: [ - Case( - ptwCycle, - [ - for (var i = 0; i < maxPagingLevel; i++) - CaseItem(Const(i, width: maxPagingLevel.bitLength), [ + If.block([ + // G-stage (second-stage) PTE returned. (checked first: during a + // G sub-walk both gWalking and walking may be set). Resolves the + // host-physical address for the pending VS access, then resumes it. + if (hasTwoStage) + Iff(busActive & wbAck & gWalking, [ + cycR < 0, + stbR < 0, + If.block([ + // Invalid G-PTE -> guest page fault. + Iff(pteInvalid(wbDatMiso), [ + gWalking < 0, + gWalkArmed < 0, + walking < 0, + walkArmed < 0, + busActive < 0, + justCompleted < 1, + dpDoneR < 1, + dpValidR < 0, + dpFaultR < 1, + dpFaultGuestR < 1, + arbState < 0, + ]), + // G leaf. Every G-stage leaf page must be user-accessible + // (PTE.U=bit4), a non-U G-leaf is a guest page fault. When + // OK, walkAddr is now host-physical; re-arm the VS access + // (gTranslated=1 makes the launch fire directly) and restore + // its original write controls. + Iff(pteLeaf(wbDatMiso), [ If( - ~devReadBusy & devReadClaim.eq(0), + ~wbDatMiso[4], then: [ - if (i == 0) pteAddress < pageTableAddress, - devReadClaim < 1, - devReadBusy < 1, - devReadEnable < 1, - devReadAddr < - (pteAddress + - vpnTop[i].zeroExtend(config.mxlen.size) * - pteBytes), + gWalking < 0, + gWalkArmed < 0, + walking < 0, + walkArmed < 0, + busActive < 0, + justCompleted < 1, + dpDoneR < 1, + dpValidR < 0, + dpFaultR < 1, + dpFaultGuestR < 1, + arbState < 0, + ], + orElse: [ + gWalking < 0, + gTranslated < 1, + walkArmed < 1, + walkAddr < leafPa(wbDatMiso, gReqAddr), + weR < gSaveWe, + datMosiR < gSaveData, + selR < gSaveSel, ], ), + ]), + // No leaf at the last level -> guest page fault. + Iff(~gWalkLevel.or(), [ + gWalking < 0, + gWalkArmed < 0, + walking < 0, + walkArmed < 0, + busActive < 0, + justCompleted < 1, + dpDoneR < 1, + dpValidR < 0, + dpFaultR < 1, + dpFaultGuestR < 1, + arbState < 0, + ]), + // Pointer G-PTE -> descend. + Iff(Const(1), [ + gWalkLevel < (gWalkLevel - 1), + gWalkArmed < 1, + gWalkAddr < + ptePtr( + pteNextBase(wbDatMiso), + vpnOf(gReqAddr, gWalkLevel - 1), + ), + ]), + ]), + ]), + + // Page-table walk: a PTE just came back. + if (hasPaging) + Iff(busActive & wbAck & walking & ~(hasTwoStage ? gWalking : Const(0)), [ + // End this PTE's transaction. + cycR < 0, + stbR < 0, + If.block([ + // Invalid PTE (V=0 or reserved W&&!R) -> page fault. + Iff(pteInvalid(wbDatMiso), [ + walking < 0, + walkArmed < 0, + busActive < 0, + justCompleted < 1, + dpDoneR < ~isFetchWalk, + dpValidR < 0, + dpFaultR < ~isFetchWalk, + ifDoneR < isFetchWalk, + ifValidR < 0, + ifFaultR < isFetchWalk, + arbState < 0, + ]), + // Leaf PTE. + Iff(pteLeaf(wbDatMiso), [ If( - devReadBusy & - devReadClaim.eq(1) & - devReadDone & - devReadValid, + leafPermFault(wbDatMiso, isFetchWalk, reqWe), then: [ - devReadBusy < 0, - devReadClaim < 0, - devReadEnable < 0, - pte < devReadData, - pteV < - (devReadData & - Const(1, width: config.mxlen.size))[0], - pteR < - ((devReadData >> 1) & - Const(1, width: config.mxlen.size))[0], - pteW < - ((devReadData >> 2) & - Const(1, width: config.mxlen.size))[0], - pteX < - ((devReadData >> 3) & - Const(1, width: config.mxlen.size))[0], - pteU < - ((devReadData >> 4) & - Const(1, width: config.mxlen.size))[0], + // Permission violation -> page fault. + walking < 0, + walkArmed < 0, + busActive < 0, + justCompleted < 1, + dpDoneR < ~isFetchWalk, + dpValidR < 0, + dpFaultR < ~isFetchWalk, + ifDoneR < isFetchWalk, + ifValidR < 0, + ifFaultR < isFetchWalk, + arbState < 0, + ], + orElse: [ + // Arm the final translated access (guest-physical when + // two-stage: gTranslated<0 makes it G-translate first). + // Cache the walked leaf so a same-page re-access skips + // the walk (4KB leaves only). Fetch leaf -> ftlb, data + // leaf -> dtlb (single-stage only, dtlbUsable gates out + // guest leaves). Cache the A/D-updated leaf so a hit + // reflects the post-Svadu state. If( - (pteV.eq(0) | (pteR.eq(0) & pteW.eq(1))) | - (privilegeMode != null - ? (privilegeMode!.eq( - Const( - PrivilegeMode.user.id, - width: 3, - ), - ) & - pteU.eq(0)) - : Const(0)) | - (privilegeMode != null - ? (privilegeMode!.eq( - Const( - PrivilegeMode.supervisor.id, - width: 3, - ), - ) & - pteU.eq(1) & - (config.hasSum - ? ~enableSum! & ~ptwAccess.eq(2) - : Const(0))) - : Const(0)), - then: [ptwDone < 1, ptwValid < 0], + isFetchWalk, + then: [ + ftlbValid < 1, + ftlbVpn < reqAddr.slice(xlen - 1, 12), + ftlbPte < pteWithAd, + ], orElse: [ If( - pteR.eq(1) | pteX.eq(1), + dtlbUsable, then: [ - If( - ~mux( - ptwAccess.eq(0), - pteR.eq(1) | - (config.hasMxr - ? enableMxr! & pteX.eq(1) - : Const(0)), - mux( - ptwAccess.eq(1), - pteW.eq(1), - mux( - ptwAccess.eq(2), - pteX.eq(1), - Const(0), - ), - ), - ), - then: [ - ptwDone < 1, - ptwValid < 0, - ptwPaddr < 0, - ptwCycle < 0, - pteAddress < 0, - ], - orElse: [ - Case( - pagingMode, - [ - for (final mode in pagingModes) - CaseItem( - Const( - mode.id, - width: pagingModeWidth, - ), - [ - ptwPaddr < - buildPhys(mode, devReadData), - ptwDone < 1, - ptwValid < 1, - ], - ), - ], - defaultItem: [ptwDone < 1, ptwValid < 0], - ), - ], - ), - ], - orElse: [ - pteAddress < - ((devReadData >> 10) & - Const( - (1 << config.mxlen.size) - 1, - width: config.mxlen.size, - )) << - 12, - Case( - pagingMode, - [ - for (final mode in pagingModes) - CaseItem( - Const(mode.id, width: pagingModeWidth), - [ - if (i < (mode.levels - 1)) ...[ - ptwCycle < (ptwCycle + 1), - ptwDone < 0, - ptwValid < 0, - ] else ...[ - ptwDone < 1, - ptwValid < 0, - ptwPaddr < 0, - ptwCycle < 0, - pteAddress < 0, - ], - ], - ), - ], - defaultItem: [ - ptwDone < 1, - ptwValid < 0, - ptwPaddr < 0, - ptwCycle < 0, - pteAddress < 0, - ], - ), + dtlbValid < 1, + dtlbVpn < reqAddr.slice(xlen - 1, 12), + dtlbPte < pteWithAd, ], ), ], ), + walking < 0, + If( + adDoWrite, + then: [ + // Svadu: write the updated PTE (A, and D on a write) + // back to its address (walkAddr still holds the PTE + // pointer), then resume with the translated access. + adWrite < 1, + adTransPa < leafPa(wbDatMiso, reqAddr), + walkArmed < 1, + weR < 1, + datMosiR < pteWithAd, + selR < fullSel, + ], + orElse: [ + // A/D already set: arm the translated access directly. + walkArmed < 1, + walkAddr < leafPa(wbDatMiso, reqAddr), + weR < reqWe, + datMosiR < reqWdata, + // A fetch reads a full word; a dport uses its size. + selR < mux(isFetchWalk, fullSel, sizeSel(reqSize)), + if (hasTwoStage) gTranslated < 0, + ], + ), ], ), ]), - ], - defaultItem: [ - ptwDone < 1, - ptwValid < 0, - ptwPaddr < 0, - ptwCycle < 0, - pteAddress < 0, - ], - ), - ], - orElse: [ - ptwDone < 0, - ptwValid < 0, - ptwPaddr < 0, - ptwCycle < 0, - pteAddress < 0, - pte < 0, - ], - ), - ]); - } - - List defineReadPort( - MemoryAccess access, - DataPortInterface readPort, - int id, - ) => [ - if (config.hasPaging) - Iff( - readPort.en & - ~devReadBusy & - devReadClaim.eq(0) & - needsPageTranslation, - [ - ptwEnable < 1, - ptwVaddr < readPort.addr, - ptwAccess < - switch (access) { - MemoryAccess.instr => 2, - MemoryAccess.write => 1, - MemoryAccess.read => 0, - }, - readPort.done < 0, - readPort.valid < 0, - readPort.data < 0, - If( - ptwDone & ptwValid, - then: [ - ptwEnable < 0, - devReadBusy < 1, - devReadEnable < 1, - devReadClaim < id, - devReadAddr < ptwPaddr, - ], - ), - If( - ptwDone & ~ptwValid, - then: [ptwEnable < 0, readPort.done < 1, readPort.valid < 0], - ), - ], - ), - Iff( - readPort.en & ~devReadBusy & devReadClaim.eq(0) & ~needsPageTranslation, - [ - devReadEnable < 1, - devReadBusy < 1, - devReadClaim < id, - devReadAddr < readPort.addr, - readPort.done < 0, - readPort.valid < 0, - readPort.data < 0, - ], - ), - Iff(readPort.en & devReadBusy & devReadClaim.eq(id) & devReadDone, [ - readPort.done < devReadDone, - readPort.valid < devReadValid, - readPort.data < devReadData, - ]), - Iff(devReadBusy & devReadClaim.eq(id) & (~readPort.en | devReadDone), [ - readPort.done < 0, - readPort.valid < 0, - readPort.data < 0, - devReadBusy < 0, - devReadClaim < 0, - devReadEnable < 0, - ]), - ElseIf(devReadBusy & devReadClaim.eq(id), [ - readPort.done < 0, - readPort.valid < 0, - readPort.data < 0, - ]), - ]; - - List defineWritePort( - MemoryAccess access, - DataPortInterface writePort, - int id, - ) => [ - if (config.hasPaging) - Iff( - writePort.en & - ~devWriteBusy & - devWriteClaim.eq(0) & - needsPageTranslation, - [ - ptwEnable < 1, - ptwAccess < - switch (access) { - MemoryAccess.instr => 2, - MemoryAccess.write => 1, - MemoryAccess.read => 0, - }, - ptwVaddr < writePort.addr, - If( - ptwDone & ptwValid, - then: [ - ptwEnable < 0, - devWriteEnable < 1, - devWriteBusy < 1, - devWriteClaim < id, - devWriteAddr < ptwPaddr, - ], - ), - If( - ptwDone & ~ptwValid, - then: [ptwEnable < 0, writePort.done < 1, writePort.valid < 0], - ), - ], - ), - Iff( - writePort.en & - ~devWriteBusy & - devWriteClaim.eq(0) & - ~needsPageTranslation, - [ - devWriteEnable < 1, - devWriteBusy < 1, - devWriteClaim < id, - devWriteAddr < writePort.addr, - devWriteData < writePort.data, - ], - ), - Iff(devWriteBusy & devWriteClaim.eq(id), [ - writePort.done < devWriteDone, - writePort.valid < devWriteValid, - If( - devWriteDone & ~writePort.en, - then: [devWriteBusy < 0, devWriteClaim < 0, devWriteEnable < 0], - ), - ]), - ]; - - Sequential(clk, [ - If( - reset, - then: [ - for (final memReadPort in memReadPorts) ...[ - memReadPort.$2.done < 0, - memReadPort.$2.valid < 0, - memReadPort.$2.data < 0, - ], - for (final memWritePort in memWritePorts) ...[ - memWritePort.$2.done < 0, - memWritePort.$2.valid < 0, - ], - for (final dev in devices.values) ...[ - if (dev.$1 != null) ...[dev.$1!.en < 0, dev.$1!.addr < 0], - if (dev.$2 != null) ...[dev.$2!.en < 0, dev.$2!.addr < 0], - ], - devReadBusy < 0, - devReadEnable < 0, - devReadDone < 0, - devReadValid < 0, - devReadClaim < 0, - devWriteBusy < 0, - devWriteEnable < 0, - devWriteDone < 0, - devWriteClaim < 0, - ...pagingReset, - ], - orElse: [ - ...pagingCycle, - for (final memPort in [ - ...memReadPorts, - ...memWritePorts, - ].map((e) => e.$2)) - If(~memPort.en, then: [memPort.done < 0, memPort.valid < 0]), - If.block([ - for (final memReadPort in memReadPorts.indexed) - ...defineReadPort( - memReadPort.$2.$1, - memReadPort.$2.$2, - memReadPort.$1 + 2, - ), - for (final memWritePort in memWritePorts.indexed) - ...defineWritePort( - memWritePort.$2.$1, - memWritePort.$2.$2, - memWritePort.$1 + 2, - ), - ]), - If( - devReadEnable, - then: [ - if (devices.isEmpty) ...[ - devReadDone < 1, - devReadData < 0, - devReadValid < 0, - ] else - If.block([ - for (final dev in devices.entries) - Iff( - devReadAddr.gte(dev.key.start) & - devReadAddr.lt(dev.key.end), - dev.value.$1 != null - ? [ - dev.value.$1!.en < devReadBusy, - dev.value.$1!.addr < - (devReadAddr - - Const( - dev.key.start, - width: config.mxlen.size, - )) - .slice(dev.value.$1!.addr.width - 1, 0), - devReadData < - dev.value.$1!.data.zeroExtend( - config.mxlen.size, - ), - devReadDone < dev.value.$1!.done, - devReadValid < dev.value.$1!.valid, - ] - : [ - devReadData < 0, - devReadDone < 1, - devReadValid < 0, - ], - ), - Else([devReadDone < 1, devReadData < 0, devReadValid < 0]), + // Non-leaf at the last level (no leaf found) -> page fault. + Iff(~walkLevel.or(), [ + walking < 0, + walkArmed < 0, + busActive < 0, + justCompleted < 1, + dpDoneR < ~isFetchWalk, + dpValidR < 0, + dpFaultR < ~isFetchWalk, + ifDoneR < isFetchWalk, + ifValidR < 0, + ifFaultR < isFetchWalk, + arbState < 0, + ]), + // Pointer PTE, descend to the next level. + Iff(Const(1), [ + walkLevel < (walkLevel - 1), + walkArmed < 1, + walkAddr < + ptePtr( + pteNextBase(wbDatMiso), + vpnOf(reqAddr, walkLevel - 1), + ), + weR < 0, + datMosiR < 0, + selR < fullSel, + if (hasTwoStage) gTranslated < 0, + ]), ]), - ], - orElse: [devReadDone < 0, devReadData < 0, devReadValid < 0], - ), - If( - devWriteEnable, - then: [ - if (devices.isEmpty) ...[ - devWriteDone < 1, - devWriteValid < 0, - ] else - If.block([ - for (final dev in devices.entries) - Iff( - devWriteAddr.gte(dev.key.start) & - devWriteAddr.lt(dev.key.end), - dev.value.$2 != null - ? [ - dev.value.$2!.en < devWriteBusy, - dev.value.$2!.addr < - (devWriteAddr - - Const( - dev.key.start, - width: config.mxlen.size, - )) - .slice(dev.value.$2!.addr.width - 1, 0), - dev.value.$2!.data < - devWriteData.slice( - dev.value.$2!.data.width - 1, - 0, - ), - devWriteDone < dev.value.$2!.done, - devWriteValid < dev.value.$2!.valid, - If( - dev.value.$2!.done, - then: [dev.value.$2!.en < 0], + ]), + + // Svadu A/D PTE writeback completed: resume with the access. + if (hasPaging) + Iff(busActive & wbAck & adWrite, [ + cycR < 0, + stbR < 0, + adWrite < 0, + walkArmed < 1, + walkAddr < adTransPa, + weR < reqWe, + datMosiR < reqWdata, + selR < mux(isFetchWalk, fullSel, sizeSel(reqSize)), + if (hasTwoStage) gTranslated < 0, + ]), + + // ACK received, complete the (non-walk) transaction. + if (hasPaging) + Iff(busActive & wbAck & ~walking & ~adWrite, [ + cycR < 0, + stbR < 0, + busActive < 0, + justCompleted < 1, + If( + arbState.eq(1), + then: [ + // Wishbone byte-lane convention: a sub-word load reads an + // aligned word with the addressed byte in its lane, so shift + // it back to lane 0 (mirrors the write path's lane shift); + // else e.g. `lbu` at byte offset 5 reads the wrong byte. + // Ifetch stays unshifted (the fetch unit extracts its own). + dpRdataR < + (wbDatMiso >> + [ + adrR.getRange( + 0, + (busConfig.effectiveSelWidth - 1).bitLength, ), - ] - : [devWriteDone < 1, devWriteValid < 0], + Const(0, width: 3), + ].swizzle()), + dpDoneR < 1, + dpValidR < 1, + ], + ), + If( + arbState.eq(2), + then: [ifRdataR < wbDatMiso, ifDoneR < 1, ifValidR < 1], + ), + arbState < 0, + ]) + else + Iff(busActive & wbAck, [ + cycR < 0, + stbR < 0, + busActive < 0, + justCompleted < 1, + If( + arbState.eq(1), + then: [ + // Wishbone byte-lane convention: a sub-word load reads an + // aligned word with the addressed byte in its lane, so shift + // it back to lane 0 (mirrors the write path's lane shift); + // else e.g. `lbu` at byte offset 5 reads the wrong byte. + // Ifetch stays unshifted (the fetch unit extracts its own). + dpRdataR < + (wbDatMiso >> + [ + adrR.getRange( + 0, + (busConfig.effectiveSelWidth - 1).bitLength, + ), + Const(0, width: 3), + ].swizzle()), + dpDoneR < 1, + dpValidR < 1, + ], + ), + If( + arbState.eq(2), + then: [ifRdataR < wbDatMiso, ifDoneR < 1, ifValidR < 1], + ), + arbState < 0, + ]), + + // Launch an armed walk access once the bus is idle. + // With two-stage active, the armed (guest-physical) address is first + // diverted through a G-stage sub-walk; once gTranslated, it launches. + if (hasPaging && hasTwoStage) + Iff(busActive & walkArmed & ~cycR, [ + walkArmed < 0, + If( + twoStage & ~gTranslated, + then: [ + gSaveWe < weR, + gSaveData < datMosiR, + gSaveSel < selR, + gWalking < 1, + gWalkLevel < gStartLevel, + gReqAddr < walkAddr, + gWalkArmed < 1, + gWalkAddr < ptePtr(gRootBase, vpnOf(walkAddr, gStartLevel)), + weR < 0, + datMosiR < 0, + selR < fullSel, + ], + orElse: [cycR < 1, stbR < 1, adrR < walkAddr], + ), + ]) + else if (hasPaging) + Iff(busActive & walkArmed & ~cycR, [ + walkArmed < 0, + cycR < 1, + stbR < 1, + adrR < walkAddr, + ]), + + // Launch an armed G-stage (second-stage) walk access. + if (hasTwoStage) + Iff(busActive & gWalkArmed & ~cycR, [ + gWalkArmed < 0, + cycR < 1, + stbR < 1, + adrR < gWalkAddr, + weR < 0, + datMosiR < 0, + selR < fullSel, + ]), + + // Bus active, waiting + Iff(busActive, []), + + // Idle, arbitrate (dport > ifetch); pause one cycle after a + // completion so the requester can update its address first. + Iff(~busActive & ~justCompleted & dportEn, [ + arbState < 1, + busActive < 1, + isFetchWalk < 0, + if (hasPaging) + If( + pagingOn, + then: [ + If( + dtlbHit, + then: [ + // Data-TLB hit: skip the walk. Re-check the permission on + // the cached leaf (priv/we may differ from when cached). + walking < 0, + If( + dtlbPermFault, + then: [ + // Permission violation -> page fault. + busActive < 0, + justCompleted < 1, + dpDoneR < 1, + dpValidR < 0, + dpFaultR < 1, + arbState < 0, + ], + orElse: [ + // Direct translated access at the cached PA. + cycR < 1, + stbR < 1, + adrR < dtlbPa, + weR < dportWe, + datMosiR < dportWdata, + selR < sizeSel(dportSize), + ], + ), + ], + orElse: [ + // TLB miss: start the page-table walk. Latch the request + // and arm the root PTE fetch (launched next cycle). + walking < 1, + walkLevel < startLevel, + reqAddr < dportAddr, + reqWe < dportWe, + reqWdata < dportWdata, + reqSize < dportSize, + walkArmed < 1, + walkAddr < + ptePtr(rootBase, vpnOf(dportAddr, startLevel)), + weR < 0, + datMosiR < 0, + selR < fullSel, + // The VS root pointer is guest-physical under two-stage. + if (hasTwoStage) gTranslated < 0, + ], ), - Else([devWriteDone < 1, devWriteValid < 0]), - ]), - ], - orElse: [devWriteDone < 0, devWriteValid < 0], - ), + ], + orElse: [ + walking < 0, + cycR < 1, + stbR < 1, + adrR < dportAddr, + weR < dportWe, + datMosiR < dportWdata, + selR < sizeSel(dportSize), + ], + ) + else ...[ + cycR < 1, + stbR < 1, + adrR < dportAddr, + weR < dportWe, + datMosiR < dportWdata, + selR < sizeSel(dportSize), + ], + ]), + + Iff(~busActive & ~justCompleted & ~dportEn & ifetchEn, [ + arbState < 2, + busActive < 1, + if (hasPaging && translateFetch) + If( + fetchPagingOn, + then: [ + If( + ftlbHit, + then: [ + // Fetch-TLB hit: skip the walk. Re-check the fetch + // permission on the cached leaf (priv may have changed). + If( + ftlbPermFault, + then: [ + // Not fetchable now -> instruction page fault. + isFetchWalk < 0, + walking < 0, + busActive < 0, + justCompleted < 1, + ifDoneR < 1, + ifValidR < 0, + ifFaultR < 1, + arbState < 0, + ], + orElse: [ + // Direct fetch at the cached physical address. + isFetchWalk < 0, + walking < 0, + cycR < 1, + stbR < 1, + adrR < ftlbPa, + weR < 0, + datMosiR < 0, + selR < fullSel, + ], + ), + ], + orElse: [ + // TLB miss: walk the page table for ifetchAddr as an + // instruction access. isFetchWalk routes the X-permission + // check, the fault, and the result to the ifetch ports, + // and the leaf is cached for subsequent re-fetches. + isFetchWalk < 1, + walking < 1, + walkLevel < startLevel, + reqAddr < ifetchAddr, + reqWe < 0, + reqWdata < 0, + reqSize < Const(3, width: 3), + walkArmed < 1, + walkAddr < + ptePtr(rootBase, vpnOf(ifetchAddr, startLevel)), + weR < 0, + datMosiR < 0, + selR < fullSel, + if (hasTwoStage) gTranslated < 0, + ], + ), + ], + orElse: [ + isFetchWalk < 0, + walking < 0, + cycR < 1, + stbR < 1, + adrR < ifetchAddr, + weR < 0, + datMosiR < 0, + selR < fullSel, + ], + ) + else ...[ + cycR < 1, + stbR < 1, + adrR < ifetchAddr, + weR < 0, + datMosiR < 0, + selR < fullSel, + ], + ]), + ]), ], ), ]); + + // Drive outputs from registers + ifetchDone <= ifDoneR; + ifetchValid <= ifValidR; + ifetchRdata <= ifRdataR; + dportDone <= dpDoneR; + dportValid <= dpValidR; + dportRdata <= dpRdataR; + dportFault <= dpFaultR; + ifetchFault <= ifFaultR; + dportFaultGuest <= dpFaultGuestR; + wbCyc <= cycR; + wbStb <= stbR; + wbWe <= weR; + // Wishbone byte-lane convention at the bus boundary. The FSM tracks exact + // byte addresses, lane-0 write data, and an unshifted size mask in selR; the + // bus carries a word-aligned address with the byte position in SEL and the + // data shifted into its lane. Walk accesses are word-aligned with fullSel, + // so this is the identity for them. + final laneBits = (busConfig.effectiveSelWidth - 1).bitLength; + final busLane = adrR.getRange(0, laneBits).named('busLane'); + wbAdr <= + [ + adrR.getRange(laneBits, busConfig.addressWidth), + Const(0, width: laneBits), + ].swizzle(); + wbDatMosi <= datMosiR << [busLane, Const(0, width: 3)].swizzle(); + wbSel <= selR << busLane; } } diff --git a/packages/river_hdl/lib/src/core/pipeline.dart b/packages/river_hdl/lib/src/core/pipeline.dart index a6c766d..a3b467f 100644 --- a/packages/river_hdl/lib/src/core/pipeline.dart +++ b/packages/river_hdl/lib/src/core/pipeline.dart @@ -1,14 +1,36 @@ import 'package:rohd/rohd.dart'; -import 'package:rohd_hcl/rohd_hcl.dart'; -import 'package:riscv/riscv.dart'; +import 'package:river/river.dart'; +import '../data_port.dart'; +import '../microcode_rom.dart'; +import 'decode_control.dart'; import 'decoder.dart'; import 'exec.dart'; +import 'compressed_fetch_buffer.dart'; import 'fetcher.dart'; +import 'prefetch_fetcher.dart'; +import 'pipelined_fetcher.dart'; +import 'fu_alu.dart'; +import 'fu_branch.dart'; +import 'fu_csr.dart'; +import 'fu_mem.dart'; +import 'issue.dart'; +import 'load_queue.dart'; +import 'lsq.dart'; +import 'rename.dart'; +import 'rob.dart'; +import 'stages.dart'; +/// River OoO dual-issue pipeline. +/// +/// Uses Harbor's [PipelineBuilder] for the in-order front-end +/// (fetch → decode → rename), then dispatches to an [IssueQueue] +/// that feeds OoO functional units (2× ALU, 1× memory, 1× branch, 1× CSR). +/// A [ReorderBuffer] ensures in-order commit. class RiverPipeline extends Module { - final Microcode microcode; - final Mxlen mxlen; + final MicrocodeRom microcode; + final RiscVMxlen mxlen; + final int vlen; Logic get done => output('done'); Logic get valid => output('valid'); @@ -18,11 +40,17 @@ class RiverPipeline extends Module { Logic get trap => output('trap'); Logic get trapCause => output('trapCause'); Logic get trapTval => output('trapTval'); + Logic get trapEpc => output('trapEpc'); + Logic get isReturn => output('isReturn'); + Logic get returnLevel => output('returnLevel'); + Logic get memGuest => output('memGuest'); Logic get fence => output('fence'); Logic get interruptHold => output('interruptHold'); Logic get counter => output('counter'); - late final FetchUnit fetcher; + // FetchUnit, or PrefetchFetchUnit when prefetchFetch is enabled. Both expose + // done/valid/result/pc_out outputs; the pipeline reads them via output wires. + late final Module fetcher; RiverPipeline( Logic clk, @@ -41,6 +69,18 @@ class RiverPipeline extends Module { DataPortInterface rdWrite, DataPortInterface? microcodeDecodeRead, DataPortInterface? microcodeExecRead, { + bool useOoO = false, + bool speculative = false, + bool dualDispatch = false, + bool prefetchFetch = false, + int prefetchDepth = 2, + int fetchOutstanding = 1, + FetchReadInterface? fetchReadPort, + BranchPredictor branchPredictor = BranchPredictor.none, + LoadStoreQueue loadStoreQueue = LoadStoreQueue.none, + int robDepth = 64, + int storeQueueDepth = 8, + int loadQueueDepth = 8, bool useMixedDecoders = false, bool useMixedExecution = false, bool hasSupervisor = false, @@ -48,10 +88,38 @@ class RiverPipeline extends Module { bool hasCompressed = false, required this.microcode, required this.mxlen, + this.vlen = 128, Logic? mideleg, Logic? medeleg, Logic? mtvec, Logic? stvec, + // mret/sret return targets (for the OoO commit-stage fetcher redirect). + Logic? mepc, + Logic? sepc, + // Backdoor seed for the OoO physical regfile (so test harnesses can preset + // architectural registers). prfSeedAddr is the 5-bit ARCH index, which the + // identity rename map (reset state) maps to the same physical reg. Driven + // only while the core is frozen (no writeback), so it is exclusive with the + // normal prf writeback. No effect on the in-order path. + Logic? prfSeedEn, + Logic? prfSeedAddr, + Logic? prfSeedData, + Logic? virt, + Logic? mstateen0Se0, + Logic? hstateen0Se0, + Logic? memFaultGuest, + // rpipelinectl vendor CSR (speculation control). When wired, bit [1] (BPD) + // suppresses branch prediction at runtime (forces predicted-not-taken). + // Other bits (SSBD/SERIALIZE/DTLBFC) are consumed elsewhere / reserved. + Logic? specCtl, + // The fetch port's instruction page-fault signal (MMU ifetch_fault). When + // wired and translateFetch is on, a faulting fetch is delivered as a fetch + // fault that the exec stage turns into instructionPageFault. + Logic? ifetchFault, + DataPortInterface? rdWrite1, + DataPortInterface? memFetchRead1, + Logic? wr0Ready, + Logic? wr1Ready, int counterWidth = 32, List staticInstructions = const [], super.name = 'river_pipeline', @@ -65,10 +133,10 @@ class RiverPipeline extends Module { currentMode = addInput('currentMode', currentMode, width: 3); if (csrRead != null) { - csrRead = csrRead!.clone() + csrRead = csrRead.clone() ..connectIO( this, - csrRead!, + csrRead, outputTags: {DataPortGroup.control}, inputTags: {DataPortGroup.data, DataPortGroup.integrity}, uniquify: (og) => 'csrRead_$og', @@ -76,10 +144,10 @@ class RiverPipeline extends Module { } if (csrWrite != null) { - csrWrite = csrWrite!.clone() + csrWrite = csrWrite.clone() ..connectIO( this, - csrWrite!, + csrWrite, outputTags: {DataPortGroup.control, DataPortGroup.data}, inputTags: {DataPortGroup.integrity}, uniquify: (og) => 'csrWrite_$og', @@ -94,6 +162,19 @@ class RiverPipeline extends Module { inputTags: {DataPortGroup.data, DataPortGroup.integrity}, uniquify: (og) => 'memFetchRead_$og', ); + // Multiple-outstanding fetch port (master side): drives the request channel, + // reads ready + response. Used instead of memFetchRead when a pipelined + // fetch memory feeds a PipelinedFetchUnit (fetchOutstanding > 1). + if (fetchReadPort != null) { + fetchReadPort = fetchReadPort.clone() + ..connectIO( + this, + fetchReadPort, + outputTags: {FetchReadGroup.request}, + inputTags: {FetchReadGroup.requestReady, FetchReadGroup.response}, + uniquify: (og) => 'fetchReadPort_$og', + ); + } memExecRead = memExecRead.clone() ..connectIO( this, @@ -102,6 +183,17 @@ class RiverPipeline extends Module { inputTags: {DataPortGroup.data, DataPortGroup.integrity}, uniquify: (og) => 'memExecRead_$og', ); + // Dual-dispatch: second instruction-fetch port (lane 1). + if (memFetchRead1 != null) { + memFetchRead1 = memFetchRead1.clone() + ..connectIO( + this, + memFetchRead1, + outputTags: {DataPortGroup.control}, + inputTags: {DataPortGroup.data, DataPortGroup.integrity}, + uniquify: (og) => 'memFetchRead1_$og', + ); + } memWrite = memWrite.clone() ..connectIO( this, @@ -136,11 +228,29 @@ class RiverPipeline extends Module { uniquify: (og) => 'rdWrite_$og', ); + // Dual-commit: second register write port + its back-pressure inputs. + if (rdWrite1 != null) { + rdWrite1 = rdWrite1.clone() + ..connectIO( + this, + rdWrite1, + outputTags: {DataPortGroup.control, DataPortGroup.data}, + inputTags: {DataPortGroup.integrity}, + uniquify: (og) => 'rdWrite1_$og', + ); + } + if (wr0Ready != null) { + wr0Ready = addInput('wr0Ready', wr0Ready); + } + if (wr1Ready != null) { + wr1Ready = addInput('wr1Ready', wr1Ready); + } + if (microcodeDecodeRead != null) { - microcodeDecodeRead = microcodeDecodeRead!.clone() + microcodeDecodeRead = microcodeDecodeRead.clone() ..connectIO( this, - microcodeDecodeRead!, + microcodeDecodeRead, outputTags: {DataPortGroup.control}, inputTags: {DataPortGroup.data, DataPortGroup.integrity}, uniquify: (og) => 'microcodeDecodeRead_$og', @@ -148,22 +258,55 @@ class RiverPipeline extends Module { } if (microcodeExecRead != null) { - microcodeExecRead = microcodeExecRead!.clone() + microcodeExecRead = microcodeExecRead.clone() ..connectIO( this, - microcodeExecRead!, + microcodeExecRead, outputTags: {DataPortGroup.control}, inputTags: {DataPortGroup.data, DataPortGroup.integrity}, uniquify: (og) => 'microcodeExecRead_$og', ); } - if (mideleg != null) + if (mideleg != null) { mideleg = addInput('mideleg', mideleg, width: mxlen.size); - if (medeleg != null) + } + if (medeleg != null) { medeleg = addInput('medeleg', medeleg, width: mxlen.size); + } if (mtvec != null) mtvec = addInput('mtvec', mtvec, width: mxlen.size); if (stvec != null) stvec = addInput('stvec', stvec, width: mxlen.size); + if (mepc != null) mepc = addInput('mepc', mepc, width: mxlen.size); + if (sepc != null) sepc = addInput('sepc', sepc, width: mxlen.size); + final prfSeedEnIn = prfSeedEn == null + ? Const(0) + : addInput('prfSeedEn', prfSeedEn); + final prfSeedAddrIn = prfSeedAddr == null + ? Const(0, width: 5) + : addInput('prfSeedAddr', prfSeedAddr, width: 5); + final prfSeedDataIn = prfSeedData == null + ? Const(0, width: mxlen.size) + : addInput('prfSeedData', prfSeedData, width: mxlen.size); + if (virt != null) virt = addInput('virtIn', virt); + if (mstateen0Se0 != null) { + mstateen0Se0 = addInput('mstateen0Se0', mstateen0Se0); + } + if (hstateen0Se0 != null) { + hstateen0Se0 = addInput('hstateen0Se0', hstateen0Se0); + } + if (memFaultGuest != null) { + memFaultGuest = addInput('memFaultGuest', memFaultGuest); + } + // Speculation-control bits (rpipelinectl). Default 0 = no override when the + // CSR is absent, so non-Zicsr cores keep their compile-time behaviour. + final specCtlIn = specCtl == null + ? Const(0, width: 4) + : addInput('specCtl', specCtl, width: 4); + final bpdDisable = specCtlIn[1].named('bpdDisable'); + final ssbdDisable = specCtlIn[0].named('ssbdDisable'); + final ifetchFaultIn = ifetchFault == null + ? Const(0) + : addInput('ifetchFault', ifetchFault); addOutput('done'); addOutput('valid'); @@ -173,543 +316,1909 @@ class RiverPipeline extends Module { addOutput('trap'); addOutput('trapCause', width: 6); addOutput('trapTval', width: mxlen.size); + addOutput('trapEpc', width: mxlen.size); + addOutput('isReturn'); + addOutput('returnLevel', width: 3); + // memGuest is a *combinational* passthrough (driven below, not registered) + // so it aligns with the direct exec mem-port -> dport path, holding the + // guest-translation routing steady across the multi-cycle MMU walk. + addOutput('memGuest'); addOutput('fence'); addOutput('interruptHold'); addOutput('counter', width: counterWidth); - fetcher = FetchUnit( - clk, - reset, - enable, - currentPc, - memFetchRead, - hasCompressed: hasCompressed, - ); + // Speculative-fetch control wires (driven in the OoO section below). When + // not speculative they stay null → FetchUnit defaults them off (lockstep). + final fetchAdvance = speculative ? Logic(name: 'fetchAdvance') : null; + final fetchRedirect = speculative ? Logic(name: 'fetchRedirect') : null; + final fetchRedirectPc = speculative + ? Logic(name: 'fetchRedirectPc', width: mxlen.size) + : null; + + // Dual-dispatch uses the CompressedFetchBuffer: one wide fetch port streams + // aligned words into a FIFO, and a variable-length aligner presents TWO + // instructions per cycle, instr0 at the current PC, instr1 at PC + size0*2 + // (works for compressed and fixed-width alike). Dispatch consumes 1 or 2 per + // cycle via consume0/consume1 (driven in the OoO section below). This + // replaces the old two-FetchUnit lane1=lane0+4 scheme, which could not align + // variable-length instructions. See project_hdl_dualissue / prefetch buffer. + final useCompressedFetch = dualDispatch; + final bufConsume0 = useCompressedFetch ? Logic(name: 'bufConsume0') : null; + final bufConsume1 = useCompressedFetch ? Logic(name: 'bufConsume1') : null; + // The pipelined prefetch fetcher (single-issue, non-compressed, speculative + // OoO only, see config validation) fetches one ahead into a FIFO so fetch + // latency overlaps decode/rename/alloc. Drop-in outputs. See + // project_hdl_prefetch. + // Multiple-outstanding fetch: a PipelinedFetchUnit over the decoupled + // fetchReadPort (fed by a pipelined fetch memory in the core) keeps several + // reads in flight, hiding fetch latency the single-outstanding fetchers + // cannot. Same constraints as prefetch (single-issue, non-compressed, + // speculative), plus fetchOutstanding > 1 and a port supplied. + final usePipelined = + prefetchFetch && + speculative && + !dualDispatch && + !hasCompressed && + fetchOutstanding > 1 && + fetchReadPort != null; + final usePrefetch = + prefetchFetch && + speculative && + !dualDispatch && + !hasCompressed && + !usePipelined; + CompressedFetchBuffer? cfb; + final Logic fetchOutDone, fetchOutValid, fetchOutResult, fetchOutPc; + if (useCompressedFetch) { + cfb = CompressedFetchBuffer( + clk, + reset, + enable, + currentPc, + memFetchRead, + redirect: fetchRedirect, + redirectPc: fetchRedirectPc, + consume0: bufConsume0, + consume1: bufConsume1, + depth: prefetchDepth < 4 ? 4 : prefetchDepth, + ); + fetcher = cfb; + // Lane 0 = the buffer's first instruction. valid0 already gates on enable, + // so present `done` high → fetchDone == valid0. + fetchOutDone = Const(1); + fetchOutValid = cfb.valid0; + fetchOutResult = cfb.instr0; + fetchOutPc = cfb.pc0; + // One wide port feeds both lanes, so the second fetch port is unused here; + // tie it off so it presents no bus traffic. + if (memFetchRead1 != null) { + memFetchRead1.en <= Const(0); + memFetchRead1.addr <= Const(0, width: memFetchRead1.addr.width); + } + } else if (usePipelined) { + // Fetch comes from the decoupled pipelined port; the single-outstanding + // memFetchRead is unused, so tie its request channel off (no bus traffic). + memFetchRead.en <= Const(0); + memFetchRead.addr <= Const(0, width: memFetchRead.addr.width); + fetcher = PipelinedFetchUnit( + clk, + reset, + enable, + currentPc, + fetchReadPort, + advance: fetchAdvance, + redirect: fetchRedirect, + redirectPc: fetchRedirectPc, + depth: prefetchDepth, + maxOutstanding: fetchOutstanding, + ); + fetchOutDone = fetcher.output('done'); + fetchOutValid = fetcher.output('valid'); + fetchOutResult = fetcher.output('result'); + fetchOutPc = fetcher.output('pc_out'); + } else { + fetcher = usePrefetch + ? PrefetchFetchUnit( + clk, + reset, + enable, + currentPc, + memFetchRead, + advance: fetchAdvance, + redirect: fetchRedirect, + redirectPc: fetchRedirectPc, + depth: prefetchDepth, + ) + : FetchUnit( + clk, + reset, + enable, + currentPc, + memFetchRead, + hasCompressed: hasCompressed, + advance: fetchAdvance, + redirect: fetchRedirect, + redirectPc: fetchRedirectPc, + fault: usePrefetch ? null : ifetchFaultIn, + ); + fetchOutDone = fetcher.output('done'); + fetchOutValid = fetcher.output('valid'); + fetchOutResult = fetcher.output('result'); + fetchOutPc = fetcher.output('pc_out'); + } + + // The fetch-fault marker (FetchUnit only; the prefetch/dual fetchers do not + // carry fetch faults yet). Used to raise an instruction page fault. + final usePlainFetchUnit = + !useCompressedFetch && !usePrefetch && !usePipelined; + final fetchFaultSig = usePlainFetchUnit + ? fetcher.output('fetch_fault') + : Const(0); + + // Helper: resize signal to target width (truncate or zero-extend) + Logic fitWidth(Logic sig, int targetWidth) { + if (sig.width == targetWidth) return sig; + if (sig.width > targetWidth) return sig.slice(targetWidth - 1, 0); + return sig.zeroExtend(targetWidth); + } + + final fetchDone = fetchOutDone & fetchOutValid & enable; + + // The fetcher's PC of the delivered instruction flows through the decoder + // (pcIn → pcOut), registered with the decode, so PC + instruction + decode + // stay paired (fixes the OoO branch/decode skew). final decoder0 = microcodeDecodeRead != null ? DynamicInstructionDecoder( clk, reset, - fetcher.done & fetcher.valid, - fetcher.result, - microcodeDecodeRead!, + fetchDone, + fetchOutResult, + microcodeDecodeRead, microcode: microcode, mxlen: mxlen, staticInstructions: staticInstructions, counterWidth: counterWidth, + pcIn: fetchOutPc, ) : StaticInstructionDecoder( clk, reset, - fetcher.done & fetcher.valid, - fetcher.result, + fetchDone, + fetchOutResult, microcode: microcode, mxlen: mxlen, staticInstructions: staticInstructions, counterWidth: counterWidth, + pcIn: fetchOutPc, ); - final decoder1 = (useMixedDecoders && microcodeDecodeRead != null) + final decodeDone = decoder0.done; + final decodeValid = decoder0.valid; + + // Lane-1 decoder (dual-dispatch). Static decoder only (dual-dispatch + // requires speculative + non-microcoded; see config validation). + final fetchDone1 = dualDispatch ? (cfb!.valid1 & enable) : null; + final decoder1 = dualDispatch ? StaticInstructionDecoder( clk, reset, - fetcher.done & fetcher.valid, - fetcher.result, + fetchDone1!, + cfb!.instr1, microcode: microcode, mxlen: mxlen, staticInstructions: staticInstructions, counterWidth: counterWidth, + pcIn: cfb.pc1, + name: 'static_instruction_decoder_1', ) : null; - final decodeIndex = decoder1 != null - ? mux(decoder0.done & decoder0.valid, decoder0.index, decoder1!.index) - : decoder0.index; - final decodeInstrTypeMap = decoder1 != null - ? decoder0.instrTypeMap.map( - (name, value) => MapEntry( - name, - mux( - decoder0.done & decoder0.valid, - value, - decoder1!.instrTypeMap[name]!, - ).named(name), - ), + if (!useOoO) { + // ======================================================================= + // Classic in-order pipeline (fetch → decode → execute) + // ======================================================================= + + final readyExecution = + (fetchOutValid & fetchOutDone & decodeValid & decodeDone).named( + 'readyExecution', + ); + + final exec = microcodeExecRead != null + ? DynamicExecutionUnit( + clk, + reset, + readyExecution, + currentSp, + currentPc, + currentMode, + decoder0.index, + decoder0.instrTypeMap, + decoder0.fields, + csrRead, + csrWrite, + memExecRead, + memWrite, + rs1Read, + rs2Read, + rdWrite, + microcodeExecRead, + hasSupervisor: hasSupervisor, + hasUser: hasUser, + microcode: microcode, + mxlen: mxlen, + mideleg: mideleg, + medeleg: medeleg, + mtvec: mtvec, + stvec: stvec, + virtIn: virt, + mstateen0Se0: mstateen0Se0, + hstateen0Se0: hstateen0Se0, + memFaultGuest: memFaultGuest, + fetchFault: fetchFaultSig, + staticInstructions: staticInstructions, + counterWidth: counterWidth, + ) + : StaticExecutionUnit( + clk, + reset, + readyExecution, + currentSp, + currentPc, + currentMode, + decoder0.index, + decoder0.instrTypeMap, + decoder0.fields, + csrRead, + csrWrite, + memExecRead, + memWrite, + rs1Read, + rs2Read, + rdWrite, + hasSupervisor: hasSupervisor, + hasUser: hasUser, + microcode: microcode, + mxlen: mxlen, + vlen: vlen, + mideleg: mideleg, + medeleg: medeleg, + mtvec: mtvec, + stvec: stvec, + virtIn: virt, + mstateen0Se0: mstateen0Se0, + hstateen0Se0: hstateen0Se0, + memFaultGuest: memFaultGuest, + fetchFault: fetchFaultSig, + staticInstructions: staticInstructions, + counterWidth: counterWidth, + ); + + final execDone = exec.done; + final execValid = exec.valid; + + Sequential(clk, [ + If( + reset | ~execDone, + then: [ + done < 0, + valid < 0, + nextSp < 0, + nextPc < 0, + nextMode < 0, + trap < 0, + trapCause < 0, + trapTval < 0, + trapEpc < 0, + isReturn < 0, + returnLevel < 0, + fence < 0, + counter < 0, + ], + orElse: [ + done < fetchOutDone & decodeDone & execDone, + valid < fetchOutValid & decodeValid & execValid, + nextSp < exec.nextSp, + nextPc < exec.nextPc, + nextMode < exec.nextMode, + trap < exec.trap, + trapCause < exec.trapCause, + trapTval < exec.trapTval, + trapEpc < exec.trapEpc, + isReturn < exec.isReturn, + returnLevel < exec.returnLevel, + fence < exec.fence, + interruptHold < exec.interruptHold, + If(enable, then: [counter < (counter + 1)]), + ], + ), + ]); + + // Combinational passthrough (NOT registered) so it tracks the direct + // exec mem-port -> dport timing throughout the MMU walk. + output('memGuest') <= exec.memGuest; + } else { + // ======================================================================= + // OoO dual-issue pipeline + // ======================================================================= + + // Decoded field signals (combinational from decoder) + final decoderFields = decoder0.fields; + final decodedRd = (decoderFields['rd'] ?? Const(0, width: 5)) + .zeroExtend(5) + .named('decoded_rd'); + final decodedRs1 = (decoderFields['rs1'] ?? Const(0, width: 5)) + .zeroExtend(5) + .named('decoded_rs1'); + final decodedRs2 = (decoderFields['rs2'] ?? Const(0, width: 5)) + .zeroExtend(5) + .named('decoded_rs2'); + final decodedImm = fitWidth( + decoderFields['imm'] ?? Const(0, width: mxlen.size), + 64, + ).named('decoded_imm'); + final decodedOpIndex = fitWidth( + decoder0.index, + kOpIndex.width, + ).named('decoded_op_idx'); + + // Lane-1 decoded fields + control ROM (dual-dispatch). + final decoder1Fields = dualDispatch ? decoder1!.fields : null; + final decodedRd1 = dualDispatch + ? (decoder1Fields!['rd'] ?? Const(0, width: 5)).zeroExtend(5) + : null; + final decodedRs1_1 = dualDispatch + ? (decoder1Fields!['rs1'] ?? Const(0, width: 5)).zeroExtend(5) + : null; + final decodedRs2_1 = dualDispatch + ? (decoder1Fields!['rs2'] ?? Const(0, width: 5)).zeroExtend(5) + : null; + final decodedImm1 = dualDispatch + ? fitWidth(decoder1Fields!['imm'] ?? Const(0, width: mxlen.size), 64) + : null; + final ctrlRom1 = dualDispatch + ? DecodeControlRom(decoder1!.index, operations: microcode.execLookup) + : null; + + // Build Harbor pipeline for the decode→rename boundary (registered) + final frontEnd = PipelineBuilder(parent: this) + .stage( + RiverStage.decode, + payloads: [ + kPC, + kInstruction, + kRd, + kRs1, + kRs2, + kImm, + kOpIndex, + kFormatType, + kWritesRd, + kIsLoad, + kIsStore, + kIsBranch, + kIsCsr, + kIsReturn, + kReturnLevel, + kMemSize, + kFuType, + kAluFunct, + kBranchCond, + kIsJump, + kIsJalr, + kUseImm, + kSignExtend, + if (dualDispatch) ...[ + kSlot1Valid, + kPC1, + kInstruction1, + kRd1, + kRs1_1, + kRs2_1, + kImm1, + kWritesRd1, + kIsLoad1, + kIsStore1, + kIsBranch1, + kIsCsr1, + kIsReturn1, + kReturnLevel1, + kMemSize1, + kFuType1, + kAluFunct1, + kBranchCond1, + kIsJump1, + kIsJalr1, + kUseImm1, + kSignExtend1, + ], + ], ) - : decoder0.instrTypeMap; - - final decodeFields = decoder1 != null - ? decoder0.fields.map( - (name, value) => MapEntry( - name, - mux( - decoder0.done & decoder0.valid, - value, - decoder1!.fields[name]!, - ).named(name), - ), + .register(clk: clk, reset: reset) + .stage( + RiverStage.rename, + payloads: [ + kPdst, + kPsrc1, + kPsrc2, + kPdstOld, + kRobTag, + if (dualDispatch) ...[ + kPdst1, + kPsrc1_1, + kPsrc2_1, + kPdstOld1, + kRobTag1, + ], + ], ) - : decoder0.fields; - - final decodeDone = decoder1 != null - ? (decoder0.done | decoder1!.done) - : decoder0.done; - final decodeValid = decoder1 != null - ? (decoder0.valid | decoder1!.valid) - : decoder0.valid; - - final readyExecution = - (fetcher.valid & fetcher.done & decodeValid & decodeDone).named( - 'readyExecution', - ); + .build(); - final memExecRead0 = (useMixedExecution && microcodeExecRead != null) - ? DataPortInterface(mxlen.size, mxlen.size) - : memExecRead; + // Decode-control ROM: op index → flat control bundle for the issue queue + // and functional units. Combinational from the (decode-stage) op index, so + // the control signals register through to rename alongside the rest of the + // decode payloads. + final ctrlRom = DecodeControlRom( + decoder0.index, + operations: microcode.execLookup, + ); - final memExecRead1 = (useMixedExecution && microcodeExecRead != null) - ? DataPortInterface(mxlen.size, mxlen.size) - : null; + // Drive decode stage (pipeline entry point) from fetch + decoder + final decodeNode = frontEnd[RiverStage.decode]; + // PC of the instruction being decoded comes from the decoder's PC + // passthrough (pcOut), which is registered alongside the decoded fields, + // so the PC and the control signals (fuType/branchCond/rd) always describe + // the same instruction. (Using a live/latched PC here races it ahead of + // the 1-cycle-registered decoder output and mis-routes branches.) + decodeNode[kPC] <= fitWidth(decoder0.pcOut, 64); + decodeNode[kInstruction] <= fetchOutResult; + decodeNode[kRd] <= decodedRd; + decodeNode[kRs1] <= decodedRs1; + decodeNode[kRs2] <= decodedRs2; + decodeNode[kImm] <= decodedImm; + decodeNode[kOpIndex] <= decodedOpIndex; + decodeNode[kFormatType] <= Const(0, width: 4); + decodeNode[kWritesRd] <= ctrlRom.writesRd; + decodeNode[kIsLoad] <= ctrlRom.isLoad; + decodeNode[kIsStore] <= ctrlRom.isStore; + decodeNode[kIsBranch] <= + ctrlRom.fuType.eq(Const(FuType.branch.index, width: 2)); + decodeNode[kIsCsr] <= ctrlRom.isCsr; + decodeNode[kIsReturn] <= ctrlRom.isReturn; + decodeNode[kReturnLevel] <= ctrlRom.returnLevel; + decodeNode[kMemSize] <= ctrlRom.memSize; + decodeNode[kFuType] <= ctrlRom.fuType; + decodeNode[kAluFunct] <= ctrlRom.aluFunct; + decodeNode[kBranchCond] <= ctrlRom.branchCond; + decodeNode[kIsJump] <= ctrlRom.isJump; + decodeNode[kIsJalr] <= ctrlRom.isJalr; + decodeNode[kUseImm] <= ctrlRom.useImm; + decodeNode[kSignExtend] <= ~ctrlRom.memUnsigned; + decodeNode.valid <= decodeDone & decodeValid; - final memWrite0 = (useMixedExecution && microcodeExecRead != null) - ? DataPortInterface(7 + mxlen.size, mxlen.size) - : memWrite; - final memWrite1 = (useMixedExecution && microcodeExecRead != null) - ? DataPortInterface(7 + mxlen.size, mxlen.size) - : null; + // Lane-1 decode payloads (dual-dispatch). + if (dualDispatch) { + decodeNode[kSlot1Valid] <= fetchDone1!; + decodeNode[kPC1] <= fitWidth(decoder1!.pcOut, 64); + decodeNode[kInstruction1] <= cfb!.instr1; + decodeNode[kRd1] <= decodedRd1!; + decodeNode[kRs1_1] <= decodedRs1_1!; + decodeNode[kRs2_1] <= decodedRs2_1!; + decodeNode[kImm1] <= decodedImm1!; + decodeNode[kWritesRd1] <= ctrlRom1!.writesRd; + decodeNode[kIsLoad1] <= ctrlRom1.isLoad; + decodeNode[kIsStore1] <= ctrlRom1.isStore; + decodeNode[kIsBranch1] <= + ctrlRom1.fuType.eq(Const(FuType.branch.index, width: 2)); + decodeNode[kIsCsr1] <= ctrlRom1.isCsr; + decodeNode[kIsReturn1] <= ctrlRom1.isReturn; + decodeNode[kReturnLevel1] <= ctrlRom1.returnLevel; + decodeNode[kMemSize1] <= ctrlRom1.memSize; + decodeNode[kFuType1] <= ctrlRom1.fuType; + decodeNode[kAluFunct1] <= ctrlRom1.aluFunct; + decodeNode[kBranchCond1] <= ctrlRom1.branchCond; + decodeNode[kIsJump1] <= ctrlRom1.isJump; + decodeNode[kIsJalr1] <= ctrlRom1.isJalr; + decodeNode[kUseImm1] <= ctrlRom1.useImm; + decodeNode[kSignExtend1] <= ~ctrlRom1.memUnsigned; + } - final csrRead0 = - (useMixedExecution && microcodeExecRead != null && csrRead != null) - ? DataPortInterface(mxlen.size, 12) - : csrRead; - final csrWrite0 = - (useMixedExecution && microcodeExecRead != null && csrWrite != null) - ? DataPortInterface(mxlen.size, 12) - : csrWrite; - - final csrRead1 = - (useMixedExecution && microcodeExecRead != null && csrRead != null) - ? DataPortInterface(mxlen.size, 12) - : null; - final csrWrite1 = - (useMixedExecution && microcodeExecRead != null && csrWrite != null) - ? DataPortInterface(mxlen.size, 12) - : null; + // ----------------------------------------------------------------------- + // Register rename + // ----------------------------------------------------------------------- - final rs1Read0 = (useMixedExecution && microcodeExecRead != null) - ? DataPortInterface(mxlen.size, 5) - : rs1Read; - final rs1Read1 = (useMixedExecution && microcodeExecRead != null) - ? DataPortInterface(mxlen.size, 5) - : null; + final renameNode = frontEnd[RiverStage.rename]; - final rs2Read0 = (useMixedExecution && microcodeExecRead != null) - ? DataPortInterface(mxlen.size, 5) - : rs2Read; - final rs2Read1 = (useMixedExecution && microcodeExecRead != null) - ? DataPortInterface(mxlen.size, 5) - : null; + // Drive the front-end's tail handshake. The register link wires + // valid forward and ready backward, but the last stage's `ready` is the + // consumer's responsibility and `cancel` is never driven by a register + // link, leaving both X, which makes `renameNode.isFiring` (valid & ready + // & ~cancel) X and poisons rename/issue/ROB. + // + // Lockstep: accept every cycle (the fetcher holds one instruction and the + // commit-driven PC paces allocation). Speculative: apply real + // back-pressure, only accept when the ROB, IQ, and free list can take the + // instruction (driven below, once those modules exist). + final renameReady = speculative ? Logic(name: 'renameReady') : Const(1); + renameNode.ready <= renameReady; - final rdWrite0 = (useMixedExecution && microcodeExecRead != null) - ? DataPortInterface(mxlen.size, 5) - : rdWrite; - final rdWrite1 = (useMixedExecution && microcodeExecRead != null) - ? DataPortInterface(mxlen.size, 5) - : null; + // Speculative redirect/flush wires (driven below, once the ROB exists). + // specFlush pulses when a committing branch/jump redirects control flow: + // it squashes the ROB/IQ, rolls back rename, and redirects the fetcher. + // After a redirect, wrong-path instructions still in the decode→rename + // register must not allocate. Rather than time the squash, suppress + // allocation by PC: while `awaitingTarget`, cancel any instruction whose + // PC is not the redirect target. The first instruction with PC==target is + // the correct-path instruction; it (and everything after) allocates. The + // PC is reliable here because it flows aligned through the decoder. + final specFlush = speculative ? Logic(name: 'specFlush') : null; + final awaitingTarget = speculative ? Logic(name: 'awaitingTarget') : null; + final targetPcReg = speculative + ? Logic(name: 'targetPcReg', width: mxlen.size) + : null; + // Flush condition for the rename table, ROB, IQ, and functional units: + // reset, plus a speculative redirect. + final flushOrRedirect = speculative ? (reset | specFlush!) : reset; + final renamePcNow = speculative + ? fitWidth(renameNode[kPC], mxlen.size) + : null; + renameNode.cancel <= + (speculative + ? (awaitingTarget! & renamePcNow!.neq(targetPcReg!)) + : Const(0)); + decodeNode.cancel <= Const(0); - final exec0 = microcodeExecRead != null - ? DynamicExecutionUnit( - clk, + // One-shot allocation. The PC only advances at commit, so the fetcher + // re-presents the same instruction for many cycles and `isFiring` would + // otherwise allocate a fresh ROB/IQ entry every cycle (one instruction → + // dozens of duplicate entries). Allocate only when the renamed PC differs + // from the last one allocated. Because each instruction therefore commits + // (updating the arch regfile) before the next is fetched, reading source + // operands from the arch regfile at rename is also correct here. + final lastAllocPc = Logic(name: 'lastAllocPc', width: mxlen.size); + final lastAllocValid = Logic(name: 'lastAllocValid'); + final renamePc = fitWidth(renameNode[kPC], mxlen.size); + final newInstr = (~lastAllocValid | renamePc.neq(lastAllocPc)).named( + 'newInstr', + ); + final doAlloc = (renameNode.isFiring & newInstr).named('doAlloc'); + Sequential(clk, [ + If( + reset, + then: [lastAllocValid < 0, lastAllocPc < 0], + orElse: [ + If(doAlloc, then: [lastAllocValid < 1, lastAllocPc < renamePc]), + ], + ), + ]); + + // ---- Lane-1 allocation + fetch coordination (dual-dispatch) ---- + // Slot-1 rename source/dest locals (Const(0) when single-dispatch so the + // rename/ROB/IQ slot-1 ports can be wired unconditionally below). + final r1Rs1 = dualDispatch ? renameNode[kRs1_1] : Const(0, width: 5); + final r1Rs2 = dualDispatch ? renameNode[kRs2_1] : Const(0, width: 5); + final r1Rd = dualDispatch ? renameNode[kRd1] : Const(0, width: 5); + final r1WritesRd = dualDispatch ? renameNode[kWritesRd1] : Const(0); + Logic doAlloc1 = Const(0); + if (dualDispatch) { + final renamePc1 = fitWidth(renameNode[kPC1], mxlen.size); + // Co-dispatch eligibility. Slot 1 must hold a decoded instruction at + // exactly slot0.pc+4 (self-correcting alignment guard); neither slot may + // be a control transfer (a taken slot-0 branch makes slot 1 wrong-path), + // a CSR (serialised), or a memory op (single mem port + ordering). + // Intra-bundle RAW (slot 1 reads a register slot 0 writes) is also NOT + // co-dispatched: slot 0's busy bit/PRF value are not yet visible the + // cycle they co-allocate. Deferring slot 1 to the next cycle turns it + // into a cross-bundle RAW, which the PRF busy scoreboard + wakeup + // forwarding handle correctly. + final intraRaw = + (doAlloc & + renameNode[kWritesRd] & + renameNode[kRd].neq(Const(0, width: 5)) & + (renameNode[kRd].eq(r1Rs1) | renameNode[kRd].eq(r1Rs2))) + .named('intraBundleRaw'); + final slot0Ctrl = + renameNode[kIsBranch] | renameNode[kIsJump] | renameNode[kIsJalr]; + final slot1Ctrl = + renameNode[kIsBranch1] | + renameNode[kIsJump1] | + renameNode[kIsJalr1]; + final slot0Mem = renameNode[kIsLoad] | renameNode[kIsStore]; + final slot1Mem = renameNode[kIsLoad1] | renameNode[kIsStore1]; + // The fetch buffer emits the pair from one aligned window, so instr1 + // always starts at instr0.pc + size0*2, lane-1's PC is correct by + // construction (compressed or fixed-width). No fixed +4 guard needed. + final pcAligned = Const(1); + final slot1Squash = awaitingTarget != null + ? (awaitingTarget & renamePc1.neq(targetPcReg!)) + : Const(0); + // With a load-store queue, memory ops MAY co-dispatch: they still leave + // the issue queue one at a time (single mem port) and execute in program + // order (slot 0 has the older sequence number), so the queue sees them + // in order and intra-bundle store→load aliasing is handled by forwarding. + // EXCEPTION: a load+load bundle currently deadlocks (two loads in flight + // through the single mem port + dual-commit); it falls back to single + // dispatch (still correct). Without an LSQ, any memory op blocks. + final bothLoad = renameNode[kIsLoad] & renameNode[kIsLoad1]; + final memBlock = (loadStoreQueue != LoadStoreQueue.none) + ? bothLoad + : (slot0Mem | slot1Mem); + final slot1Eligible = + (renameNode[kSlot1Valid] & + pcAligned & + ~slot0Ctrl & + ~slot1Ctrl & + ~renameNode[kIsCsr] & + ~renameNode[kIsCsr1] & + ~memBlock & + ~intraRaw & + ~slot1Squash) + .named('slot1Eligible'); + // Slot 1 co-dispatches ONLY together with slot 0 (doAlloc). It is the + // instruction at slot0.pc+4, so when slot 0 allocates a new bundle and + // slot 1 is eligible, slot 1 is also new, no separate one-shot is + // needed, and gating on doAlloc prevents slot 1 from allocating while + // slot 0 is a stale re-presentation (which would double-allocate slot + // 1's instruction when it later becomes slot 0). + doAlloc1 = (doAlloc & slot1Eligible).named('doAlloc1'); + // Drive the buffer's consume ports: consume slot 0 when it allocates, + // and slot 1 additionally when it co-allocates. The buffer advances its + // head by size0 (+ size1 when slot 1 co-allocates) and presents the next + // pair. A branch/predict redirect (fetchRedirect/fetchRedirectPc, driven + // below) flushes the buffer and resteers to the target, including + // mid-word (compressed-aligned) targets. + bufConsume0! <= doAlloc; + bufConsume1! <= doAlloc1; + } + + // Placeholders for commit-time connections (wired after ROB is created) + final freeValid0Wire = Logic(name: 'freeValid0Wire'); + final freeReg0Wire = Logic(name: 'freeReg0Wire', width: 7); + final freeValid1Wire = Logic(name: 'freeValid1Wire'); + final freeReg1Wire = Logic(name: 'freeReg1Wire', width: 7); + final commitValid0Wire = Logic(name: 'commitValid0Wire'); + final commitRd0Wire = Logic(name: 'commitRd0Wire', width: 5); + final commitPdst0Wire = Logic(name: 'commitPdst0Wire', width: 7); + final commitValid1Wire = Logic(name: 'commitValid1Wire'); + final commitRd1Wire = Logic(name: 'commitRd1Wire', width: 5); + final commitPdst1Wire = Logic(name: 'commitPdst1Wire', width: 7); + + final renameTable = RegisterRenameTable( + clk, + reset, + rs1Arch0: renameNode[kRs1], + rs2Arch0: renameNode[kRs2], + rdArch0: renameNode[kRd], + valid0: doAlloc, + writesRd0: renameNode[kWritesRd], + rs1Arch1: r1Rs1, + rs2Arch1: r1Rs2, + rdArch1: r1Rd, + valid1: doAlloc1, + writesRd1: r1WritesRd, + freeValid0: freeValid0Wire, + freeReg0: freeReg0Wire, + freeValid1: freeValid1Wire, + freeReg1: freeReg1Wire, + commitValid0: commitValid0Wire, + commitRd0: commitRd0Wire, + commitPdst0: commitPdst0Wire, + commitValid1: commitValid1Wire, + commitRd1: commitRd1Wire, + commitPdst1: commitPdst1Wire, + flush: flushOrRedirect, + numPhysRegs: 96, + ); + + // Drive rename stage payload outputs + renameNode[kPdst] <= renameTable.pdst0; + renameNode[kPsrc1] <= renameTable.psrc1_0; + renameNode[kPsrc2] <= renameTable.psrc2_0; + renameNode[kPdstOld] <= renameTable.pdstOld0; + if (dualDispatch) { + renameNode[kPdst1] <= renameTable.pdst1; + renameNode[kPsrc1_1] <= renameTable.psrc1_1; + renameNode[kPsrc2_1] <= renameTable.psrc2_1; + renameNode[kPdstOld1] <= renameTable.pdstOld1; + } + + // ----------------------------------------------------------------------- + // Reorder buffer, create interconnect wires first, then instantiate + // ----------------------------------------------------------------------- + + final lsqEnabled = loadStoreQueue != LoadStoreQueue.none; + final forwarding = + loadStoreQueue == LoadStoreQueue.forwarding || + loadStoreQueue == LoadStoreQueue.speculative; + final speculativeLsq = loadStoreQueue == LoadStoreQueue.speculative; + final robTagBits = robDepth.bitLength - 1; // log2(robDepth) + final numPhysRegs = + 96; // physical registers (must match RegisterRenameTable) + + // Store-queue status, forward-declared: the issue queue (in-order mem + // dispatch + store back-pressure) and the memory unit (load wait/forward) + // consume these, but the StoreQueue is built after them. Wired below. + final sqFullWire = Logic(name: 'sqFull'); + final sqEmptyWire = Logic(name: 'sqEmpty'); + final sqFwdHitWire = Logic(name: 'sqFwdHit'); + final sqFwdDataWire = Logic(name: 'sqFwdData', width: mxlen.size); + final sqFwdStallWire = Logic(name: 'sqFwdStall'); + // Speculative LSQ: a store→load ordering violation from the load queue, + // forward-declared (the LoadQueue is built after the memory unit). + final lqCamViolationWire = Logic(name: 'lqCamViolation'); + + // ROB allocate wires + final robAllocValid0 = Logic(name: 'robAllocValid0'); + final robAllocPc0 = Logic(name: 'robAllocPc0', width: mxlen.size); + final robAllocPdst0 = Logic(name: 'robAllocPdst0', width: 7); + final robAllocPdstOld0 = Logic(name: 'robAllocPdstOld0', width: 7); + final robAllocRd0 = Logic(name: 'robAllocRd0', width: 5); + final robAllocWritesRd0 = Logic(name: 'robAllocWritesRd0'); + final robAllocValid1 = Logic(name: 'robAllocValid1'); + final robAllocPc1 = Logic(name: 'robAllocPc1', width: mxlen.size); + final robAllocPdst1 = Logic(name: 'robAllocPdst1', width: 7); + final robAllocPdstOld1 = Logic(name: 'robAllocPdstOld1', width: 7); + final robAllocRd1 = Logic(name: 'robAllocRd1', width: 5); + final robAllocWritesRd1 = Logic(name: 'robAllocWritesRd1'); + + // ROB complete wires + final robCompleteValid0 = Logic(name: 'robCompleteValid0'); + final robCompleteTag0 = Logic(name: 'robCompleteTag0', width: robTagBits); + final robCompleteResult0 = Logic( + name: 'robCompleteResult0', + width: mxlen.size, + ); + final robCompleteException0 = Logic(name: 'robCompleteException0'); + final robCompleteCause0 = Logic(name: 'robCompleteCause0', width: 6); + // Port-0 (memory) redirect: a store→load violation re-fetches after it. + final robCompleteRedirects0 = Logic(name: 'robCompleteRedirects0'); + final robCompleteTarget0 = Logic( + name: 'robCompleteTarget0', + width: mxlen.size, + ); + final robCompleteValid1 = Logic(name: 'robCompleteValid1'); + final robCompleteTag1 = Logic(name: 'robCompleteTag1', width: robTagBits); + final robCompleteResult1 = Logic( + name: 'robCompleteResult1', + width: mxlen.size, + ); + final robCompleteException1 = Logic(name: 'robCompleteException1'); + final robCompleteCause1 = Logic(name: 'robCompleteCause1', width: 6); + + // Complete port 2: the branch unit (driven after it is built). Carries + // the redirect bit + target PC so the redirect applies at commit. + final robCompleteValid2 = Logic(name: 'robCompleteValid2'); + final robCompleteTag2 = Logic(name: 'robCompleteTag2', width: robTagBits); + final robCompleteResult2 = Logic( + name: 'robCompleteResult2', + width: mxlen.size, + ); + final robCompleteException2 = Logic(name: 'robCompleteException2'); + final robCompleteCause2 = Logic(name: 'robCompleteCause2', width: 6); + final robCompleteRedirects2 = Logic(name: 'robCompleteRedirects2'); + final robCompleteTarget2 = Logic( + name: 'robCompleteTarget2', + width: mxlen.size, + ); + + // ROB commit ack wires + final robCommitAck0 = Logic(name: 'robCommitAck0'); + final robCommitAck1 = Logic(name: 'robCommitAck1'); + final robFlush = Logic(name: 'robFlush'); + + // Drive allocate wires + robAllocValid0 <= doAlloc; + robAllocPc0 <= fitWidth(renameNode[kPC], mxlen.size); + robAllocPdst0 <= renameTable.pdst0; + robAllocPdstOld0 <= renameTable.pdstOld0; + robAllocRd0 <= renameNode[kRd]; + robAllocWritesRd0 <= renameNode[kWritesRd]; + robAllocValid1 <= doAlloc1; + robAllocPc1 <= + (dualDispatch + ? fitWidth(renameNode[kPC1], mxlen.size) + : Const(0, width: mxlen.size)); + robAllocPdst1 <= renameTable.pdst1.zeroExtend(7); + robAllocPdstOld1 <= renameTable.pdstOld1.zeroExtend(7); + robAllocRd1 <= r1Rd; + robAllocWritesRd1 <= r1WritesRd; + robFlush <= flushOrRedirect; + + final rob = ReorderBuffer( + clk, + reset, + allocValid0: robAllocValid0, + allocPc0: robAllocPc0, + allocPdst0: robAllocPdst0, + allocPdstOld0: robAllocPdstOld0, + allocRd0: robAllocRd0, + allocWritesRd0: robAllocWritesRd0, + allocValid1: robAllocValid1, + allocPc1: robAllocPc1, + allocPdst1: robAllocPdst1, + allocPdstOld1: robAllocPdstOld1, + allocRd1: robAllocRd1, + allocWritesRd1: robAllocWritesRd1, + allocIsStore0: lsqEnabled ? renameNode[kIsStore] : Const(0), + allocIsStore1: (lsqEnabled && dualDispatch) + ? renameNode[kIsStore1] + : Const(0), + allocIsReturn0: renameNode[kIsReturn], + allocReturnLevel0: renameNode[kReturnLevel], + allocIsReturn1: dualDispatch ? renameNode[kIsReturn1] : Const(0), + allocReturnLevel1: dualDispatch + ? renameNode[kReturnLevel1] + : Const(0, width: 2), + completeValid0: robCompleteValid0, + completeTag0: robCompleteTag0, + completeResult0: robCompleteResult0, + completeRedirects0: speculativeLsq ? robCompleteRedirects0 : null, + completeTarget0: speculativeLsq ? robCompleteTarget0 : null, + completeException0: robCompleteException0, + completeCause0: robCompleteCause0, + completeValid1: robCompleteValid1, + completeTag1: robCompleteTag1, + completeResult1: robCompleteResult1, + completeException1: robCompleteException1, + completeCause1: robCompleteCause1, + completeValid2: robCompleteValid2, + completeTag2: robCompleteTag2, + completeResult2: robCompleteResult2, + completeException2: robCompleteException2, + completeCause2: robCompleteCause2, + completeRedirects2: robCompleteRedirects2, + completeTarget2: robCompleteTarget2, + commitAck0: robCommitAck0, + commitAck1: robCommitAck1, + flush: robFlush, + depth: robDepth, + xlen: mxlen.size, + physRegBits: 7, + ); + + renameNode[kRobTag] <= rob.allocTag0.zeroExtend(7); + if (dualDispatch) { + renameNode[kRobTag1] <= rob.allocTag1.zeroExtend(7); + } + + // ----------------------------------------------------------------------- + // Issue queue, wires created externally and passed + // ----------------------------------------------------------------------- + + // IQ wakeup wires (driven after FUs are created) + final iqWakeupValid0 = Logic(name: 'iqWakeupValid0'); + final iqWakeupTag0 = Logic(name: 'iqWakeupTag0', width: 7); + final iqWakeupValue0 = Logic(name: 'iqWakeupValue0', width: mxlen.size); + final iqWakeupValid1 = Logic(name: 'iqWakeupValid1'); + final iqWakeupTag1 = Logic(name: 'iqWakeupTag1', width: 7); + final iqWakeupValue1 = Logic(name: 'iqWakeupValue1', width: mxlen.size); + // Dedicated 3rd wakeup port for the branch/CSR completion, so ALU1 (port 1) + // and branch/CSR no longer collide in dual-dispatch (dropped wakeup → + // dependent never fires → deadlock on long loop bodies). + final iqWakeupValid2 = Logic(name: 'iqWakeupValid2'); + final iqWakeupTag2 = Logic(name: 'iqWakeupTag2', width: 7); + final iqWakeupValue2 = Logic(name: 'iqWakeupValue2', width: mxlen.size); + + // Driven after the MemoryUnit is built; tells the IQ not to dispatch a + // second memory op while one is in flight. + final memBusyWire = Logic(name: 'memBusyWire'); + // Likewise for the ALUs: a multi-cycle mul/div holds the unit busy, so the + // IQ must not dispatch another op to it until the result lands. + final aluBusy0Wire = Logic(name: 'aluBusy0Wire'); + final aluBusy1Wire = Logic(name: 'aluBusy1Wire'); + + // -------------------------------------------------------------------- + // Physical register file + busy scoreboard (operand availability) + // -------------------------------------------------------------------- + // Operand VALUES come from this PRF (written at FU writeback, indexed by + // physical register), NOT the architectural regfile. That makes in-flight + // RAW correct: a consumer whose producer has not yet committed reads the + // forwarded/written-back value instead of the stale committed one. An + // operand is ready iff its source physreg is not busy. busy[p] is set when + // p is allocated as a destination and cleared when its result writes back. + // + // The FU result carries the ROB tag (the ROB is indexed by it); the + // forwarding/PRF index is the physical register. tagToPdst/tagWritesRd + // translate a completing ROB tag back to its physreg + whether it writes a + // register, both recorded at allocation. + final prf = List.generate( + numPhysRegs, + (i) => Logic(name: 'prf_$i', width: mxlen.size), + ); + final prfBusy = List.generate( + numPhysRegs, + (i) => Logic(name: 'prfBusy_$i'), + ); + final tagToPdst = List.generate( + robDepth, + (i) => Logic(name: 'tagToPdst_$i', width: 7), + ); + final tagWritesRd = List.generate( + robDepth, + (i) => Logic(name: 'tagWritesRd_$i'), + ); + + Logic muxArr(List arr, Logic idx) { + var r = arr[0]; + for (var i = 1; i < arr.length; i++) { + r = mux(idx.eq(i), arr[i], r); + } + return r; + } + + // A source is ready if its physreg is not busy, OR a writeback this cycle + // targets it (enqueue↔wakeup bypass: PRF/busy update one cycle late, so an + // instruction enqueueing the same cycle its producer writes back must take + // the value off the wakeup bus directly or it would wait forever). + // x0 reads as 0 and is always ready. River renames x0 like any register, + // so an instruction that writes x0 (e.g. the canonical nop addi x0,x0,0) + // would otherwise mark x0's physreg busy and make later x0 readers wait on + // it (a false dependency chain). Special-case the arch source x0 here so it + // never waits and always supplies 0. SAFE because this is the out-of-order + // path, which is INTEGER-ONLY (no FP functional unit; FP runs only on the + // in-order/microcode exec path), so `arch` is always an integer reg number + // and can never be an FP reg f0. If OoO FP is ever added, gate this on a + // per-source integer-reg flag. See project_hdl_frontend_perf, task #58. + final zeroReg = Const(0, width: 5); + Logic srcReady(Logic arch, Logic psrc) => + arch.eq(zeroReg) | + ~muxArr(prfBusy, psrc) | + (iqWakeupValid0 & iqWakeupTag0.eq(psrc)) | + (iqWakeupValid1 & iqWakeupTag1.eq(psrc)); + Logic srcValue(Logic arch, Logic psrc) => mux( + arch.eq(zeroReg), + Const(0, width: mxlen.size), + mux( + iqWakeupValid0 & iqWakeupTag0.eq(psrc), + iqWakeupValue0, + mux( + iqWakeupValid1 & iqWakeupTag1.eq(psrc), + iqWakeupValue1, + muxArr(prf, psrc), + ), + ), + ); + + final iq = IssueQueue( + clk, + reset, + enqValid0: doAlloc, + enqTag0: rob.allocTag0, + enqPsrc10: renameTable.psrc1_0, + enqPsrc20: renameTable.psrc2_0, + enqPdst0: renameTable.pdst0, + // For CSR ops the general imm field is unused (the csr ADDRESS is + // plumbed separately as csrAddr), so carry the 5-bit zimm (instr[19:15]) + // here for csrrwi/csrrsi/csrrci - the CsrUnit reads it as the immediate + // source. Without this it got the csr addr (the I-type imm) instead. + enqImm0: mux( + renameNode[kFuType].eq(Const(FuType.csr.index, width: 2)), + fitWidth( + renameNode[kInstruction], + 32, + ).slice(19, 15).zeroExtend(mxlen.size), + fitWidth(renameNode[kImm], mxlen.size), + ), + enqPc0: fitWidth(renameNode[kPC], mxlen.size), + enqFunct0: renameNode[kAluFunct], + enqFuType0: renameNode[kFuType], + enqWritesRd0: renameNode[kWritesRd], + enqIsStore0: renameNode[kIsStore], + enqMemSize0: renameNode[kMemSize], + enqBranchCond0: renameNode[kBranchCond], + enqIsJump0: renameNode[kIsJump], + enqIsJalr0: renameNode[kIsJalr], + enqUseImm0: renameNode[kUseImm], + // CSR op = funct3 (instr[14:12]); CSR address = instr[31:20]. The + // CsrUnit maps funct3 → read/set/clear (+ immediate variants). + enqCsrOp0: fitWidth(renameNode[kInstruction], 32).slice(14, 12), + enqCsrAddr0: fitWidth(renameNode[kInstruction], 32).slice(31, 20), + enqSignExtend0: renameNode[kSignExtend], + enqValid1: doAlloc1, + enqTag1: rob.allocTag1, + enqPsrc11: renameTable.psrc1_1, + enqPsrc21: renameTable.psrc2_1, + enqPdst1: renameTable.pdst1, + // Same CSR-zimm carry as slot 0 (a CSR is serialised so it never reaches + // slot 1, but keep the lanes consistent). + enqImm1: dualDispatch + ? mux( + renameNode[kFuType1].eq(Const(FuType.csr.index, width: 2)), + fitWidth( + renameNode[kInstruction1], + 32, + ).slice(19, 15).zeroExtend(mxlen.size), + fitWidth(renameNode[kImm1], mxlen.size), + ) + : Const(0, width: mxlen.size), + enqPc1: dualDispatch + ? fitWidth(renameNode[kPC1], mxlen.size) + : Const(0, width: mxlen.size), + enqFunct1: dualDispatch ? renameNode[kAluFunct1] : Const(0, width: 7), + enqFuType1: dualDispatch ? renameNode[kFuType1] : Const(0, width: 2), + enqWritesRd1: r1WritesRd, + enqIsStore1: dualDispatch ? renameNode[kIsStore1] : Const(0), + enqMemSize1: dualDispatch ? renameNode[kMemSize1] : Const(0, width: 3), + enqBranchCond1: dualDispatch + ? renameNode[kBranchCond1] + : Const(0, width: 3), + enqIsJump1: dualDispatch ? renameNode[kIsJump1] : Const(0), + enqIsJalr1: dualDispatch ? renameNode[kIsJalr1] : Const(0), + enqUseImm1: dualDispatch ? renameNode[kUseImm1] : Const(0), + enqCsrOp1: dualDispatch + ? fitWidth(renameNode[kInstruction1], 32).slice(14, 12) + : Const(0, width: 3), + enqCsrAddr1: dualDispatch + ? fitWidth(renameNode[kInstruction1], 32).slice(31, 20) + : Const(0, width: 12), + enqSignExtend1: dualDispatch ? renameNode[kSignExtend1] : Const(0), + enqSrc1Value0: srcValue(renameNode[kRs1], renameTable.psrc1_0), + enqSrc2Value0: srcValue(renameNode[kRs2], renameTable.psrc2_0), + enqSrc1Ready0: srcReady(renameNode[kRs1], renameTable.psrc1_0), + enqSrc2Ready0: srcReady(renameNode[kRs2], renameTable.psrc2_0), + enqSrc1Value1: srcValue(r1Rs1, renameTable.psrc1_1), + enqSrc2Value1: srcValue(r1Rs2, renameTable.psrc2_1), + enqSrc1Ready1: srcReady(r1Rs1, renameTable.psrc1_1), + enqSrc2Ready1: srcReady(r1Rs2, renameTable.psrc2_1), + wakeupValid0: iqWakeupValid0, + wakeupTag0: iqWakeupTag0, + wakeupValue0: iqWakeupValue0, + wakeupValid1: iqWakeupValid1, + wakeupTag1: iqWakeupTag1, + wakeupValue1: iqWakeupValue1, + wakeupValid2: iqWakeupValid2, + wakeupTag2: iqWakeupTag2, + wakeupValue2: iqWakeupValue2, + aluBusy0: aluBusy0Wire, + aluBusy1: aluBusy1Wire, + memBusy: memBusyWire, + branchBusy: Const(0), + csrBusy: Const(0), + flush: flushOrRedirect, + inOrderMem: lsqEnabled, + speculativeMem: speculativeLsq, + sqFull: lsqEnabled ? sqFullWire : null, + depth: 16, + xlen: mxlen.size, + physRegBits: 7, + robTagBits: robTagBits, + ); + + // Privileged trap/return delivery (#75). Computed once at the OoO-branch + // scope so BOTH the speculative fetch-redirect block (inside the + // `if (speculative)` below) and the commit output block (further down) can + // use it. A committing exception or mret/sret must flush the younger + // (wrong-path) entries and steer the fetcher, exactly like a branch + // redirect, and additionally trap/return delivery sets nextMode + isReturn + // so core.dart writes mcause/mepc/mstatus and restores pc/mode. + final commitException = (rob.commitValid0 & rob.commitException0).named( + 'commitException', + ); + final commitReturn = (rob.commitValid0 & rob.commitIsReturn0).named( + 'commitReturn', + ); + final machineMode = Const(PrivilegeMode.machine.id, width: 3); + // returnLevel: ROB stores the 2-bit privilege level (3=M/1=S); zeroExtend + // recovers the 3-bit value core.dart compares against M (==3). + final commitReturnLevel3 = rob.commitReturnLevel0 + .zeroExtend(3) + .named('commitReturnLevel3'); + final Logic trapTargetMode; + final Logic trapVecPc; + if (mtvec != null) { + final isIntr = Const(0); // commit exceptions are synchronous + trapTargetMode = selectTrapTargetModeTop( + isIntr, + rob.commitCause0, + currentMode, + mideleg, + medeleg, + hasCsr: csrRead != null && csrWrite != null, + hasSupervisor: hasSupervisor, + ).named('oooTrapMode'); + final tvec = stvec != null + ? mux(trapTargetMode.eq(machineMode), mtvec, stvec) + : mtvec; + trapVecPc = computeTrapVectorPcTop( + tvec, + rob.commitCause0, + isIntr, + mxlen, + suffix: 'Ooo', + ); + } else { + trapTargetMode = currentMode; + trapVecPc = currentPc; + } + // Return target for the fetcher: {m,s}epc by the return level. core.dart + // restores the architectural pc/mode in parallel; this only steers fetch. + final Logic retVecPc = mepc == null + ? currentPc + : (sepc != null + ? mux(commitReturnLevel3.eq(machineMode), mepc, sepc) + : mepc); + + // Speculative front-end control. Back-pressure: accept only when the ROB, + // IQ, and free list can all take the instruction. Advance the fetcher when + // an instruction is actually allocated (doAlloc), so it self-sequences to + // the next PC. On a committing branch/jump redirect: squash the back-end + // (flushOrRedirect via specFlush) and steer the fetcher to the target. + if (speculative) { + // CSR serialisation barrier: keep CSR side effects off the speculative + // path. A CSR may not allocate until the ROB has drained (so it is the + // oldest instruction → on the correct path), and once a CSR is in flight + // nothing younger may allocate until it commits (so nothing executes + // speculatively after it). CSRs are rare, so the full drain is fine. + final renameIsCsr = renameNode[kIsCsr]; + final csrInFlight = Logic(name: 'csrInFlight'); + final csrBarrierStall = (csrInFlight | (renameIsCsr & ~rob.empty)) + .named('csrBarrierStall'); + renameReady <= + (rob.allocReady & + iq.enqReady & + renameTable.ready & + ~csrBarrierStall) + .named('renameReadySpec'); + Sequential(clk, [ + If( reset, - readyExecution, - currentSp, - currentPc, - currentMode, - decodeIndex, - decodeInstrTypeMap, - decodeFields, - csrRead0, - csrWrite0, - memExecRead0, - memWrite0, - rs1Read0, - rs2Read0, - rdWrite0, - microcodeExecRead, - hasSupervisor: hasSupervisor, - hasUser: hasUser, - microcode: microcode, - mxlen: mxlen, - mideleg: mideleg, - medeleg: medeleg, - mtvec: mtvec, - stvec: stvec, - staticInstructions: staticInstructions, - counterWidth: counterWidth, - ) - : StaticExecutionUnit( - clk, + then: [csrInFlight < 0], + orElse: [ + If( + doAlloc & renameIsCsr, + then: [csrInFlight < 1], + orElse: [ + If(csrInFlight & rob.commitValid0, then: [csrInFlight < 0]), + ], + ), + ], + ), + ]); + // Alloc cadence: when the load-store queue is present (so memory is + // properly disambiguated), advance the fetcher whenever the back-end can + // accept a delivered instruction, not only when the current one + // allocates. This pipelines fetch->decode->rename (each stage holds a + // distinct instruction) instead of one round trip per instruction (the + // ~3 cyc/instr front-end floor). WITHOUT the LSQ the legacy store-at- + // execute memory path relies on the slower cadence for store->load + // visibility, so keep the doAlloc cadence there. (Correct given the fetch + // memory never emits X.) See project_hdl_frontend_perf. + fetchAdvance! <= (lsqEnabled ? (renameReady & fetchDone) : doAlloc); + // Retirement strobe (perf counter / IPC measurement). + addOutput('retire_valid') <= rob.commitValid0; + + // ---- Branch prediction (rename stage) ---- + // Predict a conditional branch's direction; when predicted taken (or for + // an unconditional JAL), redirect the FETCH stream to the target NOW, so + // a correctly-predicted branch costs no pipeline flush. The branch unit + // re-checks at execute (issuePredictedTaken) and the commit redirect only + // fires on a real misprediction. JALR is not predicted (target = rs1+imm, + // unknown at rename) → predicted not-taken → resolves at execute. + final renIsCond = renameNode[kIsBranch] & ~renameNode[kIsJump]; + final renIsJal = renameNode[kIsJump] & ~renameNode[kIsJalr]; + final renImm = fitWidth(renameNode[kImm], mxlen.size); + final immBackward = renImm[mxlen.size - 1]; // sign: negative = backward + final isPredicting = branchPredictor != BranchPredictor.none; + final Logic predDir; + switch (branchPredictor) { + case BranchPredictor.none: + predDir = Const(0); + break; + case BranchPredictor.btfn: + predDir = immBackward; // backward branches (loops) taken + break; + case BranchPredictor.bimodal: + throw UnimplementedError('bimodal predictor not yet wired'); + } + // BPD (rpipelinectl[1]) forces predicted-not-taken at runtime. + final predTaken = + ((isPredicting ? ((renIsCond & predDir) | renIsJal) : Const(0)) & + ~bpdDisable) + .named('predTaken'); + final predictTarget = (renamePcNow! + renImm).named('predictTarget'); + final predictRedirect = (doAlloc & predTaken).named('predictRedirect'); + + // A committing branch/jump misprediction, exception, or privileged + // return redirects with a full flush (squashing wrong-path younger + // entries); a new prediction just steers the fetcher (no flush). Commit + // redirect has priority. Redirect target: exception -> trap vector, + // return -> {m,s}epc, branch -> commit target. + final commitBranchRedir = (rob.commitValid0 & rob.commitRedirects0) + .named('commitBranchRedir'); + specFlush! <= + (commitBranchRedir | commitException | commitReturn).named('specF'); + final anyRedirect = (specFlush | predictRedirect).named('anyRedirect'); + final commitRedirPc = mux( + commitException, + trapVecPc, + mux(commitReturn, retVecPc, rob.commitTarget0), + ).named('commitRedirPc'); + final redirectPc = mux( + specFlush, + commitRedirPc, + predictTarget, + ).named('redirPc'); + fetchRedirect! <= anyRedirect; + fetchRedirectPc! <= redirectPc; + + // Wrong-path squash by PC: on any redirect, latch the target and suppress + // allocation (renameNode.cancel) until an instruction with PC==target + // reaches rename. (Already-allocated wrong-path entries on a commit flush + // are squashed by the flush itself.) + Sequential(clk, [ + If( reset, - readyExecution, - currentSp, - currentPc, - currentMode, - decodeIndex, - decodeInstrTypeMap, - decodeFields, - csrRead0, - csrWrite0, - memExecRead0, - memWrite0, - rs1Read0, - rs2Read0, - rdWrite0, - hasSupervisor: hasSupervisor, - hasUser: hasUser, - microcode: microcode, - mxlen: mxlen, - mideleg: mideleg, - medeleg: medeleg, - mtvec: mtvec, - stvec: stvec, - staticInstructions: staticInstructions, - counterWidth: counterWidth, + then: [awaitingTarget! < 0, targetPcReg! < 0], + orElse: [ + If( + anyRedirect, + then: [awaitingTarget < 1, targetPcReg < redirectPc], + orElse: [ + If( + awaitingTarget & + renameNode.isFiring & + renamePcNow.eq(targetPcReg), + then: [awaitingTarget < 0], + ), + ], + ), + ], + ), + ]); + } + + // ----------------------------------------------------------------------- + // Functional units + // ----------------------------------------------------------------------- + + final alu0 = AluUnit( + clk, + reset, + issueValid: iq.dispatchAluValid0, + issueTag: iq.dispatchAluTag0, + issueSrc1: iq.dispatchAluSrc10, + issueSrc2: iq.dispatchAluSrc20, + issueImm: iq.dispatchAluImm0, + issueFunct: iq.dispatchAluFunct0, + issueUseImm: iq.dispatchAluUseImm0, + issuePc: iq.dispatchAluPc0, + flush: flushOrRedirect, + xlen: mxlen.size, + robTagBits: robTagBits, + name: 'alu_0', + ); + final alu1 = AluUnit( + clk, + reset, + issueValid: iq.dispatchAluValid1, + issueTag: iq.dispatchAluTag1, + issueSrc1: iq.dispatchAluSrc11, + issueSrc2: iq.dispatchAluSrc21, + issueImm: iq.dispatchAluImm1, + issueFunct: iq.dispatchAluFunct1, + issueUseImm: iq.dispatchAluUseImm1, + issuePc: iq.dispatchAluPc1, + flush: flushOrRedirect, + xlen: mxlen.size, + robTagBits: robTagBits, + name: 'alu_1', + ); + + // Predicted-taken for the branch unit's misprediction check. Must match + // the rename-stage prediction for the same branch: BTFN predicts a + // conditional branch taken iff its displacement is negative (backward), + // and JAL always taken; JALR (and `none`) → not-taken. + final branchUnitPredTaken = (branchPredictor == BranchPredictor.none) + ? Const(0) + : ((iq.dispatchBranchIsJump & ~iq.dispatchBranchIsJalr) | + (~iq.dispatchBranchIsJump & + iq.dispatchBranchImm[mxlen.size - 1])) + .named('branchUnitPredTaken'); + + // Branch unit + final branchUnit = BranchUnit( + clk, + reset, + issueValid: iq.dispatchBranchValid, + issueTag: iq.dispatchBranchTag, + issueSrc1: iq.dispatchBranchSrc1, + issueSrc2: iq.dispatchBranchSrc2, + issueImm: iq.dispatchBranchImm, + issuePc: iq.dispatchBranchPc, + issueCondition: iq.dispatchBranchCondition, + issueIsJump: iq.dispatchBranchIsJump, + issueIsJalr: iq.dispatchBranchIsJalr, + issuePredictedTaken: branchUnitPredTaken, + flush: flushOrRedirect, + xlen: mxlen.size, + robTagBits: robTagBits, + ); + + // CSR unit (only if CSR ports available). Self-serialising FSM that reads + // then writes the CSR file and returns the OLD value as rd. CSRs are kept + // off the speculative path by the barrier in the rename backpressure + // (csrBarrierStall) below; in lockstep OoO the single-in-flight front-end + // serialises them naturally. + CsrUnit? csrUnit; + if (csrRead != null && csrWrite != null) { + csrUnit = CsrUnit( + clk, + reset, + csrRead, + csrWrite, + issueValid: iq.dispatchCsrValid, + issueTag: iq.dispatchCsrTag, + issueSrc1: iq.dispatchCsrSrc1, + issueImm: iq.dispatchCsrImm, + issueOp: iq.dispatchCsrOp, + issueCsrAddr: iq.dispatchCsrAddr, + flush: flushOrRedirect, + xlen: mxlen.size, + robTagBits: robTagBits, + ); + } + + // Complete the branch in the ROB (port 2), recording its redirect/target + // so control flow is corrected at commit. Without this a branch's ROB + // entry would never complete and the core would stall. The CSR unit shares + // this port: a branch and a CSR are mutually exclusive in flight (a CSR is + // serialised to run alone), so muxing on csr.resultValid is race-free. A + // CSR never redirects, so its redirect/target are 0. + final csrComplete = csrUnit?.resultValid ?? Const(0); + robCompleteValid2 <= branchUnit.resultValid | csrComplete; + robCompleteTag2 <= + mux( + csrComplete, + csrUnit?.resultTag ?? Const(0, width: robTagBits), + branchUnit.resultTag, ); + robCompleteResult2 <= + mux( + csrComplete, + csrUnit?.resultData ?? Const(0, width: mxlen.size), + branchUnit.resultData, + ); + robCompleteException2 <= + mux( + csrComplete, + csrUnit?.resultException ?? Const(0), + branchUnit.resultException, + ); + robCompleteCause2 <= + mux( + csrComplete, + csrUnit?.resultCause ?? Const(0, width: 6), + branchUnit.resultCause, + ); + robCompleteRedirects2 <= mux(csrComplete, Const(0), branchUnit.redirect); + robCompleteTarget2 <= + mux(csrComplete, Const(0, width: mxlen.size), branchUnit.redirectPc); - final exec1 = (useMixedExecution && microcodeExecRead != null) - ? StaticExecutionUnit( + // Memory unit (loads/stores). Speaks Wishbone; bridged to the pipeline's + // memExecRead/memWrite DataPortInterfaces below. The slave response + // (wbAck/wbDatMiso) is fed back from those ports. + final memWbAck = Logic(name: 'mem_wb_ack'); + final memWbDatMiso = Logic(name: 'mem_wb_dat_miso', width: mxlen.size); + // Page-fault for the in-flight load/store (dport done & ~valid), driven in + // the bridge below. Lets a faulting access trap at commit instead of + // hanging the request FSM (which never gets an ack on a fault). + final memFaultWire = Logic(name: 'mem_fault'); + final memUnit = MemoryUnit( + clk, + reset, + issueValid: iq.dispatchMemValid, + issueTag: iq.dispatchMemTag, + issueSrc1: iq.dispatchMemSrc1, + issueSrc2: iq.dispatchMemSrc2, + issueImm: iq.dispatchMemImm, + issueIsStore: iq.dispatchMemIsStore, + issueSize: iq.dispatchMemSize, + issueSignExtend: iq.dispatchMemSignExtend, + flush: flushOrRedirect, + wbAck: memWbAck, + wbDatMiso: memWbDatMiso, + wbErr: Const(0), + memFault: memFaultWire, + memFaultGuest: memFaultGuest, + lsqStores: lsqEnabled, + // storeQueue mode: a load waits for the queue to fully drain. forwarding + // mode: a load only waits when a store partially overlaps it (fwdStall); + // exact matches forward and non-aliasing loads read the bus immediately. + // SSBD (rpipelinectl[0]) forces the forwarding/speculative path to the + // conservative store-queue stall (wait until every older store drains) + // at runtime, closing the speculative-store-bypass v4 surface. The + // store-queue mode is already conservative, so ssbd is a no-op there. + loadStall: lsqEnabled + ? (forwarding + ? mux(ssbdDisable, ~sqEmptyWire, sqFwdStallWire) + : ~sqEmptyWire) + : null, + fwdHit: forwarding ? sqFwdHitWire : null, + fwdData: forwarding ? sqFwdDataWire : null, + issuePc: speculativeLsq ? iq.dispatchMemPc : null, + camViolation: speculativeLsq ? lqCamViolationWire : null, + xlen: mxlen.size, + robTagBits: robTagBits, + ); + memBusyWire <= memUnit.busy; + aluBusy0Wire <= alu0.busy; + aluBusy1Wire <= alu1.busy; + // Store→load violation redirect (speculative LSQ). resultRedirect is only + // high when the memory unit completes a violating store (so it implies the + // mem unit won port 0). The TARGET must be gated the same way: otherwise + // its held (stale) value would be stamped onto every other port-0 commit's + // entry, corrupting unrelated ALU0/load completions. + robCompleteRedirects0 <= memUnit.resultRedirect; + robCompleteTarget0 <= + mux( + memUnit.resultRedirect, + memUnit.resultTarget, + Const(0, width: mxlen.size), + ); + + // Bridge the MemoryUnit's Wishbone master to the DataPortInterfaces. + final memLoadReq = memUnit.wbCyc & memUnit.wbStb & ~memUnit.wbWe; + final memStoreReq = memUnit.wbCyc & memUnit.wbStb & memUnit.wbWe; + memExecRead.en <= memLoadReq; + memExecRead.addr <= memUnit.wbAdr; + memWbDatMiso <= memExecRead.data; + // memWrite.data carries {size[6:0], value[xlen-1:0]} (the core's dport + // demux decodes the byte-count prefix into a log2 size for the MMU). + + // Page fault for the active access: the dport completed (done) but did not + // validate (~valid) -> the MMU walk faulted. Gated by the MemoryUnit's own + // load/store request so the LSQ commit-drain path (which drives memWrite + // independently) never raises a spurious fault on the MemoryUnit. + memFaultWire <= + (memLoadReq & memExecRead.done & ~memExecRead.valid) | + (memStoreReq & memWrite.done & ~memWrite.valid); + + if (lsqEnabled) { + // Store queue: a store pushes at execute and RETIRES immediately at + // commit (no stall); its memory write drains in the BACKGROUND as the + // head entry, in program order. A load waits for the queue to empty. + // `commitValid` advances the queue's commit pointer when a store + // retires; the head entry then becomes drainable. + // A store retiring in slot 0, and (dual-commit) a store retiring in + // slot 1 the same cycle. robCommitAck0 == commitValid0 (the head always + // retires when valid) and commitValid1 implies commitValid0 (in-order + // dual commit), and a slot-1 store is no longer held back, so both + // signals reduce to commitValid{0,1} & commitIsStore{0,1}. The queue + // advances its commit pointer by however many fire (0/1/2), so store + // pairs need no throttling and the queue is robust to the commit + // cadence. See project_hdl_frontend_perf. + final storeCommit = + (rob.commitValid0 & rob.commitIsStore0 & robCommitAck0).named( + 'sqStoreCommit', + ); + final storeCommit1 = (rob.commitValid1 & rob.commitIsStore1).named( + 'sqStoreCommit1', + ); + final drainDone = Logic( + name: 'sqDrainDone', + ); // head write completed (set below) + + final storeQueue = StoreQueue( + clk, + reset, + flush: flushOrRedirect, + pushValid: memUnit.storeFillValid, + pushTag: memUnit.storeFillTag, + pushAddr: memUnit.storeFillAddr, + pushData: memUnit.storeFillData, + pushSize: memUnit.storeFillSize, + commitValid: storeCommit, + commitValid2: storeCommit1, + popValid: drainDone, + // Forwarding query: the dispatching load's effective address + size. + fwdQueryAddr: (iq.dispatchMemSrc1 + iq.dispatchMemImm).named( + 'loadQueryAddr', + ), + fwdQuerySize: iq.dispatchMemSize, + depth: storeQueueDepth, + xlen: mxlen.size, + robTagBits: robTagBits, + ); + sqFullWire <= storeQueue.full; + sqEmptyWire <= storeQueue.empty; + sqFwdHitWire <= storeQueue.fwdHit; + sqFwdDataWire <= storeQueue.fwdData; + sqFwdStallWire <= storeQueue.fwdStall; + + // Load queue (speculative mode): records executed loads; a resolving + // store CAMs it for younger aliasing loads that read too early. + if (speculativeLsq) { + final loadQueue = LoadQueue( clk, reset, - readyExecution & exec0.done & ~exec0.valid, - currentSp, - currentPc, - currentMode, - decodeIndex, - decodeInstrTypeMap, - decodeFields, - csrRead1, - csrWrite1, - memExecRead1!, - memWrite1!, - rs1Read1!, - rs2Read1!, - rdWrite1!, - hasSupervisor: hasSupervisor, - hasUser: hasUser, - microcode: microcode, - mxlen: mxlen, - mideleg: mideleg, - medeleg: medeleg, - mtvec: mtvec, - stvec: stvec, - staticInstructions: staticInstructions, - counterWidth: counterWidth, - ) - : null; + flush: flushOrRedirect, + // A completing load records its access. + pushValid: memUnit.resultValid & ~memUnit.resultIsStore, + pushTag: memUnit.resultTag, + pushAddr: memUnit.resultAddr, + pushSize: memUnit.resultSize, + // Any commit frees the matching load entry (no-op if not a load). + freeValid: rob.commitValid0, + freeTag: rob.headPtr.slice(robTagBits - 1, 0), + headIdx: rob.headPtr.slice(robTagBits - 1, 0), + // A store, the cycle it resolves its address, checks for violations. + camValid: memUnit.storeFillValid, + camTag: memUnit.storeFillTag, + camAddr: memUnit.storeFillAddr, + camSize: memUnit.storeFillSize, + depth: loadQueueDepth, + xlen: mxlen.size, + robTagBits: robTagBits, + ); + lqCamViolationWire <= loadQueue.camViolation; + } else { + lqCamViolationWire <= Const(0); + } - final execDone = exec1 != null ? exec0.done | exec1.done : exec0.done; - final execValid = exec1 != null ? exec0.valid | exec1.valid : exec0.valid; - - final execNextSp = exec1 != null - ? mux(exec0.done & exec0.valid, exec0.nextSp, exec1.nextSp) - : exec0.nextSp; - final execNextPc = exec1 != null - ? mux(exec0.done & exec0.valid, exec0.nextPc, exec1.nextPc) - : exec0.nextPc; - final execNextMode = exec1 != null - ? mux(exec0.done & exec0.valid, exec0.nextMode, exec1.nextMode) - : exec0.nextMode; - final execTrap = exec1 != null - ? mux(exec0.done & exec0.valid, exec0.trap, exec1.trap) - : exec0.trap; - final execTrapCause = exec1 != null - ? mux(exec0.done & exec0.valid, exec0.trapCause, exec1.trapCause) - : exec0.trapCause; - final execTrapTval = exec1 != null - ? mux(exec0.done & exec0.valid, exec0.trapTval, exec1.trapTval) - : exec0.trapTval; - final execFence = exec1 != null - ? mux(exec0.done & exec0.valid, exec0.fence, exec1.fence) - : exec0.fence; - final execInterruptHold = exec1 != null - ? mux( - exec0.done & exec0.valid, - exec0.interruptHold, - exec1.interruptHold, - ) - : exec0.interruptHold; - - Sequential(clk, [ - If( - reset | ~execDone, - then: [ - done < 0, - valid < 0, - nextSp < 0, - nextPc < 0, - nextMode < 0, - trap < 0, - trapCause < 0, - trapTval < 0, - fence < 0, - counter < 0, - if (useMixedExecution && - microcodeExecRead != null && - csrRead != null) ...[ - csrRead.en < 0, - csrRead.addr < 0, - csrRead0!.data < 0, - csrRead0!.done < 0, - csrRead0!.valid < 0, - csrRead1!.data < 0, - csrRead1!.done < 0, - csrRead1!.valid < 0, + // Background drain. SINGLE-OUTSTANDING. A level-driven memWrite.en + // would glitch an extra write during the head-pop transition (the head + // address mux moves while en is still high). Instead a `draining` + // register holds exactly one write in flight: start when the head is + // drainable, hold the address stable until the write acks, pop, repeat. + final draining = Logic(name: 'sqDraining'); + Sequential(clk, [ + If( + reset, + then: [draining < 0], + orElse: [ + If( + draining, + then: [ + If(memWrite.done, then: [draining < 0]), + ], + orElse: [ + If(storeQueue.headDrainable, then: [draining < 1]), + ], + ), + ], + ), + ]); + // The head entry is stable while draining (it pops only on done). + drainDone <= draining & memWrite.done; + memWrite.en <= draining; + memWrite.addr <= storeQueue.headAddr; + memWrite.data <= + [storeQueue.headSize.zeroExtend(7), storeQueue.headData].swizzle(); + // In LSQ mode the MemoryUnit never drives a store bus cycle; ack only + // its load reads. + memWbAck <= memLoadReq & memExecRead.valid; + } else { + sqFullWire <= Const(0); + sqEmptyWire <= Const(1); + sqFwdHitWire <= Const(0); + sqFwdDataWire <= Const(0, width: mxlen.size); + sqFwdStallWire <= Const(0); + lqCamViolationWire <= Const(0); + memWrite.en <= memStoreReq; + memWrite.addr <= memUnit.wbAdr; + memWrite.data <= + [memUnit.wbSize.zeroExtend(7), memUnit.wbDatMosi].swizzle(); + // Ack the MemoryUnit when the store/load completes *successfully* + // (done & valid). A faulting access is done & ~valid -> no ack -> it + // routes to memFaultWire and traps instead of completing as success. + memWbAck <= + (memStoreReq & memWrite.done & memWrite.valid) | + (memLoadReq & memExecRead.valid); + } + + // ----------------------------------------------------------------------- + // Result broadcast → ROB complete + IQ wakeup + // ----------------------------------------------------------------------- + + // Complete port 0: ALU0 or MemoryUnit → ROB. Only one is valid in any + // cycle (single-issue: one instruction in flight, dispatched to exactly + // one FU), so muxing on memUnit.resultValid is safe. + final memWins = memUnit.resultValid; + robCompleteValid0 <= alu0.resultValid | memWins; + robCompleteTag0 <= mux(memWins, memUnit.resultTag, alu0.resultTag); + robCompleteResult0 <= mux(memWins, memUnit.resultData, alu0.resultData); + robCompleteException0 <= + mux(memWins, memUnit.resultException, alu0.resultException); + robCompleteCause0 <= mux(memWins, memUnit.resultCause, alu0.resultCause); + + // Complete port 1: ALU1 + robCompleteValid1 <= alu1.resultValid; + robCompleteTag1 <= alu1.resultTag; + robCompleteResult1 <= alu1.resultData; + robCompleteException1 <= alu1.resultException; + robCompleteCause1 <= alu1.resultCause; + + // Wakeup broadcasts to IQ. The wakeup TAG is the producer's physical + // register (translated from the completing ROB tag), so it matches the + // waiting entries' psrc. Three dedicated ports, one per writeback source: + // port 0 = ALU0/Mem, port 1 = ALU1, port 2 = branch/CSR. Dedicated ports + // mean two FUs completing the same cycle can never drop a wakeup (the + // collision that deadlocked long dual-dispatch loop bodies). + final port0Tag = muxArr( + tagToPdst, + mux(memWins, memUnit.resultTag, alu0.resultTag), + ); + iqWakeupValid0 <= alu0.resultValid | memWins; + iqWakeupTag0 <= port0Tag; + iqWakeupValue0 <= mux(memWins, memUnit.resultData, alu0.resultData); + + // Port 1: ALU1 only. + final p2Valid = robCompleteValid2; + iqWakeupValid1 <= alu1.resultValid; + iqWakeupTag1 <= muxArr(tagToPdst, alu1.resultTag); + iqWakeupValue1 <= alu1.resultData; + // Port 2: branch/CSR completion (dedicated, no longer shares with ALU1). + iqWakeupValid2 <= p2Valid; + iqWakeupTag2 <= muxArr(tagToPdst, robCompleteTag2); + iqWakeupValue2 <= robCompleteResult2; + + // -------------------------------------------------------------------- + // PRF / scoreboard update + // -------------------------------------------------------------------- + // Allocation records tag→pdst/writesRd and marks the new physreg busy. + // Each FU writeback writes the PRF and clears busy. A flush clears all + // busy bits: the redirect is at commit, so everything older has written + // back (busy already 0) and everything younger is squashed. + final wb0Wr = + (alu0.resultValid | memWins) & + muxArr(tagWritesRd, mux(memWins, memUnit.resultTag, alu0.resultTag)); + final wb0Pdst = port0Tag; + final wb0Data = mux(memWins, memUnit.resultData, alu0.resultData); + final wb1Wr = alu1.resultValid & muxArr(tagWritesRd, alu1.resultTag); + final wb1Pdst = muxArr(tagToPdst, alu1.resultTag); + final wb1Data = alu1.resultData; + final wb2Wr = p2Valid & muxArr(tagWritesRd, robCompleteTag2); + final wb2Pdst = muxArr(tagToPdst, robCompleteTag2); + final wb2Data = robCompleteResult2; + + Sequential(clk, [ + If( + reset, + then: [ + ...List.generate(numPhysRegs, (i) => prf[i] < 0), + ...List.generate(numPhysRegs, (i) => prfBusy[i] < 0), + ...List.generate(robDepth, (i) => tagToPdst[i] < 0), + ...List.generate(robDepth, (i) => tagWritesRd[i] < 0), ], - if (useMixedExecution && - microcodeExecRead != null && - csrWrite != null) ...[ - csrWrite.en < 0, - csrWrite.addr < 0, - csrWrite0!.done < 0, - csrWrite0!.valid < 0, - csrWrite1!.done < 0, - csrWrite1!.valid < 0, + orElse: [ + // Record translation at allocation (both lanes). + ...List.generate( + robDepth, + (t) => [ + If( + doAlloc & rob.allocTag0.eq(t), + then: [ + tagToPdst[t] < renameTable.pdst0.zeroExtend(7), + tagWritesRd[t] < renameNode[kWritesRd], + ], + ), + if (dualDispatch) + If( + doAlloc1 & rob.allocTag1.eq(t), + then: [ + tagToPdst[t] < renameTable.pdst1.zeroExtend(7), + tagWritesRd[t] < r1WritesRd, + ], + ), + ], + ).expand((e) => e), + // PRF write + busy update, per physreg. + ...List.generate(numPhysRegs, (p) { + final allocSet = + (doAlloc & + renameNode[kWritesRd] & + renameTable.pdst0.zeroExtend(7).eq(p)) | + (doAlloc1 & + r1WritesRd & + renameTable.pdst1.zeroExtend(7).eq(p)); + final wbClear = + (wb0Wr & wb0Pdst.eq(p)) | + (wb1Wr & wb1Pdst.eq(p)) | + (wb2Wr & wb2Pdst.eq(p)); + // Normal writeback into prf[p]. + final Conditional prfWb = If( + wb0Wr & wb0Pdst.eq(p), + then: [prf[p] < wb0Data], + orElse: [ + If( + wb1Wr & wb1Pdst.eq(p), + then: [prf[p] < wb1Data], + orElse: [ + If(wb2Wr & wb2Pdst.eq(p), then: [prf[p] < wb2Data]), + ], + ), + ], + ); + return [ + // Backdoor seed (only physregs 0..31, the identity-mapped arch + // regs) takes priority while prfSeedEn; otherwise normal + // writeback. prfSeedEn is 0 in all non-seed operation. + if (p < 32) + If( + prfSeedEnIn & prfSeedAddrIn.eq(Const(p, width: 5)), + then: [prf[p] < prfSeedDataIn], + orElse: [prfWb], + ) + else + prfWb, + If( + flushOrRedirect, + then: [prfBusy[p] < 0], + orElse: [ + If( + wbClear, + then: [prfBusy[p] < 0], + orElse: [ + If(allocSet, then: [prfBusy[p] < 1]), + ], + ), + ], + ), + ]; + }).expand((e) => e), ], - if (useMixedExecution && microcodeExecRead != null) ...[ - memExecRead.en < 0, - memExecRead.addr < 0, - memExecRead0!.data < 0, - memExecRead0!.done < 0, - memExecRead0!.valid < 0, - memExecRead1!.data < 0, - memExecRead1!.done < 0, - memExecRead1!.valid < 0, - memWrite.en < 0, - memWrite.addr < 0, - memWrite0!.done < 0, - memWrite0!.valid < 0, - memWrite1!.done < 0, - memWrite1!.valid < 0, - rs1Read.en < 0, - rs1Read.addr < 0, - rs1Read0!.data < 0, - rs1Read0!.done < 0, - rs1Read0!.valid < 0, - rs1Read1!.data < 0, - rs1Read1!.done < 0, - rs1Read1!.valid < 0, - rs2Read.en < 0, - rs2Read.addr < 0, - rs2Read0!.data < 0, - rs2Read0!.done < 0, - rs2Read0!.valid < 0, - rs2Read1!.data < 0, - rs2Read1!.done < 0, - rs2Read1!.valid < 0, - rdWrite.en < 0, - rdWrite.addr < 0, - rdWrite0!.done < 0, - rdWrite0!.valid < 0, - rdWrite1!.done < 0, - rdWrite1!.valid < 0, + ), + ]); + + // ----------------------------------------------------------------------- + // Commit logic + // ----------------------------------------------------------------------- + + // Commit: write results back to the architectural register file. Slot 0 + // is the ROB head (the oldest committer); the register file's write + // arbiter always accepts the oldest write, so slot 0 retires whenever it + // is valid. + // A store retires as soon as it reaches the head; its memory write drains + // in the background from the store queue (in-order store visibility is + // enforced by loads waiting for the queue to empty, not by stalling + // commit). So commit acks normally for stores and everything else. + robCommitAck0 <= rob.commitValid0; + rdWrite.en <= rob.commitValid0 & rob.commitWritesRd0; + rdWrite.addr <= rob.commitRd0; + rdWrite.data <= fitWidth(rob.commitResult0, mxlen.size); + + // Drive register file reads for source operands + rs1Read.en <= renameNode.isFiring; + rs1Read.addr <= renameNode[kRs1].slice(4, 0); + rs2Read.en <= renameNode.isFiring; + rs2Read.addr <= renameNode[kRs2].slice(4, 0); + + // (memExecRead/memWrite are now driven by the MemoryUnit bridge above.) + + // Slot-0 free-list + committed-RAT updates. The slot-1 *address*/pdst + // wires are always driven (their data is don't-care unless slot 1 + // actually retires, gated below). + freeValid0Wire <= rob.commitValid0 & rob.commitWritesRd0; + freeReg0Wire <= rob.commitPdstOld0; + freeReg1Wire <= rob.commitPdstOld1; + commitValid0Wire <= rob.commitValid0 & rob.commitWritesRd0; + commitRd0Wire <= rob.commitRd0; + commitPdst0Wire <= rob.commitPdst0; + commitRd1Wire <= rob.commitRd1; + commitPdst1Wire <= rob.commitPdst1; + + if (rdWrite1 == null) { + // Single-commit: the register file has one write port, so slot 1 cannot + // write back this cycle. The front-end is single-dispatch, so two + // ready-to-commit head entries is rare; this preserves the historical + // behaviour (slot 1 effectively never retires). + robCommitAck1 <= Const(0); + freeValid1Wire <= rob.commitValid1 & rob.commitWritesRd1; + commitValid1Wire <= rob.commitValid1 & rob.commitWritesRd1; + } else { + // Dual-commit: retire slot 1 through the second write port. + // - A second write to the *same* arch reg in the same cycle (WAW) is + // deferred to next cycle (slot 1 becomes the head), avoiding a + // commit-time RAT/free-list hazard. + // - A same-bank collision on a *different* reg is back-pressured by the + // arbiter (wr1Ready=0) and likewise retried next cycle. + // Either way slot 0 still retires, so the head advances and forward + // progress is guaranteed. + final w1Writes = rob.commitWritesRd1; + final sameRd = + (rob.commitWritesRd0 & w1Writes & rob.commitRd0.eq(rob.commitRd1)) + .named('commitSameRd'); + final wr1Present = (rob.commitValid1 & w1Writes & ~sameRd).named( + 'wr1Present', + ); + rdWrite1.en <= wr1Present; + rdWrite1.addr <= rob.commitRd1; + rdWrite1.data <= fitWidth(rob.commitResult1, mxlen.size); + // Slot 1 retires iff valid AND (it writes no reg, or its write landed + // and is not a same-reg WAW). A slot-1 STORE no longer needs throttling: + // the store queue advances its commit pointer by the number of stores + // retiring this cycle (0/1/2), so a store pair commits together without + // under-counting. See project_hdl_frontend_perf. + final commit1 = (rob.commitValid1 & (~w1Writes | (wr1Ready! & ~sameRd))) + .named('commit1'); + robCommitAck1 <= commit1; + freeValid1Wire <= commit1 & w1Writes; + commitValid1Wire <= commit1 & w1Writes; + } + + // ----------------------------------------------------------------------- + // Pipeline outputs + // ----------------------------------------------------------------------- + + // Redirect is carried in the committing ROB entry (set by the branch + // unit at completion via port 2), so it is correct even when the branch + // resolved many cycles before it reaches the head (speculative mode). + final commitRedirect = (rob.commitValid0 & rob.commitRedirects0).named( + 'commitRedirect', + ); + + Sequential(clk, [ + If( + reset, + then: [ + done < 0, + valid < 0, + nextSp < 0, + nextPc < 0, + nextMode < 0, + trap < 0, + trapCause < 0, + trapTval < 0, + trapEpc < 0, + isReturn < 0, + returnLevel < 0, + fence < 0, + interruptHold < 0, + counter < 0, ], - ], - orElse: [ - done < fetcher.done & decodeDone & execDone, - valid < fetcher.valid & decodeValid & execValid, - nextSp < execNextSp, - nextPc < execNextPc, - nextMode < execNextMode, - trap < execTrap, - trapCause < execTrapCause, - trapTval < execTrapTval, - fence < execFence, - interruptHold < execInterruptHold, - If(enable, then: [counter < (counter + 1)]), - if (useMixedExecution && microcodeExecRead != null && csrRead != null) - If.block([ - Iff(csrRead0!.en, [ - csrRead.en < 1, - csrRead.addr < csrRead0.addr, - csrRead0!.data < csrRead.data, - csrRead0!.done < csrRead.done, - csrRead0!.valid < csrRead.valid, - ]), - Iff(csrRead1!.en, [ - csrRead.en < 1, - csrRead.addr < csrRead1!.addr, - csrRead1!.data < csrRead.data, - csrRead1!.done < csrRead.done, - csrRead1!.valid < csrRead.valid, - ]), - Else([ - csrRead.en < 0, - csrRead.addr < 0, - csrRead0!.data < 0, - csrRead0!.done < 0, - csrRead0!.valid < 0, - csrRead1!.data < 0, - csrRead1!.done < 0, - csrRead1!.valid < 0, - ]), - ]), - if (useMixedExecution && - microcodeExecRead != null && - csrWrite != null) - If.block([ - Iff(csrWrite0!.en, [ - csrWrite.en < 1, - csrWrite.addr < csrWrite0!.addr, - csrWrite.data < csrWrite0!.data, - csrWrite0!.done < csrWrite.done, - csrWrite0!.valid < csrWrite.valid, - ]), - Iff(csrWrite1!.en, [ - csrWrite.en < 1, - csrWrite.addr < csrWrite1!.addr, - csrWrite.data < csrWrite1!.data, - csrWrite1!.done < csrWrite.done, - csrWrite1!.valid < csrWrite.valid, - ]), - Else([ - csrWrite.en < 0, - csrWrite.addr < 0, - csrWrite0!.done < 0, - csrWrite0!.valid < 0, - csrWrite1!.done < 0, - csrWrite1!.valid < 0, - ]), - ]), - if (useMixedExecution && microcodeExecRead != null) ...[ - If.block([ - Iff(memExecRead0!.en, [ - memExecRead.en < 1, - memExecRead.addr < memExecRead0.addr, - memExecRead0!.data < memExecRead.data, - memExecRead0!.done < memExecRead.done, - memExecRead0!.valid < memExecRead.valid, - ]), - Iff(memExecRead1!.en, [ - memExecRead.en < 1, - memExecRead.addr < memExecRead1!.addr, - memExecRead1!.data < memExecRead.data, - memExecRead1!.done < memExecRead.done, - memExecRead1!.valid < memExecRead.valid, - ]), - Else([ - memExecRead.en < 0, - memExecRead.addr < 0, - memExecRead0!.data < 0, - memExecRead0!.done < 0, - memExecRead0!.valid < 0, - memExecRead1!.data < 0, - memExecRead1!.done < 0, - memExecRead1!.valid < 0, - ]), - ]), - If.block([ - Iff(memWrite0!.en, [ - memWrite.en < 1, - memWrite.addr < memWrite0!.addr, - memWrite.data < memWrite0!.data, - memWrite0!.done < memWrite.done, - memWrite0!.valid < memWrite.valid, - ]), - Iff(memWrite1!.en, [ - memWrite.en < 1, - memWrite.addr < memWrite1!.addr, - memWrite.data < memWrite1!.data, - memWrite1!.done < memWrite.done, - memWrite1!.valid < memWrite.valid, - ]), - Else([ - memWrite.en < 0, - memWrite.addr < 0, - memWrite0!.done < 0, - memWrite0!.valid < 0, - memWrite1!.done < 0, - memWrite1!.valid < 0, - ]), - ]), - If.block([ - Iff(rs1Read0!.en, [ - rs1Read.en < 1, - rs1Read.addr < rs1Read0.addr, - rs1Read0!.data < rs1Read.data, - rs1Read0!.done < rs1Read.done, - rs1Read0!.valid < rs1Read.valid, - ]), - Iff(rs1Read1!.en, [ - rs1Read.en < 1, - rs1Read.addr < rs1Read1!.addr, - rs1Read1!.data < rs1Read.data, - rs1Read1!.done < rs1Read.done, - rs1Read1!.valid < rs1Read.valid, - ]), - Else([ - rs1Read.en < 0, - rs1Read.addr < 0, - rs1Read0!.data < 0, - rs1Read0!.done < 0, - rs1Read0!.valid < 0, - rs1Read1!.data < 0, - rs1Read1!.done < 0, - rs1Read1!.valid < 0, - ]), - ]), - If.block([ - Iff(rs2Read0!.en, [ - rs2Read.en < 1, - rs2Read.addr < rs2Read0.addr, - rs2Read0!.data < rs2Read.data, - rs2Read0!.done < rs2Read.done, - rs2Read0!.valid < rs2Read.valid, - ]), - Iff(rs2Read1!.en, [ - rs2Read.en < 1, - rs2Read.addr < rs2Read1!.addr, - rs2Read1!.data < rs2Read.data, - rs2Read1!.done < rs2Read.done, - rs2Read1!.valid < rs2Read.valid, - ]), - Else([ - rs2Read.en < 0, - rs2Read.addr < 0, - rs2Read0!.data < 0, - rs2Read0!.done < 0, - rs2Read0!.valid < 0, - rs2Read1!.data < 0, - rs2Read1!.done < 0, - rs2Read1!.valid < 0, - ]), - ]), - If.block([ - Iff(rdWrite0!.en, [ - rdWrite.en < 1, - rdWrite.addr < rdWrite0!.addr, - rdWrite.data < rdWrite0!.data, - rdWrite0!.done < rdWrite.done, - rdWrite0!.valid < rdWrite.valid, - ]), - Iff(rdWrite1!.en, [ - rdWrite.en < 1, - rdWrite.addr < rdWrite1!.addr, - rdWrite.data < rdWrite1!.data, - rdWrite1!.done < rdWrite.done, - rdWrite1!.valid < rdWrite.valid, - ]), - Else([ - rdWrite.en < 0, - rdWrite.addr < 0, - rdWrite0!.done < 0, - rdWrite0!.valid < 0, - rdWrite1!.done < 0, - rdWrite1!.valid < 0, - ]), - ]), + orElse: [ + // Commit: signal done when ROB commits + done < rob.commitValid0, + valid < rob.commitValid0 & ~rob.commitException0, + + // PC update: a committing exception redirects to the trap vector + // (highest priority); else a branch/jump redirects to its target; + // otherwise advance past the committed instruction. + If( + commitException, + then: [nextPc < trapVecPc], + orElse: [ + If( + commitRedirect, + then: [nextPc < rob.commitTarget0], + orElse: [ + If( + rob.commitValid0, + then: [ + nextPc < (rob.commitPc0 + Const(4, width: mxlen.size)), + ], + orElse: [nextPc < currentPc], + ), + ], + ), + ], + ), + + nextSp < currentSp, + nextMode < mux(commitException, trapTargetMode, currentMode), + + // Trap from ROB commit + trap < (rob.commitValid0 & rob.commitException0), + trapCause < rob.commitCause0, + trapTval < Const(0, width: mxlen.size), + trapEpc < rob.commitPc0, + // Privileged return (mret/sret): core.dart restores pc<-{m,s}epc and + // mode<-{m,s}status.xPP and pops the status stack. The fetcher was + // already redirected to retVecPc + flushed via specFlush above. + isReturn < commitReturn, + returnLevel < + mux(commitReturn, commitReturnLevel3, Const(0, width: 3)), + + fence < Const(0), + interruptHold < Const(0), + + If(enable, then: [counter < (counter + 1)]), ], - ], - ), - ]); + ), + ]); + + // OoO does not support HLV/HSV guest accesses yet. + output('memGuest') <= Const(0); + } // end useOoO else } } diff --git a/packages/river_hdl/lib/src/core/pipelined_fetch_memory.dart b/packages/river_hdl/lib/src/core/pipelined_fetch_memory.dart new file mode 100644 index 0000000..45cfbfe --- /dev/null +++ b/packages/river_hdl/lib/src/core/pipelined_fetch_memory.dart @@ -0,0 +1,123 @@ +import 'package:rohd/rohd.dart'; +import 'package:rohd_hcl/rohd_hcl.dart' as hcl; +import '../data_port.dart'; + +/// Synthesizable multiple-outstanding instruction memory presenting a +/// [FetchReadInterface] slave. Storage is a rohd_hcl [hcl.RegisterFile] (the +/// library handles address decode, so there is no hand-rolled per-entry mux), +/// ROM-initialised via `resetValue` so every word is defined (never X, a fast +/// fetcher speculatively reads past the program, and an X there would poison the +/// core). A registered-read pipeline of depth [readLatency] models a fixed- +/// latency on-chip RAM and makes the port multiple-outstanding (a new read +/// accepted every cycle, responses in order `readLatency` cycles later). +/// +/// NOTE: a RegisterFile is flip-flop storage with a combinational read; it is +/// not a dedicated BRAM block (which needs a vendor macro with registered read +/// and init-file contents). This module is the sim/benchmark + simple-TCM model. +/// The real River core EXPOSES the [FetchReadInterface] port; a SoC attaches its +/// own memory (vendor BRAM, DRAM controller, AXI-read bridge). See +/// project_hdl_prefetch / project_hdl_frontend_perf. +class PipelinedFetchMemory extends Module { + /// Number of words of storage (each `dataWidth` bits). Power of two. + final int words; + + /// Registered-read latency in cycles (>= 1). 1 models a standard BRAM. + final int readLatency; + + PipelinedFetchMemory( + Logic clk, + Logic reset, + FetchReadInterface port, { + Logic? writeEn, + Logic? writeAddr, + Logic? writeData, + List initWords = const [], + this.words = 4096, + this.readLatency = 1, + super.name = 'river_pipelined_fetch_memory', + }) : super(definitionName: 'PipelinedFetchMemory') { + assert( + words >= 2 && (words & (words - 1)) == 0, + 'words must be a power of two >= 2 (got $words)', + ); + assert(readLatency >= 1, 'readLatency must be >= 1 (got $readLatency)'); + + clk = addInput('clk', clk); + reset = addInput('reset', reset); + final aw = port.addrWidth; + final dw = port.dataWidth; + final byteShift = (dw ~/ 8).bitLength - 1; // 2 for 32-bit, 3 for 64-bit + final idxBits = (words - 1).bitLength; + + port = port.clone() + ..connectIO( + this, + port, + inputTags: {FetchReadGroup.request}, + outputTags: {FetchReadGroup.requestReady, FetchReadGroup.response}, + uniquify: (og) => 'port_$og', + ); + writeEn = addInput('write_en', writeEn ?? Const(0)); + writeAddr = addInput( + 'write_addr', + writeAddr ?? Const(0, width: aw), + width: aw, + ); + writeData = addInput( + 'write_data', + writeData ?? Const(0, width: dw), + width: dw, + ); + + Logic wordIndex(Logic addr) => + addr.slice(idxBits + byteShift - 1, byteShift); + + // ROM-initialised register file: address decode handled by the library; the + // resetValue map loads the program (every other entry defaults to 0). + final wrPort = hcl.DataPortInterface(dw, idxBits); + wrPort.en <= writeEn; + wrPort.addr <= wordIndex(writeAddr); + wrPort.data <= writeData; + final rdPort = hcl.DataPortInterface(dw, idxBits); + rdPort.en <= Const(1); // BRAM reads every cycle + rdPort.addr <= wordIndex(port.reqAddr); + hcl.RegisterFile( + clk, + reset, + [wrPort], + [rdPort], + numEntries: words, + resetValue: {for (var i = 0; i < initWords.length; i++) i: initWords[i]}, + ); + final rdData = rdPort.data.named('rdData'); // combinational read + + // BRAM accepts one read per cycle; reqReady always high. + port.reqReady <= Const(1); + final accept = port.reqValid.named('accept'); + + // Registered-read pipeline: shift {valid, data} `readLatency` cycles so the + // response lands aligned to its data, in order, multiple-outstanding. + final validPipe = List.generate(readLatency, (i) => Logic(name: 'rv_$i')); + final dataPipe = List.generate( + readLatency, + (i) => Logic(name: 'rd_$i', width: dw), + ); + port.rspValid <= validPipe[readLatency - 1]; + port.rspData <= dataPipe[readLatency - 1]; + + Sequential(clk, [ + If( + reset, + then: [for (final v in validPipe) v < 0], + orElse: [ + validPipe[0] < accept, + dataPipe[0] < rdData, + for (var i = 1; i < readLatency; i++) ...[ + validPipe[i] < validPipe[i - 1], + dataPipe[i] < dataPipe[i - 1], + ], + ], + ), + ]); + } +} diff --git a/packages/river_hdl/lib/src/core/pipelined_fetcher.dart b/packages/river_hdl/lib/src/core/pipelined_fetcher.dart new file mode 100644 index 0000000..c8e635e --- /dev/null +++ b/packages/river_hdl/lib/src/core/pipelined_fetcher.dart @@ -0,0 +1,316 @@ +import 'package:rohd/rohd.dart'; +import '../data_port.dart'; + +/// Multiple-outstanding prefetch fetcher (non-compressed). Unlike +/// [PrefetchFetchUnit] (single read in flight: hold `addr` until the response), +/// this keeps up to `maxOutstanding` reads in flight over a decoupled +/// [FetchReadInterface], so responses arrive every cycle in steady state instead +/// of every `latency` cycles. That is what hides a multi-cycle fetch latency: +/// the icache answers a hit combinationally, so pipelining the REQUESTS (issue +/// addr N+1 before N responds) delivers ~1 instr/cycle on hot code where the +/// single-outstanding engine sagged toward 1/latency. +/// +/// Drop-in compatible OUTPUTS with [PrefetchFetchUnit]/[FetchUnit] +/// (done/valid/result/pcOut/compressed) and the same speculative controls +/// (advance/redirect/redirectPc/stride), so it slots into the same pipeline +/// hookup behind a config flag. +/// +/// IN-ORDER design (fetch is sequential, so no response IDs needed): +/// * Request: drive `reqValid` with `reqAddr`; the issue lands on +/// `reqValid & reqReady`. We only raise `reqValid` when there is buffer room +/// for the eventual response, so a response can always be sunk. +/// * Response: `rspValid`/`rspData` come back IN ORDER, one per accepted +/// request. We track the in-flight request PCs in a small queue so each +/// response is paired with its PC (needed for the 64-bit-word half-select). +/// * Redirect: flush the instruction FIFO and the in-flight PC queue, then +/// DRAIN the responses still owed for the pre-redirect requests via a +/// `discard` counter (the multi-outstanding generalisation of +/// [PrefetchFetchUnit]'s single `discard` bit) before delivering the +/// resteered stream. +/// +/// `maxOutstanding == 1` reduces this to the single-outstanding behaviour, so it +/// is a strict superset. See project_hdl_prefetch / project_hdl_frontend_perf. +class PipelinedFetchUnit extends Module { + /// Instruction-FIFO depth (power of two). Must be >= `maxOutstanding + 1` so + /// every in-flight response has a landing slot AND one entry can be delivered. + final int depth; + + /// Maximum reads in flight (>= 1). Higher hides more fetch latency at the cost + /// of a bigger in-flight PC queue. The `fetchOutstanding` config knob. + final int maxOutstanding; + + Logic get done => output('done'); + Logic get valid => output('valid'); + Logic get compressed => output('compressed'); + Logic get result => output('result'); + Logic get pcOut => output('pc_out'); + + PipelinedFetchUnit( + Logic clk, + Logic reset, + Logic enable, + Logic pc, + FetchReadInterface fetchRead, { + Logic? advance, + Logic? redirect, + Logic? redirectPc, + Logic? stride, + this.depth = 4, + this.maxOutstanding = 2, + super.name = 'river_pipelined_fetch_unit', + }) : super(definitionName: 'PipelinedFetchUnit') { + assert( + depth >= 2 && (depth & (depth - 1)) == 0, + 'instruction FIFO depth must be a power of two >= 2 (got $depth)', + ); + assert( + maxOutstanding >= 1, + 'maxOutstanding must be >= 1 (got $maxOutstanding)', + ); + assert( + depth >= maxOutstanding + 1, + 'depth ($depth) must be >= maxOutstanding + 1 ($maxOutstanding + 1)', + ); + + clk = addInput('clk', clk); + reset = addInput('reset', reset); + enable = addInput('enable', enable); + final w = pc.width; + pc = addInput('pc', pc, width: w); + advance = addInput('advance', advance ?? Const(0)); + redirect = addInput('redirect', redirect ?? Const(0)); + redirectPc = addInput( + 'redirect_pc', + redirectPc ?? Const(0, width: w), + width: w, + ); + + fetchRead = fetchRead.clone() + ..connectIO( + this, + fetchRead, + // Master view: we drive the request, we read ready + response. + outputTags: {FetchReadGroup.request}, + inputTags: {FetchReadGroup.requestReady, FetchReadGroup.response}, + uniquify: (og) => 'fetchRead_$og', + ); + + final dataW = fetchRead.dataWidth; + final wordBytes = dataW ~/ 8; + final instrPerWord = dataW ~/ 32; + final alignMask = Const(~(wordBytes - 1), width: w); + final strideIn = stride != null + ? addInput('stride', stride, width: w) + : Const(4, width: w); + + addOutput('done'); + addOutput('valid'); + addOutput('compressed'); + addOutput('result', width: 32); + addOutput('pc_out', width: w); + + // ---- Generic power-of-two circular FIFO helpers ------------------------- + ({ + Logic head, + Logic tail, + Logic headIdx, + Logic tailIdx, + Logic empty, + Logic full, + Logic count, + Logic Function(List) headOf, + }) + fifo(int d, String tag) { + final pb = (d - 1).bitLength; + final head = Logic(name: '${tag}_head', width: pb + 1); + final tail = Logic(name: '${tag}_tail', width: pb + 1); + final hi = head.slice(pb - 1, 0); + final ti = tail.slice(pb - 1, 0); + final empty = head.eq(tail).named('${tag}Empty'); + final full = (hi.eq(ti) & (head[pb] ^ tail[pb])).named('${tag}Full'); + final count = (tail - head).named('${tag}Count'); + Logic headOf(List arr) { + Logic r = arr[0]; + for (var i = 1; i < d; i++) { + r = mux(hi.eq(Const(i, width: pb)), arr[i], r); + } + return r; + } + + return ( + head: head, + tail: tail, + headIdx: hi, + tailIdx: ti, + empty: empty, + full: full, + count: count, + headOf: headOf, + ); + } + + // Instruction FIFO (delivered to the consumer): {result, pc}. + final if_ = fifo(depth, 'ififo'); + final resArr = List.generate( + depth, + (i) => Logic(name: 'res_$i', width: 32), + ); + final pcArr = List.generate(depth, (i) => Logic(name: 'ipc_$i', width: w)); + + // In-flight request-PC queue: the PCs of accepted-but-unanswered requests, + // so each in-order response can be paired with its PC. + final reqQDepth = + 1 << (maxOutstanding).bitLength; // >= maxOutstanding+1 slots + final rq = fifo(reqQDepth, 'reqq'); + final reqPcArr = List.generate( + reqQDepth, + (i) => Logic(name: 'reqpc_$i', width: w), + ); + + // Match the in-flight counter's pointer width so the redirect-drain + // arithmetic (discard + inflight) needs no re-extension. + final discardW = (reqQDepth - 1).bitLength + 1; + final discard = Logic(name: 'discard', width: discardW); + final started = Logic(name: 'started'); + final fetchPc = Logic(name: 'fetch_pc', width: w); + + // The PC of the request we would issue this cycle (pc until the first real + // PC is latched, matching FetchUnit's reset-to-0 then latch-currentPc). + final curReqPc = mux(started, fetchPc, pc).named('curReqPc'); + + // Issue when there is room for the eventual response (in-flight + buffered + // entries must not exceed depth) and we are under the outstanding cap. + final inflight = rq.count.named('inflight'); + final room = (if_.count.zeroExtend(w) + inflight.zeroExtend(w)) + .lt(depth) + .named('room'); + final underCap = inflight.lt(maxOutstanding).named('underCap'); + // reqValid must NOT depend on reqReady (avoids a valid<-ready combo loop). + final wantIssue = (room & underCap & enable & ~redirect).named('wantIssue'); + final accept = (wantIssue & fetchRead.reqReady).named('accept'); + + fetchRead.reqValid <= wantIssue; + fetchRead.reqAddr <= (curReqPc & alignMask); + + // Response handling: in-order; drop while draining stale (pre-redirect) ones. + final rsp = fetchRead.rspValid.named('rsp'); + final draining = discard.gt(0).named('draining'); + final realRsp = (rsp & ~draining).named('realRsp'); + final dropRsp = (rsp & draining).named('dropRsp'); + + // Extract the 32-bit instruction at the head request PC from a memory word. + // Latency-0 (combinational memory, e.g. an icache hit): the response lands + // the same cycle its request is accepted, before the PC is registered into + // the queue, so forward `curReqPc` when the queue is empty and an accept + // coincides. For latency >= 1 the queue is non-empty on a response, so the + // registered head PC is used. + final rspPcRaw = rq.headOf(reqPcArr).named('rspPcRaw'); + final rspPc = mux(rq.empty & accept, curReqPc, rspPcRaw).named('rspPc'); + Logic instrOf(Logic data, Logic atPc) { + if (instrPerWord == 1) return data.slice(31, 0); + final chunks = [ + for (var i = 0; i < instrPerWord; i++) data.slice(32 * i + 31, 32 * i), + ]; + final selBits = (instrPerWord - 1).bitLength; + final sel = atPc.slice(selBits + 1, 2); + var r = chunks[0]; + for (var i = 1; i < instrPerWord; i++) { + r = mux(sel.eq(i), chunks[i], r); + } + return r; + } + + final fetched = instrOf(fetchRead.rspData, rspPc).named('fetchedInstr'); + + final consume = (advance & ~if_.empty & enable & ~redirect).named( + 'consume', + ); + + // Outputs: deliver the instruction FIFO head. + done <= ~if_.empty & enable; + valid <= ~if_.empty & enable; + result <= if_.headOf(resArr); + pcOut <= if_.headOf(pcArr); + compressed <= Const(0); + + Sequential(clk, [ + If( + reset, + then: [ + if_.head < 0, + if_.tail < 0, + rq.head < 0, + rq.tail < 0, + discard < 0, + started < 0, + fetchPc < 0, + ], + orElse: [ + If( + ~enable, + then: [], + orElse: [ + If( + redirect, + then: [ + // Flush buffers and the in-flight PC queue; the responses owed + // for those in-flight requests must still be drained. + if_.head < 0, + if_.tail < 0, + rq.head < 0, + rq.tail < 0, + // Add the just-flushed in-flight requests to the drain count + // (a same-cycle response is consumed by the +1/-1 below). + discard < (discard + inflight - rsp.zeroExtend(discardW)), + started < 1, + fetchPc < redirectPc, + ], + orElse: [ + started < 1, + // Drain a stale response if one arrived. + If(dropRsp, then: [discard < discard - 1]), + // Pop the instruction FIFO head on consume. + If(consume, then: [if_.head < if_.head + 1]), + // A real response lands: pop its PC, push the instruction. + If( + realRsp, + then: [ + for (var i = 0; i < depth; i++) + If( + if_.tailIdx.eq( + Const(i, width: (depth - 1).bitLength), + ), + then: [resArr[i] < fetched, pcArr[i] < rspPc], + ), + if_.tail < if_.tail + 1, + rq.head < rq.head + 1, + ], + ), + // An accepted request: record its PC, bump the fetch PC. + If( + accept, + then: [ + for (var i = 0; i < reqQDepth; i++) + If( + rq.tailIdx.eq( + Const(i, width: (reqQDepth - 1).bitLength), + ), + then: [reqPcArr[i] < curReqPc], + ), + rq.tail < rq.tail + 1, + fetchPc < (curReqPc + strideIn), + ], + orElse: [ + // Latch the first real PC even if it was not accepted yet. + If(~started, then: [fetchPc < pc]), + ], + ), + ], + ), + ], + ), + ], + ), + ]); + } +} diff --git a/packages/river_hdl/lib/src/core/prefetch_fetcher.dart b/packages/river_hdl/lib/src/core/prefetch_fetcher.dart new file mode 100644 index 0000000..fb15a67 --- /dev/null +++ b/packages/river_hdl/lib/src/core/prefetch_fetcher.dart @@ -0,0 +1,285 @@ +import 'package:rohd/rohd.dart'; +import '../data_port.dart'; + +/// Pipelined prefetch fetcher (non-compressed): fetches AHEAD into a 2-deep +/// instruction FIFO so per-instruction fetch latency overlaps the downstream +/// decode/rename/alloc instead of serialising with it. Drop-in compatible with +/// [FetchUnit]'s outputs (done/valid/result/pcOut/compressed) and the +/// speculative controls (advance/redirect/redirectPc/stride). +/// +/// READ-PORT CONTRACT (interconnect-NEUTRAL, this is the only thing the engine +/// assumes, so any interconnect adapter that honours it works: the in-tree +/// MMU/Wishbone fetch port does, and an AXI/TileLink adapter presenting the same +/// [DataPortInterface] would too): +/// * Request: drive `en` high with a stable `addr`; the read is single- +/// outstanding (one address in flight at a time). +/// * Response: the port asserts `done & valid` together for the data of the +/// CURRENT `addr`. The engine captures `data` the cycle it sees that, it +/// does NOT assume `valid` stays asserted (the real MMU pulses it for one +/// cycle; see mmu.dart). It also does NOT assume any particular latency: the +/// pulse may arrive any number of cycles after the request (back-pressure +/// while the bus is busy is fine, `en`/`addr` are simply held). +/// * Exactly one response per request; in order. +/// This is validated by the pulse-port portability tests (latency sweep + +/// redirect) in prefetch_fetcher_test.dart, independent of any interconnect. +/// (NOTE: rohd_hcl's wrapReadForRegisterFile drives `valid` as a level pipe +/// keyed to `en` continuity, which does NOT honour the contract above except +/// at latency 0, it is a test artifact, not a real interconnect.) +/// +/// CORRECTNESS RULE (the trap the naive early-deliver fell into): never have +/// two bus reads overlapping. Exactly one read is issued at a time; its address +/// is held until the response is consumed, so the response always belongs to +/// the request, no mis-attribution. The prefetch win comes from doing the NEXT +/// read while the current instruction is held in the FIFO (overlapping the +/// consumer's latency), not from overlapping bus reads. On a redirect with a +/// read in flight, the stale response is drained (`discard`) before the +/// redirected read is issued, exactly like [FetchUnit]'s discardResp. See +/// project_hdl_prefetch. +/// +/// NON-COMPRESSED, fixed `stride` (single-issue). Compressed and dual-issue +/// variable-stride support are later increments. +class PrefetchFetchUnit extends Module { + /// Instruction-FIFO depth (power of two >= 2). Deeper buffers more fetched- + /// ahead instructions, so it hides longer/burstier fetch stalls (e.g. icache + /// line-fill misses), the consumer drains the buffer while the next line + /// fills. Default 2 (prefetch-one-ahead). + final int depth; + + Logic get done => output('done'); + Logic get valid => output('valid'); + Logic get compressed => output('compressed'); + Logic get result => output('result'); + Logic get pcOut => output('pc_out'); + + PrefetchFetchUnit( + Logic clk, + Logic reset, + Logic enable, + Logic pc, + DataPortInterface memRead, { + Logic? advance, + Logic? redirect, + Logic? redirectPc, + Logic? stride, + this.depth = 2, + super.name = 'river_prefetch_fetch_unit', + }) : super(definitionName: 'PrefetchFetchUnit') { + assert( + depth >= 2 && (depth & (depth - 1)) == 0, + 'prefetch FIFO depth must be a power of two >= 2 (got $depth)', + ); + clk = addInput('clk', clk); + reset = addInput('reset', reset); + enable = addInput('enable', enable); + final w = pc.width; + pc = addInput('pc', pc, width: w); + advance = addInput('advance', advance ?? Const(0)); + redirect = addInput('redirect', redirect ?? Const(0)); + redirectPc = addInput( + 'redirect_pc', + redirectPc ?? Const(0, width: w), + width: w, + ); + + memRead = memRead.clone() + ..connectIO( + this, + memRead, + outputTags: {DataPortGroup.control}, + inputTags: {DataPortGroup.data, DataPortGroup.integrity}, + uniquify: (og) => 'memRead_$og', + ); + + addOutput('done'); + addOutput('valid'); + addOutput('compressed'); + addOutput('result', width: 32); + addOutput('pc_out', width: w); + + final dataW = memRead.data.width; + final wordBytes = dataW ~/ 8; + final instrPerWord = dataW ~/ 32; // 1 (32-bit mem) or 2 (64-bit mem) + final alignMask = Const(~(wordBytes - 1), width: w); + // The default self-sequencing step is one (non-compressed) instruction. + final strideIn = stride != null + ? addInput('stride', stride, width: w) + : Const(4, width: w); + + // -- N-deep instruction FIFO (circular buffer). The head entry is delivered; + // `produce` pushes at the tail, `consume` pops the head. ---------------- + final ptrBits = (depth - 1).bitLength; + final resArr = List.generate( + depth, + (i) => Logic(name: 'fifo_res_$i', width: 32), + ); + final pcArr = List.generate( + depth, + (i) => Logic(name: 'fifo_pc_$i', width: w), + ); + final head = Logic(name: 'fifo_head', width: ptrBits + 1); + final tail = Logic(name: 'fifo_tail', width: ptrBits + 1); + final headIdx = head.slice(ptrBits - 1, 0); + final tailIdx = tail.slice(ptrBits - 1, 0); + final fifoEmpty = head.eq(tail).named('fifoEmpty'); + final fifoFull = (headIdx.eq(tailIdx) & (head[ptrBits] ^ tail[ptrBits])) + .named('fifoFull'); + Logic muxByIdx(List arr, Logic idx) { + Logic r = arr[0]; + for (var i = 1; i < depth; i++) { + r = mux(idx.eq(Const(i, width: ptrBits)), arr[i], r); + } + return r; + } + + final headRes = muxByIdx(resArr, headIdx).named('headRes'); + final headPc = muxByIdx(pcArr, headIdx).named('headPc'); + + final fetchPc = Logic( + name: 'fetch_pc', + width: w, + ); // PC of the in-flight read + // Bus handshake, modelled on FetchUnit (proven against the real MMU/Wishbone + // fetch port): hold `en` high continuously and keep `addr` stable until the + // response (`done & valid`) lands; the bus drops `valid` on an address change + // and re-asserts it when the new word is ready, so responses attribute to + // their request without toggling `en`. `discard` drops the one stale response + // that may still be in flight for the pre-redirect address (FetchUnit's + // discardResp). See project_hdl_prefetch. + final reading = Logic(name: 'reading'); // en held, a read is in flight + final discard = Logic(name: 'discard'); // drop the next (stale) response + final started = Logic(name: 'started'); // first real PC latched post-reset + + // Extract the 32-bit instruction at `fetchPc` from a memory word. + Logic instrOf(Logic data) { + if (instrPerWord == 1) return data.slice(31, 0); + // 64-bit mem: select the 32-bit half by fetchPc[2]. + final chunks = [ + for (var i = 0; i < instrPerWord; i++) data.slice(32 * i + 31, 32 * i), + ]; + final selBits = (instrPerWord - 1).bitLength; // 1 for 2/word + final sel = fetchPc.slice(selBits + 1, 2); + var r = chunks[0]; + for (var i = 1; i < instrPerWord; i++) { + r = mux(sel.eq(i), chunks[i], r); + } + return r; + } + + final readDone = (memRead.done & memRead.valid).named('readDone'); + final consume = (advance & ~fifoEmpty & enable & ~redirect).named( + 'consume', + ); + // Room for a newly fetched instruction after this cycle's pop: the FIFO is + // not full, or a consume frees a slot. + final preRoom = (~fifoFull | consume).named('preRoom'); + // A genuine instruction arrived this cycle (not a stale/discarded response, + // not redirecting) and there is room to buffer it. + final produce = + (reading & readDone & ~discard & ~redirect & enable & preRoom).named( + 'produce', + ); + + final fetched = instrOf(memRead.data).named('fetchedInstr'); + + final nFetchPc = mux( + produce, + (fetchPc + strideIn), + fetchPc, + ).named('nFetchPc'); + + // Outputs: deliver the FIFO head. + done <= ~fifoEmpty & enable; + valid <= ~fifoEmpty & enable; + result <= headRes; + pcOut <= headPc; + compressed <= Const(0); + + Sequential(clk, [ + If( + reset, + then: [ + head < 0, + tail < 0, + // Initialise to 0 (not `pc`): currentPc may be X during reset, and + // capturing it here would self-sequence X forever. The first real PC + // is latched the first cycle after reset (see `started`), matching + // FetchUnit which resets its addr/pcLatch to 0. + fetchPc < 0, + started < 0, + reading < 0, + discard < 0, + memRead.en < 0, + memRead.addr < 0, + ], + orElse: [ + If( + ~enable, + then: [reading < 0, discard < 0, memRead.en < 0], + orElse: [ + If( + redirect, + then: [ + // Squash the buffer and resteer. Hold en and point at + // redirectPc; a read for the pre-redirect address may still be + // in flight, so flag its one response for discard. + head < 0, + tail < 0, + fetchPc < redirectPc, + reading < 1, + discard < 1, + memRead.en < 1, + memRead.addr < (redirectPc & alignMask), + ], + orElse: [ + // FIFO update: pop the head on consume, push the fetched word + // at the tail on produce (independent pointers). + If(consume, then: [head < head + 1]), + If( + produce, + then: [ + for (var i = 0; i < depth; i++) + If( + tailIdx.eq(Const(i, width: ptrBits)), + then: [resArr[i] < fetched, pcArr[i] < fetchPc], + ), + tail < tail + 1, + ], + ), + reading < 1, + memRead.en < 1, + If( + ~started, + then: [ + // First cycle after reset: latch the real start PC (now + // that currentPc is valid) and issue its read. + started < 1, + fetchPc < pc, + memRead.addr < (pc & alignMask), + ], + orElse: [ + fetchPc < nFetchPc, + If( + discard, + then: [ + // Drop the one stale (pre-redirect) response, then hold + // the redirected address for the real read. + discard < ~memRead.done, + memRead.addr < (fetchPc & alignMask), + ], + orElse: [ + // On capture, advance to the next sequential read; else + // hold the current read address until its response lands. + memRead.addr < (nFetchPc & alignMask), + ], + ), + ], + ), + ], + ), + ], + ), + ], + ), + ]); + } +} diff --git a/packages/river_hdl/lib/src/core/rename.dart b/packages/river_hdl/lib/src/core/rename.dart new file mode 100644 index 0000000..214570d --- /dev/null +++ b/packages/river_hdl/lib/src/core/rename.dart @@ -0,0 +1,305 @@ +import 'package:rohd/rohd.dart'; + +/// Register Alias Table (RAT) for register renaming. +/// +/// Maps 32 architectural registers → physical register indices. +/// Supports dual-issue rename (2 instructions per cycle) and +/// rollback on flush via a committed RAT snapshot. +class RegisterRenameTable extends Module { + /// Number of physical registers. + final int numPhysRegs; + + /// Width of a physical register index. + int get physRegBits => numPhysRegs.bitLength; + + // -- Rename result ports -- + + Logic get psrc1_0 => output('psrc1_0'); + Logic get psrc2_0 => output('psrc2_0'); + Logic get pdst0 => output('pdst_0'); + Logic get pdstOld0 => output('pdst_old_0'); + + Logic get psrc1_1 => output('psrc1_1'); + Logic get psrc2_1 => output('psrc2_1'); + Logic get pdst1 => output('pdst_1'); + Logic get pdstOld1 => output('pdst_old_1'); + + Logic get ready => output('ready'); + + RegisterRenameTable( + Logic clk, + Logic reset, { + required Logic rs1Arch0, + required Logic rs2Arch0, + required Logic rdArch0, + required Logic valid0, + required Logic writesRd0, + required Logic rs1Arch1, + required Logic rs2Arch1, + required Logic rdArch1, + required Logic valid1, + required Logic writesRd1, + required Logic freeValid0, + required Logic freeReg0, + required Logic freeValid1, + required Logic freeReg1, + required Logic commitValid0, + required Logic commitRd0, + required Logic commitPdst0, + required Logic commitValid1, + required Logic commitRd1, + required Logic commitPdst1, + required Logic flush, + this.numPhysRegs = 96, + super.name = 'register_rename_table', + }) : super(definitionName: 'RegisterRenameTable') { + final pBits = physRegBits; + + clk = addInput('clk', clk); + reset = addInput('reset', reset); + + rs1Arch0 = addInput('rs1_arch_0', rs1Arch0, width: 5); + rs2Arch0 = addInput('rs2_arch_0', rs2Arch0, width: 5); + rdArch0 = addInput('rd_arch_0', rdArch0, width: 5); + valid0 = addInput('valid_0', valid0); + writesRd0 = addInput('writes_rd_0', writesRd0); + + rs1Arch1 = addInput('rs1_arch_1', rs1Arch1, width: 5); + rs2Arch1 = addInput('rs2_arch_1', rs2Arch1, width: 5); + rdArch1 = addInput('rd_arch_1', rdArch1, width: 5); + valid1 = addInput('valid_1', valid1); + writesRd1 = addInput('writes_rd_1', writesRd1); + + addOutput('psrc1_0', width: pBits); + addOutput('psrc2_0', width: pBits); + addOutput('pdst_0', width: pBits); + addOutput('pdst_old_0', width: pBits); + + addOutput('psrc1_1', width: pBits); + addOutput('psrc2_1', width: pBits); + addOutput('pdst_1', width: pBits); + addOutput('pdst_old_1', width: pBits); + + addOutput('ready'); + + freeValid0 = addInput('free_valid_0', freeValid0); + freeReg0 = addInput('free_reg_0', freeReg0, width: pBits); + freeValid1 = addInput('free_valid_1', freeValid1); + freeReg1 = addInput('free_reg_1', freeReg1, width: pBits); + + commitValid0 = addInput('commit_valid_0', commitValid0); + commitRd0 = addInput('commit_rd_0', commitRd0, width: 5); + commitPdst0 = addInput('commit_pdst_0', commitPdst0, width: pBits); + commitValid1 = addInput('commit_valid_1', commitValid1); + commitRd1 = addInput('commit_rd_1', commitRd1, width: 5); + commitPdst1 = addInput('commit_pdst_1', commitPdst1, width: pBits); + + flush = addInput('flush', flush); + + // -- Speculative RAT: 32 entries, each holds a physical register index -- + final specRat = List.generate( + 32, + (i) => Logic(name: 'spec_rat_$i', width: pBits), + ); + + // -- Committed RAT: snapshot for rollback -- + final commitRat = List.generate( + 32, + (i) => Logic(name: 'commit_rat_$i', width: pBits), + ); + + // -- Free list: circular buffer of available physical registers -- + final freeList = List.generate( + numPhysRegs, + (i) => Logic(name: 'free_$i', width: pBits), + ); + final freeHead = Logic(name: 'free_head', width: pBits); + final freeTail = Logic(name: 'free_tail', width: pBits); + final freeCount = Logic(name: 'free_count', width: pBits + 1); + // Committed allocation pointer: where freeHead would be if only committed + // (non-speculative) instructions had allocated. On a flush, freeHead rolls + // back to this so speculatively-allocated physical registers are reclaimed. + final freeHeadSnap = Logic(name: 'free_head_snap', width: pBits); + + // Ready when at least 2 physical registers are free (dual-issue) + ready <= freeCount.gte(Const(2, width: pBits + 1)); + + // -- Combinational rename lookups -- + psrc1_0 <= _ratLookup(specRat, rs1Arch0, pBits); + psrc2_0 <= _ratLookup(specRat, rs2Arch0, pBits); + pdstOld0 <= _ratLookup(specRat, rdArch0, pBits); + pdst0 <= _freeListLookup(freeList, freeHead, pBits); + + // Slot 1: check for RAW dependency on slot 0's rd + final slot0WritesRd1Rs1 = valid0 & writesRd0 & rdArch0.eq(rs1Arch1); + final slot0WritesRd1Rs2 = valid0 & writesRd0 & rdArch0.eq(rs2Arch1); + final slot0WritesRd1Rd = valid0 & writesRd0 & rdArch0.eq(rdArch1); + + psrc1_1 <= + mux(slot0WritesRd1Rs1, pdst0, _ratLookup(specRat, rs1Arch1, pBits)); + psrc2_1 <= + mux(slot0WritesRd1Rs2, pdst0, _ratLookup(specRat, rs2Arch1, pBits)); + pdstOld1 <= + mux(slot0WritesRd1Rd, pdst0, _ratLookup(specRat, rdArch1, pBits)); + pdst1 <= + _freeListLookup(freeList, (freeHead + 1).slice(pBits - 1, 0), pBits); + + // -- Free-list / RAT update next-state -- + final readyW = freeCount.gte(Const(2, width: pBits + 1)); + final c0 = (valid0 & writesRd0).named('rename_c0'); + final c1 = (valid1 & writesRd1).named('rename_c1'); + final slot0Renames = (c0 & readyW).named('slot0_renames'); + final slot1Renames = (c1 & readyW).named('slot1_renames'); + // Free registers consumed by speculative rename this cycle (0/1/2), + // suppressed on flush. Matches the original slot-0-first priority. + final consumes = mux( + flush, + Const(0, width: 2), + mux( + slot0Renames, + mux(c1, Const(2, width: 2), Const(1, width: 2)), + mux(slot1Renames, Const(1, width: 2), Const(0, width: 2)), + ), + ).named('rename_consumes'); + // Committed reg-writers / freed registers this cycle (architectural, the + // pipeline drives commitValid/freeValid as commitValid & writesRd). + final commitAllocs = + (commitValid0.zeroExtend(2) + commitValid1.zeroExtend(2)).named( + 'commit_allocs', + ); + final commitPushes = (freeValid0.zeroExtend(2) + freeValid1.zeroExtend(2)) + .named('commit_pushes'); + + final freeHeadSnapNext = (freeHeadSnap + commitAllocs.zeroExtend(pBits)) + .slice(pBits - 1, 0); + // On flush, roll freeHead back to the committed allocation pointer so the + // squashed instructions' physical registers are reclaimed. + final freeHeadNext = mux( + flush, + freeHeadSnapNext, + (freeHead + consumes.zeroExtend(pBits)).slice(pBits - 1, 0), + ); + final freeTailNext = (freeTail + commitPushes.zeroExtend(pBits)).slice( + pBits - 1, + 0, + ); + // After a flush the machine is back at the committed state, which always + // has the 32 architectural registers mapped → numPhysRegs-32 free. + final freeCountNext = mux( + flush, + Const(numPhysRegs - 32, width: pBits + 1), + freeCount - + consumes.zeroExtend(pBits + 1) + + commitPushes.zeroExtend(pBits + 1), + ); + + Sequential(clk, [ + If( + reset, + then: [ + ...List.generate(32, (i) => specRat[i] < Const(i, width: pBits)), + ...List.generate(32, (i) => commitRat[i] < Const(i, width: pBits)), + ...List.generate( + numPhysRegs, + (i) => + freeList[i] < + Const(i < numPhysRegs - 32 ? i + 32 : 0, width: pBits), + ), + freeHead < 0, + freeHeadSnap < 0, + freeTail < Const(numPhysRegs - 32, width: pBits), + freeCount < Const(numPhysRegs - 32, width: pBits + 1), + ], + orElse: [ + // Speculative RAT: update on rename, restore from committed on flush. + If( + flush, + then: [...List.generate(32, (i) => specRat[i] < commitRat[i])], + orElse: [ + If( + slot0Renames, + then: [_ratUpdate(specRat, rdArch0, pdst0, pBits)], + ), + If( + slot1Renames, + then: [_ratUpdate(specRat, rdArch1, pdst1, pBits)], + ), + ], + ), + + // Free-list return + committed-RAT update are architectural: they run + // every cycle, including during a flush. + If( + freeValid0, + then: [_freeListPush(freeList, freeTail, freeReg0, pBits)], + ), + If( + freeValid1, + then: [ + _freeListPush( + freeList, + mux(freeValid0, (freeTail + 1).slice(pBits - 1, 0), freeTail), + freeReg1, + pBits, + ), + ], + ), + If( + commitValid0, + then: [_ratUpdate(commitRat, commitRd0, commitPdst0, pBits)], + ), + If( + commitValid1, + then: [_ratUpdate(commitRat, commitRd1, commitPdst1, pBits)], + ), + + // Pointer registers (single assignment each). + freeHead < freeHeadNext, + freeHeadSnap < freeHeadSnapNext, + freeTail < freeTailNext, + freeCount < freeCountNext, + ], + ), + ]); + } + + Logic _ratLookup(List rat, Logic archReg, int pBits) { + Logic result = rat[0]; + for (var i = 1; i < 32; i++) { + result = mux(archReg.eq(Const(i, width: 5)), rat[i], result); + } + return result; + } + + Logic _freeListLookup(List freeList, Logic index, int pBits) { + Logic result = freeList[0]; + for (var i = 1; i < freeList.length; i++) { + result = mux(index.eq(Const(i, width: pBits)), freeList[i], result); + } + return result; + } + + Conditional _ratUpdate( + List rat, + Logic archReg, + Logic physReg, + int pBits, + ) { + return Case(archReg, [ + for (var i = 0; i < 32; i++) + CaseItem(Const(i, width: 5), [rat[i] < physReg]), + ]); + } + + Conditional _freeListPush( + List freeList, + Logic index, + Logic reg, + int pBits, + ) { + return Case(index, [ + for (var i = 0; i < freeList.length; i++) + CaseItem(Const(i, width: pBits), [freeList[i] < reg]), + ]); + } +} diff --git a/packages/river_hdl/lib/src/core/rob.dart b/packages/river_hdl/lib/src/core/rob.dart new file mode 100644 index 0000000..8e1f734 --- /dev/null +++ b/packages/river_hdl/lib/src/core/rob.dart @@ -0,0 +1,648 @@ +import 'package:rohd/rohd.dart'; + +/// Reorder buffer entry width decomposition. +/// +/// Each ROB entry stores: +/// - pc [xlen bits] +/// - pdst [physRegBits] +/// - pdstOld [physRegBits] +/// - rd [5 bits] +/// - writesRd [1 bit] +/// - complete [1 bit] +/// - exception [1 bit] +/// - causeCode [6 bits] +/// - result [xlen bits] +/// - redirects [1 bit] (branch/jump that changes control flow) +/// - target [xlen bits] (redirect target PC) +class RobEntry { + final int xlen; + final int physRegBits; + + const RobEntry({required this.xlen, this.physRegBits = 7}); + + int get width => + xlen + physRegBits * 2 + 5 + 1 + 1 + 1 + 6 + xlen + 1 + xlen + 1 + 1 + 2; + + // Field offsets (packed LSB-first). + int get pcStart => 0; + int get pcEnd => xlen - 1; + int get pdstStart => pcEnd + 1; + int get pdstEnd => pdstStart + physRegBits - 1; + int get pdstOldStart => pdstEnd + 1; + int get pdstOldEnd => pdstOldStart + physRegBits - 1; + int get rdStart => pdstOldEnd + 1; + int get rdEnd => rdStart + 4; + int get writesRdBit => rdEnd + 1; + int get completeBit => writesRdBit + 1; + int get exceptionBit => completeBit + 1; + int get causeStart => exceptionBit + 1; + int get causeEnd => causeStart + 5; + int get resultStart => causeEnd + 1; + int get resultEnd => resultStart + xlen - 1; + int get redirectsBit => resultEnd + 1; + int get targetStart => redirectsBit + 1; + int get targetEnd => targetStart + xlen - 1; + // Whether this entry is a store. The commit stage uses it to drain the + // store-queue head in program order (only set when an LSQ is configured). + int get isStoreBit => targetEnd + 1; + // Whether this entry is a privileged return (mret/sret) and which level, so + // the commit stage can restore pc/mode from {m,s}epc / {m,s}status. + int get isReturnBit => isStoreBit + 1; + int get returnLevelStart => isReturnBit + 1; + int get returnLevelEnd => returnLevelStart + 1; // 2 bits +} + +/// Reorder buffer for out-of-order commit. +/// +/// Supports dual allocation (2 instructions per cycle) and dual commit. +/// The ROB is a circular buffer indexed by [head] and [tail] pointers. +class ReorderBuffer extends Module { + /// Number of ROB entries (must be power of 2). + final int depth; + + /// XLEN of the core. + final int xlen; + + /// Physical register index width. + final int physRegBits; + + late final RobEntry _entry; + + // -- Allocate outputs -- + + /// Allocated ROB tag returned to rename stage. + Logic get allocTag0 => output('alloc_tag_0'); + Logic get allocTag1 => output('alloc_tag_1'); + + /// Whether allocation succeeded (ROB not full). + Logic get allocReady => output('alloc_ready'); + + // -- Commit outputs -- + + /// Commit valid: head entry is complete and can retire. + Logic get commitValid0 => output('commit_valid_0'); + Logic get commitValid1 => output('commit_valid_1'); + + /// Committed entry data (for register file writeback / free list). + Logic get commitPdst0 => output('commit_pdst_0'); + Logic get commitPdstOld0 => output('commit_pdst_old_0'); + Logic get commitRd0 => output('commit_rd_0'); + Logic get commitWritesRd0 => output('commit_writes_rd_0'); + Logic get commitResult0 => output('commit_result_0'); + Logic get commitException0 => output('commit_exception_0'); + + /// Whether the committing head instruction redirects control flow (a taken + /// branch or a jump), and its target PC. Set at completion via complete + /// port 2 (the branch unit). + Logic get commitRedirects0 => output('commit_redirects_0'); + Logic get commitTarget0 => output('commit_target_0'); + Logic get commitCause0 => output('commit_cause_0'); + Logic get commitPc0 => output('commit_pc_0'); + + /// Whether the committing head instruction is a store (drives the store-queue + /// drain at commit). Always 0 unless `allocIsStore0/1` are wired. + Logic get commitIsStore0 => output('commit_is_store_0'); + Logic get commitIsStore1 => output('commit_is_store_1'); + + /// Whether the committing entry is a privileged return (mret/sret), and its + /// level (2-bit: matches RiscVMicroOp privilegeLevel, 3=M/1=S). Always 0 + /// unless `allocIsReturn0/1` are wired. + Logic get commitIsReturn0 => output('commit_is_return_0'); + Logic get commitIsReturn1 => output('commit_is_return_1'); + Logic get commitReturnLevel0 => output('commit_return_level_0'); + Logic get commitReturnLevel1 => output('commit_return_level_1'); + + Logic get commitPdst1 => output('commit_pdst_1'); + Logic get commitPdstOld1 => output('commit_pdst_old_1'); + Logic get commitRd1 => output('commit_rd_1'); + Logic get commitWritesRd1 => output('commit_writes_rd_1'); + Logic get commitResult1 => output('commit_result_1'); + Logic get commitException1 => output('commit_exception_1'); + Logic get commitCause1 => output('commit_cause_1'); + Logic get commitPc1 => output('commit_pc_1'); + + // -- Status outputs -- + + /// Whether the ROB is empty. + Logic get empty => output('empty'); + + /// The head (commit) pointer, including its wrap bit. Used by the load-store + /// queues to order entries by program age (position from head). + Logic get headPtr => output('head_ptr'); + + /// Whether the ROB is full. + Logic get full => output('full'); + + ReorderBuffer( + Logic clk, + Logic reset, { + required Logic allocValid0, + required Logic allocPc0, + required Logic allocPdst0, + required Logic allocPdstOld0, + required Logic allocRd0, + required Logic allocWritesRd0, + required Logic allocValid1, + required Logic allocPc1, + required Logic allocPdst1, + required Logic allocPdstOld1, + required Logic allocRd1, + required Logic allocWritesRd1, + // Per-slot store flag (optional; tied to 0 for non-LSQ configs). + Logic? allocIsStore0, + Logic? allocIsStore1, + // Per-slot privileged-return flag + level (optional; tied to 0 otherwise). + Logic? allocIsReturn0, + Logic? allocIsReturn1, + Logic? allocReturnLevel0, + Logic? allocReturnLevel1, + required Logic completeValid0, + required Logic completeTag0, + required Logic completeResult0, + required Logic completeException0, + required Logic completeCause0, + required Logic completeValid1, + required Logic completeTag1, + required Logic completeResult1, + required Logic completeException1, + required Logic completeCause1, + required Logic commitAck0, + required Logic commitAck1, + required Logic flush, + // Complete port 2 (the branch unit): also carries the redirect bit + target + // PC. Optional so existing instantiations are unaffected. + Logic? completeValid2, + Logic? completeTag2, + Logic? completeResult2, + Logic? completeException2, + Logic? completeCause2, + Logic? completeRedirects2, + Logic? completeTarget2, + // Optional redirect on complete port 0 (memory unit): a store→load ordering + // violation redirects to re-fetch from after the store. Tied off otherwise. + Logic? completeRedirects0, + Logic? completeTarget0, + this.depth = 64, + this.xlen = 64, + this.physRegBits = 7, + super.name = 'reorder_buffer', + }) : super(definitionName: 'ReorderBuffer') { + _entry = RobEntry(xlen: xlen, physRegBits: physRegBits); + final tagBits = _log2(depth); + + clk = addInput('clk', clk); + reset = addInput('reset', reset); + + // Allocate inputs + allocValid0 = addInput('alloc_valid_0', allocValid0); + allocValid1 = addInput('alloc_valid_1', allocValid1); + + // Allocate data inputs (from rename stage) + allocPc0 = addInput('alloc_pc_0', allocPc0, width: xlen); + allocPc1 = addInput('alloc_pc_1', allocPc1, width: xlen); + allocPdst0 = addInput('alloc_pdst_0', allocPdst0, width: physRegBits); + allocPdst1 = addInput('alloc_pdst_1', allocPdst1, width: physRegBits); + allocPdstOld0 = addInput( + 'alloc_pdst_old_0', + allocPdstOld0, + width: physRegBits, + ); + allocPdstOld1 = addInput( + 'alloc_pdst_old_1', + allocPdstOld1, + width: physRegBits, + ); + allocRd0 = addInput('alloc_rd_0', allocRd0, width: 5); + allocRd1 = addInput('alloc_rd_1', allocRd1, width: 5); + allocWritesRd0 = addInput('alloc_writes_rd_0', allocWritesRd0); + allocWritesRd1 = addInput('alloc_writes_rd_1', allocWritesRd1); + final allocIsStore0In = addInput( + 'alloc_is_store_0', + allocIsStore0 ?? Const(0), + ); + final allocIsStore1In = addInput( + 'alloc_is_store_1', + allocIsStore1 ?? Const(0), + ); + final allocIsReturn0In = addInput( + 'alloc_is_return_0', + allocIsReturn0 ?? Const(0), + ); + final allocIsReturn1In = addInput( + 'alloc_is_return_1', + allocIsReturn1 ?? Const(0), + ); + final allocReturnLevel0In = addInput( + 'alloc_return_level_0', + allocReturnLevel0 ?? Const(0, width: 2), + width: 2, + ); + final allocReturnLevel1In = addInput( + 'alloc_return_level_1', + allocReturnLevel1 ?? Const(0, width: 2), + width: 2, + ); + + // Allocate outputs + addOutput('alloc_tag_0', width: tagBits); + addOutput('alloc_tag_1', width: tagBits); + addOutput('alloc_ready'); + + // Complete inputs + completeValid0 = addInput('complete_valid_0', completeValid0); + completeTag0 = addInput('complete_tag_0', completeTag0, width: tagBits); + completeResult0 = addInput( + 'complete_result_0', + completeResult0, + width: xlen, + ); + completeException0 = addInput('complete_exception_0', completeException0); + completeCause0 = addInput('complete_cause_0', completeCause0, width: 6); + + completeValid1 = addInput('complete_valid_1', completeValid1); + completeTag1 = addInput('complete_tag_1', completeTag1, width: tagBits); + completeResult1 = addInput( + 'complete_result_1', + completeResult1, + width: xlen, + ); + completeException1 = addInput('complete_exception_1', completeException1); + completeCause1 = addInput('complete_cause_1', completeCause1, width: 6); + + // Complete port 2 (branch unit): result + redirect/target. Tied off when + // not provided. + completeValid2 = addInput('complete_valid_2', completeValid2 ?? Const(0)); + completeTag2 = addInput( + 'complete_tag_2', + completeTag2 ?? Const(0, width: tagBits), + width: tagBits, + ); + completeResult2 = addInput( + 'complete_result_2', + completeResult2 ?? Const(0, width: xlen), + width: xlen, + ); + completeException2 = addInput( + 'complete_exception_2', + completeException2 ?? Const(0), + ); + completeCause2 = addInput( + 'complete_cause_2', + completeCause2 ?? Const(0, width: 6), + width: 6, + ); + final completeRedirects0In = addInput( + 'complete_redirects_0', + completeRedirects0 ?? Const(0), + ); + final completeTarget0In = addInput( + 'complete_target_0', + completeTarget0 ?? Const(0, width: xlen), + width: xlen, + ); + completeRedirects2 = addInput( + 'complete_redirects_2', + completeRedirects2 ?? Const(0), + ); + completeTarget2 = addInput( + 'complete_target_2', + completeTarget2 ?? Const(0, width: xlen), + width: xlen, + ); + + // Commit outputs + addOutput('commit_valid_0'); + addOutput('commit_is_store_0'); + addOutput('commit_is_store_1'); + addOutput('commit_is_return_0'); + addOutput('commit_is_return_1'); + addOutput('commit_return_level_0', width: 2); + addOutput('commit_return_level_1', width: 2); + addOutput('commit_pdst_0', width: physRegBits); + addOutput('commit_pdst_old_0', width: physRegBits); + addOutput('commit_rd_0', width: 5); + addOutput('commit_writes_rd_0'); + addOutput('commit_result_0', width: xlen); + addOutput('commit_exception_0'); + addOutput('commit_cause_0', width: 6); + addOutput('commit_pc_0', width: xlen); + addOutput('commit_redirects_0'); + addOutput('commit_target_0', width: xlen); + + addOutput('commit_valid_1'); + addOutput('commit_pdst_1', width: physRegBits); + addOutput('commit_pdst_old_1', width: physRegBits); + addOutput('commit_rd_1', width: 5); + addOutput('commit_writes_rd_1'); + addOutput('commit_result_1', width: xlen); + addOutput('commit_exception_1'); + addOutput('commit_cause_1', width: 6); + addOutput('commit_pc_1', width: xlen); + + commitAck0 = addInput('commit_ack_0', commitAck0); + commitAck1 = addInput('commit_ack_1', commitAck1); + + // Flush + flush = addInput('flush', flush); + + // Status + addOutput('empty'); + addOutput('full'); + addOutput('head_ptr', width: tagBits + 1); + + // Internal state + final head = Logic(name: 'head', width: tagBits + 1); + final tail = Logic(name: 'tail', width: tagBits + 1); + headPtr <= head; + + // Entry storage: array of packed entry words + final entries = List.generate( + depth, + (i) => Logic(name: 'rob_entry_$i', width: _entry.width), + ); + + // Count logic + final count = (tail - head).zeroExtend(tagBits + 1); + final isFull = count.gte(Const(depth - 1, width: tagBits + 1)); + final isEmpty = head.eq(tail); + + empty <= isEmpty; + full <= isFull; + allocReady <= ~isFull; + + // Allocate tags are the current tail positions + allocTag0 <= tail.slice(tagBits - 1, 0); + allocTag1 <= (tail + 1).slice(tagBits - 1, 0); + + // Commit: expose head entries + final headIdx = head.slice(tagBits - 1, 0); + final headIdx1 = (head + 1).slice(tagBits - 1, 0); + + // Mux head entry fields for commit port 0 + final headEntry = _muxEntry(entries, headIdx, tagBits); + _wireCommitPort(headEntry, '0'); + + // Mux head+1 entry fields for commit port 1 + final headEntry1 = _muxEntry(entries, headIdx1, tagBits); + _wireCommitPort(headEntry1, '1'); + + // Head entry is committable when its complete bit is set + commitValid0 <= headEntry[_entry.completeBit] & ~isEmpty; + // Slot 1 may retire the next entry only when slot 0 is NOT a redirecting + // branch: a taken branch at the head makes head+1 a wrong-path instruction, + // which the redirect-flush will squash. Committing it through slot 1 in the + // same cycle would wrongly retire the skipped instruction. + commitValid1 <= + headEntry1[_entry.completeBit] & + headEntry[_entry.completeBit] & + ~headEntry[_entry.redirectsBit] & + ~isEmpty & + ~head.eq(tail - 1); + + Sequential(clk, [ + If( + reset | flush, + then: [head < 0, tail < 0, ...entries.map((e) => e < 0)], + orElse: [ + // Allocate: push new entries at tail + If( + allocValid0 & allocReady, + then: [ + ..._packEntry( + entries, + tail.slice(tagBits - 1, 0), + tagBits, + pc: allocPc0, + pdst: allocPdst0, + pdstOld: allocPdstOld0, + rd: allocRd0, + writesRd: allocWritesRd0, + isStore: allocIsStore0In, + isReturn: allocIsReturn0In, + returnLevel: allocReturnLevel0In, + ), + If( + allocValid1, + then: [ + ..._packEntry( + entries, + (tail + 1).slice(tagBits - 1, 0), + tagBits, + pc: allocPc1, + pdst: allocPdst1, + pdstOld: allocPdstOld1, + rd: allocRd1, + writesRd: allocWritesRd1, + isStore: allocIsStore1In, + isReturn: allocIsReturn1In, + returnLevel: allocReturnLevel1In, + ), + tail < tail + 2, + ], + orElse: [tail < tail + 1], + ), + ], + ), + + // Complete: mark entries as done, write result + If( + completeValid0, + then: [ + ..._setComplete( + entries, + completeTag0, + tagBits, + result: completeResult0, + exception: completeException0, + cause: completeCause0, + redirects: completeRedirects0In, + target: completeTarget0In, + ), + ], + ), + If( + completeValid1, + then: [ + ..._setComplete( + entries, + completeTag1, + tagBits, + result: completeResult1, + exception: completeException1, + cause: completeCause1, + ), + ], + ), + // Complete port 2: the branch unit, which also records the redirect + // bit and target PC so the redirect can be applied at commit. + If( + completeValid2, + then: [ + ..._setComplete( + entries, + completeTag2, + tagBits, + result: completeResult2, + exception: completeException2, + cause: completeCause2, + redirects: completeRedirects2, + target: completeTarget2, + ), + ], + ), + + // Commit: advance head + If( + commitAck0, + then: [ + If( + commitAck1, + then: [head < head + 2], + orElse: [head < head + 1], + ), + ], + ), + ], + ), + ]); + } + + /// Mux an entry from the entries array by index. + Logic _muxEntry(List entries, Logic index, int tagBits) { + Logic result = entries[0]; + for (var i = 1; i < entries.length; i++) { + result = mux(index.eq(Const(i, width: tagBits)), entries[i], result); + } + return result; + } + + /// Wire commit port outputs from a muxed entry. + void _wireCommitPort(Logic entry, String suffix) { + output('commit_pdst_$suffix') <= + entry.slice(_entry.pdstEnd, _entry.pdstStart); + output('commit_pdst_old_$suffix') <= + entry.slice(_entry.pdstOldEnd, _entry.pdstOldStart); + output('commit_rd_$suffix') <= entry.slice(_entry.rdEnd, _entry.rdStart); + output('commit_writes_rd_$suffix') <= entry[_entry.writesRdBit]; + output('commit_result_$suffix') <= + entry.slice(_entry.resultEnd, _entry.resultStart); + output('commit_exception_$suffix') <= entry[_entry.exceptionBit]; + output('commit_cause_$suffix') <= + entry.slice(_entry.causeEnd, _entry.causeStart); + output('commit_pc_$suffix') <= entry.slice(_entry.pcEnd, _entry.pcStart); + output('commit_is_store_$suffix') <= entry[_entry.isStoreBit]; + output('commit_is_return_$suffix') <= entry[_entry.isReturnBit]; + output('commit_return_level_$suffix') <= + entry.slice(_entry.returnLevelEnd, _entry.returnLevelStart); + // Redirect info is only consumed at the head (commit port 0). + if (suffix == '0') { + output('commit_redirects_0') <= entry[_entry.redirectsBit]; + output('commit_target_0') <= + entry.slice(_entry.targetEnd, _entry.targetStart); + } + } + + /// Pack an entry into the entries array at the given index. + List _packEntry( + List entries, + Logic index, + int tagBits, { + required Logic pc, + required Logic pdst, + required Logic pdstOld, + required Logic rd, + required Logic writesRd, + required Logic isStore, + required Logic isReturn, + required Logic returnLevel, + }) { + // Build packed entry value (MSB-first): returnLevel, isReturn, isStore, + // redirects=0, target=0, complete=0, exception=0, cause=0, result=0. + final packed = [ + returnLevel.zeroExtend(2), // returnLevel (MSB, 2 bits) + isReturn.zeroExtend(1), // isReturn + isStore.zeroExtend(1), // isStore + Const(0, width: xlen), // target + Const(0), // redirects + Const(0, width: xlen), // result + Const(0, width: 6), // cause + Const(0), // exception + Const(0), // complete + writesRd.zeroExtend(1), + rd.zeroExtend(5), + pdstOld.zeroExtend(physRegBits), + pdst.zeroExtend(physRegBits), + pc.zeroExtend(xlen), + ].swizzle(); + + return [ + Case(index, [ + for (var i = 0; i < entries.length; i++) + CaseItem(Const(i, width: tagBits), [entries[i] < packed]), + ]), + ]; + } + + /// Set the complete bit and write result/exception into an entry. + List _setComplete( + List entries, + Logic tag, + int tagBits, { + required Logic result, + required Logic exception, + required Logic cause, + Logic? redirects, + Logic? target, + }) { + return [ + Case(tag, [ + for (var i = 0; i < entries.length; i++) + CaseItem(Const(i, width: tagBits), [ + // Set complete bit, exception, cause, result, and (for the branch + // port) the redirect bit + target PC. + entries[i] < + entries[i] + .withSet(_entry.completeBit, Const(1)) + .withSet(_entry.exceptionBit, exception) + .withSetRange(_entry.causeStart, _entry.causeEnd, cause) + .withSetRange(_entry.resultStart, _entry.resultEnd, result) + .withSet(_entry.redirectsBit, redirects ?? Const(0)) + .withSetRange( + _entry.targetStart, + _entry.targetEnd, + target ?? Const(0, width: xlen), + ), + ]), + ]), + ]; + } + + static int _log2(int n) { + assert(n > 0 && (n & (n - 1)) == 0, 'depth must be power of 2'); + int r = 0; + int v = n; + while (v > 1) { + v >>= 1; + r++; + } + return r; + } +} + +/// Extension to set individual bits and ranges in a Logic value. +extension _LogicBitSet on Logic { + /// Return a new Logic with bits [start..end] set to [value]. + Logic withSetRange(int start, int end, Logic value) { + final rangeWidth = end - start + 1; + // Use BigInt: for high fields (e.g. result at bits 60..91) the mask + // `((1<{}; + for (var s = 0; s < 4; s++) { + final bytes = 1 << s; + cases[s] = bytes >= selWidth ? (1 << selWidth) - 1 : (1 << bytes) - 1; + } + ones <= + cases.entries.fold( + Const(cases[0]!, width: selWidth), + (acc, e) => mux( + sbaSize.eq(Const(e.key, width: 3)), + Const(e.value, width: selWidth), + acc, + ), + ); + + wbCyc <= sbaReq; + wbStb <= sbaReq; + wbWe <= sbaWe; + wbAdr <= + (xlen >= addressWidth + ? sbaAddr.getRange(0, addressWidth) + : sbaAddr.zeroExtend(addressWidth)); + + // Write data, sign-irrelevant zero-justified to the bus width, shifted up + // into its addressed byte lane. + final wdataFull = xlen >= dataWidth + ? sbaWdata.getRange(0, dataWidth) + : sbaWdata.zeroExtend(dataWidth); + wbDatMosi <= (wdataFull << bitShift).named('wb_wdata_shifted'); + wbSel <= (ones << byteOff).getRange(0, selWidth); + + sbaAck <= wbAck; + // Shift read data down from its lane to lane 0 (right-justified). Logical + // shift (`>>>`): ROHD `>>` is arithmetic and would sign-extend. + final rdataShifted = (wbDatMiso >>> bitShift).named('sba_rdata_shifted'); + sbaRdata <= + (dataWidth >= xlen + ? rdataShifted.getRange(0, xlen) + : rdataShifted.zeroExtend(xlen)); + } +} diff --git a/packages/river_hdl/lib/src/core/stages.dart b/packages/river_hdl/lib/src/core/stages.dart new file mode 100644 index 0000000..e1ef871 --- /dev/null +++ b/packages/river_hdl/lib/src/core/stages.dart @@ -0,0 +1,200 @@ +import 'package:harbor/harbor.dart'; + +/// Pipeline stages for the River OoO dual-issue core. +/// +/// The pipeline is split into a front-end (in-order) and back-end (OoO): +/// fetch → decode → rename → issue → [execute / memory / branch / csr] → commit +enum RiverStage with HarborPipelineStage { + /// Instruction fetch from I-cache / memory. + fetch, + + /// Instruction decode and register read. + decode, + + /// Register rename: map architectural → physical via RAT. + rename, + + /// Issue queue: dispatch to functional units when operands ready. + issue, + + /// ALU / mul / div execution. + execute, + + /// Load / store / atomic memory access. + memory, + + /// Branch resolution and PC redirect. + branch, + + /// CSR read / write (serialised). + csr, + + /// Commit: retire from ROB in program order, free physical registers. + commit, +} + +// --------------------------------------------------------------------------- +// Payload constants. Width in bits, carried through pipeline registers. +// --------------------------------------------------------------------------- + +/// Program counter of this instruction. +const kPC = HarborPayload('PC', width: 64); + +/// Raw 32-bit instruction word (post-decompression). +const kInstruction = HarborPayload('INSTR', width: 32); + +/// Whether the original fetch was a compressed (16-bit) instruction. +const kCompressed = HarborPayload('COMPRESSED'); + +/// Decoded destination register index (architectural, 5 bits). +const kRd = HarborPayload('RD', width: 5); + +/// Decoded source register 1 index (architectural, 5 bits). +const kRs1 = HarborPayload('RS1', width: 5); + +/// Decoded source register 2 index (architectural, 5 bits). +const kRs2 = HarborPayload('RS2', width: 5); + +/// Sign-extended immediate value. +const kImm = HarborPayload('IMM', width: 64); + +/// Operation index into the microcode ROM. 12 bits covers the full RV64GC + +/// bit-manip op table (RC1.ma macro needs 11); fitWidth at the decode site keeps +/// it correct for smaller configs too. +const kOpIndex = HarborPayload('OP_INDEX', width: 12); + +/// Instruction format type index (R/I/S/B/U/J). +const kFormatType = HarborPayload('FORMAT_TYPE', width: 4); + +/// Physical destination register (from rename). +const kPdst = HarborPayload('PDST', width: 7); + +/// Physical source register 1 (from rename). +const kPsrc1 = HarborPayload('PSRC1', width: 7); + +/// Physical source register 2 (from rename). +const kPsrc2 = HarborPayload('PSRC2', width: 7); + +/// Previous physical mapping of rd (for rollback on mis-speculate). +const kPdstOld = HarborPayload('PDST_OLD', width: 7); + +/// Reorder buffer tag. +const kRobTag = HarborPayload('ROB_TAG', width: 7); + +/// Source operand 1 value (read from physical register file or bypass). +const kSrc1Value = HarborPayload('SRC1_VALUE', width: 64); + +/// Source operand 2 value (read from physical register file or bypass). +const kSrc2Value = HarborPayload('SRC2_VALUE', width: 64); + +/// ALU / execution result. +const kResult = HarborPayload('RESULT', width: 64); + +/// Memory load data. +const kMemData = HarborPayload('MEM_DATA', width: 64); + +/// Memory address (computed by AGU). +const kMemAddr = HarborPayload('MEM_ADDR', width: 64); + +/// Memory access size in bytes (1/2/4/8). +const kMemSize = HarborPayload('MEM_SIZE', width: 3); + +/// Whether this instruction writes a register. +const kWritesRd = HarborPayload('WRITES_RD'); + +/// Whether this is a memory load. +const kIsLoad = HarborPayload('IS_LOAD'); + +/// Whether this is a memory store. +const kIsStore = HarborPayload('IS_STORE'); + +/// Whether this is a branch/jump. +const kIsBranch = HarborPayload('IS_BRANCH'); + +/// Whether this is a CSR instruction. +const kIsCsr = HarborPayload('IS_CSR'); + +/// Whether this is a privileged return (mret/sret). +const kIsReturn = HarborPayload('IS_RETURN'); + +/// Privileged-return level (2-bit: 3=MRET, 1=SRET); meaningful when kIsReturn. +const kReturnLevel = HarborPayload('RETURN_LEVEL', width: 2); + +/// Functional unit type (FuType.index: alu=0, memory=1, branch=2, csr=3). +const kFuType = HarborPayload('FU_TYPE', width: 2); + +/// ALU operation (RiscVAluFunct.index). +const kAluFunct = HarborPayload('ALU_FUNCT', width: 7); + +/// Conditional-branch condition (RISC-V funct3 encoding). +const kBranchCond = HarborPayload('BRANCH_COND', width: 3); + +/// Unconditional jump (jal/jalr). +const kIsJump = HarborPayload('IS_JUMP'); + +/// Register-indirect jump target (jalr). +const kIsJalr = HarborPayload('IS_JALR'); + +/// ALU second operand is the immediate (I-type). +const kUseImm = HarborPayload('USE_IMM'); + +/// Sign-extend (vs zero-extend) a load result. +const kSignExtend = HarborPayload('SIGN_EXTEND'); + +/// Branch target address. +const kBranchTarget = HarborPayload('BRANCH_TARGET', width: 64); + +/// Whether the branch was taken. +const kBranchTaken = HarborPayload('BRANCH_TAKEN'); + +/// Whether this instruction caused a trap. +const kTrap = HarborPayload('TRAP'); + +/// Trap cause code. +const kTrapCause = HarborPayload('TRAP_CAUSE', width: 6); + +/// Trap value. +const kTrapVal = HarborPayload('TRAP_VAL', width: 64); + +/// Fence signal. +const kFence = HarborPayload('FENCE'); + +/// Privilege mode (M=3, S=1, U=0). +const kPrivMode = HarborPayload('PRIV_MODE', width: 2); + +// --------------------------------------------------------------------------- +// Dual-dispatch slot-1 payloads. A second instruction flows through the same +// registered decode→rename boundary as slot 0, so every slot-0 decode/rename +// field has a slot-1 twin. kSlot1Valid marks whether slot 1 holds a real +// (fetched+decoded) instruction this cycle. Only used when issueWidth==dual. +// --------------------------------------------------------------------------- +const kSlot1Valid = HarborPayload('SLOT1_VALID'); +const kPC1 = HarborPayload('PC_1', width: 64); +const kInstruction1 = HarborPayload('INSTR_1', width: 32); +const kRd1 = HarborPayload('RD_1', width: 5); +const kRs1_1 = HarborPayload('RS1_1', width: 5); +const kRs2_1 = HarborPayload('RS2_1', width: 5); +const kImm1 = HarborPayload('IMM_1', width: 64); +const kOpIndex1 = HarborPayload('OP_INDEX_1', width: 12); +const kWritesRd1 = HarborPayload('WRITES_RD_1'); +const kIsLoad1 = HarborPayload('IS_LOAD_1'); +const kIsStore1 = HarborPayload('IS_STORE_1'); +const kIsBranch1 = HarborPayload('IS_BRANCH_1'); +const kIsCsr1 = HarborPayload('IS_CSR_1'); +const kIsReturn1 = HarborPayload('IS_RETURN_1'); +const kReturnLevel1 = HarborPayload('RETURN_LEVEL_1', width: 2); +const kMemSize1 = HarborPayload('MEM_SIZE_1', width: 3); +const kFuType1 = HarborPayload('FU_TYPE_1', width: 2); +const kAluFunct1 = HarborPayload('ALU_FUNCT_1', width: 7); +const kBranchCond1 = HarborPayload('BRANCH_COND_1', width: 3); +const kIsJump1 = HarborPayload('IS_JUMP_1'); +const kIsJalr1 = HarborPayload('IS_JALR_1'); +const kUseImm1 = HarborPayload('USE_IMM_1'); +const kSignExtend1 = HarborPayload('SIGN_EXTEND_1'); + +// Slot-1 rename results. +const kPdst1 = HarborPayload('PDST_1', width: 7); +const kPsrc1_1 = HarborPayload('PSRC1_1', width: 7); +const kPsrc2_1 = HarborPayload('PSRC2_1', width: 7); +const kPdstOld1 = HarborPayload('PDST_OLD_1', width: 7); +const kRobTag1 = HarborPayload('ROB_TAG_1', width: 7); diff --git a/packages/river_hdl/lib/src/data_port.dart b/packages/river_hdl/lib/src/data_port.dart new file mode 100644 index 0000000..ad90bea --- /dev/null +++ b/packages/river_hdl/lib/src/data_port.dart @@ -0,0 +1,204 @@ +import 'package:rohd/rohd.dart'; +import 'package:rohd_hcl/rohd_hcl.dart' as hcl; + +/// Extended port group tags for [DataPortInterface]. +/// +/// Mirrors rohd_hcl's DataPortGroup and adds [integrity] +/// for done/valid handshaking signals. +enum DataPortGroup { + /// Control signals: en, addr. + control, + + /// Data signal: data. + data, + + /// Handshake signals: done, valid. + integrity, +} + +/// A data port interface with handshake signals. +/// +/// Extends the basic rohd_hcl pattern (en, addr, data) with +/// done and valid signals for request/response handshaking. +class DataPortInterface extends Interface { + /// Data width in bits. + final int dataWidth; + + /// Address width in bits. + final int addrWidth; + + /// Enable signal. + Logic get en => port('en'); + + /// Address signal. + Logic get addr => port('addr'); + + /// Data signal. + Logic get data => port('data'); + + /// Transaction complete signal. + Logic get done => port('done'); + + /// Response valid signal. + Logic get valid => port('valid'); + + /// Creates a data port interface with the given [dataWidth] and [addrWidth]. + DataPortInterface(this.dataWidth, this.addrWidth) { + setPorts( + [Logic.port('en'), Logic.port('addr', addrWidth)], + [DataPortGroup.control], + ); + + setPorts([Logic.port('data', dataWidth)], [DataPortGroup.data]); + + setPorts( + [Logic.port('done'), Logic.port('valid')], + [DataPortGroup.integrity], + ); + } + + @override + DataPortInterface clone() => DataPortInterface(dataWidth, addrWidth); +} + +/// Port groups for [FetchReadInterface]. +enum FetchReadGroup { + /// Request channel (master -> slave): reqValid, reqAddr. + request, + + /// Request back-pressure (slave -> master): reqReady. + requestReady, + + /// Response channel (slave -> master): rspValid, rspData. + response, +} + +/// A decoupled, multiple-outstanding read-port interface for instruction fetch. +/// +/// Unlike [DataPortInterface] (single-outstanding: hold `en`/`addr` until a +/// `done & valid` pulse), this splits request and response so the master can +/// issue read N+1 before read N's response lands. That is what lets the fetcher +/// hide a multi-cycle fetch latency: keep several reads in flight so responses +/// arrive every cycle in steady state instead of every `latency` cycles. +/// +/// CONTRACT (in-order, no IDs needed because fetch is sequential): +/// * Request handshake: master raises `reqValid` with a stable `reqAddr`; the +/// transfer happens on the cycle `reqValid & reqReady` are both high. The +/// slave drops `reqReady` to back-pressure when it cannot accept more (its +/// outstanding capacity is full). +/// * Response: the slave returns `rspValid` + `rspData` for accepted requests +/// IN ORDER, any number of cycles later, one response per request. The +/// master must always be able to sink a response (the prefetch FIFO sizing +/// guarantees this, see prefetchDepth vs fetchOutstanding validation). +/// +/// An AXI4 AR/R or TileLink A/D adapter presents exactly this shape; the +/// in-tree single-outstanding MMU/Wishbone port is the `fetchOutstanding == 1` +/// degenerate case. See project_hdl_prefetch / project_hdl_frontend_perf. +class FetchReadInterface extends Interface { + /// Data width in bits. + final int dataWidth; + + /// Address width in bits. + final int addrWidth; + + /// Request valid (master -> slave): a read is being offered this cycle. + Logic get reqValid => port('req_valid'); + + /// Request address (master -> slave): the address to read. + Logic get reqAddr => port('req_addr'); + + /// Request ready (slave -> master): the slave can accept a request this cycle. + Logic get reqReady => port('req_ready'); + + /// Response valid (slave -> master): `rspData` carries the next response. + Logic get rspValid => port('rsp_valid'); + + /// Response data (slave -> master): the read result, in request order. + Logic get rspData => port('rsp_data'); + + /// Creates a fetch-read interface with the given [dataWidth] and [addrWidth]. + FetchReadInterface(this.dataWidth, this.addrWidth) { + setPorts( + [Logic.port('req_valid'), Logic.port('req_addr', addrWidth)], + [FetchReadGroup.request], + ); + setPorts([Logic.port('req_ready')], [FetchReadGroup.requestReady]); + setPorts( + [Logic.port('rsp_valid'), Logic.port('rsp_data', dataWidth)], + [FetchReadGroup.response], + ); + } + + @override + FetchReadInterface clone() => FetchReadInterface(dataWidth, addrWidth); +} + +/// Wraps a [DataPortInterface] for use with rohd_hcl's [hcl.RegisterFile]. +/// +/// Creates a rohd_hcl [hcl.DataPortInterface] that shares the en, addr, and +/// data signals. The done and valid signals are driven to constant 1 when +/// the enable is active. +hcl.DataPortInterface wrapForRegisterFile(DataPortInterface dpi) { + final hclDpi = hcl.DataPortInterface(dpi.dataWidth, dpi.addrWidth); + hclDpi.en <= dpi.en; + hclDpi.addr <= dpi.addr; + // For read ports, data flows from RegisterFile to our port + // For write ports, data flows from our port to RegisterFile + // We need bidirectional support - just connect both ways + // Actually this won't work directly. We need separate read/write helpers. + return hclDpi; +} + +/// Creates a rohd_hcl read port backed by our [DataPortInterface]. +/// +/// The en and addr signals are driven from [dpi], and the data signal +/// from the rohd_hcl port is connected back to [dpi.data]. +/// With [readLatency] > 0, done/valid are delayed to match the +/// MemoryModel's pipeline latency. +hcl.DataPortInterface wrapReadForRegisterFile( + DataPortInterface dpi, { + Logic? clk, + int readLatency = 0, +}) { + final hclDpi = hcl.DataPortInterface(dpi.dataWidth, dpi.addrWidth); + hclDpi.en <= dpi.en; + hclDpi.addr <= dpi.addr; + dpi.data <= hclDpi.data; + dpi.done <= dpi.en; + + if (readLatency > 0 && clk != null) { + final pipe = List.generate( + readLatency + 1, + (i) => Logic(name: 'rd_valid_pipe_$i'), + ); + Sequential(clk, [ + If( + dpi.en, + then: [ + pipe[0] < 1, + for (var i = 1; i < pipe.length; i++) pipe[i] < pipe[i - 1], + ], + orElse: [for (final p in pipe) p < 0], + ), + ]); + dpi.valid <= pipe.last; + } else { + dpi.valid <= dpi.en; + } + + return hclDpi; +} + +/// Creates a rohd_hcl write port backed by our [DataPortInterface]. +/// +/// The en, addr, and data signals are driven from [dpi]. +/// done and valid on [dpi] are driven to 1 when en is active. +hcl.DataPortInterface wrapWriteForRegisterFile(DataPortInterface dpi) { + final hclDpi = hcl.DataPortInterface(dpi.dataWidth, dpi.addrWidth); + hclDpi.en <= dpi.en; + hclDpi.addr <= dpi.addr; + hclDpi.data <= dpi.data; + dpi.done <= dpi.en; + dpi.valid <= dpi.en; + return hclDpi; +} diff --git a/packages/river_hdl/lib/src/dev.dart b/packages/river_hdl/lib/src/dev.dart deleted file mode 100644 index 7baccde..0000000 --- a/packages/river_hdl/lib/src/dev.dart +++ /dev/null @@ -1,343 +0,0 @@ -import 'package:riscv/riscv.dart'; -import 'package:river/river.dart'; -import 'package:rohd/rohd.dart'; -import 'package:rohd_bridge/rohd_bridge.dart'; -import 'package:rohd_hcl/rohd_hcl.dart'; - -typedef DeviceModuleFactory = - DeviceModule Function(Mxlen, Device, Map); - -class MmioReadInterface extends PairInterface { - late final int dataWidth; - late final int addrWidth; - - Logic get en => port('en'); - Logic get addr => port('addr'); - Logic get data => port('data'); - Logic get done => port('done'); - Logic get valid => port('valid'); - - MmioReadInterface(int dataWidth, int addrWidth) - : super( - portsFromConsumer: [Logic.port('en'), Logic.port('addr', addrWidth)], - portsFromProvider: [ - Logic.port('data', dataWidth), - Logic.port('done'), - Logic.port('valid'), - ], - ) { - this.dataWidth = dataWidth; - this.addrWidth = addrWidth; - } - - @override - MmioReadInterface clone() => MmioReadInterface(dataWidth, addrWidth); -} - -class MmioWriteInterface extends PairInterface { - late final int dataWidth; - late final int addrWidth; - - Logic get en => port('en'); - Logic get addr => port('addr'); - Logic get data => port('data'); - Logic get done => port('done'); - Logic get valid => port('valid'); - - MmioWriteInterface(int dataWidth, int addrWidth) - : super( - portsFromConsumer: [Logic.port('done'), Logic.port('valid')], - portsFromProvider: [ - Logic.port('en'), - Logic.port('addr', addrWidth), - Logic.port('data', dataWidth), - ], - ) { - this.dataWidth = dataWidth; - this.addrWidth = addrWidth; - } - - @override - MmioWriteInterface clone() => MmioWriteInterface(dataWidth, addrWidth); -} - -class DeviceModule extends BridgeModule { - final Mxlen mxlen; - late final Device config; - final bool? useFields; - final bool resetState; - - late Map _state; - - Logic? get interrupt => - config.interrupts.isNotEmpty ? output('interrupt') : null; - - late final InterfaceReference? mmioRead; - late final InterfaceReference? mmioWrite; - - DeviceModule( - this.mxlen, - Device config, { - this.useFields, - this.resetState = true, - }) : super(config.module, name: config.name) { - this.config = config; - - if (config.clock != null) createPort('clk', PortDirection.input); - createPort('reset', PortDirection.input); - - if (config.interrupts.isNotEmpty) - addOutput('interrupt', width: config.interrupts.length.bitLength); - - for (final port in config.ports) { - createPort( - port.name, - port.isOutput ? PortDirection.output : PortDirection.input, - width: port.width, - ); - } - - if (config.range != null) { - final addrWidth = config.range!.size.bitLength; - - mmioRead = addInterface( - MmioReadInterface(mxlen.size, addrWidth), - name: 'mmioRead', - role: PairRole.provider, - ); - mmioWrite = addInterface( - MmioWriteInterface(mxlen.size, addrWidth), - name: 'mmioWrite', - role: PairRole.consumer, - ); - } else { - mmioRead = null; - mmioWrite = null; - } - - final clk = config.clock != null ? port('clk').port : null; - final reset = port('reset').port; - - _state = initState(); - - final innerReset = this.reset(); - final resetUses = innerReset - .map((r) => r.receivers) - .fold>([], (acc, i) => [...acc, ...i]); - - List doReset = [ - if (config.interrupts.isNotEmpty) interrupt! < 0, - for (final p - in config.ports - .where((p) => p.isOutput) - .where((p) => !resetUses.contains(port(p.name).port))) - port(p.name).port < 0, - if (resetState) - for (final s in _state.values.where((r) => !resetUses.contains(r))) - s < 0, - ...innerReset, - ]; - - List inner = [if (config.clock != null) ...increment()]; - - if (config.range != null) { - doReset.addAll([ - mmioRead!.internalInterface!.data < 0, - mmioRead!.internalInterface!.done < 0, - mmioRead!.internalInterface!.valid < 0, - mmioWrite!.internalInterface!.done < 0, - mmioWrite!.internalInterface!.valid < 0, - ]); - - inner.addAll([ - if (config.interrupts.isNotEmpty) interrupt! < interrupts(), - ...readPort( - mmioRead!.internalInterface!.en, - mmioRead!.internalInterface!.addr, - mmioRead!.internalInterface!.data, - mmioRead!.internalInterface!.done, - mmioRead!.internalInterface!.valid, - ), - ...writePort( - mmioWrite!.internalInterface!.en, - mmioWrite!.internalInterface!.addr, - mmioWrite!.internalInterface!.data, - mmioWrite!.internalInterface!.done, - mmioWrite!.internalInterface!.valid, - ), - ]); - } - - if (config.clock != null) { - assert(clk != null, 'Device requires a clock input'); - - Sequential(clk!, [If(reset, then: doReset, orElse: inner)]); - } else { - Combinational([If(reset, then: doReset, orElse: inner)]); - } - } - - Logic state(String name) => _state[name]!; - - Map initState() => {}; - - List reset() => []; - - List increment() => []; - - Logic interrupts() => Const(0, width: config.interrupts.length.bitLength); - - List readField(String name, Logic data) => [data < 0]; - - List writeField(String name, Logic data) => []; - - List read(Logic addr, Logic data, Logic done, Logic valid) { - if (!(useFields ?? config.accessor != null)) return []; - - final busBytes = data.width ~/ 8; - final busEnd = addr + Const(busBytes, width: addr.width); - - final conds = []; - - final fieldValues = Map.fromEntries( - config.accessor!.fields.values.map( - (field) => MapEntry( - field.name, - Logic(name: 'readField_${field.name}', width: field.width * 8), - ), - ), - ); - - final hitAny = Logic(name: 'mmioReadHit'); - - conds.addAll([data < 0, done < 1, hitAny < 0, valid < 0]); - - for (final field in config.accessor!.fields.values) { - final fieldStart = config.accessor!.fieldAddress(field.name)!; - final fieldBytes = field.width; - final fieldEnd = fieldStart + fieldBytes; - - final overlaps = - Const(fieldStart, width: addr.width).lt(busEnd) & - Const(fieldEnd, width: addr.width).gt(addr); - - final fieldValue = fieldValues[field.name]!; - - conds.add( - If( - overlaps, - then: [ - ...readField(field.name, fieldValue), - - for (var lane = 0; lane < busBytes; lane++) - for (var fb = 0; fb < fieldBytes; fb++) ...[ - If( - (addr + Const(lane, width: addr.width)).eq( - Const(fieldStart + fb, width: addr.width), - ), - then: [ - hitAny < 1, - data < - (data | - (fieldValue - .getRange(fb * 8, (fb + 1) * 8) - .zeroExtend(data.width) << - (lane * 8))), - ], - ), - ], - ], - ), - ); - } - - conds.add(valid < hitAny); - return conds; - } - - List write(Logic addr, Logic data, Logic done, Logic valid) { - if (!(useFields ?? config.accessor != null)) return []; - - final busBytes = data.width ~/ 8; - final busEnd = addr + Const(busBytes, width: addr.width); - - final conds = []; - - final hitAny = Logic(name: 'mmioWriteHit'); - - conds.addAll([done < 1, hitAny < 0, valid < 0]); - - for (final field in config.accessor!.fields.values) { - final fieldStart = config.accessor!.fieldAddress(field.name)!; - final fieldBytes = field.width; - final fieldEnd = fieldStart + fieldBytes; - - final overlaps = - Const(fieldStart, width: addr.width).lt(busEnd) & - Const(fieldEnd, width: addr.width).gt(addr); - - final fieldValue = Logic( - name: 'writeField_${field.name}', - width: fieldBytes * 8, - ); - final fieldHit = Logic(name: 'writeFieldHit_${field.name}'); - - conds.addAll([fieldValue < 0, fieldHit < 0]); - - conds.add( - If( - overlaps, - then: [ - for (var lane = 0; lane < busBytes; lane++) - for (var fb = 0; fb < fieldBytes; fb++) ...[ - If( - (addr + Const(lane, width: addr.width)).eq( - Const(fieldStart + fb, width: addr.width), - ), - then: [ - fieldHit < 1, - hitAny < 1, - fieldValue < - (fieldValue | - (data - .getRange(lane * 8, (lane + 1) * 8) - .zeroExtend(fieldValue.width) << - (fb * 8))), - ], - ), - ], - ], - ), - ); - - conds.add(If(fieldHit, then: [...writeField(field.name, fieldValue)])); - } - - conds.add(valid < hitAny); - return conds; - } - - List readPort( - Logic en, - Logic addr, - Logic data, - Logic done, - Logic valid, - ) => [ - If( - en, - then: read(addr, data, done, valid), - orElse: [data < 0, done < 0, valid < 0], - ), - ]; - - List writePort( - Logic en, - Logic addr, - Logic data, - Logic done, - Logic valid, - ) => [ - If(en, then: write(addr, data, done, valid), orElse: [done < 0, valid < 0]), - ]; -} diff --git a/packages/river_hdl/lib/src/devices.dart b/packages/river_hdl/lib/src/devices.dart deleted file mode 100644 index ef2c560..0000000 --- a/packages/river_hdl/lib/src/devices.dart +++ /dev/null @@ -1,14 +0,0 @@ -import 'devices/flash.dart'; -import 'devices/sram.dart'; -import 'devices/uart.dart'; -import 'dev.dart'; - -export 'devices/flash.dart'; -export 'devices/sram.dart'; -export 'devices/uart.dart'; - -const Map kDeviceModuleFactory = { - 'river,flash': RiverFlashModule.create, - 'river,sram': RiverSramModule.create, - 'river,uart': RiverUartModule.create, -}; diff --git a/packages/river_hdl/lib/src/devices/flash.dart b/packages/river_hdl/lib/src/devices/flash.dart deleted file mode 100644 index cfdec7b..0000000 --- a/packages/river_hdl/lib/src/devices/flash.dart +++ /dev/null @@ -1,28 +0,0 @@ -import 'package:rohd/rohd.dart'; -import 'package:rohd_hcl/rohd_hcl.dart'; -import 'package:riscv/riscv.dart'; -import 'package:river/river.dart'; -import '../dev.dart'; - -class RiverFlashModule extends DeviceModule { - RiverFlashModule(super.mxlen, super.config); - - @override - List read(Logic addr, Logic data, Logic done, Logic valid) => [ - data < 0, - done < 1, - valid < 0, - ]; - - @override - List write(Logic addr, Logic data, Logic done, Logic valid) => [ - done < 1, - valid < 0, - ]; - - static DeviceModule create( - Mxlen mxlen, - Device config, - Map _options, - ) => RiverFlashModule(mxlen, config); -} diff --git a/packages/river_hdl/lib/src/devices/sram.dart b/packages/river_hdl/lib/src/devices/sram.dart deleted file mode 100644 index 64391af..0000000 --- a/packages/river_hdl/lib/src/devices/sram.dart +++ /dev/null @@ -1,326 +0,0 @@ -import 'package:rohd/rohd.dart'; -import 'package:rohd_hcl/rohd_hcl.dart'; -import 'package:riscv/riscv.dart'; -import 'package:river/river.dart'; -import '../dev.dart'; - -const _kSramAddrWidth = {'SB_RAM40_4K': 11}; - -const _kSramDataWidth = {'SB_RAM40_4K': 16}; - -class _RiverSramExternal extends ExternalSystemVerilogModule { - _RiverSramExternal( - String defName, - Logic clk, - Logic reset, - DataPortInterface read, - DataPortInterface write, { - String name = 'external_module', - }) : super(definitionName: defName, name: name) { - final mapping = switch (defName) { - 'SB_RAM40_4K' => const { - 'clk': ['RCLK', 'WCLK'], - 'read.en': ['RE'], - 'read.addr': ['RADDR'], - 'read.data': ['RDATA'], - 'read.done': ['0'], - 'read.valid': ['1'], - 'write.en': ['WE'], - 'write.addr': ['WADDR'], - 'write.data': ['WDATA'], - 'write.done': ['0'], - 'write.valid': ['1'], - }, - _ => throw UnsupportedError('Unknown SRAM block $defName'), - }; - - final inputs = { - 'clk': clk, - 'reset': reset, - 'read.en': read.en, - 'read.addr': read.addr, - 'write.en': write.en, - 'write.addr': write.addr, - 'write.data': write.data, - }; - - final outputs = { - 'read.data': read.data, - 'read.done': read.done, - 'read.valid': read.valid, - 'write.done': write.done, - 'write.valid': write.valid, - }; - - for (final i in inputs.entries) { - if (mapping.containsKey(i.key)) { - for (final n in mapping[i.key]!) { - addInput(n, i.value, width: i.value.width); - } - } - } - - for (final o in outputs.entries) { - if (mapping.containsKey(o.key)) { - for (final n in mapping[o.key]!) { - final c = int.tryParse(n); - if (c != null) { - o.value <= Const(c, width: o.value.width); - } else { - o.value <= addOutput(n, width: o.value.width); - } - } - } - } - } -} - -class _RiverSramArray extends Module { - late final LogicArray _mem; - - _RiverSramArray( - Logic clk, - Logic reset, - DataPortInterface read, - DataPortInterface write, { - super.name = 'array', - }) { - clk = addInput('clk', clk); - reset = addInput('reset', reset); - - read = read.clone() - ..connectIO( - this, - read, - outputTags: {DataPortGroup.data, DataPortGroup.integrity}, - inputTags: {DataPortGroup.control}, - uniquify: (og) => 'read_$og', - ); - - write = write.clone() - ..connectIO( - this, - write, - outputTags: {DataPortGroup.integrity}, - inputTags: {DataPortGroup.control, DataPortGroup.data}, - uniquify: (og) => 'write_$og', - ); - - _mem = LogicArray([1 << read.addrWidth], write.dataWidth, name: 'mem'); - - final int shift = switch (read.dataWidth ~/ 8) { - 4 => 2, - 8 => 3, - _ => throw UnsupportedError('Invalid XLEN=${read.dataWidth}'), - }; - - Sequential(clk, [ - If( - reset, - then: [ - read.data < 0, - read.done < 0, - read.valid < 0, - write.done < 0, - write.valid < 0, - ], - orElse: [ - If( - read.en, - then: [ - read.data < - List.generate( - read.dataWidth, - (i) => _mem[(read.addr + i) >> shift], - ).swizzle(), - read.done < 1, - read.valid < 1, - ], - orElse: [read.data < 0, read.done < 0, read.valid < 0], - ), - If( - write.en, - then: [ - _mem < - (_mem | - (write.data << (write.addr * write.dataWidth)).zeroExtend( - _mem.width, - )), - write.done < 1, - write.valid < 1, - ], - orElse: [write.done < 0, write.valid < 0], - ), - ], - ), - ]); - } -} - -class RiverSramModule extends DeviceModule { - final String? externalName; - - RiverSramModule(Mxlen mxlen, Device config) - : externalName = null, - super(mxlen, config, resetState: false); - RiverSramModule.ext(Mxlen mxlen, Device config, String name) - : externalName = name, - super(mxlen, config, resetState: false); - - @override - Map initState() { - final clk = port('clk').port; - final reset = port('reset').port; - - final busDataWidth = mxlen.size; - final busAddrWidth = (config.mmap!.size ~/ mxlen.width).bitLength + 2; - - final dataWidth = externalName != null - ? _kSramDataWidth[externalName!]! - : busDataWidth; - final addrWidth = externalName != null - ? _kSramAddrWidth[externalName!]! - : busAddrWidth; - - final readPort = DataPortInterface(busDataWidth, busAddrWidth); - final writePort = DataPortInterface(busDataWidth, busAddrWidth); - - if (externalName == null) { - _RiverSramArray(clk, reset, readPort, writePort); - } else { - if (busDataWidth != dataWidth && busAddrWidth != addrWidth) { - final count = (busAddrWidth ~/ addrWidth) > 1 - ? (busAddrWidth ~/ addrWidth) - : busDataWidth ~/ dataWidth; - - final shift = switch (mxlen.width) { - 4 => 2, - 8 => 3, - _ => throw UnsupportedError('Unsupported XLEN=${mxlen.size}'), - }; - - final readAddr = (readPort.addr >> shift).slice(addrWidth - 1, 0); - final writeAddr = (writePort.addr >> shift).slice(addrWidth - 1, 0); - - List reads = []; - List writes = []; - - for (var i = 0; i < count; i++) { - final innerRead = DataPortInterface(dataWidth, addrWidth); - reads.add(innerRead); - - final innerWrite = DataPortInterface(dataWidth, addrWidth); - writes.add(innerWrite); - - innerRead.en <= readPort.en; - innerRead.addr <= readAddr; - - final hi = i * dataWidth; - final lo = (i + 1) * dataWidth - 1; - - innerWrite.en <= writePort.en; - innerWrite.addr <= writeAddr; - innerWrite.data <= writePort.data.slice(hi, lo); - - _RiverSramExternal( - externalName!, - clk, - reset, - innerRead, - innerWrite, - name: 'bank$i', - ); - } - - readPort.data <= reads.map((r) => r.data).toList().swizzle(); - readPort.done <= - reads.map((r) => r.done).fold(Const(1), (acc, i) => acc & i); - readPort.valid <= - reads.map((r) => r.valid).fold(Const(1), (acc, i) => acc & i); - - writePort.done <= - writes.map((w) => w.done).fold(Const(1), (acc, i) => acc & i); - writePort.valid <= - writes.map((w) => w.valid).fold(Const(1), (acc, i) => acc & i); - } else { - _RiverSramExternal(externalName!, clk, reset, readPort, writePort); - } - } - - return { - 'readEnable': readPort.en, - 'readAddr': readPort.addr, - 'readData': readPort.data, - 'readDone': readPort.done, - 'readValid': readPort.valid, - 'writeEnable': writePort.en, - 'writeAddr': writePort.addr, - 'writeData': writePort.data, - 'writeDone': writePort.done, - 'writeValid': writePort.valid, - }; - } - - @override - List reset() => [ - state('readEnable') < 0, - state('readAddr') < 0, - state('writeEnable') < 0, - state('writeAddr') < 0, - state('writeData') < 0, - ]; - - @override - List readPort( - Logic en, - Logic addr, - Logic data, - Logic done, - Logic valid, - ) => [ - state('readEnable') < en, - state('readAddr') < addr, - If( - en, - then: [ - data < state('readData'), - done < state('readDone'), - valid < state('readValid'), - ], - orElse: [ - data < Const(0, width: mxlen.size), - done < 0, - valid < 0, - ], - ), - ]; - - @override - List writePort( - Logic en, - Logic addr, - Logic data, - Logic done, - Logic valid, - ) => [ - state('writeEnable') < en, - state('writeAddr') < addr, - state('writeData') < data, - If( - en, - then: [done < state('writeDone'), valid < state('writeValid')], - orElse: [done < 0, valid < 0], - ), - ]; - - static DeviceModule create( - Mxlen mxlen, - Device config, - Map options, - ) { - if (options.containsKey('definitionName')) { - return RiverSramModule.ext(mxlen, config, options['definitionName']!); - } - return RiverSramModule(mxlen, config); - } -} diff --git a/packages/river_hdl/lib/src/devices/uart.dart b/packages/river_hdl/lib/src/devices/uart.dart deleted file mode 100644 index 05ef358..0000000 --- a/packages/river_hdl/lib/src/devices/uart.dart +++ /dev/null @@ -1,325 +0,0 @@ -import 'package:rohd/rohd.dart'; -import 'package:rohd_hcl/rohd_hcl.dart'; -import 'package:riscv/riscv.dart'; -import 'package:river/river.dart'; -import '../dev.dart'; - -class RiverUartModule extends DeviceModule { - final int rxFifoDepth; - final int txFifoDepth; - - late final Fifo _rxFifo; - late final Fifo _txFifo; - - RiverUartModule( - super.mxlen, - super.config, { - this.rxFifoDepth = 8, - this.txFifoDepth = 8, - }) : super(useFields: true); - - @override - Map initState() { - final clk = port('clk').port; - final reset = port('reset').port; - - final rxWrite = Logic(name: 'rxWrite'); - final rxRead = Logic(name: 'rxRead'); - final rxData = Logic(name: 'rxData', width: 8); - - final txWrite = Logic(name: 'txWrite'); - final txRead = Logic(name: 'txRead'); - final txData = Logic(name: 'txData', width: 8); - - _rxFifo = Fifo( - clk, - reset, - writeEnable: rxWrite, - writeData: rxData, - readEnable: rxRead, - depth: rxFifoDepth, - name: 'rx_fifo', - ); - - _txFifo = Fifo( - clk, - reset, - writeEnable: txWrite, - writeData: txData, - readEnable: txRead, - depth: txFifoDepth, - name: 'tx_fifo', - ); - - return { - 'dll': Logic(width: 8), - 'dlm': Logic(width: 8), - 'ier': Logic(width: 8), - 'iir': Logic(width: 8), - 'lcr': Logic(width: 8), - 'mcr': Logic(width: 8), - 'lsr': Logic(width: 8), - 'msr': Logic(width: 8), - 'scr': Logic(width: 8), - 'fcr': Logic(width: 8), - - 'rxWrite': rxWrite, - 'rxRead': rxRead, - 'rxData': rxData, - - 'txWrite': txWrite, - 'txRead': txRead, - 'txData': txData, - - 'baudCount': Logic(width: 16), - 'baudDiv': Logic(width: 16), - 'baudTick': Logic(), - - 'rxDiv': Logic(width: 16), - 'rxCount': Logic(width: 16), - 'rxTick': Logic(), - - 'txBusy': Logic(), - 'txCount': Logic(width: 4), - 'txShift': Logic(width: 10), - - 'rxBusy': Logic(), - 'rxPhase': Logic(width: 4), - 'rxSample': Logic(width: 4), - 'rxShift': Logic(width: 8), - }; - } - - @override - List reset() => [ - state('iir') < Const(1, width: 8), - state('lsr') < Const(0x60, width: 8), - port('tx').port < 1, - ]; - - @override - List increment() { - final rx = port('rx').port; - final tx = port('tx').port; - - final dlab = state('lcr')[7]; - final div16 = [state('dlm'), state('dll')].swizzle(); - final rxDiv = mux( - div16.lt(Const(16, width: 16)), - Const(1, width: 16), - div16 >> 4, - ); - - return [ - state('rxWrite') < 0, - state('rxRead') < 0, - state('txWrite') < 0, - state('txRead') < 0, - state('baudTick') < 0, - state('rxTick') < 0, - - state('baudDiv') < div16, - If( - state('baudCount').eq(0), - then: [ - state('baudCount') < mux(div16.eq(0), Const(1, width: 16), div16), - state('baudTick') < 1, - ], - orElse: [state('baudCount') < state('baudCount') - 1], - ), - - state('rxDiv') < rxDiv, - If( - state('rxCount').eq(0), - then: [state('rxCount') < rxDiv, state('rxTick') < 1], - orElse: [state('rxCount') < state('rxCount') - 1], - ), - - If( - ~state('txBusy') & ~_txFifo.empty, - then: [ - state('txRead') < 1, - state('txShift') < - [ - Const(0, width: 1), - _txFifo.readData, - Const(1, width: 1), - ].swizzle(), - state('txCount') < 0, - state('txBusy') < 1, - ], - ), - - If( - state('txBusy') & state('baudTick'), - then: [ - tx < state('txShift')[state('txCount')], - state('txCount') < state('txCount') + 1, - If(state('txCount').eq(9), then: [state('txBusy') < 0, tx < 1]), - ], - orElse: [ - If(~state('txBusy'), then: [tx < 1]), - ], - ), - - If( - ~state('rxBusy') & rx.eq(0), - then: [ - state('rxBusy') < 1, - state('rxPhase') < 0, - state('rxSample') < 0, - ], - ), - - If( - state('rxBusy') & state('rxTick'), - then: [ - state('rxSample') < state('rxSample') + 1, - If( - state('rxSample').eq(7), - then: [ - If( - state('rxPhase').eq(0), - then: [ - If( - rx.eq(0), - then: [state('rxPhase') < 1, state('rxShift') < 0], - orElse: [state('rxBusy') < 0], - ), - ], - orElse: [ - If( - state('rxPhase').gte(1) & state('rxPhase').lte(8), - then: [ - state('rxShift') < - (state('rxShift') | - (rx.zeroExtend(8) << (state('rxPhase') - 1))), - state('rxPhase') < state('rxPhase') + 1, - ], - orElse: [ - If( - state('rxPhase').eq(9), - then: [ - If( - rx.eq(1) & ~_rxFifo.full, - then: [ - state('rxWrite') < 1, - state('rxData') < state('rxShift'), - ], - ), - state('rxBusy') < 0, - ], - ), - ], - ), - ], - ), - state('rxSample') < 0, - ], - ), - ], - ), - - state('lsr') < - (Const(0, width: 8) | - mux(~_rxFifo.empty, Const(0x01, width: 8), Const(0, width: 8)) | - mux( - ~_txFifo.empty | state('txBusy'), - Const(0, width: 8), - Const(0x20, width: 8), - ) | - mux( - ~_txFifo.empty | state('txBusy'), - Const(0, width: 8), - Const(0x40, width: 8), - )), - - If( - state('ier')[0] & ~_rxFifo.empty, - then: [state('iir') < Const(0x04, width: 8)], - orElse: [ - If( - state('ier')[1] & ~state('txBusy') & _txFifo.empty, - then: [state('iir') < Const(0x02, width: 8)], - orElse: [state('iir') < Const(0x01, width: 8)], - ), - ], - ), - ]; - } - - @override - Logic interrupts() => - (~state('iir')[0]).zeroExtend(config.interrupts.length.bitLength); - - @override - List readField(String name, Logic data) => switch (name) { - 'rbr_thr_dll' => [ - data < - mux( - state('lcr')[7], - state('dll'), - mux(~_rxFifo.empty, _rxFifo.readData, Const(0, width: 8)), - ), - If(~state('lcr')[7] & ~_rxFifo.empty, then: [state('rxRead') < 1]), - ], - 'ier_dlm' => [data < mux(state('lcr')[7], state('dlm'), state('ier'))], - 'iir_fcr' => [ - data < (state('iir') | (state('fcr') & Const(0xC0, width: 8))), - ], - 'lcr' => [data < state('lcr')], - 'mcr' => [data < state('mcr')], - 'lsr' => [data < state('lsr')], - 'msr' => [data < state('msr')], - 'scr' => [data < state('scr')], - _ => [data < 0], - }; - - @override - List writeField(String name, Logic data) => switch (name) { - 'rbr_thr_dll' => [ - If( - state('lcr')[7], - then: [state('dll') < data], - orElse: [ - If( - ~_txFifo.full, - then: [state('txWrite') < 1, state('txData') < data], - ), - ], - ), - ], - 'ier_dlm' => [ - If( - state('lcr')[7], - then: [state('dlm') < data], - orElse: [state('ier') < data], - ), - ], - 'iir_fcr' => [state('fcr') < data], - 'lcr' => [state('lcr') < data], - 'mcr' => [state('mcr') < data], - 'scr' => [state('scr') < data], - _ => [], - }; - - static DeviceModule create( - Mxlen mxlen, - Device config, - Map options, - ) { - final rxFifoDepth = options.containsKey('rxFifoDepth') - ? int.parse(options['rxFifoDepth']!) - : 8; - final txFifoDepth = options.containsKey('txFifoDepth') - ? int.parse(options['txFifoDepth']!) - : 8; - - return RiverUartModule( - mxlen, - config, - rxFifoDepth: rxFifoDepth, - txFifoDepth: txFifoDepth, - ); - } -} diff --git a/packages/river_hdl/lib/src/genip.dart b/packages/river_hdl/lib/src/genip.dart new file mode 100644 index 0000000..30424d3 --- /dev/null +++ b/packages/river_hdl/lib/src/genip.dart @@ -0,0 +1,2476 @@ +import 'dart:io'; +import 'dart:typed_data'; + +import 'package:rohd/rohd.dart' show Logic, Sequential, Const; +import 'package:river/river.dart'; +import 'package:river_adl/river_adl.dart' as adl; +import 'package:river_maskrom/river_maskrom.dart'; +import 'package:rohd_bridge/rohd_bridge.dart'; + +import 'boards.dart'; +import 'core.dart'; +import 'core/debug_subsystem.dart'; +import 'usb_dfu_subsystem.dart'; + +/// How the USB DFU subsystem is integrated. +enum UsbDfuMode { + /// Hardware RAM-sink integration: a second bus master ([UsbDfuRamSink]) DMAs + /// the downloaded firmware into an on-chip SRAM through a [HarborCdcFifo] and + /// a [RiverWishboneArbiter]. The maskrom polls image_ready and jumps. Heavy. + hardware, + + /// Lean software/CAR integration: only the PHY + [UsbEp0Engine] + a small + /// MMIO slave ([RiverDfuSubsystemSw]). The maskrom reads received bytes over + /// MMIO and stores them into Cache-as-RAM itself. No RAM-sink, no CDC FIFO, + /// no arbiter, no second master, no SRAM region. Light. + software, +} + +/// Structured `key=val,...` params carried by a [Device] spec (e.g. +/// `dram:0x...:arty-s7-x8:ddr3fast=true,clockfreq=200000000`). Every field is +/// nullable: null means "not set", so genip falls back to the board default then +/// a literal default. +class DeviceParams { + // --- DDR controller tuning (`dram` devices) --- + + /// Expose the CPU read-training MMIO window (HarborDdrController.trainableRead). + final bool? trainable; + + /// ddr3Fast command CK edge (0..3), forwarded to the Xilinx PHY. + final int? cmdSlot; + + /// ddr3Fast write-launch window slide (may be negative). + final int? wrShift; + + /// ddr3Fast sub-tick DDR write beat rotation (null derives from CWL). + final int? wrBeat; + + /// Static/initial read tap (the per-DQ read-eye centering knob). + final int? readTap; + + /// Read-capture window slack in cycles. + final int? readSlack; + + /// DRAM read-retry / read-voting depth (0 disables). + final int? readRetry; + + /// ddr3Fast runtime read-window tap reset (reg12 default). + final int? window; + + /// Hardware write-verify-retry on every array write. + final bool? writeVerify; + + /// Diagnostic MR3.MPR mode (every read returns the part MPR pattern). + final bool? mpr; + + /// Real-speed DDR3-667 ISERDESE2 datapath (else the DLL-off IDDR read path). + /// Per controller: two dram devices may differ. + final bool? ddr3Fast; + + /// DRAM clock-domain (CDC) frequency in Hz. Above the oscillator PLLs the + /// `ddr` domain to a higher DLL-off / DLL-on rate than the core drives. + final int? clockFreq; + + /// Separate oscillator (Hz) sourcing the DDR3 clock tree. When set genip mints + /// the top-level `ddr_osc` pin (site via `--pin ddr_osc=`). + final int? oscFreq; + + // --- usb-dfu device --- + + /// DFU integration style: `hardware` (RAM-sink DMA + 2nd master) or `software` + /// (lean MMIO slave, maskrom stores into Cache-as-RAM). + final String? mode; + + // --- flash-firmware device --- + + /// External firmware binary bundled into flash (takes precedence over program). + final String? path; + + /// Built-in firmware program baked into flash (e.g. `hexdump`). + final String? program; + + const DeviceParams({ + this.trainable, + this.cmdSlot, + this.wrShift, + this.wrBeat, + this.readTap, + this.readSlack, + this.readRetry, + this.window, + this.writeVerify, + this.mpr, + this.ddr3Fast, + this.clockFreq, + this.oscFreq, + this.mode, + this.path, + this.program, + }); + + /// Accepted param keys (case-insensitive), for error messages. + static const _keys = [ + 'trainable', + 'cmdslot', + 'wrshift', + 'wrbeat', + 'readtap', + 'readslack', + 'readretry', + 'window', + 'writeverify', + 'mpr', + 'ddr3fast', + 'clockfreq', + 'oscfreq', + 'mode', + 'path', + 'program', + ]; + + static bool _parseBool(String v) { + switch (v.toLowerCase()) { + case 'true': + case '1': + return true; + case 'false': + case '0': + return false; + default: + throw FormatException( + 'Device param bool must be true/false/1/0, got: $v', + ); + } + } + + /// Parses `key=val,key=val,...` into a [DeviceParams]. Keys are + /// case-insensitive. Unknown keys throw. Int values use [int.parse] so + /// negatives (e.g. `wrshift=-1`) work. Split on the FIRST `=`, so a path may + /// contain `=`. + static DeviceParams parse(String s) { + bool? trainable; + int? cmdSlot; + int? wrShift; + int? wrBeat; + int? readTap; + int? readSlack; + int? readRetry; + int? window; + bool? writeVerify; + bool? mpr; + bool? ddr3Fast; + int? clockFreq; + int? oscFreq; + String? mode; + String? path; + String? program; + for (final pair in s.split(',')) { + final eq = pair.indexOf('='); + if (eq < 0) { + throw FormatException('Device param must be key=val, got: $pair'); + } + final key = pair.substring(0, eq).trim().toLowerCase(); + final val = pair.substring(eq + 1).trim(); + switch (key) { + case 'trainable': + trainable = _parseBool(val); + case 'cmdslot': + cmdSlot = int.parse(val); + case 'wrshift': + wrShift = int.parse(val); + case 'wrbeat': + wrBeat = int.parse(val); + case 'readtap': + readTap = int.parse(val); + case 'readslack': + readSlack = int.parse(val); + case 'readretry': + readRetry = int.parse(val); + case 'window': + window = int.parse(val); + case 'writeverify': + writeVerify = _parseBool(val); + case 'mpr': + mpr = _parseBool(val); + case 'ddr3fast': + ddr3Fast = _parseBool(val); + case 'clockfreq': + clockFreq = int.parse(val); + case 'oscfreq': + oscFreq = int.parse(val); + case 'mode': + if (val != 'hardware' && val != 'software') { + throw FormatException( + 'Device param mode must be hardware/software, got: $val', + ); + } + mode = val; + case 'path': + path = val; + case 'program': + program = val; + default: + throw FormatException( + 'Unknown device param "$key"; accepted: ${_keys.join(', ')}', + ); + } + } + return DeviceParams( + trainable: trainable, + cmdSlot: cmdSlot, + wrShift: wrShift, + wrBeat: wrBeat, + readTap: readTap, + readSlack: readSlack, + readRetry: readRetry, + window: window, + writeVerify: writeVerify, + mpr: mpr, + ddr3Fast: ddr3Fast, + clockFreq: clockFreq, + oscFreq: oscFreq, + mode: mode, + path: path, + program: program, + ); + } +} + +/// Deprecated alias, retained while [MemoryRegion.ddrParams] still uses this name. +typedef DdrRegionParams = DeviceParams; + +class MemoryRegion { + final int address; + final int size; + final String type; + + /// Board name for off-chip memory (`dram` regions): selects the DDR part + /// configuration and pad constraint table from [DdrBoard.byName]. + final String? board; + + /// Per-region DDR tuning knobs (`dram` regions only). Null when the spec + /// carried no params field. Each set field overrides the board default. + final DdrRegionParams? ddrParams; + + const MemoryRegion({ + required this.address, + required this.size, + required this.type, + this.board, + this.ddrParams, + }); + + static MemoryRegion parse(String spec) { + final parts = spec.split(':'); + if (parts.length < 3 || parts.length > 5) { + throw FormatException( + 'Memory format: addr:size:type[:board][:key=val,...], got: $spec', + ); + } + // parts[3..] may carry a board name (no '=') and/or a params field (has + // '='), in either combination up to two extra fields. + String? board; + DdrRegionParams? ddrParams; + for (final extra in parts.skip(3)) { + if (extra.contains('=')) { + ddrParams = DdrRegionParams.parse(extra); + } else { + board = extra; + } + } + final region = MemoryRegion( + address: int.parse(parts[0]), + size: _parseSize(parts[1]), + type: parts[2], + board: board, + ddrParams: ddrParams, + ); + if (region.type == 'dram' && region.board != null) { + final board = DdrBoard.byName[region.board]; + if (board == null) { + throw ArgumentError( + 'Unknown dram board "${region.board}"; ' + 'known: ${DdrBoard.byName.keys.join(', ')}', + ); + } + if (board.config.size != region.size) { + throw ArgumentError( + 'dram size ${region.size} does not match the ${region.board} ' + 'part (${board.config.size} bytes)', + ); + } + } + return region; + } + + /// The DDR board definition, when this is a board-qualified `dram` region. + /// Board-less `dram` keeps the legacy on-chip placeholder. + DdrBoard? get ddrBoard => type == 'dram' ? DdrBoard.byName[board] : null; + + /// The flash board definition, when this is a board-qualified `flash` region. + FlashBoard? get flashBoard => + type == 'flash' && board != null ? FlashBoard.byName[board] : null; +} + +class DeviceEntry { + final String name; + final String type; + final int address; + final String? compatible; + + const DeviceEntry({ + required this.name, + required this.type, + required this.address, + this.compatible, + }); + + /// Parses `[name=]type:addr[:compat]`. + /// + /// Examples: + /// - `uart:0x10000000`, name defaults to type + /// - `myuart=uart:0x10000000:ns16550a`, explicit name + static DeviceEntry parse(String spec) { + String? name; + var rest = spec; + final eq = spec.indexOf('='); + if (eq > 0 && spec.indexOf(':') > eq) { + name = spec.substring(0, eq); + rest = spec.substring(eq + 1); + } + final parts = rest.split(':'); + if (parts.length < 2) { + throw FormatException( + 'Device format: [name=]type:addr[:compat], got: $spec', + ); + } + return DeviceEntry( + name: name ?? parts[0], + type: parts[0], + address: int.parse(parts[1]), + compatible: parts.length > 2 ? parts[2] : null, + ); + } + + static const _defaultCompat = { + 'uart': 'ns16550a', + 'clint': 'riscv,clint0', + 'plic': 'riscv,plic0', + 'sram': 'river,sram', + 'flash': 'river,flash', + 'psram': 'river,psram', + 'dram': 'river,dram', + 'gpio': 'river,gpio', + }; + + static const _defaultSizes = { + 'clint': 0x10000, + 'plic': 0x4000000, + 'uart': 0x1000, + 'gpio': 0x1000, + }; + + String get effectiveCompat => + compatible ?? _defaultCompat[type] ?? 'river,$type'; + int get effectiveSize => _defaultSizes[type] ?? 0x1000; +} + +/// A unified addressed thing in the SoC, replacing the old separate +/// [MemoryRegion] and [DeviceEntry]. One of: +/// - a sized memory-backed region (`sram`/`flash`/`dram`): needs addr + size, +/// may carry a `board` and (dram) tuning params. +/// - a fixed-function MMIO peripheral (`uart`/`clint`/`plic`/`gpio`): needs an +/// addr, size defaults from the peripheral class. +/// - a pseudo-device that drives an integration (`usb-dfu`, `debug-jtag`, +/// `flash-firmware`): `buildSoC` detects these and wires the subsystem. +class Device { + final String name; + final String type; + + /// Bus base address. Null for addressless devices (`debug-jtag`). For + /// `flash-firmware` this is the flash byte offset, not an absolute address. + final int? address; + + /// Address-window size. Null uses the type's class default (fixed + /// peripherals). Required for the memory-backed types. + final int? size; + + /// Board name (`dram`/`flash`): selects the DdrBoard/FlashBoard config + pads. + final String? board; + + /// Devicetree `compatible` override (currently inert, kept for the + /// `uart:addr:compat` back-compat form). + final String? compatible; + + /// Trailing `key=val,...` tuning params. + final DeviceParams? params; + + const Device({ + required this.name, + required this.type, + this.address, + this.size, + this.board, + this.compatible, + this.params, + }); + + /// Memory-backed types: they require a user-chosen size and address. + static const _memBacked = {'sram', 'flash', 'psram', 'dram'}; + + /// Class-default window sizes for fixed MMIO peripherals. + static const _defaultSizes = { + 'clint': 0x10000, + 'plic': 0x4000000, + 'uart': 0x1000, + 'gpio': 0x1000, + 'usb-dfu': 0x1000, + }; + + static final _numberRe = RegExp(r'^0[xX][0-9a-fA-F]+$|^[0-9]+$'); + + static bool _looksLikeSize(String s) { + final u = s.toUpperCase(); + return (u.endsWith('K') || u.endsWith('M') || u.endsWith('G')) && + _numberRe.hasMatch(u.substring(0, u.length - 1)); + } + + /// Parses `[name=]type[:addr][:size][:board|compat][:key=val,...]`. + /// + /// The colon parts after the type are classified by shape, not position. + /// A `key=val` blob is params. A size-suffixed number is size. A bare number + /// is address (first) then size. A known board name is board. Anything else + /// is compatible. Examples: + /// - `uart:0x10000000:ns16550a` (addr + compat, the legacy device form) + /// - `sram:0x08000000:64K` (addr + size, a legacy memory region) + /// - `dram:0x80000000:128M:arty-s7-x8:ddr3fast=true` (addr+size+board+params) + /// - `debug-jtag` (type only, addressless) + /// - `usb-dfu:0x0C000000:mode=software` + /// - `flash-firmware:0x100000:path=weir.bin` (addr field is the flash offset) + static Device parse(String spec) { + String? name; + var rest = spec; + final eq = spec.indexOf('='); + final colon = spec.indexOf(':'); + // `name=` prefix only when the first '=' precedes the first ':'. A later + // '=' belongs to a params blob (`type:...:key=val`). + if (eq > 0 && (colon < 0 || colon > eq)) { + name = spec.substring(0, eq); + rest = spec.substring(eq + 1); + } + final parts = rest.split(':'); + final type = parts[0]; + int? address; + int? size; + String? board; + String? compatible; + DeviceParams? params; + for (final tok in parts.skip(1)) { + if (tok.contains('=')) { + params = DeviceParams.parse(tok); + } else if (_looksLikeSize(tok)) { + size = _parseSize(tok); + } else if (_numberRe.hasMatch(tok)) { + if (address == null) { + address = int.parse(tok); + } else { + size ??= _parseSize(tok); + } + } else if (type == 'dram' || type == 'flash') { + // A plain word on a board-qualified region is the board name. An unknown + // one is caught by _validate rather than silently becoming compat. + board = tok; + } else { + compatible = tok; + } + } + final dev = Device( + name: name ?? type, + type: type, + address: address, + size: size, + board: board, + compatible: compatible, + params: params, + ); + _validate(dev, spec); + return dev; + } + + static void _validate(Device d, String spec) { + if (_memBacked.contains(d.type)) { + if (d.address == null || d.size == null) { + throw FormatException( + 'Device "${d.type}" needs an address and size ' + '(type:addr:size[:board][:key=val,...]), got: $spec', + ); + } + } + if (d.type == 'dram' && d.board != null) { + final b = DdrBoard.byName[d.board]; + if (b == null) { + throw ArgumentError( + 'Unknown dram board "${d.board}"; ' + 'known: ${DdrBoard.byName.keys.join(', ')}', + ); + } + if (b.config.size != d.size) { + throw ArgumentError( + 'dram size ${d.size} does not match the ${d.board} ' + 'part (${b.config.size} bytes)', + ); + } + } + } + + /// The DDR board definition, when this is a board-qualified `dram` device. + DdrBoard? get ddrBoard => type == 'dram' ? DdrBoard.byName[board] : null; + + /// The flash board definition, when this is a board-qualified `flash` device. + FlashBoard? get flashBoard => + type == 'flash' && board != null ? FlashBoard.byName[board] : null; + + /// The bus window size: the explicit [size] or the peripheral class default. + int get effectiveSize => size ?? _defaultSizes[type] ?? 0x1000; + + /// True when this device is a sized, memory-backed region (`sram`/`flash`/ + /// `dram`) rather than an MMIO peripheral or a pseudo-device. + bool get isMemoryBacked => _memBacked.contains(type); +} + +/// Target for RTL generation, either FPGA or ASIC. +/// +/// FPGA format: `ecp5:lfe5u-45f:CABGA381` or `ice40:up5k:sg48` +/// ASIC format: `sky130:hd` or `gf180mcu:3v3` +// TODO: replace with the harbor target class +sealed class Target { + const Target(); + + static Target parse(String spec) { + final parts = spec.split(':'); + if (parts.length < 2) { + throw FormatException( + 'Target format: vendor:device[:package], got: $spec', + ); + } + switch (parts[0]) { + case 'ecp5': + case 'ice40': + case 'spartan7': + if (parts.length != 3) { + throw FormatException( + 'FPGA target format: vendor:device:package, got: $spec', + ); + } + return FpgaTarget( + vendor: parts[0], + device: parts[1], + package: parts[2], + ); + case 'sky130': + return AsicTarget( + pdk: 'sky130', + variant: parts.length > 1 ? parts[1] : 'hd', + ); + case 'gf180mcu': + return AsicTarget( + pdk: 'gf180mcu', + variant: parts.length > 1 ? parts[1] : '3v3', + ); + default: + throw UnsupportedError('Unknown target vendor: ${parts[0]}'); + } + } + + HarborDeviceTarget toHarborTarget({ + required String topCell, + required int frequency, + Map pins = const {}, + Map extraConstraints = const {}, + String? pdkRoot, + }); +} + +// TODO: replace with the harbor target class +class FpgaTarget extends Target { + final String vendor; + final String device; + final String package; + + const FpgaTarget({ + required this.vendor, + required this.device, + required this.package, + }); + + @override + HarborDeviceTarget toHarborTarget({ + required String topCell, + required int frequency, + Map pins = const {}, + Map extraConstraints = const {}, + String? pdkRoot, + }) { + switch (vendor) { + case 'ecp5': + return HarborFpgaTarget.ecp5( + device: device, + package: package, + frequency: frequency, + pinMap: pins, + extraConstraints: extraConstraints, + ); + case 'ice40': + return HarborFpgaTarget.ice40( + device: device, + package: package, + frequency: frequency, + pinMap: pins, + extraConstraints: extraConstraints, + ); + case 'spartan7': + // Xilinx Spartan-7 via the open-source openXC7 flow (yosys + // synth_xilinx + nextpnr-xilinx + prjxray), the only Xilinx flow that + // runs natively on this aarch64 box (x86 Vivado/qemu is unavailable). + return HarborFpgaTarget.spartan7( + device: device, + package: package, + frequency: frequency, + pinMap: pins, + extraConstraints: extraConstraints, + useOpenXc7: true, + ); + default: + throw UnsupportedError('Unknown FPGA vendor: $vendor'); + } + } +} + +// TODO: replace with the harbor target class +class AsicTarget extends Target { + final String pdk; + final String variant; + + const AsicTarget({required this.pdk, required this.variant}); + + PdkProvider _createProvider(String pdkRoot) { + switch (pdk) { + case 'sky130': + final sky130Variant = + { + 'hd': Sky130Variant.hd, + 'hs': Sky130Variant.hs, + 'ms': Sky130Variant.ms, + 'ls': Sky130Variant.ls, + 'lp': Sky130Variant.lp, + 'hdll': Sky130Variant.hdll, + }[variant] ?? + Sky130Variant.hd; + return Sky130Provider(pdkRoot: pdkRoot, variant: sky130Variant); + case 'gf180mcu': + final voltage = variant == '5v0' + ? Gf180mcuVoltage.v5_0 + : Gf180mcuVoltage.v3_3; + return Gf180mcuProvider(pdkRoot: pdkRoot, voltage: voltage); + default: + throw UnsupportedError('Unknown PDK: $pdk'); + } + } + + @override + HarborDeviceTarget toHarborTarget({ + required String topCell, + required int frequency, + Map pins = const {}, + Map extraConstraints = const {}, + String? pdkRoot, + }) { + if (pdkRoot == null) { + throw ArgumentError('ASIC target requires --pdk-root'); + } + return HarborAsicTarget( + provider: _createProvider(pdkRoot), + topCell: topCell, + frequency: frequency, + ); + } +} + +/// Pin assignment: maps an external signal name to a device port and FPGA pin. +/// +/// Format: `external_name=device@port:fpga_pin` +/// +/// Example: `--pin uart_tx=uart@tx:B6` +class PinAssignment { + /// External signal name (used in constraint file and SoC top-level port). + final String externalName; + + /// Device name (as given in --device). + final String deviceName; + + /// Port name on the device. + final String portName; + + /// FPGA physical pin (e.g., `B6`, `A9`). + final String fpgaPin; + + const PinAssignment({ + required this.externalName, + required this.deviceName, + required this.portName, + required this.fpgaPin, + }); + + /// Parses `external_name=device@port:fpga_pin`. + static PinAssignment parse(String spec) { + final eq = spec.indexOf('='); + if (eq < 0) { + throw FormatException('Pin format: name=device@port:pin, got: $spec'); + } + final externalName = spec.substring(0, eq); + final rest = spec.substring(eq + 1); + + final at = rest.indexOf('@'); + if (at < 0) { + // Simple format: name=pin (for clk, etc.) + return PinAssignment( + externalName: externalName, + deviceName: '', + portName: '', + fpgaPin: rest, + ); + } + + final deviceName = rest.substring(0, at); + final afterAt = rest.substring(at + 1); + final colon = afterAt.indexOf(':'); + if (colon < 0) { + throw FormatException('Pin format: name=device@port:pin, got: $spec'); + } + return PinAssignment( + externalName: externalName, + deviceName: deviceName, + portName: afterAt.substring(0, colon), + fpgaPin: afterAt.substring(colon + 1), + ); + } + + bool get isDevicePin => deviceName.isNotEmpty; +} + +class RiverGenIpConfig { + final String name; + final List cores; + final String interconnect; + final int clockFrequency; + final int oscFrequency; + + /// The unified `--device` list: every addressed thing in the SoC (memory-backed + /// regions, MMIO peripherals, and the usb-dfu/debug-jtag/flash-firmware + /// pseudo-devices). [memories] and [mmioDevices] are typed views over this. + final List devices; + final Target? target; + + /// Optional board name (`--board arty-s7-50`): pulls the FPGA target identity + /// (when [target] is unset) and the board's standard pin catalog (clk/uart/...) + /// from the Harbor [HarborBoard.byName] registry, so a build need not hand-enter + /// the target and boilerplate `--pin`s. Explicit `--pin` still overrides. + final String? boardName; + + final List pins; + final String? maskromPath; + final String? pdkRoot; + + /// Bakes a built-in boot program directly into an on-chip boot ROM at + /// [bootRomBase] and boots from it. This is the "skip cache-as-RAM" path + /// for SRAM-class systems: the program runs straight from the boot ROM and + /// uses the data RAM directly, with no copy/training bootstrap. + /// + /// Programs: `hello` ([RiverHelloWorld] bring-up smoke test), `monitor` + /// ([RiverSerialMonitor], loads payloads into RAM over the UART), and + /// `hexdump` ([RiverFlashHexdump], dumps two flash windows over the UART + /// straight from ROM, a SILENT-bring-up probe with no flash/maskrom + /// dependency). + final String? bootProgram; + + /// When false, restrict the core to bare (no-paging) mode (machine-mode + /// bring-up). Defaults to the full-MMU build. + final bool enableMmu; + + /// Address of the on-chip boot ROM (maskrom / boot demo). + static const int bootRomBase = 0x00010000; + + /// Diagnostic: the baked `ddrtest` writes/reads ONLY the first DRAM word + /// (isolates a broken read path from BL8-line DM-mask clobber). + final bool ddrSingleWord; + + const RiverGenIpConfig({ + required this.name, + required this.cores, + this.interconnect = 'wishbone', + this.clockFrequency = 48000000, + this.oscFrequency = 12000000, + this.devices = const [], + this.target, + this.boardName, + this.pins = const [], + this.maskromPath, + this.pdkRoot, + this.bootProgram, + this.enableMmu = true, + this.ddrSingleWord = false, + }); + + // --- Typed views over the unified [devices] list --- + + /// Types that are not addPeripheral MMIO slaves: the memory-backed regions and + /// the pseudo-devices that drive a subsystem integration instead. + static const _pseudoTypes = {'usb-dfu', 'debug-jtag', 'flash-firmware'}; + + /// The memory-backed regions (`sram`/`flash`/`dram`), preserving `--device` + /// order, as [MemoryRegion] value objects so the memory build loop and the + /// region getters read them unchanged. + List get memories => [ + for (final d in devices) + if (d.isMemoryBacked) + MemoryRegion( + address: d.address!, + size: d.size!, + type: d.type, + board: d.board, + ddrParams: d.params, + ), + ]; + + /// The fixed-function MMIO peripherals (`uart`/`clint`/`plic`/`gpio`/...): every + /// device that is neither memory-backed nor a pseudo-device. This is what the + /// peripheral loop, PLIC source count, and pin binding iterate. + List get mmioDevices => [ + for (final d in devices) + if (!d.isMemoryBacked && !_pseudoTypes.contains(d.type)) + DeviceEntry( + name: d.name, + type: d.type, + address: d.address!, + compatible: d.compatible, + ), + ]; + + Device? _firstDeviceOfType(String type) { + for (final d in devices) { + if (d.type == type) return d; + } + return null; + } + + // --- usb-dfu (derived from a `usb-dfu` device) --- + + /// True when a `usb-dfu` device is present: integrate the USB DFU subsystem. + bool get usbDfu => _firstDeviceOfType('usb-dfu') != null; + + /// DFU integration style, from the `usb-dfu` device's `mode` param (default + /// [UsbDfuMode.hardware], the heavy RAM-sink path). + UsbDfuMode get usbDfuMode => + _firstDeviceOfType('usb-dfu')?.params?.mode == 'software' + ? UsbDfuMode.software + : UsbDfuMode.hardware; + + /// MMIO base of the DFU status/control block: the `usb-dfu` device address, or + /// the default free window clear of flash/clint/plic/uart/sram. + int get dfuStatusBase => _firstDeviceOfType('usb-dfu')?.address ?? 0x0C000000; + + /// CONTROL register (write 1 -> usb_enable). Word offset 1. + int get dfuControlAddr => dfuStatusBase + 0x04; + + /// STATUS register (bit0 = image_ready). Word offset 0. + int get dfuStatusAddr => dfuStatusBase + 0x00; + + /// ENTRY register (RAM entry address). Word offset 2. + int get dfuEntryAddr => dfuStatusBase + 0x08; + + /// RXDATA register (captured download byte) in [UsbDfuMode.software]. + int get dfuRxDataAddr => dfuStatusBase + 0x08; + + // --- debug-jtag (derived from a `debug-jtag` device) --- + + /// True when a `debug-jtag` device is present: wire the JTAG debug subsystem + /// (TAP+DTM+DM+SBA) as a second fabric master and build the core with debug. + bool get enableDebug => _firstDeviceOfType('debug-jtag') != null; + + // --- flash-firmware (derived from a `flash-firmware` device) --- + + /// Built-in firmware program baked into flash (the device `program` param). + String? get flashFirmware => + _firstDeviceOfType('flash-firmware')?.params?.program; + + /// External firmware binary bundled into flash (the device `path` param). Takes + /// precedence over [flashFirmware]. + String? get flashFirmwarePath => + _firstDeviceOfType('flash-firmware')?.params?.path; + + /// Byte offset into the SPI flash where the bundled firmware lives (the + /// `flash-firmware` device address). Default 1 MiB, clear of the bitstream. + int get flashFirmwareOffset => + _firstDeviceOfType('flash-firmware')?.address ?? 0x100000; + + // --- DDR clock/datapath (derived from the `dram` devices) --- + // Whole-SoC aggregates: the single-controller RTL stays byte-identical to the + // old global flags. + + /// True when ANY `dram` device selects the ISERDESE2 datapath. + bool get ddr3Fast => + devices.any((d) => d.type == 'dram' && (d.params?.ddr3Fast ?? false)); + + /// DRAM clock-domain (CDC) frequency: the first `dram` device that sets one. + int? get ddrClockFrequency { + for (final d in devices) { + if (d.type == 'dram' && d.params?.clockFreq != null) { + return d.params!.clockFreq; + } + } + return null; + } + + /// Separate DDR3 oscillator (mints the shared `ddr_osc` pin): the first `dram` + /// device that sets one. + int? get ddrOscFrequency { + for (final d in devices) { + if (d.type == 'dram' && d.params?.oscFreq != null) { + return d.params!.oscFreq; + } + } + return null; + } + + /// The clock-tree params (`ddr3fast`/`clockfreq`/`oscfreq`) mint ONE shared + /// `ddr_osc` pin and one DDR3 MMCM tree, so every `dram` controller shares them. + /// Two disagreeing `dram` devices would silently get the first one's clock, so + /// throw instead. Per-region data-eye tuning (cmdslot/wrshift/readtap/trainable) + /// may still differ. Independent per-controller trees are future work. + void _validateDdrClockAgreement() { + final drams = [ + for (final d in devices) + if (d.type == 'dram') d, + ]; + if (drams.length < 2) return; + bool differ(T Function(Device) sel) => drams.map(sel).toSet().length > 1; + if (differ((d) => d.params?.ddr3Fast ?? false) || + differ((d) => d.params?.clockFreq) || + differ((d) => d.params?.oscFreq)) { + throw ArgumentError( + 'Multiple dram devices must agree on the shared-clock-tree params ' + '(ddr3fast/clockfreq/oscfreq): they mint one shared ddr_osc pin and one ' + 'DDR3 clock tree. Per-controller data-eye tuning (cmdslot/wrshift/readtap/' + 'trainable/readretry/window/etc) may still differ; independent ' + 'per-controller clock trees are not yet supported.', + ); + } + } + + /// The first `flash` memory region (the SPI NOR XIP window), or null. + MemoryRegion? get flashRegion { + for (final mem in memories) { + if (mem.type == 'flash') return mem; + } + return null; + } + + /// The first `sram` region (the bundled-firmware copy target), or null. + MemoryRegion? get sramRegion => dfuRamRegion; + + /// The SRAM region the DFU image is downloaded into (= the RAM-sink loadBase + /// and the maskrom jump target). Picks the first `sram` region. + MemoryRegion? get dfuRamRegion { + for (final mem in memories) { + if (mem.type == 'sram') return mem; + } + return null; + } + + static const _coreModels = { + 'rc1-n': RiverCoreConfigV1.nano, + 'rc1-mi': RiverCoreConfigV1.micro, + 'rc1-s': RiverCoreConfigV1.small, + 'rc1-m': RiverCoreConfigV1.macro, + }; + + RiscVMxlen get mxlen { + final primaryCore = cores.first; + switch (primaryCore) { + case 'rc1-n': + case 'rc1-mi': + return RiscVMxlen.rv32; + default: + return RiscVMxlen.rv64; + } + } + + RiverCoreConfig buildCoreConfig( + HarborClockConfig clock, + String coreModel, { + int hartId = 0, + }) { + // When [enableMmu] is false, restrict the core to bare (no-paging) mode so + // `HarborMmuConfig.hasPaging` is false: the core/MMU gate off the entire + // Sv39 page-table-walk datapath + satp/SUM/MXR hookups, leaving only the + // bare bus arbiter. Used for machine-mode bring-up bitstreams. + final pagingOn = enableMmu && mxlen == RiscVMxlen.rv64; + final mmu = HarborMmuConfig( + mxlen: mxlen, + pagingModes: pagingOn + ? const [RiscVPagingMode.bare, RiscVPagingMode.sv39] + : const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + hasSupervisorUserMemory: pagingOn, + hasMakeExecutableReadable: pagingOn, + ); + + final factory = _coreModels[coreModel]; + if (factory == null) { + throw UnsupportedError('Unknown core model: $coreModel'); + } + + return factory( + hartId: hartId, + mmu: mmu, + interrupts: [], + clock: clock, + resetVector: + (maskromPath != null || + bootProgram != null || + usbDfu || + flashFirmware != null || + flashFirmwarePath != null) + ? bootRomBase + : (memories.isNotEmpty ? memories.first.address : 0), + ); + } + + WishboneConfig buildBusConfig() => WishboneConfig( + addressWidth: mxlen.size, + dataWidth: mxlen.size, + selWidth: mxlen.size ~/ 8, + ); + + /// The resolved Harbor board, when `--board` names one. + HarborBoard? get board => + boardName != null ? HarborBoard.get(boardName!) : null; + + /// The effective FPGA/ASIC target: the explicit `--target`, else one + /// synthesised from the `--board` identity (so the board can stand in for + /// `--target`). The synthesised target routes through the same [FpgaTarget] + /// path as `--target`, so the generated RTL is identical. + Target? get effectiveTarget { + if (target != null) return target; + final b = board; + if (b == null) return null; + final vendor = switch (b.vendor) { + HarborFpgaVendor.ice40 => 'ice40', + HarborFpgaVendor.ecp5 => 'ecp5', + HarborFpgaVendor.vivado => 'spartan7', + HarborFpgaVendor.openXc7 => 'spartan7', + }; + return FpgaTarget(vendor: vendor, device: b.device, package: b.package); + } + + /// A board catalog entry turned into a [PinAssignment]. A key shaped like + /// `_` whose `` matches an MMIO device binds to that + /// device port (like `--pin uart_tx=uart@tx:`). Anything else is a simple + /// pin (constraint only, e.g. `clk`, `ddr_osc`). The value is the catalog + /// `"SITE [IO_TYPE] [ATTR]"` string. + PinAssignment _boardPinAssignment(String signal, String site) { + final us = signal.indexOf('_'); + if (us > 0) { + final devName = signal.substring(0, us); + final port = signal.substring(us + 1); + if (mmioDevices.any((d) => d.name == devName)) { + return PinAssignment( + externalName: signal, + deviceName: devName, + portName: port, + fpgaPin: site, + ); + } + } + return PinAssignment( + externalName: signal, + deviceName: '', + portName: '', + fpgaPin: site, + ); + } + + /// The user `--pin` assignments plus the board catalog pins for any signal the + /// user did not already assign (explicit `--pin` wins). Board device-convention + /// entries become device bindings, the rest are simple constraint pins. + List get effectivePins { + final b = board; + if (b == null) return pins; + final userNames = {for (final p in pins) p.externalName}; + return [ + for (final e in b.pins.entries) + if (!userNames.contains(e.key)) _boardPinAssignment(e.key, e.value), + ...pins, + ]; + } + + Map get fpgaPinMap => { + for (final p in effectivePins) p.externalName: p.fpgaPin, + // Board-qualified dram/flash regions bring their whole pad constraint table. + // DQS constraints are DLL-aware ([DdrBoard.pinsFor]). DLL-ON: the single + // SSTL135D_I diff pad (nextpnr derives _n). DLL-OFF: the explicit + // pseudo-differential pair (sdram_dqs[*] SSTL135_I + sdram_dqs_n[*]), matching + // the complement ODDR the PHY drives. dllOn = DDR CK rate > ~60 MHz. + for (final mem in memories) + if (mem.ddrBoard != null) + ...mem.ddrBoard!.pinsFor( + dllOn: + (ddrClockFrequency != null && ddrClockFrequency! > oscFrequency) + ? ddrClockFrequency! > 60000000 + : oscFrequency > 60000000, + ), + for (final mem in memories) + if (mem.flashBoard != null) ...mem.flashBoard!.pins, + }; + + HarborDeviceTarget? buildTarget() => effectiveTarget?.toHarborTarget( + topCell: name, + // The `clk` pin is the external oscillator, so its LPF FREQUENCY constraint + // must be the oscillator frequency, NOT the post-PLL system frequency. A wrong + // input frequency makes nextpnr derive the PLL VCO for the wrong band (e.g. + // 24 MHz in -> VCO 300 MHz, out of range), so the PLL never locks and the + // silicon stays in reset. + frequency: oscFrequency, + pins: fpgaPinMap, + extraConstraints: _ddrClockBelConstraints, + pdkRoot: pdkRoot, + ); + + /// openXC7 clock-BEL placement constraints for the ddr3Fast DDR3 PHY. + /// + /// All DDR clocks (CK / CLKDIV / idelayref / ck90) ride plain GLOBAL BUFGs and + /// the read ISERDESE2 CLK shares the CK BUFG net, with zero regional BUFH/BUFHCE + /// (matching the HW-verified UberDDR3 oracle). A global BUFG reaches any region's + /// HCLK leaf, so there is no region to mis-bind, so NO constraints are emitted. + Map get _ddrClockBelConstraints => const {}; + + /// Builds the bundled flash firmware image for the primary core, for emitting + /// as a standalone `firmware.bin` (flashed at [flashFirmwareOffset]). + Future buildFlashFirmwareImage() async { + final coreClock = HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(clockFrequency), + ); + final primaryConfig = buildCoreConfig(coreClock, cores.first); + return buildFlashFirmware(primaryConfig); + } + + Future buildSoC() async { + _validateDdrClockAgreement(); + // Single-oscillator Xilinx DDR3-fast (e.g. the Arty S7, one 100 MHz R2 osc): + // a second MMCM on the raw clock pin cannot share the pin's one dedicated + // clock-capable route on openXC7, so the core MMCM never clocks and the core + // never leaves reset. Fold the core clock onto a spare CLKOUT of the DDR3 + // MMCM instead (one MMCM on the pin). A separate `ddr_osc` pin has no + // contention and keeps its own core MMCM. + final useDdr3TreeCoreClk = ddr3Fast && ddrOscFrequency == null; + final xilinxDdr3Tree = useDdr3TreeCoreClk + ? XilinxDdr3TreeSpec( + sourceHz: oscFrequency, + ddrCkHz: ddrClockFrequency ?? 333333333, + coreClkHz: clockFrequency, + dqsPhaseDeg: 180.0, + ) + : null; + final coreClock = HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(clockFrequency), + ); + + final coreConfigs = cores.indexed + .map((e) => buildCoreConfig(coreClock, e.$2, hartId: e.$1)) + .toList(); + final busConfig = buildBusConfig(); + final target = buildTarget(); + + // The clk90 DDR controller (DLL-off, CK = system clock) shares the single SoC + // clock domain: no separate DRAM clock, CDC bridge, or train-control MMIO. The + // matching GenIpConfig knobs are retained as accepted-but-ignored no-ops. + + // A board-backed DRAM region runs its DQS PHY on the `ddr` clock domain while + // the core/fabric runs on the divided `sys` clock. The `ddr` domain is the raw + // osc (48 MHz CK, DLL-off) by default, or a PLL output at --ddr-clock-freq + // (e.g. 144 MHz CK, DLL-on) when set above the osc. The controller bridges its + // slow `bus` face with an internal HarborWishboneCdcBridge (asyncClock). The + // PHY halves `ddr_clk` to the sclk fabric the DQS x2 datapath runs on. + final hasDdrBoard = memories.any((m) => m.ddrBoard != null); + // ddr3Fast provides its OWN clocking (the DDR3 MMCM tree built inline below), + // so it does NOT use the ECP5-style shared `ddr`/`sys` PLL domain. The core + // rides a standalone `sys` domain and the DDR controller runs on the tree's + // ctrl83 (asyncClock), so the ECP5 DDR clock plumbing is gated off here. + final ecp5DdrDomain = hasDdrBoard && !ddr3Fast; + + final soc = HarborSoC( + name: name, + compatible: 'midstall,${name.replaceAll('_', '-')}', + busConfig: busConfig, + acpiOemId: 'MIDSTL', + acpiOemTableId: 'RIVER', + cpus: coreConfigs + .map( + (coreConfig) => HarborCpu( + hartId: coreConfig.hartId, + isa: coreConfig.isa.implementsString, + clockFrequency: clockFrequency, + // The CLINT ticks mtime once per bus clock, so the timer's + // timebase equals the SoC clock. + timebaseFrequency: clockFrequency, + mmu: coreConfig.mmu.hasPaging ? 'riscv,sv39' : null, + ), + ) + .toList(), + target: target, + xilinxDdr3Tree: xilinxDdr3Tree, + clocks: [ + // System/bus domain: PLL from the osc down to the core clock. This is + // [defaultClock], so every master/peripheral lands here by default. When + // a DDR board is present the `sys` domain instead rides the DDR PLL's + // CLKOS (the `ddr` entry below is the CLKOP primary, since nextpnr only + // routes the dedicated ECLK network from CLKOP), sharing one EHXPLLL. So a + // standalone sys domain is only added when there is NO DDR board. + if (!ecp5DdrDomain) + HarborClockConfig( + name: 'sys', + rate: HarborFixedClockRate(clockFrequency), + sourceFrequency: oscFrequency, + // Single-oscillator Xilinx DDR3-fast: run the core off the DDR MMCM's + // spare core CLKOUT instead of a second MMCM contending for the pin. + providedByDdr3Tree: useDdr3TreeCoreClk, + ), + // USB full-speed domain: the RAW oscillator, passed straight through + // (isPrimary). The 48 MHz osc is already the SoC `clk`, handed to the USB + // engine while the core runs on the PLL-divided `sys`. Only when USB DFU + // is integrated. + if (usbDfu) + HarborClockConfig( + name: 'usb', + rate: HarborFixedClockRate(oscFrequency), + isPrimary: true, + ), + // DDR domain. Two cases, keyed on --ddr-clock-freq (ddrClockFrequency): + // - unset or <= osc: the RAW osc (48 MHz), DLL-OFF at the osc rate (the + // proven bring-up path), no DRAM DLL lock. + // - above the osc (e.g. 144 MHz): an EHXPLLL CLKOP from the osc, so the + // DRAM CK runs faster than the core. At 144 MHz the DRAM DLL locks and + // the DQSBUFM DLL-on read scheme works, CDC bridging the slow `sys` bus + // face. 48 -> 144 is a clean ECP5 target (VCO 576 MHz, in band). + // Only when a board-backed DRAM region is present. + if (ecp5DdrDomain) + (ddrClockFrequency != null && ddrClockFrequency! > oscFrequency) + // DLL-ON: the DDR CK is the CLKOP primary (its eclk needs the + // dedicated ECLK network) and the core/sys clock rides CLKOS off the + // same VCO. VCO = ddrCk*CLKOP_DIV (576) must be an integer multiple + // of the core clock. The CLKOS_CPHASE fix in + // createDomainWithSecondary makes this single PLL lock on silicon. + ? HarborClockConfig( + name: 'ddr', + rate: HarborFixedClockRate(ddrClockFrequency!), + sourceFrequency: oscFrequency, + coClkosSecondary: (name: 'sys', frequency: clockFrequency), + ) + // DLL-OFF: the DDR CK is a real PLL CLKOP with the core/sys clock on + // CLKOS off the same PLL. Default CK = osc (48->48). Setting + // --ddr-clock-freq below the osc (e.g. 24 MHz) halves the CK, which + // doubles the absolute DLL-off read eye so the marginal DQS jitter is + // a smaller eye fraction. The ECP5 ECLK network only routes from a + // PLL CLKOP, not a raw osc pad. Sharing one PLL for ddr+sys leaves + // the 2nd EHXPLLL for the DQS clk90. + : HarborClockConfig( + name: 'ddr', + rate: HarborFixedClockRate( + (ddrClockFrequency != null && + ddrClockFrequency! < oscFrequency) + ? ddrClockFrequency! + : oscFrequency, + ), + sourceFrequency: oscFrequency, + coClkosSecondary: (name: 'sys', frequency: clockFrequency), + ), + ], + ); + + RiverCore? debugCore; + for (final coreConfig in coreConfigs) { + final core = RiverCore( + coreConfig, + busConfig: busConfig, + target: target, + withDebug: enableDebug, + ); + soc.addMaster(core, busInterfaceName: 'dataBus'); + debugCore ??= core; + } + + // Boot ROM. The hello-world demo bakes the application directly into the + // ROM (skip cache-as-RAM: the core runs from ROM and uses SRAM directly). + // Otherwise a maskrom path requests the copy/training bootstrap. + if (bootProgram != null) { + final primaryConfig = coreConfigs.first; + final bootBin = await _buildBootProgram(primaryConfig); + soc.addPeripheral( + HarborMaskRom( + baseAddress: primaryConfig.resetVector, + initialData: _bytesToWords(bootBin, busConfig.dataWidth ~/ 8), + dataWidth: busConfig.dataWidth, + busAddressWidth: busConfig.addressWidth, + busDataWidth: busConfig.dataWidth, + ), + ); + } else if (maskromPath != null || + usbDfu || + flashFirmware != null || + flashFirmwarePath != null) { + // A maskrom path (copy/training bootstrap), USB DFU mode (arm USB, wait + // for a host download into SRAM, jump to it), or a bundled flash firmware + // (copy from a flash offset into SRAM, jump to it) all bake a RiverMaskrom + // into the boot ROM. + final primaryConfig = coreConfigs.first; + final maskromBin = await _buildMaskrom(primaryConfig, busConfig); + soc.addPeripheral( + HarborMaskRom( + baseAddress: primaryConfig.resetVector, + initialData: _bytesToWords(maskromBin, busConfig.dataWidth ~/ 8), + dataWidth: busConfig.dataWidth, + busAddressWidth: busConfig.addressWidth, + busDataWidth: busConfig.dataWidth, + ), + ); + } + + for (var i = 0; i < memories.length; i++) { + final mem = memories[i]; + final board = mem.ddrBoard; + if (board != null && ddr3Fast) { + // Real-speed DDR3-667 (Xilinx ISERDESE2). + // Build the DDR3 clock tree from the board oscillator: an MMCM (ZHOLD + + // BUFG feedback, the only openXC7-lockable form) fans one VCO into ck333 + // (DDR CK / ISERDESE2 CLK), ctrl83 (CK/4, controller + ISERDESE2 CLKDIV), + // a ~200 MHz IDELAYCTRL reference, and ck333@90 (write launch), each on + // its own BUFG. The controller runs on ctrl83 (asyncClock CDC to the slow + // sys core/bus). This is the UberDDR3 / LiteDRAM open-tools read + // arrangement (no BUFR/BUFIO/PHASER). + // Tree source: with --ddr-osc-freq, a separate `ddr_osc` pin (the Arty S7 + // 100 MHz R2 osc), leaving the core/UART on the 12 MHz `clk`. Otherwise + // the main `clk` osc. + final Logic ddrTreeSource; + final int ddrTreeSourceHz; + if (ddrOscFrequency != null) { + soc.createPort('ddr_osc', PortDirection.input); + ddrTreeSource = soc.input('ddr_osc'); + ddrTreeSourceHz = ddrOscFrequency!; + } else { + ddrTreeSource = soc.input('clk'); + ddrTreeSourceHz = oscFrequency; + } + // DDR3 CK target. With the 100 MHz osc the oracle PLLE2 solves CK 400 MHz + // (DDR3-800), controller 100 MHz, IDELAYCTRL ref 200 MHz exact. Default to + // 400 MHz on the 100 MHz path so the solver lands the exact oracle + // dividers. Keep 333 for the legacy 12 MHz path. + final ck333Hz = + ddrClockFrequency ?? + (ddrOscFrequency == 100000000 ? 400000000 : 333333333); + const idelayRefHz = 200000000; + // DQS launch phase (CLKOUT4). Default 180 = the UberDDR3 Arty HR-bank + // oracle: DQS on 180-deg CK while DQ/DM ride ck90 centers the DQS edge in + // the DQ eye and edge-frames the write off CK (tDQSS). + const dqsPhaseDeg = 180.0; + // When the SoC already built the DDR3 clock tree in its clock generation + // (single-oscillator core-clock-off-spare-CLKOUT path), reuse it so the + // core and the DDR clocks share ONE MMCM. Otherwise build it here (the + // separate `ddr_osc` pin case has no clock-pin contention). + final tree = + soc.xilinxDdr3Clocks ?? + buildXilinxDdr3ClockTree( + soc, + source: ddrTreeSource, + sourceHz: ddrTreeSourceHz, + ddrCkHz: ck333Hz, + idelayRefHz: idelayRefHz, + dqsPhaseDeg: dqsPhaseDeg, + name: 'ddr3clk', + ); + // Controller clock = ctrl83 (CK/4). All DRAM us/ns timing counters derive + // from this rate. The sequencer is told CK = ctrl83 * 4 (ckCyclesPerTick=4) + // so the CK-relative JEDEC latencies + MR CL/CWL compute against the true + // DDR CK. + final ctrlHz = tree.controllerMhz.round() * 1000000; + // DDR3 speed-bin CL/CWL from the REALISED CK period (UberDDR3 JEDEC table, + // ddr3_controller.v CL_generator/CWL_generator): + // tCK >= 3000 ps (DDR3-667) -> CL=5, CWL=5 + // 2500..3000 ps (DDR3-800) -> CL=6, CWL=5 + // 1875..2500 ps -> CL=7, CWL=6 ... + // Deriving from the realised period keeps MR CL/CWL correct whatever the + // tree solves. On the 100 MHz path hard-match the HW-verified oracle + // (CL=5, CWL=5): it runs the DDR3-667 MR latencies on the faster 400 MHz CK + // (read data arrives 1 nCK early, conservative + proven). The legacy 12 MHz + // path keeps deriving from the realised period. + final tCkPs = (1.0e6 / tree.ddrCkMhz); + final int ddr3Cl; + final int ddr3Cwl; + if (ddrOscFrequency == 100000000) { + ddr3Cl = 5; + ddr3Cwl = 5; + } else { + ddr3Cl = tCkPs >= 3000 ? 5 : (tCkPs >= 2500 ? 6 : 7); + ddr3Cwl = tCkPs >= 2500 ? 5 : (tCkPs >= 1875 ? 6 : 7); + } + final ddr3CwlEff = ddr3Cwl; + final ddr = HarborDdrController( + config: board.config, + baseAddress: mem.address, + clockHz: ctrlHz, + busAddressWidth: busConfig.addressWidth, + busDataWidth: busConfig.dataWidth, + target: target, + // Sequencer/PHY on ctrl83, bus face on the slow sys clock (CDC). + asyncClock: true, + // The real-speed ISERDESE2 DW8 read gearbox. + ddr3Fast: true, + ddr3FastCkMhz: tree.ddrCkMhz, + ddr3FastIdelayRefMhz: tree.idelayRefMhz, + ddr3FastCl: ddr3Cl, + ddr3FastCwl: ddr3CwlEff, + // ddr3Fast write/command timing. Effective value = region param, else + // board default, else the global default. cmdSlot/wrShift/window fall + // back to 0/0/5. wrBeat falls back to null (the PHY then derives it + // from CWL). + cmdSlot: mem.ddrParams?.cmdSlot ?? board.cmdSlot ?? 0, + writeShift: mem.ddrParams?.wrShift ?? board.wrShift ?? 0, + wrBeatOffset: mem.ddrParams?.wrBeat ?? board.wrBeat, + windowTapReset: mem.ddrParams?.window ?? board.window ?? 5, + // Per-lane IDELAY(VAR_LOAD) + BITSLIP leveling MMIO for the ddrlevelx + // firmware (defaults on for the DDR read-path boot programs). Region + // param / board default win over the boot-program default set. + trainableRead: + mem.ddrParams?.trainable ?? + board.trainable ?? + const { + 'ddrtest', + 'ddrprobe', + 'ddrlevel', + 'ddrlevelx', + 'ddreye', + 'ddrdiag', + }.contains(bootProgram), + readSlack: mem.ddrParams?.readSlack ?? board.readSlack ?? 1, + readTaps: mem.ddrParams?.readTap ?? board.readTap ?? 40, + readRetryTries: mem.ddrParams?.readRetry ?? board.readRetry ?? 0, + // Bring-up diagnostic: leave MR3.MPR set so every read returns the part + // MPR pattern (0xFFFF0000) with no write dependency, decoupling a broken + // write from a broken init/read. From the dram region `mpr` param + // (defaults off), on both the ddr3Fast and ECP5 paths. + mprDebug: mem.ddrParams?.mpr ?? false, + // Marginal-write boards (openXC7 Arty x8) carry writeVerify in their + // DdrBoard so a plain build is correct with no extra flag. A region + // param can still force it on/off. + writeVerify: mem.ddrParams?.writeVerify ?? board.writeVerify, + name: '${mem.type}_$i', + ); + soc.addPeripheral(ddr); + // Wire the DDR domain: controller/CLKDIV = ctrl83, plus the three tree + // clocks into the PHY (ck333, ck333@90, 200 MHz IDELAYCTRL ref). + ddr.input('ddr_clk').srcConnection! <= tree.controller; + // ddr_reset: the sys clock domain reset (an FPGA target uses an internal + // power-on reset, no external `reset` pin). The controller stretches the + // IDELAYCTRL RST internally, so this only needs a valid domain reset for + // the sequencer/PHY. The `sys` domain is always present on ddr3Fast. + final sysDomainForDdr = soc.clockDomain('sys'); + if (sysDomainForDdr == null) { + throw StateError('ddr3Fast needs the sys clock domain for ddr_reset'); + } + ddr.input('ddr_reset').srcConnection! <= sysDomainForDdr.reset; + ddr.input('ddr_ck_fast').srcConnection! <= tree.ddrCk; + ddr.input('ddr_ck90_fast').srcConnection! <= tree.ddrCk90; + // 180-deg DQS launch clock (CLKOUT4): DQS edge centered in the DQ eye + + // edge-framed to CK (tDQSS), the UberDDR3 Arty HR-bank oracle scheme. + ddr.input('ddr_ck_dqs_fast').srcConnection! <= tree.ddrCkDqs; + ddr.input('ddr_idelay_ref').srcConnection! <= tree.idelayRef; + // DDR3 pads (single-ended SSTL135 _p + explicit _n complement, like the + // ECP5 DLL-off path). The Xilinx PHY drives both DQS rails. + final padPorts = [...DdrBoard.padPorts, 'sdram_dqs_n']; + for (final pad in padPorts) { + soc.exposePin(ddr, pad, externalName: pad); + } + } else if (board != null) { + // DQS-strobed (DQSBUFM) DDR3 PHY. The ECP5 read path captures DQ with the + // DRAM's own DQS strobe (DQSBUFM DQSR90 + IDDRX2DQA), so the DQ IOLOGIC is + // x2-geared. An ECP5 DQ pad's input and output IOLOGIC must share gearing, + // so the write is x2 too. The x2 gearbox needs a half-rate fabric clock: + // the PHY derives eclk (CK rate = 48 MHz) and sclk (eclk/2 = 24 MHz) from + // the `ddr` domain. The asyncClock controller keeps its `bus` slave face + // on the slow `sys` fabric (24 MHz) and runs the sequencer/PHY on the + // 48 MHz `ddr_clk`, bridged by an internal HarborWishboneCdcBridge. CK + // stays 48 MHz. The controller also owns the 64->32 downsizer. + // + // The DDR CK rate = the `ddr` clock domain rate: the raw osc (DLL-off) by + // default, or the PLL'd --ddr-clock-freq when set above the osc (DLL-on). + // All DRAM timing counters and the DLL-on/off init choice derive from this + // CK rate. Any explicit --ddr-clock-freq is the real CK. Only an unset + // frequency falls back to the raw osc. A sub-osc CK (e.g. 24 MHz) widens + // the DLL-off read eye. + final ddrCkHz = ddrClockFrequency ?? oscFrequency; + // DLL engagement (CK > ~60 MHz). DLL-OFF takes the x1 IDDRX1F/ODDRX1F + // read/write datapath whose write->read turnaround eats beat0's rise + // sample. readCrossPair recovers it via the cross-cycle sliding pair. + // readSlack=1 is the proven full-cycle window for the x1 read. + final ddrCkDllOn = ddrCkHz > 60000000; + final ddr = HarborDdrController( + config: board.config, + baseAddress: mem.address, + // Sequencer/PHY clock = the `ddr` domain CK rate (osc for DLL-off, the + // PLL'd rate for DLL-on). The PHY halves it to the sclk fabric. All + // DRAM timing counters derive from this CK rate. + clockHz: ddrCkHz, + busAddressWidth: busConfig.addressWidth, + busDataWidth: busConfig.dataWidth, + // ECP5 board target so the controller builds the Lattice DQS PHY. + target: target, + // Second (faster) DRAM clock domain: bus face on `sys`, sequencer/PHY + // on `ddr_clk`, bridged by the controller's internal CDC. + asyncClock: true, + // Runtime-trainable DQS read: anchors beat0 on the DQSBUFM DATAVALID + // burst (the cold-read fix) and exposes the train-control MMIO window + // (the controller auto-extends its decoded span by trainCtrlSize). + // Resolves region param, then board default, then default ON for the + // DDR3 read-path boot programs. The set MUST include every program that + // touches the train-control window, else its accesses are unmapped and + // hang on the first STATUS read. + trainableRead: + mem.ddrParams?.trainable ?? + board.trainable ?? + const { + 'ddrtest', + 'ddrprobe', + 'ddrlevel', + 'ddrlevelx', + 'ddreye', + 'ddrdiag', + }.contains(bootProgram), + // JEDEC DDR3 write-leveling FSM (MR1 A7=1, sweep the write DQS delay + // until the CK-vs-DQS feedback flips, exit WL): trains tDQSS so the BL8 + // deposit lands aligned. DLL-ON only. DLL-OFF used the fixed litedram + // tie-off and worked. Enabling WL there parks the pointer at a mistrained + // tap and garbages every write. So gate WL (and the DYNDELAY write-trim) + // on the DLL-on band. ddreye/ddrdiag MUST be in the set too: without the + // WL FSM the trainable sequencer never completes DLL-on init and hangs. + writeLevel: + (ddrClockFrequency != null && + ddrClockFrequency! > oscFrequency) && + (mem.ddrParams?.trainable ?? + board.trainable ?? + const { + 'ddrtest', + 'ddrprobe', + 'ddrlevel', + 'ddreye', + 'ddrdiag', + }.contains(bootProgram)), + // Firmware DQSBUFM DYNDELAY[7:0] write-trim (reg8): a per-byte-lane + // dynamic DQS-delay sweep to trim the fixed below-strobe-pad write skew + // that floats the first-cycle DQ bits. DLL-on only (same reason as WL). + writeTrimTrainable: + (ddrClockFrequency != null && + ddrClockFrequency! > oscFrequency) && + (mem.ddrParams?.trainable ?? + board.trainable ?? + const { + 'ddrtest', + 'ddrprobe', + 'ddrlevel', + 'ddreye', + 'ddrdiag', + }.contains(bootProgram)), + mprDebug: mem.ddrParams?.mpr ?? false, + // Read-eye knobs (bench sweep axes), from the dram region + // `read-tap`/`read-slack` params or board defaults: + // readTaps = per-DQ static DELAYG delay (the eye-centering knob). + // readSlack = full-cycle read-window slide. DLL-on keeps 2 (proven x2). + // DLL-off uses the region read-slack (default 1). + readTaps: mem.ddrParams?.readTap ?? board.readTap ?? 40, + readSlack: ddrCkDllOn + ? 2 + : (mem.ddrParams?.readSlack ?? board.readSlack ?? 1), + // x1 read deserialize assembly. With the write-side DQS fix (DQS on the + // 50%-duty CLKOS2, both write beats centered), the read uses HEAD + // same-cycle MODE 0 {q1,q0}. No effect on the DLL-on x2 path. + readPairMode: 0, + readRetryTries: mem.ddrParams?.readRetry ?? board.readRetry ?? 0, + name: '${mem.type}_$i', + ); + // The fabric-facing `bus` slave auto-clocks on `sys` (24 MHz): this is the + // peripheral the SoC decoder maps at mem.address. The internal CDC's fast + // master side + sequencer + PHY run on the `ddr` 48 MHz domain wired below. + // The PHY divides it to the 24 MHz sclk for the DQS x2 datapath. + soc.addPeripheral(ddr); + final ddrDomain = soc.clockDomain('ddr'); + if (ddrDomain == null) { + throw StateError( + 'board-backed DRAM present but the "ddr" clock domain is missing', + ); + } + ddr.input('ddr_clk').srcConnection! <= ddrDomain.clk; + ddr.input('ddr_reset').srcConnection! <= ddrDomain.reset; + // The pads keep their port names so the board's constraint table (sdram_*) + // lines up with the netlist. DLL-OFF: the controller adds an explicit + // sdram_dqs_n complement port, so expose it too. DLL-ON: the single + // SSTL135D_I diff DQS pad has no _n port (nextpnr derives _n). + final ddrDllOn = ddrCkHz > 60000000; + final padPorts = [...DdrBoard.padPorts, if (!ddrDllOn) 'sdram_dqs_n']; + for (final pad in padPorts) { + soc.exposePin(ddr, pad, externalName: pad); + } + } else if (mem.type == 'flash') { + // Real SPI NOR flash with XIP: the CPU fetches firmware directly from the + // part, no on-chip copy. 16MB maps to the W25Q128 (the OrangeCrab/ + // iCEBreaker part). Other sizes get a generic quad-read config sized to + // the region. + final spiConfig = mem.size == 16 * 1024 * 1024 + ? const HarborSpiFlashConfig.w25q128() + : HarborSpiFlashConfig( + size: mem.size, + mode: HarborSpiFlashMode.quad, + readCommand: 0x6B, + addressBytes: mem.size > 16 * 1024 * 1024 ? 4 : 3, + dummyCycles: 8, + ); + // The config-flash clock has no I/O pad on either family: route it + // through the ECP5 USRMCLK macro or the Xilinx STARTUPE2 (USRCCLKO -> + // CCLK) inside the controller, so there is no spi_clk port. + final isEcp5 = + target is HarborFpgaTarget && + target.vendor == HarborFpgaVendor.ecp5; + final isXilinx = + target is HarborFpgaTarget && + (target.vendor == HarborFpgaVendor.openXc7 || + target.vendor == HarborFpgaVendor.vivado); + final flash = HarborSpiFlashController( + config: spiConfig, + baseAddress: mem.address, + busAddressWidth: busConfig.addressWidth, + busDataWidth: busConfig.dataWidth, + useUsrmclk: isEcp5, + useStartupe2: isXilinx, + name: '${mem.type}_$i', + ); + soc.addPeripheral(flash); + // Expose the SPI pads. The clock is absent on ECP5 (USRMCLK). Quad/dual + // flash exposes split tristate IO (spi_io_out/oe/in). Standard mode is + // spi_mosi/spi_miso. + final dataPins = spiConfig.mode == HarborSpiFlashMode.standard + ? const ['spi_cs_n', 'spi_mosi', 'spi_miso'] + : const ['spi_cs_n', 'spi_io_out', 'spi_io_oe', 'spi_io_in']; + final spiPins = [if (!isEcp5 && !isXilinx) 'spi_clk', ...dataPins]; + // Prefix when more than one SPI device shares the pinout (multiple flash, + // or flash alongside PSRAM) so spi_clk/spi_cs_n/spi_io do not collide. + final spiCount = memories + .where((m) => m.type == 'flash' || m.type == 'psram') + .length; + final prefix = spiCount > 1 ? '${mem.type}_' : ''; + for (final pin in spiPins) { + soc.exposePin(flash, pin, externalName: '$prefix$pin'); + } + } else if (mem.type == 'psram') { + // External QSPI PSRAM (APS6404 / LY68L6400): a bus slave serving RAM over + // SPI, sized to the region. Quad mode by default (the Tiny Tapeout QSPI + // Pmod). Like flash it exposes split-tristate SPI pads. On the TT Pmod + // flash and PSRAM share one physical bus (separate CS), wired in the + // hand-maintained SoC top, not here. Genip exposes each device's pins + // independently. + final psram = HarborPsramController( + config: HarborPsramConfig(size: mem.size, mode: HarborPsramMode.quad), + baseAddress: mem.address, + busAddressWidth: busConfig.addressWidth, + busDataWidth: busConfig.dataWidth, + name: '${mem.type}_$i', + ); + soc.addPeripheral(psram); + // Prefix when more than one SPI device shares the pinout (see flash). + final spiCount = memories + .where((m) => m.type == 'flash' || m.type == 'psram') + .length; + final prefix = spiCount > 1 ? '${mem.type}_' : ''; + // Quad PSRAM exposes split tristate IO (spi_io_out/oe/in) so the pad ring + // (or the hand-written shared-QSPI SoC top) resolves the bidirectional + // lines. Standard mode is spi_mosi/spi_miso. + final ioPins = psram.config.mode == HarborPsramMode.quad + ? const ['spi_io_out', 'spi_io_oe', 'spi_io_in'] + : const ['spi_mosi', 'spi_miso']; + for (final pin in ['spi_clk', 'spi_cs_n', ...ioPins]) { + soc.exposePin(psram, pin, externalName: '$prefix$pin'); + } + } else { + soc.addPeripheral( + HarborSram( + baseAddress: mem.address, + size: mem.size, + dataWidth: busConfig.dataWidth, + busAddressWidth: busConfig.addressWidth, + target: target, + name: '${mem.type}_$i', + ), + ); + } + } + + final peripheralsByName = {}; + for (final dev in mmioDevices) { + final peripheral = _createPeripheral(dev, busConfig, target: target); + if (peripheral != null) { + soc.addPeripheral(peripheral); + peripheralsByName[dev.name] = peripheral; + } + } + + // Expose peripheral pins referenced by --pin flags (and the board catalog). + for (final pin in effectivePins) { + if (!pin.isDevicePin) continue; + final peri = peripheralsByName[pin.deviceName]; + if (peri == null) { + throw ArgumentError( + 'Pin "${pin.externalName}": unknown device "${pin.deviceName}"', + ); + } + soc.exposePin(peri, pin.portName, externalName: pin.externalName); + } + + if (usbDfu && usbDfuMode == UsbDfuMode.hardware) { + if (enableDebug) { + // The hardware DFU path uses a fixed 2-master arbiter (core + DFU + // RAM-sink). The debug JTAG SBA would be a third master it cannot route. + // Make it an explicit error rather than silently dropping JTAG. + throw ArgumentError( + 'debug-jtag is not supported with hardware usb-dfu (the 2-master ' + 'arbitrated fabric has no slot for the debug SBA master); use ' + 'usb-dfu:...:mode=software or drop debug-jtag', + ); + } + _integrateUsbDfu(soc, busConfig, target); + } else if (usbDfu && usbDfuMode == UsbDfuMode.software) { + _integrateUsbDfuSoftware(soc, busConfig, target); + if (enableDebug) _integrateDebugJtag(soc, busConfig, debugCore!); + soc.buildFabric(); + } else { + if (enableDebug) _integrateDebugJtag(soc, busConfig, debugCore!); + soc.buildFabric(); + } + + return soc; + } + + /// Wire the JTAG debug subsystem as a second fabric master: connect its + /// core-facing control ports to the [core]'s `withDebug` ports and expose the + /// JTAG pins (tck/tms/tdi/tdo/trst_n) as top-level SoC pads. + void _integrateDebugJtag( + HarborSoC soc, + WishboneConfig busConfig, + RiverCore core, + ) { + final xlen = busConfig.dataWidth; + final dbg = RiverDebugSubsystem(busConfig, xlen: xlen); + soc.addMaster(dbg, busInterfaceName: 'bus'); + + // To the core. + core.input('debug_halt_req').srcConnection! <= dbg.output('halt_req'); + core.input('debug_resume_req').srcConnection! <= dbg.output('resume_req'); + core.input('debug_reg_read').srcConnection! <= dbg.output('reg_read'); + core.input('debug_reg_write').srcConnection! <= dbg.output('reg_write'); + core.input('debug_reg_addr').srcConnection! <= dbg.output('reg_addr'); + core.input('debug_reg_wdata').srcConnection! <= dbg.output('reg_wdata'); + // From the core. + dbg.input('hart_halted').srcConnection! <= core.output('debug_halted'); + dbg.input('reg_rdata').srcConnection! <= core.output('debug_reg_rdata'); + dbg.input('reg_ready').srcConnection! <= core.output('debug_reg_ready'); + + // No top-level JTAG pads: the TAP comes off the ECP5 config JTAG (dirtyJtag) + // via the JTAGG primitive inside the subsystem. OpenOCD reaches it with + // `riscv use_bscan_tunnel 6 1` over the ECP5 TAP. + } + + /// Integrates the USB DFU subsystem into [soc]: instantiates the subsystem + /// (engine + RAM sink + line tristate, dual clock domain) as a SECOND bus + /// master, the [RiverDfuStatus] control/status slave as a peripheral, exposes + /// the USB + button pads, and builds a two-master Wishbone fabric (core + + /// DFU sink) through a [RiverWishboneArbiter] into a single decoder. + void _integrateUsbDfu( + HarborSoC soc, + WishboneConfig busConfig, + HarborDeviceTarget? target, + ) { + final ram = dfuRamRegion; + if (ram == null) { + throw ArgumentError( + '--usb-dfu requires an SRAM region (-m sram:...) for the download ' + 'target; none found.', + ); + } + + // The control/status slave the maskrom polls. + final status = RiverDfuStatus( + baseAddress: dfuStatusBase, + busAddressWidth: busConfig.addressWidth, + busDataWidth: busConfig.dataWidth, + ); + soc.addPeripheral(status); // bus (sys) domain, auto-clocked. + + // The DFU subsystem (engine + sink + pads). Its bus master runs on `sys` + // (auto-wired via addMaster). The 48 MHz USB side is wired manually. + final dfu = RiverDfuSubsystem( + loadBase: ram.address, + busAddressWidth: busConfig.addressWidth, + busDataWidth: busConfig.dataWidth, + ); + soc.addMaster(dfu, busInterfaceName: 'bus'); // clk/reset <- sys domain. + + // Hand the raw 48 MHz osc (the `usb` primary clock domain) to the USB side. + final usbDomain = soc.clockDomain('usb'); + if (usbDomain == null) { + throw StateError('usb-dfu enabled but the "usb" clock domain is missing'); + } + dfu.input('usb_clk').srcConnection! <= usbDomain.clk; + dfu.input('usb_reset').srcConnection! <= usbDomain.reset; + + // Status wiring between the subsystem and the slave (all bus domain). + status.input('image_ready').srcConnection! <= dfu.output('image_ready'); + status.input('entry_addr').srcConnection! <= dfu.output('entry_addr'); + status.input('bytes_written').srcConnection! <= dfu.output('bytes_written'); + dfu.input('usb_enable').srcConnection! <= status.output('usb_enable'); + + // Expose the USB line pads + pull-up + button to the SoC top. + soc.exposePin(dfu, 'usb_dp', externalName: 'usb_dp'); + soc.exposePin(dfu, 'usb_dm', externalName: 'usb_dm'); + soc.exposePin(dfu, 'usb_pullup', externalName: 'usb_pullup'); + + // Two-master fabric: arbitrate [core, dfu] onto one decoder. buildFabric's + // per-master decoders would multiply-drive the slaves, so build it here. + _buildArbitratedWishboneFabric(soc, busConfig); + } + + /// Integrates the LEAN, software-driven USB DFU subsystem + /// ([RiverDfuSubsystemSw]) into [soc]. Unlike [_integrateUsbDfu], this adds a + /// single MMIO SLAVE (no second master, no arbiter, no RAM-sink, no CDC + /// FIFO), so the stock single-master [HarborSoC.buildFabric] handles routing. + /// The maskrom reads received bytes over MMIO and stores them into CAR. + void _integrateUsbDfuSoftware( + HarborSoC soc, + WishboneConfig busConfig, + HarborDeviceTarget? target, + ) { + final dfu = RiverDfuSubsystemSw( + baseAddress: dfuStatusBase, + busAddressWidth: busConfig.addressWidth, + busDataWidth: busConfig.dataWidth, + ); + // Add as a peripheral (bus/sys-domain slave, auto-clocked). + soc.addPeripheral(dfu); + + // Hand the raw 48 MHz osc (the `usb` primary clock domain) to the USB side. + final usbDomain = soc.clockDomain('usb'); + if (usbDomain == null) { + throw StateError('usb-dfu enabled but the "usb" clock domain is missing'); + } + dfu.input('usb_clk').srcConnection! <= usbDomain.clk; + dfu.input('usb_reset').srcConnection! <= usbDomain.reset; + + // Expose the USB line pads + pull-up to the SoC top. + soc.exposePin(dfu, 'usb_dp', externalName: 'usb_dp'); + soc.exposePin(dfu, 'usb_dm', externalName: 'usb_dm'); + soc.exposePin(dfu, 'usb_pullup', externalName: 'usb_pullup'); + } + + /// Builds a Wishbone fabric for exactly two masters (the River core and the + /// DFU RAM-sink) sharing the peripheral set, by merging them through a + /// [RiverWishboneArbiter] into a single [WishboneDecoder]. + void _buildArbitratedWishboneFabric(HarborSoC soc, WishboneConfig busConfig) { + final errors = soc.validate(); + if (errors.isNotEmpty) { + throw StateError( + 'Validation errors in ${soc.name}:\n${errors.join("\n")}', + ); + } + + final masters = soc.masters; + if (masters.length != 2) { + throw StateError( + 'USB DFU fabric expects exactly 2 masters (core + dfu), got ' + '${masters.length}', + ); + } + final core = masters[0]; + final dfu = masters[1]; + + final peripherals = soc.peripherals; + final mappings = []; + for (var i = 0; i < peripherals.length; i++) { + final p = peripherals[i] as HarborDeviceTreeNodeProvider; + mappings.add(HarborAddressMapping(range: p.dtNode.reg, slaveIndex: i)); + } + + // Arbiter: merge the two masters' provider interfaces into one slave. + final (clk, reset) = soc.defaultClock; + final arbiter = RiverWishboneArbiter(busConfig); + soc.addSubModule(arbiter); + arbiter.input('clk').srcConnection! <= clk; + arbiter.input('reset').srcConnection! <= reset; + connectInterfaces(core.interface('dataBus'), arbiter.interface('m0')); + connectInterfaces(dfu.interface('bus'), arbiter.interface('m1')); + + // Decoder: route the merged master to every peripheral slave. + final decoder = WishboneDecoder(busConfig, mappings); + soc.addSubModule(decoder); + connectInterfaces(arbiter.interface('slave'), decoder.interface('master')); + for (var i = 0; i < peripherals.length; i++) { + connectInterfaces( + decoder.interface('slave_$i'), + peripherals[i].interface('bus'), + ); + } + } + + BridgeModule? _createPeripheral( + DeviceEntry dev, + WishboneConfig busConfig, { + HarborDeviceTarget? target, + }) { + switch (dev.type) { + case 'uart': + return HarborUart( + baseAddress: dev.address, + clockFrequency: clockFrequency, + busAddressWidth: busConfig.addressWidth, + busDataWidth: busConfig.dataWidth, + ); + case 'clint': + return HarborClint( + baseAddress: dev.address, + busAddressWidth: busConfig.addressWidth, + busDataWidth: busConfig.dataWidth, + ); + case 'plic': + // Size the PLIC to the SoC's actual interrupt sources, not the 32-source + // default. One source per interrupt-generating peripheral (the CLINT goes + // direct to the hart), so the device count +1 (reserved source 0) is a + // safe upper bound. Priority/claim logic scales with source count, a real + // LUT win on small SoCs. + return HarborPlic( + baseAddress: dev.address, + busAddressWidth: busConfig.addressWidth, + busDataWidth: busConfig.dataWidth, + sources: mmioDevices.length + 1, + ); + default: + return null; + } + } + + Future _buildMaskrom( + RiverCoreConfig coreConfig, + WishboneConfig busConfig, + ) async { + final firstMem = memories.isNotEmpty ? memories.first : null; + // When USB DFU is integrated, the maskrom arms USB, waits for the host to + // download an image into SRAM, then jumps to the reported entry address. + final dfuConfig = usbDfu + ? RiverDfuConfig( + controlAddr: dfuControlAddr, + statusAddr: dfuStatusAddr, + entryAddr: dfuEntryAddr, + ) + : null; + // Bundled flash firmware: copy from flash[firmwareOffset] into SRAM and jump + // there. flashSource is the firmware OFFSET (not flash base 0, the bitstream), + // copyDest is SRAM, copySize is the firmware byte length. The `dramexec` boot + // program consumes --flash-firmware-path itself (copies it into DRAM and jumps + // there), so skip the flash->SRAM bundling for it and let the external binary + // reach the dramexec case below. + if ((flashFirmware != null || flashFirmwarePath != null) && + bootProgram != 'dramexec') { + final flash = flashRegion ?? firstMem; + final sram = sramRegion; + if (flash == null || sram == null) { + throw StateError( + 'flash-firmware bundle needs both a flash and an sram region', + ); + } + // An external binary (e.g. the Weir FSBL) takes precedence over a built-in + // firmware program: the maskrom copies its raw bytes into SRAM and jumps. + final firmware = flashFirmwarePath != null + ? await File(flashFirmwarePath!).readAsBytes() + : await buildFlashFirmware(coreConfig); + final rom = RiverMaskrom( + RiverMaskromConfig( + isa: coreConfig.isa, + resetVector: coreConfig.resetVector, + flashSource: flash.address + flashFirmwareOffset, + copyDest: sram.address, + // Round up to a word so the maskrom's word copy covers the tail byte. + copySize: (firmware.length + 3) & ~3, + stackTop: sram.address + sram.size, + ), + ); + await rom.build(); + return Uint8List.fromList(rom.generateBinary()); + } + // In DFU mode the stack lives in writable SRAM (the download target), + // not the read-only flash that `memories.first` usually is. + final stackMem = usbDfu ? (dfuRamRegion ?? firstMem) : firstMem; + final rom = RiverMaskrom( + RiverMaskromConfig( + isa: coreConfig.isa, + resetVector: coreConfig.resetVector, + flashSource: firstMem?.address ?? 0, + copyDest: firstMem?.address ?? 0, + copySize: 4, + stackTop: (stackMem?.address ?? 0) + (stackMem?.size ?? 0x1000), + dfu: dfuConfig, + ), + ); + await rom.build(); + return Uint8List.fromList(rom.generateBinary()); + } + + /// Builds the bundled flash firmware ([flashFirmware]) against the first UART + /// and the flash region. Returns the raw bytes to be flashed at + /// [flashFirmwareOffset] (and which the maskrom copies into SRAM). + Future buildFlashFirmware(RiverCoreConfig coreConfig) async { + final uart = mmioDevices.firstWhere( + (d) => d.type == 'uart', + orElse: () => throw StateError('flash firmware needs a uart device'), + ); + final flash = flashRegion; + if (flash == null) { + throw StateError('flash firmware needs a flash region'); + } + switch (flashFirmware) { + case 'hexdump': + final fw = RiverFlashHexdump( + isa: coreConfig.isa, + uartBase: uart.address, + flashBase: flash.address, + clockHz: clockFrequency, + ); + await fw.build(); + return Uint8List.fromList(fw.generateBinary()); + default: + throw UnsupportedError('Unknown flash firmware: $flashFirmware'); + } + } + + /// Builds the selected built-in boot program for the boot ROM, against the + /// first UART and the first RAM region. + /// + /// `hello` ([RiverHelloWorld]) streams a banner after round-tripping it + /// through RAM. `monitor` ([RiverSerialMonitor]) additionally loads + /// checksummed payloads into RAM over the UART and jumps to them. + Future _buildBootProgram(RiverCoreConfig coreConfig) async { + final uart = mmioDevices.firstWhere( + (d) => d.type == 'uart', + orElse: () => throw StateError('boot program needs a uart device'), + ); + if (memories.isEmpty) { + throw StateError('boot program needs a RAM region'); + } + // The boot program scratchpads through writable RAM, so ramBase must be a RAM + // region, NOT flash. `memories.first` is the read-only flash region in the + // usual (flash, sram, dram) ordering. Storing there drops the bytes and the + // program streams garbage. Prefer SRAM, fall back to any non-flash region. + final ram = memories.firstWhere( + (m) => m.type == 'sram', + orElse: () => memories.firstWhere( + (m) => m.type != 'flash', + orElse: () => throw StateError( + 'boot program needs a writable RAM region (sram or dram)', + ), + ), + ); + final adl.Module program; + switch (bootProgram) { + case 'hello': + program = RiverHelloWorld( + isa: coreConfig.isa, + uartBase: uart.address, + ramBase: ram.address, + clockHz: clockFrequency, + // Stream the banner continuously so bring-up can dial in the UART + // baud without racing a one-shot that fires the instant the FPGA + // configures (before a terminal is attached). + loop: true, + ); + case 'trapwfi': + // Silicon proof for the creek dynamic-microcode MRET + WFI fixes: runs + // straight from the boot ROM (romBase = resetVector), no RAM copy, and + // streams CREEK/M/R/W/OK markers. No "R" => MRET still loops. No "W"/"OK" + // => WFI still wedges. + program = RiverTrapWfiTest( + isa: coreConfig.isa, + uartBase: uart.address, + romBase: coreConfig.resetVector, + clockHz: clockFrequency, + ); + case 'monitor': + program = RiverSerialMonitor( + isa: coreConfig.isa, + uartBase: uart.address, + ramBase: ram.address, + clockHz: clockFrequency, + ); + case 'ddrtest': + // Isolates the DDR array from the FSBL/main: the maskrom runs the proven + // RiverDdrTest (8-offset word sweep + byte ops) straight from ROM against + // the dram region and prints "DDR OK" or "DDR ER". No FSBL, no flash copy. + final dram = memories.firstWhere( + (m) => m.type == 'dram', + orElse: () => + throw StateError('ddrtest boot program needs a dram region'), + ); + program = RiverDdrTest( + isa: coreConfig.isa, + uartBase: uart.address, + dramBase: dram.address, + // Train-control MMIO sits just above the DRAM array (board-relative, + // NOT a fixed 128M offset which lands inside a 256M array). + trainCtrlBase: dram.address + dram.size, + clockHz: clockFrequency, + // Loop the verdict: FPGA reconfig glitches the first UART bytes on + // hardware, so a one-shot print is unreadable. Streaming repeats + // gives a clean read once the line settles. + loopForever: true, + singleWord: ddrSingleWord, + ); + case 'ddrprobe': + // Diagnostic hex dump: printer self-test (0x12345678) then two passes + // writing distinct patterns and dumping the readbacks. Tracks-pattern = + // writes land but read suspect. Identical junk both passes = writes never + // reach the array. + final dram = memories.firstWhere( + (m) => m.type == 'dram', + orElse: () => + throw StateError('ddrprobe boot program needs a dram region'), + ); + program = RiverDdrProbe( + isa: coreConfig.isa, + uartBase: uart.address, + dramBase: dram.address, + clockHz: clockFrequency, + ); + case 'ddrlevel': + // DDR3 READ-vs-WRITE discriminator (no scope). Programs the trainable-read + // MMIO block and runs two sub-tests across RDSLACK 0..4 x READCLKSEL 0..7, + // judged by data. Test A (RDADDR) reads four distinct rows/banks with no + // writes: DISTINCT = read captures array, ALLSAME = read-side bug. Test B + // (WRCHG) writes then re-reads A0: CHANGES = writes modify the cell, + // NOCHANGE = writes never land. Needs trainableRead (genip auto-enables it + // plus writeLevel here). + final dram = memories.firstWhere( + (m) => m.type == 'dram', + orElse: () => + throw StateError('ddrlevel boot program needs a dram region'), + ); + program = RiverDdrLevel( + isa: coreConfig.isa, + uartBase: uart.address, + dramBase: dram.address, + // The train-control window sits immediately above the DRAM array. + trainCtrlBase: dram.address + dram.size, + clockHz: clockFrequency, + ); + case 'ddrlevelx': + // Xilinx (Arty S7) ISERDESE2 read-leveling. Walks the per-lane IDELAY + // tap (reg10 LD/CE/INC) to center each DQ eye against a written pattern, + // then searches the fabric BITSLIP (reg11) for the beat rotation that + // reads it clean, reporting LVLX L= TAP/LO/HI + LVLX SLIP over the + // UART. Drives the train-control MMIO exposed by the Xilinx DDR PHY when + // the read path is trainable (genip auto-enables trainableRead here). + final dram = memories.firstWhere( + (m) => m.type == 'dram', + orElse: () => + throw StateError('ddrlevelx boot program needs a dram region'), + ); + program = RiverDdrLevelXilinx( + isa: coreConfig.isa, + uartBase: uart.address, + dramBase: dram.address, + // The train-control window sits immediately above the DRAM array. + trainCtrlBase: dram.address + dram.size, + clockHz: clockFrequency, + // dram region `mpr` param => run MPR read-eye centering (write- + // independent 0101 target). Real build => park the baked center + run + // the A/B/C write-store test with the clean read. + mprMode: dram.ddrParams?.mpr ?? false, + ); + case 'ddrdiag': + // DDR train-control ADDRESS diagnostic (no scope). Prints the train-control + // STATUS address as a full 64-bit value (CTLADDR= ) to check + // whether the upper 32 bits are sign-extended, then brackets a control + // WRITE (TRYWR/WROK) and READ (TRYRD/RDOK=) so a missing OK marker + // pinpoints which access never acks. Needs the train-control window + // (genip auto-enables trainableRead here). + final dram = memories.firstWhere( + (m) => m.type == 'dram', + orElse: () => + throw StateError('ddrdiag boot program needs a dram region'), + ); + program = RiverDdrDiag( + isa: coreConfig.isa, + uartBase: uart.address, + dramBase: dram.address, + // The train-control window sits immediately above the DRAM array. + trainCtrlBase: dram.address + dram.size, + clockHz: clockFrequency, + ); + case 'ddreye': + // DDR3 read-leveling EYE SWEEP. Sweeps RDTAP {0,8,..,120} x READCLKSEL 0..7 + // x RDSLACK 0..4 (640 combos), writing + reading the C0DE pattern each, + // printing INTERESTING lines (EYE ... [MATCH]) and a looped summary + // (EYEBEST / EYEDV) so a UART read finds the read eye (or proves DATAVALID + // never fires, a deeper analog read-strobe issue). Needs the train-control + // window + writeLevel (genip auto-enables both here). + final dram = memories.firstWhere( + (m) => m.type == 'dram', + orElse: () => + throw StateError('ddreye boot program needs a dram region'), + ); + program = RiverDdrEyeSweep( + isa: coreConfig.isa, + uartBase: uart.address, + dramBase: dram.address, + // The train-control window sits immediately above the DRAM array. + trainCtrlBase: dram.address + dram.size, + clockHz: clockFrequency, + ); + case 'ddrverify': + // Minimal DDR probe: prints the STATUS reg (DLL lock / valid flags), then + // a write->readback loop + a retention check. Unambiguous output where the + // eye diagnostics are degraded. Needs the train-control window for STATUS + // (genip builds it here via the board default trainable). + final dram = memories.firstWhere( + (m) => m.type == 'dram', + orElse: () => + throw StateError('ddrverify boot program needs a dram region'), + ); + program = RiverDdrVerify( + isa: coreConfig.isa, + uartBase: uart.address, + dramBase: dram.address, + trainCtrlBase: dram.address + dram.size, + clockHz: clockFrequency, + ); + case 'dramexec': + // Proves the core can FETCH+EXECUTE from DRAM, not just load/store: prints + // "DEXEC", copies a PIC banner stub into DRAM, then jalrs to it. Banner + // streams = I-fetch from DRAM works. Dead after "DEXEC" = the core cannot + // fetch from DRAM. + final dram = memories.firstWhere( + (m) => m.type == 'dram', + orElse: () => + throw StateError('dramexec boot program needs a dram region'), + ); + // The DRAM payload: an external binary via --flash-firmware-path (e.g. a + // Weir linked at the dram base), or the built-in PIC "DRAM EXEC OK" banner + // stub when none is given. RiverDramExec copies to dram.address and jalrs + // there, so the payload must be linked at dram.address. + final List dxBytes; + if (flashFirmwarePath != null) { + dxBytes = await File(flashFirmwarePath!).readAsBytes(); + } else { + final dxStub = RiverHelloWorld( + isa: coreConfig.isa, + uartBase: uart.address, + ramBase: dram.address + 0x10000, + clockHz: clockFrequency, + message: 'DRAM EXEC OK\r\n', + loop: true, + ); + await dxStub.build(); + dxBytes = dxStub.generateBinary(); + } + program = RiverDramExec( + isa: coreConfig.isa, + uartBase: uart.address, + dramBase: dram.address, + clockHz: clockFrequency, + stubBytes: dxBytes, + ); + case 'dramping': + // Like dramexec, but the DRAM stub prints from immediates with pacing + // (no DRAM data buffer, no UART saturation). Clean [PING] lines = fetch + // from DRAM is sound. Garbled = fetch itself is marginal. + final dram = memories.firstWhere( + (m) => m.type == 'dram', + orElse: () => + throw StateError('dramping boot program needs a dram region'), + ); + final dpStub = RiverDramPing( + isa: coreConfig.isa, + uartBase: uart.address, + ); + await dpStub.build(); + program = RiverDramExec( + isa: coreConfig.isa, + uartBase: uart.address, + dramBase: dram.address, + clockHz: clockFrequency, + stubBytes: dpStub.generateBinary(), + ); + case 'dramstress': + case 'dramstress64': + case 'dramstresshi': + // Reproduces the Weir bss-memset hang in isolation: a stub that runs FROM + // DRAM while streaming heavy stores TO DRAM (fetch-under-write contention + // through the MMU arbiter + downsizer + CDC). Steady dots = sound. Dots + // stop/garble = the core wandered mid-sweep. `dramstress64` uses 64-bit + // `sd` (both downsizer lanes) vs `sw`. + final dram = memories.firstWhere( + (m) => m.type == 'dram', + orElse: () => + throw StateError('dramstress boot program needs a dram region'), + ); + final dsStub = RiverDramWriteStress( + isa: coreConfig.isa, + uartBase: uart.address, + dramBase: dram.address, + useSd: bootProgram != 'dramstress', // 64-bit for 64 + hi + // dramstress: sw from a PAGE-MISALIGNED base (0x95d0, == Weir bss_start + // low bits) to reproduce the Weir +1MiB hang outside Weir. + // dramstresshi: 96MB up. dramstress64: aligned sd. + writeOffset: switch (bootProgram) { + 'dramstresshi' => 0x6000000, + 'dramstress' => 0x95d0, + _ => 0x100000, + }, + ); + await dsStub.build(); + program = RiverDramExec( + isa: coreConfig.isa, + uartBase: uart.address, + dramBase: dram.address, + clockHz: clockFrequency, + stubBytes: dsStub.generateBinary(), + ); + case 'hexdump': + // Silent bring-up probe: hex-dump two flash windows straight from ROM, no + // flash-write or maskrom-copy dependency. Region A is the bitstream + // preamble (offset 0), region B the firmware slot at 0x100000. Both read + // by lbu XIP from the flash region base. + final flash = flashRegion; + if (flash == null) { + throw StateError('hexdump boot program needs a flash region'); + } + program = RiverFlashHexdump( + isa: coreConfig.isa, + uartBase: uart.address, + flashBase: flash.address, + clockHz: clockFrequency, + regions: [ + HexdumpRegion( + base: flash.address, + length: 512, + header: 'FLASH @0:', + ), + HexdumpRegion( + base: flash.address + 0x100000, + length: 64, + header: 'FLASH @100000:', + ), + ], + ); + case 'bundleselftest': + // SILENT-bundle diagnostic: mirror the maskrom flash->SRAM copy+jump + // from ROM with checkpoints, so one boot localizes which boundary breaks + // (flash read / copy / jump). Needs flash + sram and the firmware length. + final flash = flashRegion; + final sram = sramRegion; + if (flash == null || sram == null) { + throw StateError( + 'bundleselftest boot program needs both a flash and an sram region', + ); + } + // Build the SAME hexdump firmware the bundle flashes, just to learn its + // length (the copy word count). Independent of the --flash-firmware + // option, so the probe works as a plain --boot-program. + final fw = RiverFlashHexdump( + isa: coreConfig.isa, + uartBase: uart.address, + flashBase: flash.address, + clockHz: clockFrequency, + ); + await fw.build(); + final firmware = fw.generateBinary(); + program = RiverBundleSelfTest( + isa: coreConfig.isa, + uartBase: uart.address, + flashSource: flash.address + flashFirmwareOffset, + copyDest: sram.address, + copyWords: (firmware.length + 3) >> 2, + clockHz: clockFrequency, + ); + case 'xipboot': + // creek "maskrom -> FSBL in XIP -> Weir in DDR" boot with NO SRAM: run + // from the BRAM boot ROM (reset vector), warm up the flash XIP controller + // (the Xilinx STARTUPE2/CCLK path is not fetch-ready at the first + // cold-reset cycle), then jump to the FSBL executing IN PLACE from flash. + // The FSBL is flashed at the flash region base (QSPI 0, free because the + // bitstream is JTAG-loaded). Main Weir sits above it and the FSBL copies + // it into DRAM. + final flash = flashRegion; + if (flash == null) { + throw StateError('xipboot boot program needs a flash region'); + } + final stackMem = memories.firstWhere( + (m) => m.type != 'flash', + orElse: () => flash, + ); + program = RiverMaskrom( + RiverMaskromConfig( + isa: coreConfig.isa, + resetVector: coreConfig.resetVector, + flashSource: flash.address, + copyDest: flash.address, // jump target = FSBL entry (flash base) + copySize: 256, // warmup read window + stackTop: stackMem.address + stackMem.size, + bootMode: RiverBootMode.xipLaunch, + ), + ); + default: + throw UnsupportedError('Unknown boot program: $bootProgram'); + } + await program.build(); + return Uint8List.fromList(program.generateBinary()); + } + + static List _bytesToWords(Uint8List bytes, int bytesPerWord) { + final words = []; + for (var i = 0; i < bytes.length; i += bytesPerWord) { + var word = 0; + for (var b = 0; b < bytesPerWord && (i + b) < bytes.length; b++) { + word |= bytes[i + b] << (b * 8); + } + words.add(word); + } + return words; + } +} + +int _parseSize(String s) { + final upper = s.toUpperCase(); + if (upper.endsWith('G')) { + return int.parse(upper.substring(0, upper.length - 1)) * 1024 * 1024 * 1024; + } + if (upper.endsWith('M')) { + return int.parse(upper.substring(0, upper.length - 1)) * 1024 * 1024; + } + if (upper.endsWith('K')) { + return int.parse(upper.substring(0, upper.length - 1)) * 1024; + } + return int.parse(s); +} diff --git a/packages/river_hdl/lib/src/inferred_rom.dart b/packages/river_hdl/lib/src/inferred_rom.dart new file mode 100644 index 0000000..58d1c69 --- /dev/null +++ b/packages/river_hdl/lib/src/inferred_rom.dart @@ -0,0 +1,91 @@ +import 'package:rohd/rohd.dart'; + +/// Target-agnostic, BRAM-inferable initialised ROM/RAM. +/// +/// Emits behavioural SystemVerilog (a packed [mem] array with an `initial` block +/// and a registered read) that yosys `synth_xilinx` maps to a RAMB (and +/// `synth_ecp5` to a DP16KD). Xilinx counterpart of [Ecp5InitRom]: on Xilinx the +/// flop-based `RegisterFile(resetValue:)` fallback explodes to ~94k FF for the +/// exec microcode ROM. Read latency 1 (registered) and optional single write +/// port, so callers wire it exactly like [Ecp5InitRom]. +class InferredInitRom extends Module with SystemVerilog { + /// Registered read data, one cycle behind [rdAddr]. + Logic get rdData => output('rd_data'); + + final List _contents; + final int _width; + final int _addrW; + final bool _hasWrite; + + InferredInitRom( + Logic clk, { + required List contents, + required int width, + required Logic rdAddr, + Logic? wrEn, + Logic? wrAddr, + Logic? wrData, + super.name = 'inferred_init_rom', + // Distinct stable module name per ROM (two instances with different + // contents/width are different modules), matching Ecp5InitRom. + super.definitionName, + super.reserveDefinitionName = true, + }) : _contents = contents, + _width = width, + _addrW = rdAddr.width, + _hasWrite = wrEn != null { + addInput('clk', clk); + addInput('rd_addr', rdAddr, width: rdAddr.width); + if (wrEn != null) { + addInput('wr_en', wrEn); + addInput('wr_addr', wrAddr!, width: wrAddr.width); + addInput('wr_data', wrData!, width: width); + } + addOutput('rd_data', width: width); + } + + @override + String? definitionVerilog(String definitionType) { + final depth = 1 << _addrW; + final aHi = _addrW - 1; + final wHi = _width - 1; + final b = StringBuffer() + ..writeln('module $definitionType (') + ..writeln(' input logic clk,') + ..writeln(' input logic [$aHi:0] rd_addr,'); + if (_hasWrite) { + b + ..writeln(' input logic wr_en,') + ..writeln(' input logic [$aHi:0] wr_addr,') + ..writeln(' input logic [$wHi:0] wr_data,'); + } + b + ..writeln(' output logic [$wHi:0] rd_data') + ..writeln(');') + // ram_style hint steers yosys/vivado to block RAM. + ..writeln( + ' (* ram_style = "block" *) logic [$wHi:0] mem [0:${depth - 1}];', + ) + ..writeln(' initial begin') + ..writeln( + ' for (int unsigned i = 0; i < $depth; i++) mem[i] = ${_width}\'d0;', + ); + for (var i = 0; i < _contents.length && i < depth; i++) { + final hex = _contents[i].toRadixString(16); + b.writeln(" mem[$i] = ${_width}'h$hex;"); + } + b + ..writeln(' end') + ..writeln(' logic [$wHi:0] rd_q;') + ..writeln(' always_ff @(posedge clk) begin'); + if (_hasWrite) { + b.writeln(' if (wr_en) mem[wr_addr] <= wr_data;'); + } + b + ..writeln(' rd_q <= mem[rd_addr];') + ..writeln(' end') + ..writeln(' assign rd_data = rd_q;') + ..writeln('endmodule'); + return b.toString(); + } +} diff --git a/packages/river_hdl/lib/src/memory/port.dart b/packages/river_hdl/lib/src/memory/port.dart index a94f0d8..98c3ef6 100644 --- a/packages/river_hdl/lib/src/memory/port.dart +++ b/packages/river_hdl/lib/src/memory/port.dart @@ -1,5 +1,5 @@ import 'package:rohd/rohd.dart'; -import 'package:rohd_hcl/rohd_hcl.dart'; +import '../data_port.dart'; /// A sized prefix data port writer to multiple output data ports. /// @@ -48,10 +48,10 @@ class SizedWriteMultiDataPort extends Module { ); if (backingWriteDword != null) { - backingWriteDword = backingWriteDword!.clone() + backingWriteDword = backingWriteDword.clone() ..connectIO( this, - backingWriteDword!, + backingWriteDword, outputTags: {DataPortGroup.control, DataPortGroup.data}, inputTags: {DataPortGroup.integrity}, uniquify: (og) => 'backingWriteDword_$og', @@ -81,8 +81,8 @@ class SizedWriteMultiDataPort extends Module { backingWriteWord.addr < 0, if (backingWriteDword != null) ...[ - backingWriteDword!.en < 0, - backingWriteDword!.addr < 0, + backingWriteDword.en < 0, + backingWriteDword.addr < 0, ], ], orElse: [ @@ -115,11 +115,11 @@ class SizedWriteMultiDataPort extends Module { ]), if (backingWriteDword != null) CaseItem(Const(64, width: 7), [ - backingWriteDword!.en < 1, - backingWriteDword!.addr < source.addr, - backingWriteDword!.data < source.data.slice(70, 7), - source.done < backingWriteDword!.done, - source.valid < backingWriteDword!.valid, + backingWriteDword.en < 1, + backingWriteDword.addr < source.addr, + backingWriteDword.data < source.data.slice(70, 7), + source.done < backingWriteDword.done, + source.valid < backingWriteDword.valid, ]), ], defaultItem: [ @@ -133,8 +133,8 @@ class SizedWriteMultiDataPort extends Module { backingWriteWord.addr < 0, if (backingWriteDword != null) ...[ - backingWriteDword!.en < 0, - backingWriteDword!.addr < 0, + backingWriteDword.en < 0, + backingWriteDword.addr < 0, ], ], ), @@ -150,8 +150,8 @@ class SizedWriteMultiDataPort extends Module { backingWriteWord.addr < 0, if (backingWriteDword != null) ...[ - backingWriteDword!.en < 0, - backingWriteDword!.addr < 0, + backingWriteDword.en < 0, + backingWriteDword.addr < 0, ], ], ), diff --git a/packages/river_hdl/lib/src/microcode_rom.dart b/packages/river_hdl/lib/src/microcode_rom.dart new file mode 100644 index 0000000..583e931 --- /dev/null +++ b/packages/river_hdl/lib/src/microcode_rom.dart @@ -0,0 +1,461 @@ +import 'package:harbor/harbor.dart'; + +class BitRange { + final int start; + final int end; + + const BitRange(this.start, this.end); + const BitRange.single(this.start) : end = start; + + int get width => end - start + 1; + int get mask => (1 << width) - 1; + + BigInt get bigMask => (BigInt.one << width) - BigInt.one; + + int encode(int value) => (value & mask) << start; + int decode(int value) => (value >> start) & mask; + + BigInt bigEncode(BigInt value) => (value & bigMask) << start; + BigInt bigDecode(BigInt value) => (value >> start) & bigMask; +} + +class BitStruct { + final Map mapping; + + const BitStruct(this.mapping); + + Map decode(int value) { + final result = {}; + mapping.forEach((name, range) { + result[name] = range.decode(value); + }); + return result; + } + + int encode(Map fields) { + int result = 0; + fields.forEach((name, val) { + final range = mapping[name]!; + result |= range.encode(val); + }); + return result; + } + + Map bigDecode(BigInt value) { + final result = {}; + mapping.forEach((name, range) { + result[name] = range.bigDecode(value).toInt(); + }); + return result; + } + + BigInt bigEncode(Map fields) { + BigInt result = BigInt.zero; + fields.forEach((name, val) { + final range = mapping[name]!; + result |= range.bigEncode(BigInt.from(val)); + }); + return result; + } + + int get mask { + var map = {}; + for (final field in mapping.entries) { + map[field.key] = field.value.mask; + } + return encode(map); + } + + int get width { + var i = 0; + mapping.forEach((name, val) { + i = (val.end + 1) > i ? (val.end + 1) : i; + }); + return i; + } +} + +int signExtend(int value, int bits) { + final mask = (1 << bits) - 1; + value &= mask; + final signBit = 1 << (bits - 1); + if ((value & signBit) != 0) { + return value | ~mask; + } else { + return value; + } +} + +/// Encoding entry for a single micro-op type in the ROM. +class MicroOpEncoding { + final String name; + final int funct; + final BitStruct Function(RiscVMxlen) struct; + final Map Function(RiscVMicroOp) toMap; + + const MicroOpEncoding({ + required this.name, + required this.funct, + required this.struct, + required this.toMap, + }); + + BigInt encodeMop(RiscVMicroOp op, RiscVMxlen mxlen) => + struct(mxlen).bigEncode(toMap(op)); +} + +/// Decode pattern for matching instructions in hardware. +class OperationDecodePattern { + final int mask; + final int value; + final int opIndex; + final int type; + final int nzfMask; + final int zfMask; + + const OperationDecodePattern( + this.mask, + this.value, + this.opIndex, + this.type, + this.nzfMask, + this.zfMask, + ); + + OperationDecodePattern copyWith({int? opIndex, int? type}) => + OperationDecodePattern( + mask, + value, + opIndex ?? this.opIndex, + type ?? this.type, + nzfMask, + zfMask, + ); + + Map toMap() => { + 'mask': mask, + 'value': value, + 'opIndex': opIndex, + 'type': type, + 'nzfMask': nzfMask, + 'zfMask': zfMask, + }; + + BigInt encode(int opIndexWidth, int typeWidth) => + struct(opIndexWidth, typeWidth).bigEncode(toMap()); + + static BitStruct struct(int opIndexWidth, int typeWidth) { + final mapping = {}; + mapping['mask'] = BitRange(0, 31); + mapping['value'] = BitRange(32, 63); + mapping['opIndex'] = BitRange(64, 64 + opIndexWidth - 1); + mapping['type'] = BitRange( + 64 + opIndexWidth, + 64 + opIndexWidth + typeWidth - 1, + ); + mapping['nzfMask'] = BitRange( + 64 + opIndexWidth + typeWidth, + 64 + opIndexWidth + typeWidth + 31, + ); + mapping['zfMask'] = BitRange( + 64 + opIndexWidth + typeWidth + 32, + 64 + opIndexWidth + typeWidth + 32 + 31, + ); + return BitStruct(mapping); + } +} + +/// Microcode ROM builder that works with Harbor's RiscVIsaConfig. +/// +/// Takes an ISA configuration and compiles all operations and their +/// microcode sequences into hardware-friendly ROM representations. +class MicrocodeRom { + final RiscVIsaConfig isa; + final List operations; + final Map map; + + MicrocodeRom(this.isa, {List encodings = const []}) + : operations = isa.allOperations, + map = _buildDecodeMap(isa.allOperations) { + if (encodings.isNotEmpty) mopEncodings = encodings; + } + + int get patternWidth { + final opIdxBits = opIndexWidth; + final typeBits = _formatNames.length.bitLength; + return OperationDecodePattern.struct(opIdxBits, typeBits).width; + } + + int get opIndexWidth => + decodeLookup.keys.fold(0, (a, b) => a > b ? a : b).bitLength; + + int mopWidth(RiscVMxlen mxlen) => operations + .map((op) => _maxMopWidth(op, mxlen)) + .fold(0, (a, b) => a > b ? a : b); + + int mopIndexWidth(RiscVMxlen mxlen) => encodedMops(mxlen).length.bitLength; + + List encodedMops(RiscVMxlen mxlen) => operations + .map((op) => _encodeMops(op, mxlen)) + .fold([], (a, b) => [...a, ...b]); + + Map get decodeLookup { + final result = {}; + var i = 0; + for (final e in map.entries) { + result[i] = e.key.copyWith(opIndex: i); + i += e.value.microcode.length + 1; + } + return result; + } + + Set get _formatNames { + final result = {}; + for (final op in operations) { + result.add(instrType(op)); + } + return result; + } + + List get encodedPatterns { + final opIdxBits = opIndexWidth; + final typeBits = _formatNames.length.bitLength; + return decodeLookup.values + .map((p) => p.encode(opIdxBits, typeBits)) + .toList(); + } + + RiscVOperation? lookup(int instr) { + for (final entry in map.entries) { + final nzfMatch = + entry.key.nzfMask == 0 || (instr & entry.key.nzfMask) != 0; + final zfMatch = entry.key.zfMask == 0 || (instr & entry.key.zfMask) == 0; + if ((instr & entry.key.mask) == entry.key.value && nzfMatch && zfMatch) { + return entry.value; + } + } + return null; + } + + static Map _buildDecodeMap( + List operations, + ) { + // Build format name → index mapping + final formatNames = []; + for (final op in operations) { + final name = instrType(op); + if (!formatNames.contains(name)) formatNames.add(name); + } + + final result = {}; + var i = 0; + for (final op in operations) { + final typeIndex = formatNames.indexOf(instrType(op)); + final pattern = _buildDecodePattern(op, i, typeIndex); + result[pattern] = op; + i += op.microcode.length + 1; + } + return result; + } + + static OperationDecodePattern _buildDecodePattern( + RiscVOperation op, + int index, + int typeIndex, + ) { + // Compressed ops live in quadrants 0/1/2 (bits[1:0] != 0b11): opcode is in + // bits[1:0] and funct3 in bits[15:13]. 32-bit ops have opcode in bits[6:0] + // and funct3 in bits[14:12]. The two pattern spaces are disjoint because a + // 32-bit instruction always has bits[1:0] == 0b11. + final isCompressed = (op.opcode & 0x3) != 0x3; + int mask; + int value; + if (isCompressed) { + mask = 0x3; + value = op.opcode & 0x3; + if (op.funct3 != null) { + mask |= 0x7 << 13; + value |= op.funct3! << 13; + } + } else { + mask = 0x7F; // opcode always 7 bits + value = op.opcode & 0x7F; + if (op.funct3 != null) { + mask |= (0x7 << 12); + value |= (op.funct3! << 12); + } + if (op.funct7 != null) { + // RV64 shift-immediates (slli/srli/srai = OP-IMM, funct3 1/5) encode a + // 6-bit shamt where bit 25 is shamt[5]; match only funct6 (bits 31:26) + // so shamt>=32 still decodes. Word variants (slliw/… = OP-IMM-32) keep + // the 5-bit shamt + full funct7 match. + final isShiftImm = + (op.opcode & 0x7F) == 0x13 && + (op.funct3 == 0x1 || op.funct3 == 0x5); + if (isShiftImm) { + mask |= (0x3F << 26); + value |= ((op.funct7! >> 1) << 26); + } else { + mask |= (0x7F << 25); + value |= (op.funct7! << 25); + } + } + } + + // Raw-bit discriminators (e.g. c.mv vs c.add differ in bit 12). + if (op.matchMask != null) { + mask |= op.matchMask!; + value |= op.matchValue ?? 0; + } + + return OperationDecodePattern( + mask, + value, + index, + typeIndex, + op.nonZeroMask ?? 0, + op.zeroMask ?? 0, + ); + } + + static int _maxMopWidth(RiscVOperation op, RiscVMxlen mxlen) { + if (op.microcode.isEmpty) return 0; + return op.microcode + .map((mop) { + final enc = _findEncoding(mop); + if (enc != null) return enc.struct(mxlen).width; + return _mopFunct(mop).bitLength + 5; + }) + .fold(0, (a, b) => a > b ? a : b); + } + + static List _encodeMops(RiscVOperation op, RiscVMxlen mxlen) => [ + BigInt.from(op.microcode.length), + ...op.microcode.map((mop) { + final enc = _findEncoding(mop); + if (enc != null) return enc.encodeMop(mop, mxlen); + return BigInt.from(_mopFunct(mop)); + }), + ]; + + static MicroOpEncoding? _findEncoding(RiscVMicroOp mop) { + final funct = _mopFunct(mop); + try { + return mopEncodings.firstWhere((e) => e.funct == funct); + } catch (_) { + return null; + } + } + + /// Register the micro-op encoding table. Must be set before + /// calling [encodedMops] or [mopWidth]. + static List mopEncodings = const []; + + /// Builds a map from format name to the HarborBitStruct for that format. + Map get typeStructs { + final result = {}; + for (final op in operations) { + final name = instrType(op); + result.putIfAbsent(name, () => op.format); + } + return result; + } + + /// Builds a map of field name -> (format name -> BitRange). + /// + /// Extracts all field names from all formats and maps them + /// to their bit ranges per format type. + Map> get fields { + final result = >{}; + for (final op in operations) { + final formatName = instrType(op); + for (final field in op.format.fields.entries) { + result.putIfAbsent(field.key, () => {}); + result[field.key]!.putIfAbsent( + formatName, + () => BitRange(field.value.start, field.value.end), + ); + } + } + return result; + } + + /// Map from operation index to the RiscVOperation. + Map get execLookup { + final result = {}; + var i = 0; + for (final op in map.values) { + result[i] = op; + i += op.microcode.length + 1; + } + return result; + } + + /// All operation indices used in the decode map. + List get opIndices => decodeLookup.keys.toList(); + + /// Micro-op sequences for each operation, keyed by opIndex. + Map ops})> get microOpSequences { + final result = ops})>{}; + var i = 0; + for (final op in map.values) { + result[i] = (ops: op.microcode); + i += op.microcode.length + 1; + } + return result; + } + + static String instrType(RiscVOperation op) { + final fmt = op.format; + // Use the format name if available (avoids const canonicalization issues) + if (fmt.name != null) return fmt.name!; + // Fallback: check for CSR/system I-type variants by field names + if (fmt.fields.containsKey('csr')) return 'SystemIType'; + return 'Unknown_${fmt.fields.keys.join('_')}'; + } + + static String mopType(MicroOpEncoding enc) => enc.name; + + /// The set of micro-op funct codes this ROM actually emits. Any funct-Case + /// arm in the dynamic execution unit whose funct is not in this set is dead + /// logic for this config and can be dropped (it can never be reached). + Set get emittedFuncts { + final result = {}; + for (final op in map.values) { + for (final mop in op.microcode) { + result.add(_mopFunct(mop)); + } + } + return result; + } + + static int _mopFunct(RiscVMicroOp mop) => switch (mop) { + RiscVWriteCsr() => 1, + RiscVReadRegister() => 2, + RiscVWriteRegister() => 3, + RiscVAlu() => 5, + RiscVBranch() => 6, + RiscVUpdatePc() => 7, + RiscVMemLoad() => 8, + RiscVMemStore() => 9, + RiscVTrapOp() => 10, + RiscVTlbFenceOp() => 11, + RiscVTlbInvalidateOp() => 12, + RiscVFenceOp() => 13, + RiscVReturnOp() => 14, + RiscVWriteLinkRegister() => 15, + RiscVInterruptHold() => 16, + RiscVLoadReserved() => 17, + RiscVStoreConditional() => 18, + RiscVAtomicMemory() => 19, + RiscVReadCsr() => 22, + RiscVCopyField() => 23, + RiscVSetField() => 24, + RiscVFpuOp() => 25, + // wfi's wait micro-op. Needs a real funct (not the 0 catch-all, which is the + // dynamic interpreter's empty padding case) so cycleMicrocode can dispatch it + // and advance; otherwise wfi stalls the creek path forever. + RiscVWaitForInterrupt() => 20, + _ => 0, + }; +} diff --git a/packages/river_hdl/lib/src/soc.dart b/packages/river_hdl/lib/src/soc.dart index b4f044c..29b5e22 100644 --- a/packages/river_hdl/lib/src/soc.dart +++ b/packages/river_hdl/lib/src/soc.dart @@ -1,103 +1,7 @@ -import 'package:river/river.dart'; -import 'package:rohd/rohd.dart'; -import 'package:rohd_bridge/rohd_bridge.dart'; - -import 'core.dart'; -import 'dev.dart'; -import 'devices.dart'; - -class RiverSoCIP extends BridgeModule { - final RiverSoC config; - - RiverSoCIP( - this.config, { - Map> deviceOptions = const {}, - Map deviceFactory = kDeviceModuleFactory, - List staticInstructions = const [], - }) : super('RiverSoC') { - createPort('reset', PortDirection.input); - - final reset = port('reset'); - - for (final clk in config.clocks) { - createPort('clk_${clk.name}', PortDirection.input); - } - - for (final port in config.ports) { - createPort( - port.name, - port.isOutput ? PortDirection.output : PortDirection.input, - width: port.width, - ); - } - - final mxlen = config.cores.first.mxlen; - - List devices = []; - - for (final entry in config.devices.indexed) { - final index = entry.$1; - final devConfig = entry.$2; - - final dev = addSubModule( - deviceFactory.containsKey(devConfig.compatible) - ? deviceFactory[devConfig.compatible]!( - mxlen, - devConfig, - deviceOptions[devConfig.name] ?? {}, - ) - : DeviceModule(mxlen, devConfig), - ); - devices.add(dev); - - connectPorts(reset, dev.port('reset')); - - if (devConfig.clock != null) { - final clk = port('clk_${devConfig.clock!.name}'); - connectPorts(clk, dev.port('clk')); - } - - for (final p in devConfig.ports) { - final host = config.ports.firstWhere( - (h) => h.devices[devConfig.name] == p.name, - ); - - if (p.isOutput) - connectPorts(dev.port(p.name), port(host.name)); - else - connectPorts(port(host.name), dev.port(p.name)); - } - } - - for (final coreConfig in config.cores) { - final clk = port('clk_${coreConfig.clock.name}'); - - final core = addSubModule( - RiverCoreIP(coreConfig, staticInstructions: staticInstructions), - ); - - connectPorts(clk, core.port('clk')); - connectPorts(reset, core.port('reset')); - - for (final entry in coreConfig.mmu.blocks.indexed) { - final index = entry.$1; - final block = entry.$2; - - final dev = devices.firstWhere( - (dev) => dev.config.accessor?.path == block.accessor.path, - ); - - if (dev.config.range == null) continue; - - connectInterfaces( - core.interface('mmioRead$index'), - dev.interface('mmioRead'), - ); - connectInterfaces( - core.interface('mmioWrite$index'), - dev.interface('mmioWrite'), - ); - } - } - } -} +// River SoC generation is handled by GenIpConfig.buildSoC() in genip.dart, +// which constructs a HarborSoC directly. +// +// For programmatic use: +// final config = GenIpConfig(name: 'my_soc', coreModel: 'rc1-s', ...); +// final soc = config.buildSoC(); +// await soc.generateAll(Directory('output')); diff --git a/packages/river_hdl/lib/src/usb_dfu_subsystem.dart b/packages/river_hdl/lib/src/usb_dfu_subsystem.dart new file mode 100644 index 0000000..3d6e2e1 --- /dev/null +++ b/packages/river_hdl/lib/src/usb_dfu_subsystem.dart @@ -0,0 +1,592 @@ +import 'package:rohd/rohd.dart'; +import 'package:rohd_bridge/rohd_bridge.dart'; +// river.dart re-exports harbor (UsbEp0Engine, UsbDfuRamSink, Wishbone*, +// BusSlavePort, HarborDeviceTreeNode(Provider), BusAddressRange, etc.). +import 'package:river/river.dart'; + +/// [BridgeModule] wrapper that merges the two SoC masters (River core + DFU +/// RAM-sink writeback master) onto a single decoder master. Exposes two CONSUMER +/// master ports (`m0`, `m1`) the upstream masters connect into and one PROVIDER +/// `slave` port into the decoder. Single bus clock domain (12 MHz `bus_clk` / +/// `bus_reset`); the USB crossing already happened in [UsbDfuRamSink]'s CDC FIFO. +class RiverWishboneArbiter extends BridgeModule { + RiverWishboneArbiter(WishboneConfig config, {String? name}) + : super('RiverWishboneArbiter', name: name ?? 'wb_arbiter2') { + createPort('clk', PortDirection.input); + createPort('reset', PortDirection.input); + + // Two upstream masters: this module is the CONSUMER (it receives the + // master's CYC/ADR/... and drives ACK/DAT_MISO back), so the upstream + // PROVIDER interfaces connect down into these. + final m0Ref = addInterface( + WishboneInterface(config), + name: 'm0', + role: PairRole.consumer, + ); + final m1Ref = addInterface( + WishboneInterface(config), + name: 'm1', + role: PairRole.consumer, + ); + // Downstream merged slave: this module is the PROVIDER, driving the decoder. + final slaveRef = addInterface( + WishboneInterface(config), + name: 'slave', + role: PairRole.provider, + ); + + final m0 = m0Ref.internalInterface as WishboneInterface; + final m1 = m1Ref.internalInterface as WishboneInterface; + final s = slaveRef.internalInterface as WishboneInterface; + + // Arbitration is inline (not via the raw WishboneArbiter Module): the slave + // response signals (ACK/DAT_MISO) driven in by the parent decoder must be + // consumed within this module's boundary; nesting the raw arbiter would tap + // them across the module edge, which ROHD forbids. + // + // Grant policy: registered CYC-held round-robin. The grant only changes while + // no transfer is in flight, so a burst is never torn mid-transaction. + final clk = input('clk'); + final reset = input('reset'); + + // grantM1: 0 -> master 0 (core) is granted, 1 -> master 1 (DFU sink). + final grantM1 = Logic(name: 'grant_m1'); + // last: who was served last, for round-robin fairness. + final last = Logic(name: 'last_grant'); + + final m0Req = m0.cyc; + final m1Req = m1.cyc; + final grantedCyc = mux(grantM1, m1Req, m0Req); // current grantee's CYC + final busIdle = ~grantedCyc; + + Sequential(clk, [ + If( + reset, + then: [grantM1 < Const(0), last < Const(0)], + orElse: [ + // Re-arbitrate only when the bus is idle (no granted transfer running). + If( + busIdle, + then: [ + // Round-robin: prefer the master that was NOT served last. + If( + last & m0Req, + then: [grantM1 < Const(0), last < Const(0)], + orElse: [ + If( + ~last & m1Req, + then: [grantM1 < Const(1), last < Const(1)], + orElse: [ + // Otherwise keep whichever single master is requesting. + If(m0Req, then: [grantM1 < Const(0), last < Const(0)]), + If( + m1Req & ~m0Req, + then: [grantM1 < Const(1), last < Const(1)], + ), + ], + ), + ], + ), + ], + ), + ], + ), + ]); + + // Forward the granted master to the slave. + s.cyc <= mux(grantM1, m1.cyc, m0.cyc); + s.stb <= mux(grantM1, m1.stb, m0.stb); + s.we <= mux(grantM1, m1.we, m0.we); + s.adr <= mux(grantM1, m1.adr, m0.adr); + s.datMosi <= mux(grantM1, m1.datMosi, m0.datMosi); + s.sel <= mux(grantM1, m1.sel, m0.sel); + + // Route the slave response back: ACK gated per master, DAT_MISO broadcast. + m0.ack <= s.ack & ~grantM1; + m1.ack <= s.ack & grantM1; + m0.datMiso <= s.datMiso; + m1.datMiso <= s.datMiso; + } +} + +/// Small Wishbone SLAVE status/control block the maskrom polls to drive a USB +/// DFU download into RAM. Single-cycle registered ACK, bus (12 MHz) domain. +/// +/// Word-mapped registers (word offset within [baseAddress]): +/// 0x00 STATUS (R) bit0 = image_ready (sticky from the RAM sink). +/// 0x04 CONTROL (R/W) bit0 = usb_enable: write 1 to assert the USB pull-up +/// enable so the host enumerates. Reads back latched value. +/// 0x08 ENTRY (R) RAM entry address the image landed at (= sink loadBase). +/// 0x0C BYTES (R) image bytes written so far (debug). +/// +/// Status inputs come from [UsbDfuRamSink]'s bus-domain outputs; usb_enable is +/// the only writable bit, surfaced as an output to gate the USB pull-up. +class RiverDfuStatus extends BridgeModule with HarborDeviceTreeNodeProvider { + final int baseAddress; + final int busAddressWidth; + final int busDataWidth; + + /// The control bit the CPU writes to enable USB (drives the pull-up enable). + Logic get usbEnable => output('usb_enable'); + + late final BusSlavePort bus; + + RiverDfuStatus({ + required this.baseAddress, + this.busAddressWidth = 32, + this.busDataWidth = 32, + String? name, + }) : super('RiverDfuStatus', name: name ?? 'dfu_status') { + createPort('clk', PortDirection.input); + createPort('reset', PortDirection.input); + + // Bus-domain status inputs from the RAM sink. + createPort('image_ready', PortDirection.input); + createPort('entry_addr', PortDirection.input, width: busAddressWidth); + createPort('bytes_written', PortDirection.input, width: 32); + + addOutput('usb_enable'); + + bus = BusSlavePort.create( + module: this, + name: 'bus', + protocol: BusProtocol.wishbone, + addressWidth: busAddressWidth, + dataWidth: busDataWidth, + ); + + final clk = input('clk'); + final reset = input('reset'); + + final imageReadyIn = input('image_ready'); + final entryAddrIn = input('entry_addr'); + final bytesWrittenIn = input('bytes_written'); + + // Sticky image_ready: once the sink pulses/holds it, latch it so the + // maskrom poll cannot miss a transient. + final imageReadySticky = Logic(name: 'image_ready_sticky'); + // usb_enable control bit (R/W). + final usbEnableReg = Logic(name: 'usb_enable_reg'); + // Registered ACK: one cycle per strobe. + final ackReg = Logic(name: 'dfu_status_ack'); + + final stb = bus.stb; + final we = bus.we; + // Word offset (drop the in-word byte bits). A 32-bit bus has a 4-byte word; + // the register select is addr bits above the byte offset. + final wordSel = bus.addr.getRange(2, 4); // bits [3:2] -> 0..3 + + Sequential(clk, [ + If( + reset, + then: [ + imageReadySticky < Const(0), + usbEnableReg < Const(0), + ackReg < Const(0), + ], + orElse: [ + // Latch image_ready forever once seen. + If(imageReadyIn, then: [imageReadySticky < Const(1)]), + + // ACK is a single-cycle pulse on an unacked strobe. + ackReg < (stb & ~ackReg), + + // Register write: CONTROL (word offset 1, byte addr 0x04). + If( + stb & we & ~ackReg & wordSel.eq(Const(1, width: 2)), + then: [usbEnableReg < bus.dataIn.getRange(0, 1)], + ), + ], + ), + ]); + + bus.ack <= ackReg; + output('usb_enable') <= usbEnableReg; + + // Read mux: select the addressed register, zero-extended to the bus width. + final statusWord = imageReadySticky + .zeroExtend(busDataWidth) + .named('status_word'); + final controlWord = usbEnableReg + .zeroExtend(busDataWidth) + .named('control_word'); + final entryWord = entryAddrIn.zeroExtend(busDataWidth).named('entry_word'); + final bytesWord = bytesWrittenIn + .zeroExtend(busDataWidth) + .named('bytes_word'); + + bus.dataOut <= + mux( + wordSel.eq(Const(0, width: 2)), + statusWord, + mux( + wordSel.eq(Const(1, width: 2)), + controlWord, + mux(wordSel.eq(Const(2, width: 2)), entryWord, bytesWord), + ), + ); + } + + @override + HarborDeviceTreeNode get dtNode => HarborDeviceTreeNode( + compatible: ['river,dfu-status'], + reg: BusAddressRange(baseAddress, 0x1000), + ); +} + +/// The USB DFU subsystem: EP0 enumeration engine + RAM-sink writeback master + +/// line tristate pads, so the SoC sees one bus MASTER and a few pads. +/// +/// Dual clock domain: `usb_clk`/`usb_reset` is the raw 48 MHz osc (already the +/// SoC `clk`; runs [UsbEp0Engine] and the USB side of [UsbDfuRamSink]). +/// `bus_clk`/`bus_reset` is the 12 MHz core/bus domain (the sink's Wishbone +/// master + CDC FIFO bus side). The FIFO inside the sink bridges the two. +/// +/// Exposed: PROVIDER Wishbone `bus` (RAM-sink master); `usb_dp`/`usb_dm` inOut +/// pads (PHY dp_out/dm_out + oe tristate, pad fed back to the PHY); `usb_pullup` +/// (D+ enable, gated by `usb_enable`); status outputs image_ready/entry_addr/ +/// bytes_written and a `usb_enable` input for the [RiverDfuStatus] slave. +class RiverDfuSubsystem extends BridgeModule { + final int loadBase; + final int busAddressWidth; + final int busDataWidth; + + RiverDfuSubsystem({ + this.loadBase = 0x80000000, + this.busAddressWidth = 32, + this.busDataWidth = 32, + String? name, + }) : super('RiverDfuSubsystem', name: name ?? 'usb_dfu') { + // Bus-domain clock/reset (12 MHz). Named clk/reset so addMaster auto-wires + // them from the bus domain; the 48 MHz usb_clk/usb_reset are wired manually. + createPort('clk', PortDirection.input); + createPort('reset', PortDirection.input); + createPort('usb_clk', PortDirection.input); + createPort('usb_reset', PortDirection.input); + + // USB line pads (bidirectional) + pull-up enable + the user button. + createPort('usb_dp', PortDirection.inOut); + createPort('usb_dm', PortDirection.inOut); + addOutput('usb_pullup'); + + // Control/status bridge to the RiverDfuStatus slave (bus domain). + createPort('usb_enable', PortDirection.input); + addOutput('image_ready'); + addOutput('entry_addr', width: busAddressWidth); + addOutput('bytes_written', width: 32); + + final usbClk = input('usb_clk'); + final usbReset = input('usb_reset'); + final busClk = input('clk'); + final busReset = input('reset'); + + // EP0 enumeration engine (48 MHz USB domain). + final engine = UsbEp0Engine(name: 'ep0'); + addSubModule(engine); + engine.input('clk').srcConnection! <= usbClk; + engine.input('reset').srcConnection! <= usbReset; + + // RAM writeback sink (dual domain, Wishbone master). + final ramSink = UsbDfuRamSink( + loadBase: loadBase, + busAddressWidth: busAddressWidth, + busDataWidth: busDataWidth, + // Depth-8 is plenty: sink_ready back-pressure means the engine never + // outruns the bus drain, so a deep FIFO buys nothing but local cells. + fifoDepth: 8, + name: 'ram_sink', + ); + addSubModule(ramSink); + ramSink.input('usb_clk').srcConnection! <= usbClk; + ramSink.input('usb_reset').srcConnection! <= usbReset; + ramSink.input('bus_clk').srcConnection! <= busClk; + ramSink.input('bus_reset').srcConnection! <= busReset; + + // engine <-> ramSink sink stream (USB domain). + ramSink.input('sink_data').srcConnection! <= engine.output('sink_data'); + ramSink.input('sink_valid').srcConnection! <= engine.output('sink_valid'); + ramSink.input('dnload_done').srcConnection! <= engine.output('dnload_done'); + ramSink.input('image_target').srcConnection! <= + engine.output('image_target'); + ramSink.input('alt_setting').srcConnection! <= engine.output('alt_setting'); + engine.input('sink_ready').srcConnection! <= ramSink.output('sink_ready'); + + // Status outputs (bus domain) to the slave. + output('image_ready') <= ramSink.output('image_ready'); + output('entry_addr') <= ramSink.output('entry_addr'); + output('bytes_written') <= ramSink.output('bytes_written'); + + // USB line tristate pads: drive when oe is high, else high-Z, and feed the + // pad value back into the PHY's dp/dm inputs. + final dpPad = inOut('usb_dp'); + final dmPad = inOut('usb_dm'); + final oe = engine.output('oe'); + final dpDrive = TriStateBuffer(engine.output('dp_out'), enable: oe); + final dmDrive = TriStateBuffer(engine.output('dm_out'), enable: oe); + dpPad <= dpDrive.out; + dmPad <= dmDrive.out; + engine.input('dp').srcConnection! <= dpPad; + engine.input('dm').srcConnection! <= dmPad; + + // Pull-up enable, gated by the CPU-written usb_enable so the device only + // connects once the maskrom has armed DFU mode. + output('usb_pullup') <= engine.output('usb_pullup') & input('usb_enable'); + + // Expose the RAM-sink Wishbone master as this subsystem's `bus`. + pullUpInterface(ramSink.interface('bus'), newIntfName: 'bus'); + } +} + +/// The lean, software-driven USB DFU subsystem (CAR target): the cheap +/// alternative to [RiverDfuSubsystem] for the LFE5U-25F. Drops the whole +/// hardware RAM-sink tier (no [UsbDfuRamSink], no [HarborCdcFifo], no +/// [RiverWishboneArbiter], no second bus master); this block is a single MMIO +/// SLAVE and the River core is the only bus participant. Keeps the PHY (inside +/// [UsbEp0Engine]) and a small register file with a one-byte receive handshake. +/// +/// The maskrom drives the download in software: poll STATUS for a captured byte, +/// read RXDATA, store into Cache-as-RAM (via the rcache CSRs), ack to release the +/// next byte. No SRAM region; the DFU target is CAR. +/// +/// Byte path / CDC: engine `sink_valid`/`sink_data` are 48 MHz USB domain, the +/// bus is 12 MHz. A single-entry two-phase handshake crosses each byte: a USB +/// `producer toggle` flips per byte, the bus domain syncs it ([HarborCdcSync]) +/// and on an edge captures RXDATA + sets sticky `rx_valid`; the CPU's CONTROL +/// `advance` write flips a `consumer toggle` synced back so `sink_ready` re-arms. +/// sink_ready == (producer == consumer) is the depth-1 back-pressure, so no deep +/// FIFO is needed. +/// +/// Word-mapped registers (word offsets within [baseAddress]): +/// 0x00 STATUS (R) bit0 = rx_valid, bit1 = dnload_done, bit2 = configured, +/// bits[7:4] = dfu_state, rest reserved 0. +/// 0x04 CONTROL (R/W) bit0 = usb_enable (pull-up/connect), bit1 = advance +/// (W1P: ack current byte, release next). usb_enable reads back. +/// 0x08 RXDATA (R) bits[7:0] = captured download byte. +/// 0x0C BYTES (R) running count of bytes captured (debug). +class RiverDfuSubsystemSw extends BridgeModule + with HarborDeviceTreeNodeProvider { + final int baseAddress; + final int busAddressWidth; + final int busDataWidth; + + RiverDfuSubsystemSw({ + required this.baseAddress, + this.busAddressWidth = 32, + this.busDataWidth = 32, + String? name, + }) : super('RiverDfuSubsystemSw', name: name ?? 'usb_dfu_sw') { + // Bus-domain clock/reset (12 MHz). Auto-wired from the bus domain by + // addPeripheral. The 48 MHz usb_clk/usb_reset are wired manually. + createPort('clk', PortDirection.input); + createPort('reset', PortDirection.input); + createPort('usb_clk', PortDirection.input); + createPort('usb_reset', PortDirection.input); + + // USB line pads (bidirectional) + pull-up enable. + createPort('usb_dp', PortDirection.inOut); + createPort('usb_dm', PortDirection.inOut); + addOutput('usb_pullup'); + + final usbClk = input('usb_clk'); + final usbReset = input('usb_reset'); + final busClk = input('clk'); + final busReset = input('reset'); + + // MMIO slave (bus / 12 MHz domain). + final bus = BusSlavePort.create( + module: this, + name: 'bus', + protocol: BusProtocol.wishbone, + addressWidth: busAddressWidth, + dataWidth: busDataWidth, + ); + + // EP0 enumeration engine + PHY (48 MHz USB domain). + final engine = UsbEp0Engine(name: 'ep0'); + addSubModule(engine); + engine.input('clk').srcConnection! <= usbClk; + engine.input('reset').srcConnection! <= usbReset; + + final sinkData = engine.output('sink_data'); // [7:0], USB domain + final sinkValid = engine.output('sink_valid'); // pulse, USB domain + final dnloadDoneUsb = engine.output('dnload_done'); // pulse, USB domain + + // Bus-domain control regs first (so the consumer toggle exists). + final usbEnableReg = Logic(name: 'usb_enable_reg'); + final advancePulse = Logic(name: 'advance_pulse'); // bus-domain W1P decode + // consumerToggle (bus domain): flips each time the CPU acks a byte. + final consumerToggle = Logic(name: 'consumer_toggle'); + + // Synchronize the consumer toggle into the USB domain so the engine knows + // its last byte was consumed and it may release the next. + final consSyncUsb = HarborCdcSync(stages: 2, name: 'cons_sync'); + addSubModule(consSyncUsb); + consSyncUsb.input('async_in').srcConnection! <= consumerToggle; + consSyncUsb.input('dst_clk').srcConnection! <= usbClk; + consSyncUsb.input('dst_reset').srcConnection! <= usbReset; + final consumerInUsb = consSyncUsb.output('sync_out'); + + // USB-domain producer side: latch byte + flip producer toggle. + final producerToggle = Logic(name: 'producer_toggle'); + final byteHold = Logic(name: 'byte_hold', width: 8); + final doneHold = Logic(name: 'done_hold'); + // sink_ready: the engine may push the next byte/marker only once the prior + // one has been consumed, i.e. producer and (synchronized) consumer toggles + // match. This is the depth-1 back-pressure that replaces the deep FIFO. + final sinkReady = producerToggle.eq(consumerInUsb).named('sink_ready'); + + Sequential(usbClk, [ + If( + usbReset, + then: [ + producerToggle < Const(0), + byteHold < Const(0, width: 8), + doneHold < Const(0), + ], + orElse: [ + // Capture a byte (or the done marker) only when the engine actually + // strobes AND we are allowed to advance (sink_ready high). + If( + sinkReady & (sinkValid | dnloadDoneUsb), + then: [ + byteHold < sinkData, + doneHold < dnloadDoneUsb, + producerToggle < ~producerToggle, + ], + ), + ], + ), + ]); + + // Drive the engine's back-pressure input. + engine.input('sink_ready').srcConnection! <= sinkReady; + + // Synchronize the producer toggle into the bus domain. + final prodSyncBus = HarborCdcSync(stages: 2, name: 'prod_sync'); + addSubModule(prodSyncBus); + prodSyncBus.input('async_in').srcConnection! <= producerToggle; + prodSyncBus.input('dst_clk').srcConnection! <= busClk; + prodSyncBus.input('dst_reset').srcConnection! <= busReset; + final producerInBus = prodSyncBus.output('sync_out'); + + // Bus-domain capture + register file. + final rxData = Logic(name: 'rx_data_reg', width: 8); + final rxValid = Logic(name: 'rx_valid_reg'); + final dnloadDoneSticky = Logic(name: 'dnload_done_sticky'); + final bytesCount = Logic(name: 'bytes_count', width: 32); + final ackReg = Logic(name: 'sw_ack'); + // Last seen producer toggle (bus domain) to detect a fresh byte edge. + final prodSeen = Logic(name: 'prod_seen'); + + final stb = bus.stb; + final we = bus.we; + final wordSel = bus.addr.getRange(2, 4); // bits [3:2] -> 0..3 + + // A new byte is present when the synchronized producer toggle differs from + // what we last captured. + final newByte = producerInBus.neq(prodSeen).named('new_byte'); + + Sequential(busClk, [ + If( + busReset, + then: [ + usbEnableReg < Const(0), + consumerToggle < Const(0), + rxData < Const(0, width: 8), + rxValid < Const(0), + dnloadDoneSticky < Const(0), + bytesCount < Const(0, width: 32), + ackReg < Const(0), + prodSeen < Const(0), + advancePulse < Const(0), + ], + orElse: [ + // Single-cycle registered ACK. + ackReg < (stb & ~ackReg), + + // Capture a freshly-crossed byte into RXDATA, set rx_valid. + If( + newByte, + then: [ + rxData < byteHold, + prodSeen < producerInBus, + rxValid < Const(1), + If(doneHold, then: [dnloadDoneSticky < Const(1)]), + bytesCount < bytesCount + Const(1, width: 32), + ], + ), + + // Register writes (CONTROL at word offset 1). + advancePulse < Const(0), + If( + stb & we & ~ackReg & wordSel.eq(Const(1, width: 2)), + then: [ + usbEnableReg < bus.dataIn.getRange(0, 1), + // advance (bit1, write-1-pulse): ack the current byte. + If( + bus.dataIn.getRange(1, 2).eq(Const(1, width: 1)), + then: [ + consumerToggle < ~consumerToggle, + rxValid < Const(0), + advancePulse < Const(1), + ], + ), + ], + ), + ], + ), + ]); + + bus.ack <= ackReg; + + // Read mux. + final dfuState = engine.output('dfu_state'); // [3:0], USB domain (slow) + final configured = engine.output('configured'); + // configured/dfu_state are slow status; sampling them directly across the + // domain is acceptable for polling (they change at human/USB-transfer rate). + final statusWord = [ + Const(0, width: busDataWidth - 8), + dfuState, // [7:4] + Const(0), // [3] reserved + configured, // [2] + dnloadDoneSticky, // [1] + rxValid, // [0] + ].swizzle().named('status_word'); + final controlWord = usbEnableReg + .zeroExtend(busDataWidth) + .named('ctrl_word'); + final rxWord = rxData.zeroExtend(busDataWidth).named('rx_word'); + final bytesWord = bytesCount.zeroExtend(busDataWidth).named('bytes_word'); + + bus.dataOut <= + mux( + wordSel.eq(Const(0, width: 2)), + statusWord, + mux( + wordSel.eq(Const(1, width: 2)), + controlWord, + mux(wordSel.eq(Const(2, width: 2)), rxWord, bytesWord), + ), + ); + + // USB line tristate pads. + final dpPad = inOut('usb_dp'); + final dmPad = inOut('usb_dm'); + final oe = engine.output('oe'); + final dpDrive = TriStateBuffer(engine.output('dp_out'), enable: oe); + final dmDrive = TriStateBuffer(engine.output('dm_out'), enable: oe); + dpPad <= dpDrive.out; + dmPad <= dmDrive.out; + engine.input('dp').srcConnection! <= dpPad; + engine.input('dm').srcConnection! <= dmPad; + + // Pull-up enable, gated by the CPU-written usb_enable. + output('usb_pullup') <= engine.output('usb_pullup') & usbEnableReg; + } + + @override + HarborDeviceTreeNode get dtNode => HarborDeviceTreeNode( + compatible: ['river,dfu-sw'], + reg: BusAddressRange(baseAddress, 0x1000), + ); +} diff --git a/packages/river_hdl/pubspec.yaml b/packages/river_hdl/pubspec.yaml index d5c1f8a..4ef9c01 100644 --- a/packages/river_hdl/pubspec.yaml +++ b/packages/river_hdl/pubspec.yaml @@ -5,23 +5,26 @@ resolution: workspace # repository: https://github.com/my_org/my_repo environment: - sdk: ^3.9.3 + sdk: ^3.11.2 # Add regular dependencies here. dependencies: args: ^2.7.0 + bintools: ^1.0.0 + harbor: ^0.0.1 logging: ^1.3.0 path: ^1.9.1 - riscv: ^1.0.0 river: ^1.0.0 - rohd: ^0.6.6 - rohd_bridge: ^0.2.0 - rohd_hcl: - git: - url: https://github.com/MidstallSoftware/rohd-hcl.git - ref: integration + river_adl: ^1.0.0 + river_maskrom: ^1.0.0 + rohd: ^0.6.8 + rohd_bridge: ^0.2.2 + rohd_hcl: ^0.2.1 dev_dependencies: lints: ^6.0.0 test: ^1.28.0 dartdoc: ^9.0.0 + # Differential parity tests run the same program on the emulator (golden) and + # the HDL and compare architectural state. No cycle (emulator doesn't dep hdl). + river_emulator: ^1.0.0 diff --git a/packages/river_hdl/test/a/rv32_inorder_test.dart b/packages/river_hdl/test/a/rv32_inorder_test.dart new file mode 100644 index 0000000..0166e7f --- /dev/null +++ b/packages/river_hdl/test/a/rv32_inorder_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'a'; + const mxlen = RiscVMxlen.rv32; + const uarch = Uarch.inOrder; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/a/rv64_inorder_microcode_test.dart b/packages/river_hdl/test/a/rv64_inorder_microcode_test.dart new file mode 100644 index 0000000..81a89c7 --- /dev/null +++ b/packages/river_hdl/test/a/rv64_inorder_microcode_test.dart @@ -0,0 +1,22 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +/// In-order MICROCODE path (DynamicExecutionUnit + microcode ROM, +/// MicrocodeMode.full) for the 'a' category, validated against the emulator +/// golden. This is the area-first path rc1-s (creek) uses on small FPGAs. Split +/// per-category so dart test parallelizes across isolates (one big file +/// accumulates heap across builds and times out - see project_parity / +/// feedback_test_parallelism). +void main() { + const category = 'a'; + const mxlen = RiscVMxlen.rv64; + const uarch = Uarch.inOrder; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)} (microcode)', + matrixConfig(mxlen, uarch, category, microcodeMode: MicrocodeMode.full), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/a/rv64_inorder_test.dart b/packages/river_hdl/test/a/rv64_inorder_test.dart new file mode 100644 index 0000000..352cff6 --- /dev/null +++ b/packages/river_hdl/test/a/rv64_inorder_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'a'; + const mxlen = RiscVMxlen.rv64; + const uarch = Uarch.inOrder; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/base/rv32_inorder_test.dart b/packages/river_hdl/test/base/rv32_inorder_test.dart new file mode 100644 index 0000000..6ca63ef --- /dev/null +++ b/packages/river_hdl/test/base/rv32_inorder_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'base'; + const mxlen = RiscVMxlen.rv32; + const uarch = Uarch.inOrder; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/base/rv32_ooo_dual_test.dart b/packages/river_hdl/test/base/rv32_ooo_dual_test.dart new file mode 100644 index 0000000..f6edc0e --- /dev/null +++ b/packages/river_hdl/test/base/rv32_ooo_dual_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'base'; + const mxlen = RiscVMxlen.rv32; + const uarch = Uarch.oooDual; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/base/rv32_ooo_test.dart b/packages/river_hdl/test/base/rv32_ooo_test.dart new file mode 100644 index 0000000..75454f9 --- /dev/null +++ b/packages/river_hdl/test/base/rv32_ooo_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'base'; + const mxlen = RiscVMxlen.rv32; + const uarch = Uarch.ooo; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/base/rv64_inorder_microcode_test.dart b/packages/river_hdl/test/base/rv64_inorder_microcode_test.dart new file mode 100644 index 0000000..7edb8b3 --- /dev/null +++ b/packages/river_hdl/test/base/rv64_inorder_microcode_test.dart @@ -0,0 +1,22 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +/// In-order MICROCODE path (DynamicExecutionUnit + microcode ROM, +/// MicrocodeMode.full) for the 'base' category, validated against the emulator +/// golden. This is the area-first path rc1-s (creek) uses on small FPGAs. Split +/// per-category so dart test parallelizes across isolates (one big file +/// accumulates heap across builds and times out - see project_parity / +/// feedback_test_parallelism). +void main() { + const category = 'base'; + const mxlen = RiscVMxlen.rv64; + const uarch = Uarch.inOrder; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)} (microcode)', + matrixConfig(mxlen, uarch, category, microcodeMode: MicrocodeMode.full), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/base/rv64_inorder_test.dart b/packages/river_hdl/test/base/rv64_inorder_test.dart new file mode 100644 index 0000000..93f47e2 --- /dev/null +++ b/packages/river_hdl/test/base/rv64_inorder_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'base'; + const mxlen = RiscVMxlen.rv64; + const uarch = Uarch.inOrder; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/base/rv64_ooo_dual_test.dart b/packages/river_hdl/test/base/rv64_ooo_dual_test.dart new file mode 100644 index 0000000..c5bbc6a --- /dev/null +++ b/packages/river_hdl/test/base/rv64_ooo_dual_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'base'; + const mxlen = RiscVMxlen.rv64; + const uarch = Uarch.oooDual; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/base/rv64_ooo_test.dart b/packages/river_hdl/test/base/rv64_ooo_test.dart new file mode 100644 index 0000000..11748ce --- /dev/null +++ b/packages/river_hdl/test/base/rv64_ooo_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'base'; + const mxlen = RiscVMxlen.rv64; + const uarch = Uarch.ooo; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/bitmanip/rv32_inorder_test.dart b/packages/river_hdl/test/bitmanip/rv32_inorder_test.dart new file mode 100644 index 0000000..536af0a --- /dev/null +++ b/packages/river_hdl/test/bitmanip/rv32_inorder_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'bitmanip'; + const mxlen = RiscVMxlen.rv32; + const uarch = Uarch.inOrder; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/bitmanip/rv32_ooo_dual_test.dart b/packages/river_hdl/test/bitmanip/rv32_ooo_dual_test.dart new file mode 100644 index 0000000..4d0f97d --- /dev/null +++ b/packages/river_hdl/test/bitmanip/rv32_ooo_dual_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'bitmanip'; + const mxlen = RiscVMxlen.rv32; + const uarch = Uarch.oooDual; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/bitmanip/rv32_ooo_test.dart b/packages/river_hdl/test/bitmanip/rv32_ooo_test.dart new file mode 100644 index 0000000..a498fdc --- /dev/null +++ b/packages/river_hdl/test/bitmanip/rv32_ooo_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'bitmanip'; + const mxlen = RiscVMxlen.rv32; + const uarch = Uarch.ooo; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/bitmanip/rv64_inorder_test.dart b/packages/river_hdl/test/bitmanip/rv64_inorder_test.dart new file mode 100644 index 0000000..ad92765 --- /dev/null +++ b/packages/river_hdl/test/bitmanip/rv64_inorder_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'bitmanip'; + const mxlen = RiscVMxlen.rv64; + const uarch = Uarch.inOrder; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/bitmanip/rv64_ooo_dual_test.dart b/packages/river_hdl/test/bitmanip/rv64_ooo_dual_test.dart new file mode 100644 index 0000000..a247535 --- /dev/null +++ b/packages/river_hdl/test/bitmanip/rv64_ooo_dual_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'bitmanip'; + const mxlen = RiscVMxlen.rv64; + const uarch = Uarch.oooDual; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/bitmanip/rv64_ooo_test.dart b/packages/river_hdl/test/bitmanip/rv64_ooo_test.dart new file mode 100644 index 0000000..57c4054 --- /dev/null +++ b/packages/river_hdl/test/bitmanip/rv64_ooo_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'bitmanip'; + const mxlen = RiscVMxlen.rv64; + const uarch = Uarch.ooo; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/bpred/core_bpred_test.dart b/packages/river_hdl/test/bpred/core_bpred_test.dart new file mode 100644 index 0000000..a1abfa2 --- /dev/null +++ b/packages/river_hdl/test/bpred/core_bpred_test.dart @@ -0,0 +1,122 @@ +import 'package:river/river.dart'; +import 'package:rohd/rohd.dart'; +import 'package:test/test.dart'; + +import '../core_harness.dart'; + +/// Branch-predictor correctness: with BTFN prediction the architectural results +/// must be identical to no-prediction, prediction only changes timing. Covers +/// a backward branch (predicted taken), a forward taken branch (predicted +/// not-taken → misprediction recovery), and JAL (predicted taken). +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + RiverCoreConfig bpred() => RiverCoreConfig( + clock: HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ), + mxlen: RiscVMxlen.rv32, + extensions: [rv32i, rvZicsr, rvZifencei, rvM], + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv32, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + executionMode: ExecutionMode.outOfOrder, + speculativeFetch: true, + branchPredictor: BranchPredictor.btfn, + ); + + int iimm(int imm, int rs1, int f3, int rd) => + (imm << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x13; + int b(int imm, int rs2, int rs1, int f3) => + (((imm >> 12) & 0x1) << 31) | + (((imm >> 5) & 0x3F) << 25) | + (rs2 << 20) | + (rs1 << 15) | + (f3 << 12) | + (((imm >> 1) & 0xF) << 8) | + (((imm >> 11) & 0x1) << 7) | + 0x63; + int jal(int imm, int rd) => + (((imm >> 20) & 0x1) << 31) | + (((imm >> 1) & 0x3FF) << 21) | + (((imm >> 11) & 0x1) << 20) | + (((imm >> 12) & 0xFF) << 12) | + (rd << 7) | + 0x6F; + String prog(List words) { + final sb = StringBuffer('@0\n'); + for (final w in words) { + for (var i = 0; i < 4; i++) { + sb.write(((w >> (i * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + return '$sb\n'; + } + + // Backward branch (loop), BTFN predicts taken (correct for all but the last + // iteration). Result must be x1=0, x2=3. + test( + 'bpred: counted loop (predicted-taken back-edge)', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + iimm(3, 0, 0x0, 1), // addi x1, x0, 3 + iimm(0, 0, 0x0, 2), // addi x2, x0, 0 + iimm(1, 2, 0x0, 2), // loop: addi x2, x2, 1 <- target 0x08 + iimm(-1, 1, 0x0, 1), // addi x1, x1, -1 + b(-8, 0, 1, 0x1), // bne x1, x0, -8 -> 0x08 while x1!=0 + ...List.filled(11, 0x00000013), // nop tail + ]), + {Register.x1: 0, Register.x2: 3}, + bpred(), + nextPc: 0x3C, + ), + ); + + // Forward taken branch, BTFN predicts NOT-taken, so this exercises the + // misprediction recovery (flush + redirect at commit). x3 must be skipped. + test( + 'bpred: forward taken branch (mispredict recovery)', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + iimm(5, 0, 0x0, 1), // addi x1, x0, 5 + iimm(5, 0, 0x0, 2), // addi x2, x0, 5 + b(8, 2, 1, 0x0), // beq x1, x2, +8 -> taken (forward), skip 0x0C + iimm(99, 0, 0x0, 3), // addi x3, x0, 99 (SKIPPED) + iimm(7, 0, 0x0, 4), // addi x4, x0, 7 (target 0x10) + ...List.filled(8, 0x00000013), // nop tail + ]), + {Register.x1: 5, Register.x2: 5, Register.x3: 0, Register.x4: 7}, + bpred(), + nextPc: 0x34, + ), + ); + + // JAL, BTFN predicts taken; link + skip must be correct. + test( + 'bpred: JAL (predicted taken) with link', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + iimm(5, 0, 0x0, 1), // addi x1, x0, 5 + jal(8, 3), // jal x3, +8 -> link x3=0x08, jump 0x0C + iimm(99, 0, 0x0, 4), // addi x4, x0, 99 (SKIPPED) + iimm(7, 0, 0x0, 2), // addi x2, x0, 7 (target 0x0C) + ...List.filled(8, 0x00000013), // nop tail + ]), + {Register.x1: 5, Register.x2: 7, Register.x3: 0x08, Register.x4: 0}, + bpred(), + nextPc: 0x30, + ), + ); +} diff --git a/packages/river_hdl/test/branch/rv32_inorder_test.dart b/packages/river_hdl/test/branch/rv32_inorder_test.dart new file mode 100644 index 0000000..141ae44 --- /dev/null +++ b/packages/river_hdl/test/branch/rv32_inorder_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'branch'; + const mxlen = RiscVMxlen.rv32; + const uarch = Uarch.inOrder; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/branch/rv32_ooo_dual_test.dart b/packages/river_hdl/test/branch/rv32_ooo_dual_test.dart new file mode 100644 index 0000000..287594b --- /dev/null +++ b/packages/river_hdl/test/branch/rv32_ooo_dual_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'branch'; + const mxlen = RiscVMxlen.rv32; + const uarch = Uarch.oooDual; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/branch/rv32_ooo_test.dart b/packages/river_hdl/test/branch/rv32_ooo_test.dart new file mode 100644 index 0000000..5248993 --- /dev/null +++ b/packages/river_hdl/test/branch/rv32_ooo_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'branch'; + const mxlen = RiscVMxlen.rv32; + const uarch = Uarch.ooo; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/branch/rv64_inorder_microcode_test.dart b/packages/river_hdl/test/branch/rv64_inorder_microcode_test.dart new file mode 100644 index 0000000..4bed988 --- /dev/null +++ b/packages/river_hdl/test/branch/rv64_inorder_microcode_test.dart @@ -0,0 +1,22 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +/// In-order MICROCODE path (DynamicExecutionUnit + microcode ROM, +/// MicrocodeMode.full) for the 'branch' category, validated against the emulator +/// golden. This is the area-first path rc1-s (creek) uses on small FPGAs. Split +/// per-category so dart test parallelizes across isolates (one big file +/// accumulates heap across builds and times out - see project_parity / +/// feedback_test_parallelism). +void main() { + const category = 'branch'; + const mxlen = RiscVMxlen.rv64; + const uarch = Uarch.inOrder; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)} (microcode)', + matrixConfig(mxlen, uarch, category, microcodeMode: MicrocodeMode.full), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/branch/rv64_inorder_test.dart b/packages/river_hdl/test/branch/rv64_inorder_test.dart new file mode 100644 index 0000000..e31b780 --- /dev/null +++ b/packages/river_hdl/test/branch/rv64_inorder_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'branch'; + const mxlen = RiscVMxlen.rv64; + const uarch = Uarch.inOrder; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/branch/rv64_ooo_dual_test.dart b/packages/river_hdl/test/branch/rv64_ooo_dual_test.dart new file mode 100644 index 0000000..1115d67 --- /dev/null +++ b/packages/river_hdl/test/branch/rv64_ooo_dual_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'branch'; + const mxlen = RiscVMxlen.rv64; + const uarch = Uarch.oooDual; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/branch/rv64_ooo_test.dart b/packages/river_hdl/test/branch/rv64_ooo_test.dart new file mode 100644 index 0000000..d2cf12c --- /dev/null +++ b/packages/river_hdl/test/branch/rv64_ooo_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'branch'; + const mxlen = RiscVMxlen.rv64; + const uarch = Uarch.ooo; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/cache/core_icache_test.dart b/packages/river_hdl/test/cache/core_icache_test.dart new file mode 100644 index 0000000..e968173 --- /dev/null +++ b/packages/river_hdl/test/cache/core_icache_test.dart @@ -0,0 +1,125 @@ +import 'package:river/river.dart'; +import 'package:rohd/rohd.dart'; +import 'package:test/test.dart'; + +import '../core_harness.dart'; + +/// L1 instruction cache integration: the core fetches through the icache +/// (hits in one cycle, misses fill a line from the MMU). Verifies correctness +/// with the cache enabled, in both single- and dual-dispatch. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + HarborMmuConfig mmu() => HarborMmuConfig( + mxlen: RiscVMxlen.rv32, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ); + + RiverCoreConfig icacheSingle() => RiverCoreConfig( + clock: HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ), + mxlen: RiscVMxlen.rv32, + extensions: [rv32i, rvZicsr, rvZifencei, rvM], + interrupts: [], + mmu: mmu(), + type: RiverCoreType.general, + executionMode: ExecutionMode.outOfOrder, + speculativeFetch: true, + l1cache: HarborL1CacheConfig.split( + iSize: 32, + dSize: 64, + ways: 1, + lineSize: 4, + ), + ); + + RiverCoreConfig icacheDual() => RiverCoreConfig( + clock: HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ), + mxlen: RiscVMxlen.rv32, + extensions: [rv32i, rvZicsr, rvZifencei, rvM], + interrupts: [], + mmu: mmu(), + type: RiverCoreType.general, + executionMode: ExecutionMode.outOfOrder, + speculativeFetch: true, + issueWidth: IssueWidth.dual, + l1cache: HarborL1CacheConfig.split( + iSize: 32, + dSize: 64, + ways: 1, + lineSize: 4, + ), + ); + + int iimm(int imm, int rs1, int f3, int rd) => + (imm << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x13; + String prog(List words) { + final sb = StringBuffer('@0\n'); + for (final w in words) { + for (var b = 0; b < 4; b++) { + sb.write(((w >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + return '$sb\n'; + } + + // Single-dispatch through the icache: tight RAW chain (also re-fetches the + // same lines as the program is short, exercising cache hits). + test( + 'icache: single-dispatch RAW chain', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + iimm(1, 0, 0x0, 1), + iimm(1, 1, 0x0, 2), + iimm(1, 2, 0x0, 3), + iimm(1, 3, 0x0, 4), + iimm(1, 4, 0x0, 5), + ...List.filled(8, 0x00000013), + ]), + { + Register.x1: 1, + Register.x2: 2, + Register.x3: 3, + Register.x4: 4, + Register.x5: 5, + }, + icacheSingle(), + nextPc: 0x34, + ), + ); + + // Dual-dispatch through the icache: independent ALU pairs. Both fetch lanes + // hit the same cache line and are served the same cycle. + test( + 'icache: dual-dispatch independent pairs', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + iimm(0x111, 0, 0x0, 1), + iimm(0x222, 0, 0x0, 2), + iimm(0x333, 0, 0x0, 3), + iimm(0x444, 0, 0x0, 4), + ...List.filled(8, 0x00000013), + ]), + { + Register.x1: 0x111, + Register.x2: 0x222, + Register.x3: 0x333, + Register.x4: 0x444, + }, + icacheDual(), + nextPc: 0x2C, + ), + ); +} diff --git a/packages/river_hdl/test/cache/icache_evict_test.dart b/packages/river_hdl/test/cache/icache_evict_test.dart new file mode 100644 index 0000000..6779a8c --- /dev/null +++ b/packages/river_hdl/test/cache/icache_evict_test.dart @@ -0,0 +1,185 @@ +import 'dart:async'; + +import 'package:rohd/rohd.dart'; +import 'package:river_hdl/src/core/icache.dart'; +import 'package:test/test.dart'; + +/// Eviction / aliasing / thrash stress for RiverICache in the CREEK geometry +/// (direct-mapped, numLines: 8, lineWords: 1, xlen: 64) with a MULTI-CYCLE +/// backing that models the slow DDR fill latency. +/// +/// The conduit-walk boot failure only appears once main runs a code footprint +/// far larger than the 8-word icache, so the icache constantly misses, evicts, +/// and re-fills lines while executing from DRAM. The existing icache_test only +/// touches a few addresses and never forces an eviction, nor a re-access of an +/// evicted line, nor a back-to-back miss under realistic fill latency. This test +/// exercises exactly that: every fetch must return its own address (the backing +/// returns addr), so any stale-hit, tag-aliasing, or fill/settle-timing bug +/// surfaces as a wrong word. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + Future runEvict({required int latency}) async { + final clk = SimpleClockGenerator(10).clk; + final reset = Logic(); + final req0En = Logic(); + final req0Addr = Logic(width: 64); + final memDone = Logic(); + final memValid = Logic(); + final memRdata = Logic(width: 64); + final flush = Logic(); + + final ic = RiverICache( + clk, + reset, + req0En: req0En, + req0Addr: req0Addr, + req1En: null, + req1Addr: null, + memDone: memDone, + memValid: memValid, + memRdata: memRdata, + flush: flush, + xlen: 64, + lineWords: 1, + numLines: 8, + dualPort: false, + ); + await ic.build(); + + // Multi-cycle backing: when memEn asserts, count `latency` cycles, then + // pulse memDone/memValid with memRdata = the (latched) fill address. This is + // the DDR fill latency the combinational test-backing never modeled. + final busy = Logic(name: 'bk_busy'); + final cnt = Logic(name: 'bk_cnt', width: 8); + final addrLatched = Logic(name: 'bk_addr', width: 64); + final doneR = Logic(name: 'bk_done'); + final validR = Logic(name: 'bk_valid'); + final rdataR = Logic(name: 'bk_rdata', width: 64); + memDone <= doneR; + memValid <= validR; + memRdata <= rdataR; + Sequential(clk, reset: reset, [ + doneR < 0, + validR < 0, + If( + ~busy & ic.memEn & ~doneR, + then: [busy < 1, cnt < 0, addrLatched < ic.memAddr], + orElse: [ + If( + busy, + then: [ + cnt < cnt + 1, + If( + cnt.eq(Const(latency, width: 8)), + then: [busy < 0, doneR < 1, validR < 1, rdataR < addrLatched], + ), + ], + ), + ], + ), + ]); + + reset.inject(1); + req0En.inject(0); + req0Addr.inject(0); + flush.inject(0); + Simulator.setMaxSimTime(2000000); + unawaited(Simulator.run()); + await clk.nextPosedge; + reset.inject(0); + await clk.nextPosedge; + + Future fetch(int addr) async { + req0En.inject(1); + req0Addr.inject(addr); + for (var i = 0; i < 200; i++) { + await clk.nextNegedge; + if (ic.done0.value.toBool()) { + final d = ic.rdata0.value.toInt(); + req0En.inject(0); + await clk.nextPosedge; // let the fetcher advance one cycle + return d; + } + } + req0En.inject(0); + throw StateError('fetch of 0x${addr.toRadixString(16)} timed out'); + } + + // Line index = addr[5:3] (8-byte words, 8 lines). base+0x00..0x38 fill lines + // 0..7; base+0x40 aliases line 0 with a new tag (evicts it). + const base = 0x80000000; + Future check(int addr) async { + final d = await fetch(addr); + expect( + d, + addr, + reason: + 'fetch 0x${addr.toRadixString(16)} returned ' + '0x${d.toRadixString(16)} (stale/aliased line)', + ); + } + + // 1) Fill all 8 lines. + for (var i = 0; i < 8; i++) { + await check(base + i * 8); + } + // 2) Re-fetch all 8 (should all hit, still correct). + for (var i = 0; i < 8; i++) { + await check(base + i * 8); + } + // 3) Evict line 0 with an aliasing tag, then re-fetch the original: must MISS + // and re-fill, not serve the evictor's or the stale word. + await check(base + 0x40); // idx 0, new tag -> evicts line 0 + await check(base + 0x00); // idx 0, original tag -> must re-miss + refill + await check(base + 0x40); // idx 0 again + await check(base + 0x00); + + // 4) Thrash a single line back-to-back (alternating tags at the same index). + for (var i = 0; i < 16; i++) { + await check(base + (i.isEven ? 0x00 : 0x40)); + } + + // 5) Streaming walk over 64 consecutive words (8x the cache), twice, the + // real conduit-walk shape: constant miss/evict/refill. + for (var pass = 0; pass < 2; pass++) { + for (var w = 0; w < 64; w++) { + await check(base + w * 8); + } + } + + // 6) Back-to-back distinct-line misses with no idle gap between them. + for (var i = 0; i < 8; i++) { + req0En.inject(1); + req0Addr.inject(base + 0x1000 + i * 8); // fresh tags, each a miss + var got = -1; + for (var k = 0; k < 200; k++) { + await clk.nextNegedge; + if (ic.done0.value.toBool()) { + got = ic.rdata0.value.toInt(); + break; + } + } + expect( + got, + base + 0x1000 + i * 8, + reason: 'back-to-back miss $i returned 0x${got.toRadixString(16)}', + ); + // do NOT drop req0En between: keep the stream flowing, just change addr + } + req0En.inject(0); + + await Simulator.endSimulation(); + } + + test( + 'icache eviction/thrash, fast fill (latency 2)', + () => runEvict(latency: 2), + ); + test( + 'icache eviction/thrash, slow DDR-like fill (latency 12)', + () => runEvict(latency: 12), + ); +} diff --git a/packages/river_hdl/test/cache/icache_test.dart b/packages/river_hdl/test/cache/icache_test.dart new file mode 100644 index 0000000..79ee223 --- /dev/null +++ b/packages/river_hdl/test/cache/icache_test.dart @@ -0,0 +1,125 @@ +import 'dart:async'; + +import 'package:rohd/rohd.dart'; +import 'package:river_hdl/src/core/icache.dart'; +import 'package:test/test.dart'; + +/// Unit test for RiverICache with a simple combinational backing "memory": +/// every fill word returns its own address, so a request to word-aligned addr A +/// must eventually return data == A. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + Future runCase({required bool dual}) async { + final clk = SimpleClockGenerator(10).clk; + final reset = Logic(); + final req0En = Logic(); + final req0Addr = Logic(width: 32); + final req1En = dual ? Logic() : null; + final req1Addr = dual ? Logic(width: 32) : null; + final memDone = Logic(); + final memValid = Logic(); + final memRdata = Logic(width: 32); + final flush = Logic(); + + final ic = RiverICache( + clk, + reset, + req0En: req0En, + req0Addr: req0Addr, + req1En: req1En, + req1Addr: req1Addr, + memDone: memDone, + memValid: memValid, + memRdata: memRdata, + flush: flush, + xlen: 32, + lineWords: 4, + numLines: 8, + dualPort: dual, + ); + await ic.build(); + + // Combinational backing memory: word at addr returns addr. + memDone <= ic.memEn; + memValid <= ic.memEn; + memRdata <= ic.memAddr; + + reset.inject(1); + req0En.inject(0); + req0Addr.inject(0); + flush.inject(0); + if (dual) { + req1En!.inject(0); + req1Addr!.inject(0); + } + Simulator.setMaxSimTime(100000); + unawaited(Simulator.run()); + await clk.nextPosedge; + reset.inject(0); + await clk.nextPosedge; + + Future fetch0(int addr) async { + req0En.inject(1); + req0Addr.inject(addr); + for (var i = 0; i < 50; i++) { + await clk.nextNegedge; + if (ic.done0.value.toBool()) { + final d = ic.rdata0.value.toInt(); + req0En.inject(0); + return d; + } + } + req0En.inject(0); + throw StateError('port0 fetch of $addr timed out'); + } + + // Miss → fill → hit. + expect(await fetch0(0x100), 0x100); + await clk.nextPosedge; + // Same line, different word → hit (fast). + expect(await fetch0(0x104), 0x104); + await clk.nextPosedge; + expect(await fetch0(0x10C), 0x10C); + await clk.nextPosedge; + // Different line → miss → fill → hit. + expect(await fetch0(0x200), 0x200); + await clk.nextPosedge; + + if (dual) { + // Both ports, same line (0x100 already cached): both hit same cycle. + req0En.inject(1); + req0Addr.inject(0x100); + req1En!.inject(1); + req1Addr!.inject(0x104); + var ok = false; + for (var i = 0; i < 10; i++) { + await clk.nextNegedge; + if (ic.done0.value.toBool() && ic.done1.value.toBool()) { + expect(ic.rdata0.value.toInt(), 0x100); + expect(ic.rdata1.value.toInt(), 0x104); + ok = true; + break; + } + } + req0En.inject(0); + req1En.inject(0); + expect(ok, isTrue, reason: 'dual same-line hit did not fire'); + await clk.nextPosedge; + } + + // Flush invalidates → 0x100 misses again (still returns correct data). + flush.inject(1); + await clk.nextPosedge; + flush.inject(0); + await clk.nextPosedge; + expect(await fetch0(0x100), 0x100); + + await Simulator.endSimulation(); + } + + test('icache single-port miss/fill/hit/flush', () => runCase(dual: false)); + test('icache dual-port same-line both hit', () => runCase(dual: true)); +} diff --git a/packages/river_hdl/test/cdc/cdc_fifo_ifetch_load_stream_test.dart b/packages/river_hdl/test/cdc/cdc_fifo_ifetch_load_stream_test.dart new file mode 100644 index 0000000..1b05eb9 --- /dev/null +++ b/packages/river_hdl/test/cdc/cdc_fifo_ifetch_load_stream_test.dart @@ -0,0 +1,289 @@ +import 'dart:async'; + +import 'package:harbor/src/clock/wishbone_cdc.dart'; +import 'package:harbor/src/clock/wishbone_cdc_fifo.dart'; +import 'package:harbor/src/clock/wishbone_downsizer.dart'; +import 'package:river/river.dart'; +import 'package:rohd/rohd.dart'; +import 'package:rohd_hcl/rohd_hcl.dart' hide DataPortInterface, DataPortGroup; +import 'package:river_hdl/river_hdl.dart'; +import 'package:test/test.dart'; + +/// Sim bisection of the creek execute-from-DRAM corruption, one cut below the +/// core. The core-only sim (rv32+rv64, latency memory, no CDC) is clean, so the +/// bug is in the downsizer/CDC/DDR path. The EXISTING ifetch_load_deadlock_test +/// has two gaps vs creek: it uses HarborWishboneCdcBridge (creek/ddr3Fast uses +/// HarborWishboneCdcFifoBridge) and only a few loads. This runs a SUSTAINED +/// icache-thrashing load-sum blob (code >> the rc1-s 64B icache, so the icache +/// refills from DRAM the whole time while the dcache loads) through the REAL +/// creek chain: core(64) -> downsizer(64->32) -> CDC bridge -> fast 32b memory, +/// and CHECKS the summed result (stored back to DRAM). Runs both bridge kinds so +/// a FIFO-only corruption is obvious. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + // rv64 rc1-s (matches creek's core+caches exactly). + RiverCoreConfig cfg() => RiverCoreConfigV1.small( + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + interrupts: const [], + clock: HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ), + ); + + // Program: sum N loads of K from a data region, store the low 32 bits back to + // DRAM at resultAddr. Code is long enough to thrash the 64B icache. + const dataBase = 0x400; + const resultAddr = 0x780; + const k = 0x5A5A5A5A; + const n = 8; + // encoders + int addi(int rd, int rs1, int imm) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (rd << 7) | 0x13; + int lw(int rd, int rs1, int imm) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (0x2 << 12) | (rd << 7) | 0x03; + int add(int rd, int rs1, int rs2) => + (rs2 << 20) | (rs1 << 15) | (rd << 7) | 0x33; + int sw(int rs2, int rs1, int imm) => + (((imm >> 5) & 0x7F) << 25) | + (rs2 << 20) | + (rs1 << 15) | + (0x2 << 12) | + ((imm & 0x1F) << 7) | + 0x23; + const nop = 0x00000013; + + final program = [ + addi(3, 0, dataBase), // x3 = data base + addi(2, 0, 0), // x2 = 0 (accumulator) + for (var i = 0; i < n; i++) ...[ + lw(1, 3, 0), // x1 = [x3] + add(2, 2, 1), // x2 += x1 + addi(3, 3, 8), // x3 += 8 (new 8B line each -> dcache miss) + ], + addi(5, 0, resultAddr), // x5 = result addr + sw(2, 5, 0), // [x5] = x2 (store the sum back to DRAM) + nop, + nop, + ]; + final expected = (n * k) & 0xFFFFFFFF; // low 32 bits of the sum + + /// core -> downsizer(64->32) -> [bridge] -> 32b fast memory. bridgeKind picks + /// the real creek FIFO bridge vs the legacy gray-counter bridge. Returns the + /// 32b word stored at resultAddr (null if never written) and whether it stalled. + Future<({int? result, bool stalled, int maxAddr})> run( + String bridgeKind, { + int sPeriod = 40, + int mPeriod = 10, + int memLatency = 6, + int maxCycles = 6000, + }) async { + await Simulator.reset(); + final config = cfg(); + final xlen = config.mxlen.size; + final sClk = SimpleClockGenerator(sPeriod).clk; + final mClk = SimpleClockGenerator(mPeriod).clk; + final reset = Logic(name: 'reset'); + final wbConfig = WishboneConfig( + addressWidth: xlen, + dataWidth: xlen, + selWidth: xlen ~/ 8, + ); + final core = RiverCore(config, busConfig: wbConfig); + core.input('clk').srcConnection! <= sClk; + core.input('reset').srcConnection! <= reset; + await core.build(); + + final wbCyc = core.output('dataBus_CYC'); + final wbStb = core.output('dataBus_STB'); + final wbWe = core.output('dataBus_WE'); + final wbAdr = core.output('dataBus_ADR'); + + const narrow = 32; + final ds = HarborWishboneDownsizer( + addressWidth: xlen, + wideWidth: xlen, + narrowWidth: narrow, + paceCycles: 8, + ); + ds.input('clk').srcConnection! <= sClk; + ds.input('reset').srcConnection! <= reset; + ds.input('s_cyc').srcConnection! <= wbCyc; + ds.input('s_stb').srcConnection! <= wbStb; + ds.input('s_we').srcConnection! <= wbWe; + ds.input('s_adr').srcConnection! <= wbAdr; + ds.input('s_dat_w').srcConnection! <= core.output('dataBus_DAT_MOSI'); + ds.input('s_sel').srcConnection! <= core.output('dataBus_SEL'); + core.input('dataBus_ACK').srcConnection! <= ds.output('s_ack'); + core.input('dataBus_DAT_MISO').srcConnection! <= ds.output('s_dat_r'); + + // Pick the bridge. Both are port-compatible. + late final Module bridge; + if (bridgeKind == 'fifo') { + bridge = HarborWishboneCdcFifoBridge( + addressWidth: xlen, + dataWidth: narrow, + selWidth: narrow ~/ 8, + depth: 16, + ); + } else { + bridge = HarborWishboneCdcBridge(addressWidth: xlen, dataWidth: narrow); + } + bridge.input('s_clk').srcConnection! <= sClk; + bridge.input('s_reset').srcConnection! <= reset; + bridge.input('m_clk').srcConnection! <= mClk; + bridge.input('m_reset').srcConnection! <= reset; + bridge.input('s_cyc').srcConnection! <= ds.output('m_cyc'); + bridge.input('s_stb').srcConnection! <= ds.output('m_stb'); + bridge.input('s_we').srcConnection! <= ds.output('m_we'); + bridge.input('s_adr').srcConnection! <= ds.output('m_adr'); + bridge.input('s_dat_w').srcConnection! <= ds.output('m_dat_w'); + bridge.input('s_sel').srcConnection! <= ds.output('m_sel'); + ds.input('m_ack').srcConnection! <= bridge.output('s_ack'); + ds.input('m_dat_r').srcConnection! <= bridge.output('s_dat_r'); + + final storage = SparseMemoryStorage( + addrWidth: xlen, + dataWidth: narrow, + alignAddress: (addr) => addr, + onInvalidRead: (addr, dataWidth) => + LogicValue.filled(dataWidth, LogicValue.zero), + ); + final memRead = DataPortInterface(narrow, xlen); + final memWrite = DataPortInterface(narrow, xlen); + // ignore: unused_local_variable + final mem = MemoryModel( + mClk, + reset, + [wrapWriteForRegisterFile(memWrite)], + [wrapReadForRegisterFile(memRead, clk: mClk, readLatency: memLatency)], + readLatency: memLatency, + storage: storage, + ); + final mCyc = bridge.output('m_cyc'); + final mStb = bridge.output('m_stb'); + final mWe = bridge.output('m_we'); + memRead.en <= mCyc & mStb & ~mWe; + memRead.addr <= bridge.output('m_adr'); + memWrite.en <= mCyc & mStb & mWe; + memWrite.addr <= bridge.output('m_adr'); + memWrite.data <= bridge.output('m_dat_w'); + bridge.input('m_ack').srcConnection! <= + (mCyc & mStb & (mWe | memRead.valid)); + bridge.input('m_dat_r').srcConnection! <= memRead.data; + + reset.inject(1); + Simulator.setMaxSimTime(1000000000); + unawaited(Simulator.run()); + for (var i = 0; i < 4; i++) { + await sClk.nextPosedge; + } + + // Load program @0 and data (K) @dataBase. + final sb = StringBuffer('@0\n'); + for (final w in program) { + for (var b = 0; b < 4; b++) { + sb.write(((w >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + sb.write('\n@${dataBase.toRadixString(16)}\n'); + for (var i = 0; i < n * 2 + 4; i++) { + // fill dataBase..+ generously with K (every 32b word) + for (var b = 0; b < 4; b++) { + sb.write(((k >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + storage.loadMemString('${sb.toString().trimRight()}\n'); + reset.inject(0); + await sClk.nextPosedge; + + var maxAddr = 0; + var lastProgress = 0; + for (var i = 0; i < maxCycles; i++) { + if (wbCyc.value == LogicValue.one && + wbStb.value == LogicValue.one && + wbWe.value == LogicValue.zero) { + final a = wbAdr.value.toInt(); + if (a < 0x400 && a > maxAddr) { + maxAddr = a; + lastProgress = i; + } + } + final res = storage.getData(LogicValue.ofInt(resultAddr, xlen))?.toInt(); + if (res != null && res != 0) { + await Simulator.endSimulation(); + return (result: res, stalled: false, maxAddr: maxAddr); + } + if (i - lastProgress > 1500 && wbCyc.value == LogicValue.one) { + await Simulator.endSimulation(); + return (result: null, stalled: true, maxAddr: maxAddr); + } + await sClk.nextPosedge; + } + final res = storage.getData(LogicValue.ofInt(resultAddr, xlen))?.toInt(); + await Simulator.endSimulation(); + return (result: res, stalled: false, maxAddr: maxAddr); + } + + for (final kind in ['gray', 'fifo']) { + test( + 'sustained ifetch+load through the $kind CDC bridge sums correctly', + timeout: Timeout(Duration(seconds: 240)), + () async { + final r = await run(kind); + expect( + r.stalled, + isFalse, + reason: + '$kind bridge: core stalled at fetch ' + '0x${r.maxAddr.toRadixString(16)} (never stored the sum)', + ); + expect( + r.result, + equals(expected), + reason: + '$kind bridge: sum came back ' + '0x${r.result?.toRadixString(16)} not 0x${expected.toRadixString(16)} ' + '- execute-from-DRAM corruption reproduced in sim', + ); + }, + ); + } + + // REAL creek clock ratio: sys 25MHz / ctrl 50MHz = 2:1 phase-locked (one MMCM), + // vs the 4:1 above. The FIFO bridge exists because phase-locked clocks hit a + // pathological fixed phase; the arbitrary 4:1 may dodge the phase the 2:1 + // mesochronous pair lands on. If THIS corrupts, the bug is the CDC bridge under + // the real clock phase. + for (final mp in [20, 16, 12]) { + test( + 'fifo bridge at ${(40 / mp).toStringAsFixed(2)}:1 clock ratio (mPeriod=$mp)', + timeout: Timeout(Duration(seconds: 300)), + () async { + final r = await run('fifo', sPeriod: 40, mPeriod: mp); + expect( + r.stalled, + isFalse, + reason: 'stalled at 0x${r.maxAddr.toRadixString(16)}', + ); + expect( + r.result, + equals(expected), + reason: + 'ratio 40:$mp sum=0x${r.result?.toRadixString(16)} not ' + '0x${expected.toRadixString(16)} - i+d corruption reproduced', + ); + }, + ); + } +} diff --git a/packages/river_hdl/test/cdc/ifetch_load_deadlock_test.dart b/packages/river_hdl/test/cdc/ifetch_load_deadlock_test.dart new file mode 100644 index 0000000..5d459a3 --- /dev/null +++ b/packages/river_hdl/test/cdc/ifetch_load_deadlock_test.dart @@ -0,0 +1,335 @@ +import 'dart:async'; + +import 'package:harbor/src/clock/wishbone_cdc.dart'; +import 'package:harbor/src/clock/wishbone_downsizer.dart'; +import 'package:river/river.dart'; +import 'package:rohd/rohd.dart'; +import 'package:rohd_hcl/rohd_hcl.dart' hide DataPortInterface, DataPortGroup; +import 'package:river_hdl/river_hdl.dart'; +import 'package:test/test.dart'; + +/// Deterministic repro for the creek #131 hardware hang: a blocking DRAM LOAD +/// issued while the core fetches instructions from DRAM wedges the core. On +/// hardware the DRAM sits behind a 12->48MHz HarborWishboneCdcBridge; the +/// single-clock latency model does NOT reproduce it (latency alone lets the core +/// progress), so this puts the REAL CDC bridge between the real RiverCore and a +/// fast-clock memory and runs a fetch+load loop across the clock domains. +/// +/// Result is the highest instruction-fetch address the core reaches before a +/// stall: a healthy run climbs to the trailing nop; a deadlock freezes far +/// below (the on-hardware symptom: wedges on the first load). +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + /// Build core (slow clk) -> HarborWishboneCdcBridge -> MemoryModel (fast clk), + /// load [program] at 0, run, and return (maxFetchAddr, stalled?). [sPeriod]/ + /// [mPeriod] set the core/memory clock periods (creek = 12MHz core / 48MHz + /// dram ~= 4:1). + Future<({int maxAddr, bool stalled, int? probed, Map written})> + run({ + required List program, + int sPeriod = 40, + int mPeriod = 10, + int memLatency = 12, // fast-side DDR-like multi-cycle read latency + int maxCycles = 3500, + int probeAddr = + -1, // >=0: return the 32b memory word at this addr after run + List scanAddrs = const [], // addrs to snapshot from memory after run + }) async { + await Simulator.reset(); + final config = RiverCoreConfigV1.small( + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + interrupts: const [], + clock: HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ), + ); + final xlen = config.mxlen.size; + + final sClk = SimpleClockGenerator(sPeriod).clk; // core (slow) + final mClk = SimpleClockGenerator(mPeriod).clk; // memory (fast) + final reset = Logic(name: 'reset'); + + final wbConfig = WishboneConfig( + addressWidth: xlen, + dataWidth: xlen, + selWidth: xlen ~/ 8, + ); + final core = RiverCore(config, busConfig: wbConfig); + core.input('clk').srcConnection! <= sClk; + core.input('reset').srcConnection! <= reset; + await core.build(); + + final wbCyc = core.output('dataBus_CYC'); + final wbStb = core.output('dataBus_STB'); + final wbWe = core.output('dataBus_WE'); + final wbAdr = core.output('dataBus_ADR'); + + // The real creek DRAM face order: core(64) -> downsizer(64->32, core clk) -> + // CDC bridge(32, core clk slave / mem clk master) -> memory(32, mem clk). + const narrow = 32; + final ds = HarborWishboneDownsizer( + addressWidth: xlen, + wideWidth: xlen, + narrowWidth: narrow, + paceCycles: 8, // matches ddr.dart + ); + ds.input('clk').srcConnection! <= sClk; + ds.input('reset').srcConnection! <= reset; + ds.input('s_cyc').srcConnection! <= wbCyc; + ds.input('s_stb').srcConnection! <= wbStb; + ds.input('s_we').srcConnection! <= wbWe; + ds.input('s_adr').srcConnection! <= wbAdr; + ds.input('s_dat_w').srcConnection! <= core.output('dataBus_DAT_MOSI'); + ds.input('s_sel').srcConnection! <= core.output('dataBus_SEL'); + core.input('dataBus_ACK').srcConnection! <= ds.output('s_ack'); + core.input('dataBus_DAT_MISO').srcConnection! <= ds.output('s_dat_r'); + + final bridge = HarborWishboneCdcBridge( + addressWidth: xlen, + dataWidth: narrow, + ); + bridge.input('s_clk').srcConnection! <= sClk; + bridge.input('s_reset').srcConnection! <= reset; + bridge.input('m_clk').srcConnection! <= mClk; + bridge.input('m_reset').srcConnection! <= reset; + bridge.input('s_cyc').srcConnection! <= ds.output('m_cyc'); + bridge.input('s_stb').srcConnection! <= ds.output('m_stb'); + bridge.input('s_we').srcConnection! <= ds.output('m_we'); + bridge.input('s_adr').srcConnection! <= ds.output('m_adr'); + bridge.input('s_dat_w').srcConnection! <= ds.output('m_dat_w'); + bridge.input('s_sel').srcConnection! <= ds.output('m_sel'); + ds.input('m_ack').srcConnection! <= bridge.output('s_ack'); + ds.input('m_dat_r').srcConnection! <= bridge.output('s_dat_r'); + + // Fast-side 32-bit memory holding the program. + final storage = SparseMemoryStorage( + addrWidth: xlen, + dataWidth: narrow, + alignAddress: (addr) => addr, + onInvalidRead: (addr, dataWidth) => + LogicValue.filled(dataWidth, LogicValue.zero), + ); + final memRead = DataPortInterface(narrow, xlen); // (dataWidth, addrWidth) + final memWrite = DataPortInterface(narrow, xlen); + // ignore: unused_local_variable + final mem = MemoryModel( + mClk, + reset, + [wrapWriteForRegisterFile(memWrite)], + [wrapReadForRegisterFile(memRead, clk: mClk, readLatency: memLatency)], + readLatency: memLatency, + storage: storage, + ); + final mCyc = bridge.output('m_cyc'); + final mStb = bridge.output('m_stb'); + final mWe = bridge.output('m_we'); + memRead.en <= mCyc & mStb & ~mWe; + memRead.addr <= bridge.output('m_adr'); + memWrite.en <= mCyc & mStb & mWe; + memWrite.addr <= bridge.output('m_adr'); + memWrite.data <= bridge.output('m_dat_w'); + bridge.input('m_ack').srcConnection! <= + (mCyc & mStb & (mWe | memRead.valid)); + bridge.input('m_dat_r').srcConnection! <= memRead.data; + + reset.inject(1); + Simulator.setMaxSimTime(1000000000); + unawaited(Simulator.run()); + for (var i = 0; i < 4; i++) { + await sClk.nextPosedge; + } + + final sb = StringBuffer('@0\n'); + for (final w in program) { + for (var b = 0; b < 4; b++) { + sb.write(((w >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + storage.loadMemString('${sb.toString().trimRight()}\n'); + reset.inject(0); + await sClk.nextPosedge; + + var maxAddr = 0; + var lastProgressCycle = 0; + for (var i = 0; i < maxCycles; i++) { + if (wbCyc.value == LogicValue.one && + wbStb.value == LogicValue.one && + wbWe.value == LogicValue.zero) { + final a = wbAdr.value.toInt(); + if (a < 0x1000 && a > maxAddr) { + maxAddr = a; + lastProgressCycle = i; + } + } + // Stall = the core has held a request but made no fetch progress for a + // long stretch (1000 core cycles >> any microcode instruction latency). + if (i - lastProgressCycle > 1000 && wbCyc.value == LogicValue.one) { + final p = probeAddr < 0 + ? null + : storage.getData(LogicValue.ofInt(probeAddr, xlen))?.toInt(); + await Simulator.endSimulation(); + return ( + maxAddr: maxAddr, + stalled: true, + probed: p, + written: {}, + ); + } + await sClk.nextPosedge; + } + final probed = probeAddr < 0 + ? null + : storage.getData(LogicValue.ofInt(probeAddr, xlen))?.toInt(); + final written = {}; + for (final a in scanAddrs) { + final v = storage.getData(LogicValue.ofInt(a, xlen))?.toInt(); + if (v != null) written[a] = v; + } + await Simulator.endSimulation(); + return (maxAddr: maxAddr, stalled: false, probed: probed, written: written); + } + + // x3 = 0x800 (data region), then a run of `lw x1, 0(x3)` so the core fetches + // AND loads every iteration, ending at a trailing nop. + const liX3 = 0x80000193; // addi x3, x0, 0x800 + const lwX1 = 0x0001a083; // lw x1, 0(x3) + const nop = 0x00000013; + final program = [liX3, ...List.filled(6, lwX1), nop]; + final nopAddr = (program.length - 1) * 4; + + test( + 'fetch+load loop across the real CDC bridge must not deadlock', + () async { + final r = await run(program: program); + expect( + r.stalled, + isFalse, + reason: + 'core wedged at fetch addr 0x${r.maxAddr.toRadixString(16)} ' + '(nop at 0x${nopAddr.toRadixString(16)}): reproduces the creek ' + 'ifetch+load CDC deadlock', + ); + expect( + r.maxAddr, + greaterThanOrEqualTo(nopAddr - 4), + reason: 'should fetch through to the nop', + ); + }, + ); + + // ---- L1 dcache data-correctness across the real CDC bridge ---- + // NB: RV64 `lui rd,0x80000` sign-extends bit 31 to 0xFFFFFFFF80000000, so build + // the DRAM base 0x80000000 as (1<<31): addi x3,x0,1 ; slli x3,x3,31. + const swX1 = 0x0011a023; // sw x1, 0(x3) (cacheable write-through) + const lwX2 = 0x0001a103; // lw x2, 0(x3) (cacheable fill) + const li1X3 = 0x00100193; // addi x3, x0, 1 + const slli31X3 = 0x01f19193; // slli x3, x3, 31 -> x3 = 0x80000000 + const luiX1 = 0x123450b7; // lui x1, 0x12345 + const addiX1 = 0x67808093; // addi x1, x1, 0x678 -> x1 = 0x12345678 + const swX2o64 = 0x0421a023; // sw x2, 64(x3) + + test('dcache write-through lands correct data in DRAM', () async { + final prog = [li1X3, slli31X3, luiX1, addiX1, swX1, nop]; + final r = await run(program: prog, maxCycles: 1500, probeAddr: 0x80000000); + expect( + r.probed, + equals(0x12345678), + reason: + 'write-through wrote 0x${r.probed?.toRadixString(16)} not ' + '0x12345678 to DRAM (data corruption)', + ); + }); + + // S-mode Bare load must not hang the core (the Ferrite read-sweep hangs on the + // first S-mode load of 0x80000000; this checks whether that is CORE logic or + // hardware). mret into S-mode (MPP=S), then load 0x80000000 with satp=Bare. + // If the core treats an S-mode Bare load like an M-mode one (it should: no + // translation/walk/perm-check when satp=0), it fetches through to the tail. + test('S-mode Bare load does not hang the core', () async { + final prog = [ + 0x00100593, // addi x11, x0, 1 + 0x00b59593, // slli x11, x11, 11 -> x11 = 0x800 (mstatus.MPP = S) + 0x30059073, // csrw mstatus, x11 + 0x02000613, // addi x12, x0, 0x20 (S-mode entry PC) + 0x34161073, // csrw mepc, x12 + 0x30200073, // mret -> S-mode @ 0x20 + 0x00000013, // nop (0x18) + 0x00000013, // nop (0x1c) + 0x00100193, // addi x3, x0, 1 (0x20, S-mode) + 0x01f19193, // slli x3, x3, 31 -> x3 = 0x80000000 + 0x0001a203, // lw x4, 0(x3) (the load that hangs on hardware) + 0x00000013, // nop (0x2c) + ]; + final r = await run(program: prog, maxCycles: 1500); + expect( + r.stalled, + isFalse, + reason: + 'S-mode Bare load wedged the core at fetch ' + '0x${r.maxAddr.toRadixString(16)} (load is at 0x28): the hang is ' + 'core logic, not hardware', + ); + expect( + r.maxAddr, + greaterThanOrEqualTo(0x28), + reason: 'should fetch past the S-mode load', + ); + }); + + // Store to DRAM, load it back (fill), then store the loaded value to a 2nd + // DRAM address so we can observe what the fill returned (the FSBL copy+verify + // pattern). Catches a fill returning wrong/stale data. + test('dcache round-trip store->fill->store preserves data', () async { + final prog = [ + li1X3, + slli31X3, + luiX1, + addiX1, + swX1, + lwX2, + swX2o64, + nop, + ]; + final r = await run(program: prog, maxCycles: 1500, probeAddr: 0x80000040); + expect( + r.probed, + equals(0x12345678), + reason: + 'fill returned 0x${r.probed?.toRadixString(16)} not 0x12345678 ' + '(read-back corruption)', + ); + }); + + // Round-trip at a 4-aligned (NOT 8-aligned) DRAM address. The dcache fills the + // 8-byte line word, so if exec's byte extraction disagrees with the line + // alignment, an unaligned load reads the wrong half. sw/lw at offset 4. + const swX1o4 = 0x0011a223; // sw x1, 4(x3) + const lwX2o4 = 0x0041a103; // lw x2, 4(x3) + test('dcache round-trip at 4-aligned addr preserves data', () async { + final prog = [ + li1X3, slli31X3, luiX1, addiX1, + swX1o4, // DRAM[0x80000004] = 0x12345678 + lwX2o4, // x2 = DRAM[0x80000004] (fill of the 0x80000000 line, extract hi) + swX2o64, // DRAM[0x80000040] = x2 + nop, + ]; + final r = await run(program: prog, maxCycles: 1500, probeAddr: 0x80000040); + expect( + r.probed, + equals(0x12345678), + reason: + 'unaligned fill returned 0x${r.probed?.toRadixString(16)} not ' + '0x12345678 (line-alignment vs exec-extract mismatch)', + ); + }); +} diff --git a/packages/river_hdl/test/constants.dart b/packages/river_hdl/test/constants.dart index 7e13839..fe8644c 100644 --- a/packages/river_hdl/test/constants.dart +++ b/packages/river_hdl/test/constants.dart @@ -1,61 +1,56 @@ -import 'package:rohd/rohd.dart'; -import 'package:riscv/riscv.dart'; import 'package:river/river.dart'; import 'package:test/test.dart'; -const kCpuConfigs = { - 'RC1.n': const RiverCoreV1.nano( - mmu: Mmu( - mxlen: Mxlen.mxlen_32, - blocks: [ - MemoryBlock( - 0, - (1 << 32) - 1, - DeviceAccessor('/mem', {}, type: DeviceAccessorType.memory), - ), - ], +final kCpuConfigs = { + 'RC1.n': RiverCoreConfigV1.nano( + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv32, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, ), interrupts: [], - clock: ClockConfig(name: 'test', baseFreqHz: 10000), + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), ), - 'RC1.mi': const RiverCoreV1.micro( - mmu: Mmu( - mxlen: Mxlen.mxlen_32, - blocks: [ - MemoryBlock( - 0, - (1 << 32) - 1, - DeviceAccessor('/mem', {}, type: DeviceAccessorType.memory), - ), - ], + 'RC1.mi': RiverCoreConfigV1.micro( + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv32, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, ), interrupts: [], - clock: ClockConfig(name: 'test', baseFreqHz: 10000), + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), ), - 'RC1.s': const RiverCoreV1.small( - mmu: Mmu( - mxlen: Mxlen.mxlen_64, - blocks: [ - MemoryBlock( - 0, - 0xFFFFFFFFFFFF, - DeviceAccessor('/mem', {}, type: DeviceAccessorType.memory), - ), - ], + 'RC1.s': RiverCoreConfigV1.small( + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, ), interrupts: [], - clock: ClockConfig(name: 'test', baseFreqHz: 10000), + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), ), }; void cpuTests( String name, - dynamic Function(RiverCore) body, { - bool Function(RiverCore)? condition, + dynamic Function(RiverCoreConfig) body, { + bool Function(RiverCoreConfig)? condition, }) { for (final entry in kCpuConfigs.entries) { if (condition != null) { - if (!condition!(entry.value)) continue; + if (!condition(entry.value)) continue; } group('${entry.key} - $name', () => body(entry.value)); } diff --git a/packages/river_hdl/test/core/compressed_fetch_buffer_test.dart b/packages/river_hdl/test/core/compressed_fetch_buffer_test.dart new file mode 100644 index 0000000..ff5d838 --- /dev/null +++ b/packages/river_hdl/test/core/compressed_fetch_buffer_test.dart @@ -0,0 +1,399 @@ +import 'dart:async'; + +import 'package:rohd/rohd.dart'; +import 'package:river_hdl/river_hdl.dart'; +import 'package:test/test.dart'; + +/// A single instruction in a synthetic stream: its raw encoding and length in +/// halfwords (1 = compressed/16-bit, 2 = 32-bit). +class _Instr { + final int value; + final int halves; // 1 or 2 + const _Instr(this.value, this.halves); +} + +/// A compressed (16-bit) instruction: low 2 bits must NOT be 0b11. +_Instr _comp(int v) { + assert(v & 0x3 != 0x3, 'compressed encoding must have low bits != 11'); + return _Instr(v & 0xFFFF, 1); +} + +/// A 32-bit instruction: low 2 bits == 0b11. +_Instr _w32(int v) { + assert(v & 0x3 == 0x3, '32-bit encoding must have low bits == 11'); + return _Instr(v & 0xFFFFFFFF, 2); +} + +/// Lay a stream of variable-length instructions into the 2-byte-aligned halfword +/// stream and return (expected (pc, value) list, word memory map keyed by byte +/// address). Words are [dataWidth] bits ([dataWidth]/16 halfwords each). +/// Instructions start at [base]. +(List<(int, int)>, Map) _layout( + List<_Instr> stream, { + int base = 0, + int dataWidth = 64, +}) { + final wordHalves = dataWidth ~/ 16; + final wordBytes = dataWidth ~/ 8; + final expected = <(int, int)>[]; + final halfwords = []; // flat little-endian halfword stream + var pc = base; + for (final ins in stream) { + expected.add((pc, ins.value)); + halfwords.add(ins.value & 0xFFFF); + if (ins.halves == 2) halfwords.add((ins.value >> 16) & 0xFFFF); + pc += ins.halves * 2; + } + // Pad to a whole word with NOPs (c.nop = 0x0001). + while (halfwords.length % wordHalves != 0) { + halfwords.add(0x0001); + } + final mem = {}; + for (var wi = 0; wi * wordHalves < halfwords.length; wi++) { + var word = 0; + for (var h = 0; h < wordHalves; h++) { + word |= (halfwords[wi * wordHalves + h] & 0xFFFF) << (16 * h); + } + mem[base ~/ wordBytes * wordBytes + wi * wordBytes] = word; + } + return (expected, mem); +} + +/// Run the [CompressedFetchBuffer] over a 64-bit response-pulse memory (the +/// interconnect-neutral contract) and collect the (pc, instr) stream it +/// delivers, consuming up to two instructions per cycle. +/// Returns (delivered stream, split index) where the split index is the number +/// of instructions delivered before a redirect fired (== collected.length when +/// no redirect). +Future<(List<(int, int)>, int)> runBuffer( + Map mem, { + required int count, + int latency = 0, + int depth = 4, + int startPc = 0, + int dataWidth = 64, + int consumeStride = 1, // cycles to wait between consumes (>1 = slow consumer) + int? redirectAfter, + int? redirectPc, +}) async { + final clk = SimpleClockGenerator(20).clk; + final reset = Logic(); + final enable = Logic(); + final redirect = Logic(); + final redirectPcL = Logic(width: dataWidth); + final consume0 = Logic(); + final consume1 = Logic(); + final memRead = DataPortInterface(dataWidth, dataWidth); + + Logic wordOf(Logic addr) { + Logic r = Const(0, width: dataWidth); + for (final e in mem.entries) { + r = mux( + addr.eq(Const(e.key, width: dataWidth)), + Const(e.value, width: dataWidth), + r, + ); + } + return r; + } + + // Single-outstanding response-pulse responder (held en+addr; after `latency` + // cycles assert done&valid for one cycle, then a one-cycle gap). + final st = Logic(name: 'rstate', width: 2); + final cnt = Logic(name: 'rcnt', width: 16); + final capAddr = Logic(name: 'rcap', width: dataWidth); + final doneR = Logic(name: 'rdone'); + final validR = Logic(name: 'rvalid'); + final dataR = Logic(name: 'rdata', width: dataWidth); + memRead.done <= doneR; + memRead.valid <= validR; + memRead.data <= dataR; + Sequential(clk, [ + If( + reset, + then: [st < 0, cnt < 0, capAddr < 0, doneR < 0, validR < 0, dataR < 0], + orElse: [ + doneR < 0, + validR < 0, + If.block([ + Iff(st.eq(0) & memRead.en, [ + capAddr < memRead.addr, + if (latency == 0) ...[ + doneR < 1, + validR < 1, + dataR < wordOf(memRead.addr), + st < 2, + ] else ...[ + cnt < Const(latency - 1, width: 16), + st < 1, + ], + ]), + Iff(st.eq(1), [ + If( + cnt.eq(0), + then: [doneR < 1, validR < 1, dataR < wordOf(capAddr), st < 2], + orElse: [cnt < cnt - 1], + ), + ]), + Iff(st.eq(2), [st < 0]), + ]), + ], + ), + ]); + + final buf = CompressedFetchBuffer( + clk, + reset, + enable, + Const(startPc, width: dataWidth), + memRead, + redirect: redirect, + redirectPc: redirectPcL, + consume0: consume0, + consume1: consume1, + depth: depth, + ); + await buf.build(); + + reset.inject(1); + enable.inject(0); + redirect.inject(0); + redirectPcL.inject(0); + consume0.inject(0); + consume1.inject(0); + Simulator.registerAction(15, () { + reset.put(0); + enable.put(1); + }); + Simulator.setMaxSimTime(60000 + latency * 600); + unawaited(Simulator.run()); + await clk.nextPosedge; + while (reset.value.toBool()) { + await clk.nextPosedge; + } + + final collected = <(int, int)>[]; + var splitIndex = -1; + var guard = 0; + while (collected.length < count && guard < 9000 + latency * 300) { + await clk.nextPosedge; + guard++; + + if (redirectAfter != null && collected.length >= redirectAfter) { + splitIndex = + collected.length; // exact boundary (may exceed redirectAfter) + redirect.inject(1); + redirectPcL.inject(redirectPc!); + consume0.inject(0); + consume1.inject(0); + await clk.nextPosedge; + redirect.inject(0); + redirectAfter = null; + continue; + } + + // Slow consumer: only consume every `consumeStride` cycles. With stride > 1 + // the FIFO fills to `depth` and sits full, the regression case for the + // wordCount*wordHalves width-overflow that made a full buffer read as empty. + final mayConsume = (guard % consumeStride == 0); + final v0 = buf.valid0.value; + final v1 = buf.valid1.value; + if (mayConsume && v0.isValid && v0.toBool()) { + collected.add((buf.pc0.value.toInt(), buf.instr0.value.toInt())); + consume0.inject(1); + if (v1.isValid && v1.toBool() && collected.length < count) { + collected.add((buf.pc1.value.toInt(), buf.instr1.value.toInt())); + consume1.inject(1); + } else { + consume1.inject(0); + } + } else { + consume0.inject(0); + consume1.inject(0); + } + } + + await Simulator.endSimulation(); + await Simulator.simulationEnded; + return (collected, splitIndex < 0 ? collected.length : splitIndex); +} + +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + // A mixed variable-length stream (compressed + 32-bit interleaved). Distinct + // values so each delivered instruction is identifiable. + final stream = <_Instr>[ + _comp(0x4505), // c.li x10,1 + _w32(0x00100513), // addi x10,x0,1 + _comp(0x4585), // c.li x11,1 + _comp(0x4609), // c.li x12,2 + _w32(0x00200593), // addi x11,x0,2 + _w32(0x00300613), // addi x12,x0,3 + _comp(0x4685), // c.li x13,1 + _w32(0x00400693), // addi x13,x0,4 + _comp(0x4709), // c.li x14,2 + _comp(0x4789), // c.li x15,2 + _w32(0x00500713), // addi x14,x0,5 + _comp(0x4805), // c.li x16,1 + ]; + + test('all-compressed stream delivers each instr with PC += 2', () async { + final s = [for (var i = 0; i < 12; i++) _comp(0x4501 | (i << 7))]; + final (expected, mem) = _layout(s); + final (got, _) = await runBuffer(mem, count: 12); + expect(got.length, 12); + for (var i = 0; i < 12; i++) { + expect(got[i], expected[i], reason: 'compressed instr $i'); + } + }); + + test('all-32-bit stream delivers each instr with PC += 4', () async { + final s = [for (var i = 0; i < 10; i++) _w32(0x00000013 | ((i + 1) << 20))]; + final (expected, mem) = _layout(s); + final (got, _) = await runBuffer(mem, count: 10); + expect(got.length, 10); + for (var i = 0; i < 10; i++) { + expect(got[i], expected[i], reason: '32-bit instr $i'); + } + }); + + test( + 'mixed variable-length stream delivers correct PCs and values', + () async { + final (expected, mem) = _layout(stream); + final (got, _) = await runBuffer(mem, count: stream.length); + expect(got.length, stream.length); + for (var i = 0; i < stream.length; i++) { + expect(got[i], expected[i], reason: 'mixed instr $i'); + } + }, + ); + + for (final latency in [0, 1, 2, 4]) { + test( + 'mixed stream correct at memory latency $latency', + () async { + final (expected, mem) = _layout(stream); + final (got, _) = await runBuffer( + mem, + count: stream.length, + latency: latency, + ); + expect(got.length, stream.length); + for (var i = 0; i < stream.length; i++) { + expect(got[i], expected[i], reason: 'mixed instr $i lat $latency'); + } + }, + timeout: Timeout(Duration(seconds: 40 + latency * 2)), + ); + } + + for (final d in [4, 8]) { + test( + 'mixed stream correct at FIFO depth $d', + () async { + final (expected, mem) = _layout(stream); + final (got, _) = await runBuffer( + mem, + count: stream.length, + depth: d, + latency: 2, + ); + expect(got.length, stream.length); + for (var i = 0; i < stream.length; i++) { + expect(got[i], expected[i], reason: 'mixed instr $i depth $d'); + } + }, + timeout: Timeout(Duration(seconds: 40)), + ); + } + + // 32-bit fetch port (wordHalves=2), the RV32 dual-dispatch regression width. + // The window must span up to 3 words at this width, so this proves the narrow + // path the in-pipeline integration depends on. + test('32-bit port: mixed variable-length stream correct', () async { + final (expected, mem) = _layout(stream, dataWidth: 32); + final (got, _) = await runBuffer( + mem, + count: stream.length, + dataWidth: 32, + latency: 1, + ); + expect(got.length, stream.length); + for (var i = 0; i < stream.length; i++) { + expect(got[i], expected[i], reason: '32-bit port mixed instr $i'); + } + }); + + test('32-bit port: all-32-bit stream correct (RV32I-like)', () async { + final s = [for (var i = 0; i < 10; i++) _w32(0x00000013 | ((i + 1) << 20))]; + final (expected, mem) = _layout(s, dataWidth: 32); + final (got, _) = await runBuffer(mem, count: 10, dataWidth: 32, latency: 2); + expect(got.length, 10); + for (var i = 0; i < 10; i++) { + expect(got[i], expected[i], reason: '32-bit port 32-bit instr $i'); + } + }); + + // Slow consumer drives the FIFO to FULL and holds it there. Regression for + // the width-overflow bug: wordCount (ptrBits+1 bits) * wordHalves overflowed + // its width when the FIFO was full, collapsing validHalves to 0 so a full + // buffer falsely reported empty and the stream stalled. + for (final dw in [32, 64]) { + for (final stride in [3, 5]) { + test( + '${dw}b port: full FIFO (slow consumer x$stride) keeps streaming', + () async { + final (expected, mem) = _layout(stream, dataWidth: dw); + final (got, _) = await runBuffer( + mem, + count: stream.length, + dataWidth: dw, + depth: 4, + consumeStride: stride, + ); + expect(got.length, stream.length); + for (var i = 0; i < stream.length; i++) { + expect(got[i], expected[i], reason: '${dw}b full-FIFO instr $i'); + } + }, + timeout: Timeout(Duration(seconds: 40)), + ); + } + } + + test( + 'redirect to a mid-word (compressed-aligned) PC resteers correctly', + () async { + // Source stream at 0, target stream at 0x40 (8-byte aligned base) but we + // redirect to 0x42, a 2-byte (mid-word) offset to prove headOff handling. + final (srcExp, srcMem) = _layout(stream); + final tgt = [for (var i = 0; i < 8; i++) _comp(0x4401 | (i << 7))]; + // Lay the target so that 0x42 lands on a real compressed instruction: put a + // filler compressed at 0x40, then the tgt stream from 0x42. + final tgtStream = [_comp(0x4001), ...tgt]; + final (tgtExpRaw, tgtMem) = _layout(tgtStream, base: 0x40); + final mem = {...srcMem, ...tgtMem}; + // Expected after redirect: the tgt stream starting at 0x42. + final tgtExp = tgtExpRaw.where((e) => e.$1 >= 0x42).toList(); + + final (got, split) = await runBuffer( + mem, + count: 4 + tgt.length, + redirectAfter: 4, + redirectPc: 0x42, + ); + // Everything before the redirect boundary comes from the source stream. + for (var i = 0; i < split; i++) { + expect(got[i], srcExp[i], reason: 'pre-redirect $i'); + } + // Everything after comes from the target stream at 0x42. + for (var i = split; i < got.length; i++) { + expect(got[i], tgtExp[i - split], reason: 'post-redirect ${i - split}'); + } + }, + ); +} diff --git a/packages/river_hdl/test/core/csr_stateen_test.dart b/packages/river_hdl/test/core/csr_stateen_test.dart new file mode 100644 index 0000000..3bf75a6 --- /dev/null +++ b/packages/river_hdl/test/core/csr_stateen_test.dart @@ -0,0 +1,99 @@ +import 'dart:async'; + +import 'package:rohd/rohd.dart'; +import 'package:river/river.dart'; +import 'package:river_hdl/river_hdl.dart'; +import 'package:test/test.dart'; + +/// Drives [RiscVCsrFile] directly to check the Smstateen SE0 access gate: when +/// mstateen0.SE0 (bit 63) is clear, an sstateen0 access from below M is illegal +/// (csrRead.valid drops, which the pipeline turns into a trap); when set, it is +/// allowed and reads 0. Mirrors the emulator's stateen_test. +void main() { + const mstateen0 = 0x30C; + const sstateen0 = 0x10C; + final se0 = BigInt.one << 63; + + test('mstateen0.SE0 gates S-mode sstateen0 (and WARL)', () async { + await Simulator.reset(); + final clk = SimpleClockGenerator(10).clk; + final reset = Logic(name: 'reset'); + final mode = Logic(name: 'mode', width: 3); + final csrRead = DataPortInterface(64, 12); + final csrWrite = DataPortInterface(64, 12); + + final csrs = RiscVCsrFile( + clk, + reset, + mode, + mxlen: RiscVMxlen.rv64, + misa: RiscVMxlen.rv64.misa, + hasSupervisor: true, + hasStateen: true, + csrRead: csrRead, + csrWrite: csrWrite, + ); + await csrs.build(); + + csrRead.en.inject(0); + csrRead.addr.inject(0); + csrWrite.en.inject(0); + csrWrite.addr.inject(0); + csrWrite.data.inject(0); + mode.inject(3); // machine + reset.inject(1); + Simulator.setMaxSimTime(100000); + unawaited(Simulator.run()); + await clk.nextPosedge; + await clk.nextPosedge; + reset.inject(0); + await clk.nextPosedge; + + // Frontdoor write a CSR from M-mode (mstateen0 is an M CSR). + Future writeM(int addr, BigInt data) async { + mode.inject(3); + csrWrite.addr.inject(addr); + csrWrite.data.inject(LogicValue.ofBigInt(data, 64)); + csrWrite.en.inject(1); + await clk.nextPosedge; + csrWrite.en.inject(0); + await clk.nextPosedge; + } + + // Drive a read in [m] mode and return (valid, data). + Future<(int, BigInt)> read(int modeId, int addr) async { + mode.inject(modeId); + csrRead.addr.inject(addr); + csrRead.en.inject(1); + await clk.nextPosedge; + final v = csrRead.valid.value.toInt(); + final d = csrRead.data.value.toBigInt(); + csrRead.en.inject(0); + return (v, d); + } + + // SE0 set -> S-mode sstateen0 access allowed, reads 0. + await writeM(mstateen0, se0); + final (vAllowed, dAllowed) = await read(1, sstateen0); + expect(vAllowed, 1, reason: 'SE0 set -> sstateen0 access legal'); + expect(dAllowed, BigInt.zero, reason: 'sstateen0 reads 0'); + + // SE0 clear -> S-mode sstateen0 access denied (illegal -> valid drops). + await writeM(mstateen0, BigInt.zero); + final (vDenied, _) = await read(1, sstateen0); + expect(vDenied, 0, reason: 'SE0 clear -> sstateen0 access illegal'); + + // M-mode is never gated, even with SE0 clear. + final (vM, _) = await read(3, sstateen0); + expect(vM, 1, reason: 'M-mode sstateen0 access is always legal'); + + // WARL: only SE0 (bit 63) sticks. + await writeM(mstateen0, (BigInt.one << 64) - BigInt.one); // all ones + final (vWarl, dWarl) = await read(3, mstateen0); + expect(vWarl, 1); + expect(dWarl, se0, reason: 'only SE0 writable; other bits WARL-0'); + + await Simulator.endSimulation(); + await Simulator.simulationEnded; + }); +} diff --git a/packages/river_hdl/test/core/decode_control_test.dart b/packages/river_hdl/test/core/decode_control_test.dart new file mode 100644 index 0000000..80b4aa7 --- /dev/null +++ b/packages/river_hdl/test/core/decode_control_test.dart @@ -0,0 +1,91 @@ +import 'package:harbor/harbor.dart'; +import 'package:river/river.dart'; +import 'package:river_hdl/src/core/decode_control.dart'; +import 'package:river_hdl/src/core/issue.dart' show FuType; +import 'package:test/test.dart'; + +import '../constants.dart'; + +void main() { + group('decodeControlForOp', () { + // RC1.mi (RV32IMAC + Zicsr) has the full mix: ALU, mem, branch, jump, CSR. + final ops = kCpuConfigs['RC1.mi']!.isa.allOperations; + DecodeControl ctrl(String mnemonic) { + final op = ops.firstWhere( + (o) => o.mnemonic == mnemonic, + orElse: () => throw StateError('no op "$mnemonic" in RC1.mi'), + ); + return decodeControlForOp(op); + } + + test('add → ALU, add, writes rd, register operand', () { + final c = ctrl('add'); + expect(c.fuType, FuType.alu); + expect(c.aluFunct, RiscVAluFunct.add); + expect(c.writesRd, isTrue); + expect(c.useImm, isFalse); + expect(c.isLoad, isFalse); + expect(c.isStore, isFalse); + }); + + test('addi → ALU, add, immediate operand', () { + final c = ctrl('addi'); + expect(c.fuType, FuType.alu); + expect(c.aluFunct, RiscVAluFunct.add); + expect(c.useImm, isTrue); + expect(c.writesRd, isTrue); + }); + + test('sub → ALU, sub', () { + expect(ctrl('sub').aluFunct, RiscVAluFunct.sub); + }); + + test('lw → memory load, writes rd, word size', () { + final c = ctrl('lw'); + expect(c.fuType, FuType.memory); + expect(c.isLoad, isTrue); + expect(c.isStore, isFalse); + expect(c.writesRd, isTrue); + expect(c.memSize, RiscVMemSize.word); + }); + + test('sw → memory store, no rd write', () { + final c = ctrl('sw'); + expect(c.fuType, FuType.memory); + expect(c.isStore, isTrue); + expect(c.isLoad, isFalse); + expect(c.writesRd, isFalse); + }); + + test('beq → branch, eq condition, no jump, no rd write', () { + final c = ctrl('beq'); + expect(c.fuType, FuType.branch); + expect(c.branchCond, RiscVBranchCondition.eq); + expect(c.isJump, isFalse); + expect(c.writesRd, isFalse); + }); + + test('jal → unconditional jump, PC-relative, writes link', () { + final c = ctrl('jal'); + expect(c.fuType, FuType.branch); + expect(c.isJump, isTrue); + expect(c.isJalr, isFalse); + expect(c.writesRd, isTrue); + }); + + test('jalr → unconditional jump, register-indirect, writes link', () { + final c = ctrl('jalr'); + expect(c.fuType, FuType.branch); + expect(c.isJump, isTrue); + expect(c.isJalr, isTrue); + expect(c.writesRd, isTrue); + }); + + test('csrrw → CSR unit, writes rd', () { + final c = ctrl('csrrw'); + expect(c.fuType, FuType.csr); + expect(c.isCsr, isTrue); + expect(c.writesRd, isTrue); + }); + }); +} diff --git a/packages/river_hdl/test/core/decoder_test.dart b/packages/river_hdl/test/core/decoder_test.dart index 7b975ec..3ec0604 100644 --- a/packages/river_hdl/test/core/decoder_test.dart +++ b/packages/river_hdl/test/core/decoder_test.dart @@ -1,17 +1,17 @@ import 'dart:async'; import 'package:rohd/rohd.dart'; -import 'package:rohd_hcl/rohd_hcl.dart'; -import 'package:riscv/riscv.dart'; +import 'package:rohd_hcl/rohd_hcl.dart' hide DataPortInterface, DataPortGroup; +import 'package:harbor/harbor.dart'; import 'package:river/river.dart'; import 'package:river_hdl/river_hdl.dart'; import 'package:test/test.dart'; -Future decoderTest( +Future decoderTest( int instr, Map fields, - Mxlen mxlen, - Microcode microcode, { + RiscVMxlen mxlen, + MicrocodeRom microcode, { bool isDynamic = false, }) async { final clk = SimpleClockGenerator(20).clk; @@ -29,7 +29,7 @@ Future decoderTest( clk, reset, [], - [microcodeRead], + [wrapReadForRegisterFile(microcodeRead)], numEntries: microcode.map.length, resetValue: microcode.encodedPatterns, ); @@ -55,8 +55,6 @@ Future decoderTest( await decoder.build(); - WaveDumper(decoder); - reset.inject(1); enable.inject(0); @@ -73,28 +71,27 @@ Future decoderTest( await clk.nextPosedge; } - while (!decoder.done.value.toBool()) { + while (true) { + final d = decoder.done.value; + if (d.isValid && d.toBool()) break; await clk.nextPosedge; } + // Capture field values when done is asserted + final valid = decoder.valid.value; + final fieldValues = {}; + for (final entry in fields.entries) { + final f = decoder.fields[entry.key]; + if (f != null) fieldValues[entry.key] = f.value; + } + await Simulator.endSimulation(); await Simulator.simulationEnded; - expect(decoder.valid.value.toBool(), isTrue); - - final typeName = T.toString(); - - for (final entry in decoder.instrTypeMap.entries) { - final value = entry.value.value.toBool(); - if (entry.key == typeName) { - expect(value, isTrue); - } else { - expect(value, isFalse); - } - } + expect(valid.toBool(), isTrue); for (final entry in fields.entries) { - final value = decoder.fields[entry.key]!.value.toInt(); + final value = fieldValues[entry.key]!.toInt(); expect(value, equals(entry.value), reason: '${entry.key}=$value'); } } @@ -106,10 +103,12 @@ void main() { void define(bool isDynamic) { group('RV32I', () { - final microcode = Microcode(Microcode.buildDecodeMap([rv32i])); + final microcode = MicrocodeRom( + RiscVIsaConfig(mxlen: RiscVMxlen.rv32, extensions: [rv32i]), + ); test('R-type: add x3, x1, x2', () async { - await decoderTest( + await decoderTest( 0x002081B3, { 'opcode': 0x33, @@ -119,27 +118,45 @@ void main() { 'funct3': 0, 'funct7': 0, }, - Mxlen.mxlen_32, + RiscVMxlen.rv32, microcode, isDynamic: isDynamic, ); }); test('I-type: addi x5, x1, 10', () async { - await decoderTest( + await decoderTest( 0x00A08293, {'opcode': 0x13, 'rd': 5, 'rs1': 1, 'imm': 10, 'funct3': 0}, - Mxlen.mxlen_32, + RiscVMxlen.rv32, microcode, isDynamic: isDynamic, ); }); test('S-type: sw x2, 12(x1)', () async { - await decoderTest( + await decoderTest( 0x0020A623, - {'opcode': 0x23, 'rs1': 1, 'rs2': 2, 'funct3': 0x2, 'imm[4:0]': 12}, - Mxlen.mxlen_32, + {'opcode': 0x23, 'rs1': 1, 'rs2': 2, 'funct3': 0x2, 'immLo': 12}, + RiscVMxlen.rv32, + microcode, + isDynamic: isDynamic, + ); + }); + + // A negative store offset must sign-extend the S-type immediate to full + // width. Regression for the zero-extend-then-sign-extend no-op bug. + test('S-type sign-extend: sw x2, -4(x1)', () async { + await decoderTest( + 0xFE20AE23, + { + 'opcode': 0x23, + 'rs1': 1, + 'rs2': 2, + 'funct3': 0x2, + 'imm': 0xFFFFFFFC, + }, + RiscVMxlen.rv32, microcode, isDynamic: isDynamic, ); diff --git a/packages/river_hdl/test/core/exec_test.dart b/packages/river_hdl/test/core/exec_test.dart index 61e2ab3..73cdc20 100644 --- a/packages/river_hdl/test/core/exec_test.dart +++ b/packages/river_hdl/test/core/exec_test.dart @@ -1,8 +1,7 @@ import 'dart:async'; import 'package:rohd/rohd.dart'; -import 'package:rohd_hcl/rohd_hcl.dart'; -import 'package:riscv/riscv.dart'; +import 'package:rohd_hcl/rohd_hcl.dart' hide DataPortInterface, DataPortGroup; import 'package:river/river.dart'; import 'package:river_hdl/river_hdl.dart'; import 'package:test/test.dart'; @@ -10,8 +9,8 @@ import 'package:test/test.dart'; Future execTest( int instr, Map regStates, - Microcode microcode, - Mxlen mxlen, { + MicrocodeRom microcode, + RiscVMxlen mxlen, { Map memStates = const {}, Map csrStates = const {}, Map initMem = const {}, @@ -64,11 +63,12 @@ Future execTest( LogicValue.filled(dataWidth, LogicValue.zero), ); + // ignore: unused_local_variable final mem = MemoryModel( clk, reset, - [backingMemWrite], - [memRead, backingMemRead], + [wrapWriteForRegisterFile(backingMemWrite)], + [wrapReadForRegisterFile(memRead), wrapReadForRegisterFile(backingMemRead)], readLatency: memLatency, storage: storage, ); @@ -88,8 +88,8 @@ Future execTest( final regs = RegisterFile( clk, reset, - [rdWrite], - [rs1Read, rs2Read], + [wrapWriteForRegisterFile(rdWrite)], + [wrapReadForRegisterFile(rs1Read), wrapReadForRegisterFile(rs2Read)], numEntries: 32, ); @@ -102,7 +102,7 @@ Future execTest( clk, reset, [], - [microcodeRead], + [wrapReadForRegisterFile(microcodeRead)], numEntries: microcode.encodedMops(mxlen).length, resetValue: microcode.encodedMops(mxlen), ); @@ -166,13 +166,6 @@ Future execTest( Simulator.registerAction(15, () { reset.put(0); - for (final regState in initRegisters.entries) { - regs.setData( - LogicValue.ofInt(regState.key.value, 5), - LogicValue.ofInt(regState.value, mxlen.size), - ); - } - for (final memState in initMem.entries) { storage.setData( LogicValue.ofInt(memState.key, mxlen.size), @@ -186,10 +179,9 @@ Future execTest( LogicValue.ofInt(csrState.value, mxlen.size), ); } - - enable.inject(1); }); + Simulator.setMaxSimTime(10000); unawaited(Simulator.run()); await clk.nextPosedge; @@ -198,6 +190,18 @@ Future execTest( await clk.nextPosedge; } + // Write initial register values one per cycle + for (final regState in initRegisters.entries) { + rdWrite.en.inject(1); + rdWrite.addr.inject(LogicValue.ofInt(regState.key.value, 5)); + rdWrite.data.inject(LogicValue.ofInt(regState.value, mxlen.size)); + await clk.nextPosedge; + } + + // Disable register write port after init + rdWrite.en.inject(0); + await clk.nextPosedge; + for (final csrState in initCsrs.entries) { csrs .getBackdoor(LogicValue.ofInt(csrState.key.address, 12)) @@ -205,16 +209,15 @@ Future execTest( .inject(0); } - while (!exec.done.value.toBool()) { - await clk.nextPosedge; - } + // Enable execution + enable.inject(1); - while (exec.nextPc.value.toInt() != nextPc) { + for (var i = 0; i < 100; i++) { await clk.nextPosedge; + final d = exec.done.value; + if (d.isValid && d.toBool()) break; } - await clk.nextPosedge; - await Simulator.endSimulation(); await Simulator.simulationEnded; @@ -251,7 +254,10 @@ void main() { void define(bool isDynamic) { group('RV32I', () { - final microcode = Microcode(Microcode.buildDecodeMap([rv32i])); + final microcode = MicrocodeRom( + RiscVIsaConfig(mxlen: RiscVMxlen.rv32, extensions: [rv32i]), + encodings: kMicroOpTable, + ); test( 'addi increments register', @@ -259,7 +265,7 @@ void main() { 0x00a08293, {Register.x5: 10}, microcode, - Mxlen.mxlen_32, + RiscVMxlen.rv32, isDynamic: isDynamic, ), ); @@ -270,7 +276,7 @@ void main() { 0x005303B3, {Register.x7: 16}, microcode, - Mxlen.mxlen_32, + RiscVMxlen.rv32, initRegisters: {Register.x5: 7, Register.x6: 9}, isDynamic: isDynamic, ), @@ -282,7 +288,7 @@ void main() { 0x0042A303, {Register.x6: 0xDEADBEEF}, microcode, - Mxlen.mxlen_32, + RiscVMxlen.rv32, initRegisters: {Register.x5: 0x20}, initMem: {0x24: 0xDEADBEEF}, isDynamic: isDynamic, @@ -295,7 +301,7 @@ void main() { 0x0062A223, {}, microcode, - Mxlen.mxlen_32, + RiscVMxlen.rv32, initRegisters: {Register.x5: 0x20, Register.x6: 0xDEADBEEF}, initMem: {}, isDynamic: isDynamic, @@ -308,7 +314,7 @@ void main() { 0x00628463, {}, microcode, - Mxlen.mxlen_32, + RiscVMxlen.rv32, initRegisters: {Register.x5: 5, Register.x6: 5}, nextPc: 8, isDynamic: isDynamic, @@ -321,7 +327,7 @@ void main() { 0x00628463, {}, microcode, - Mxlen.mxlen_32, + RiscVMxlen.rv32, initRegisters: {Register.x5: 5, Register.x6: 7}, nextPc: 4, isDynamic: isDynamic, @@ -334,7 +340,7 @@ void main() { 0x123452B7, {Register.x5: 0x12345000}, microcode, - Mxlen.mxlen_32, + RiscVMxlen.rv32, isDynamic: isDynamic, ), ); @@ -345,7 +351,7 @@ void main() { 0x100002EF, {Register.x5: 4}, microcode, - Mxlen.mxlen_32, + RiscVMxlen.rv32, nextPc: 0x100, isDynamic: isDynamic, ), @@ -357,7 +363,7 @@ void main() { 0x00010297, {Register.x5: 0x10000}, microcode, - Mxlen.mxlen_32, + RiscVMxlen.rv32, isDynamic: isDynamic, ), ); @@ -368,7 +374,7 @@ void main() { 0x00A22293, {Register.x5: 1}, microcode, - Mxlen.mxlen_32, + RiscVMxlen.rv32, initRegisters: {Register.x4: 5}, isDynamic: isDynamic, ), @@ -376,7 +382,9 @@ void main() { }); group('Zicsr', () { - final microcode = Microcode(Microcode.buildDecodeMap([rv32i, rv32Zicsr])); + final microcode = MicrocodeRom( + RiscVIsaConfig(mxlen: RiscVMxlen.rv32, extensions: [rv32i, rvZicsr]), + ); test( 'csrrw: atomic swap (rd=old, CSR=new)', @@ -384,7 +392,7 @@ void main() { 0x34029373, {Register.x6: 0xAAAA}, microcode, - Mxlen.mxlen_32, + RiscVMxlen.rv32, initRegisters: {Register.x5: 0x1234}, initCsrs: {CsrAddress.mscratch: 0xAAAA}, csrStates: {CsrAddress.mscratch: 0x1234}, @@ -398,7 +406,7 @@ void main() { 0x34029073, {Register.x0: 0}, microcode, - Mxlen.mxlen_32, + RiscVMxlen.rv32, initRegisters: {Register.x5: 0x2222}, initCsrs: {CsrAddress.mscratch: 0x1111}, csrStates: {CsrAddress.mscratch: 0x2222}, @@ -412,7 +420,7 @@ void main() { 0x3402A373, {Register.x6: 0x100}, microcode, - Mxlen.mxlen_32, + RiscVMxlen.rv32, initRegisters: {Register.x5: 0x0F}, initCsrs: {CsrAddress.mscratch: 0x100}, csrStates: {CsrAddress.mscratch: 0x10F}, @@ -426,7 +434,7 @@ void main() { 0x3400A073, {}, microcode, - Mxlen.mxlen_32, + RiscVMxlen.rv32, initCsrs: {CsrAddress.mscratch: 0xABCDE}, csrStates: {CsrAddress.mscratch: 0xABCDE}, isDynamic: isDynamic, @@ -439,7 +447,7 @@ void main() { 0x3402B373, {Register.x6: 0xFF}, microcode, - Mxlen.mxlen_32, + RiscVMxlen.rv32, initRegisters: {Register.x5: 0x0F}, initCsrs: {CsrAddress.mscratch: 0xFF}, csrStates: {CsrAddress.mscratch: 0xF0}, @@ -453,7 +461,7 @@ void main() { 0x3402D373, {Register.x6: 0x7777}, microcode, - Mxlen.mxlen_32, + RiscVMxlen.rv32, initCsrs: {CsrAddress.mscratch: 0x7777}, csrStates: {CsrAddress.mscratch: 5}, isDynamic: isDynamic, @@ -466,7 +474,7 @@ void main() { 0x3401E073, {}, microcode, - Mxlen.mxlen_32, + RiscVMxlen.rv32, initCsrs: {CsrAddress.mscratch: 0x10}, csrStates: {CsrAddress.mscratch: 0x13}, isDynamic: isDynamic, @@ -479,7 +487,7 @@ void main() { 0x3401F073, {}, microcode, - Mxlen.mxlen_32, + RiscVMxlen.rv32, initCsrs: {CsrAddress.mscratch: 0xF}, csrStates: {CsrAddress.mscratch: 0xC}, isDynamic: isDynamic, diff --git a/packages/river_hdl/test/core/fetcher_test.dart b/packages/river_hdl/test/core/fetcher_test.dart index f5bc8fc..b164890 100644 --- a/packages/river_hdl/test/core/fetcher_test.dart +++ b/packages/river_hdl/test/core/fetcher_test.dart @@ -1,9 +1,7 @@ import 'dart:async'; import 'package:rohd/rohd.dart'; -import 'package:rohd_hcl/rohd_hcl.dart'; -import 'package:riscv/riscv.dart'; -import 'package:river/river.dart'; +import 'package:rohd_hcl/rohd_hcl.dart' hide DataPortInterface, DataPortGroup; import 'package:river_hdl/river_hdl.dart'; import 'package:test/test.dart'; @@ -19,11 +17,12 @@ Future fetcherTest( final memRead = DataPortInterface(32, 32); + // ignore: unused_local_variable final mem = MemoryModel( clk, reset, [], - [memRead], + [wrapReadForRegisterFile(memRead, clk: clk, readLatency: latency)], readLatency: latency, storage: SparseMemoryStorage( addrWidth: 32, @@ -53,6 +52,7 @@ Future fetcherTest( reset.inject(1); enable.inject(0); + Simulator.setMaxSimTime(10000 + latency * 50); unawaited(Simulator.run()); await clk.nextPosedge; @@ -63,20 +63,24 @@ Future fetcherTest( await clk.nextPosedge; - while (!fetcher.done.value.toBool()) { + while (true) { await clk.nextPosedge; + final d = fetcher.done.value; + if (d.isValid && d.toBool()) break; } - await clk.nextPosedge; + final resultValue = fetcher.result.value; + final doneValue = fetcher.done.value; + final compressedValue = hasCompressed ? fetcher.compressed.value : null; await Simulator.endSimulation(); await Simulator.simulationEnded; - expect(fetcher.done.value.toBool(), isTrue); - expect(fetcher.result.value.toInt(), instr); + expect(doneValue.toBool(), isTrue); + expect(resultValue.toInt(), instr); if (hasCompressed) { - expect(fetcher.compressed.value.toBool(), isCompressed); + expect(compressedValue!.toBool(), isCompressed); } } @@ -91,7 +95,11 @@ void main() { const latencies = [12, 24, 36, 120, 240, 360, 1200]; for (final latency in latencies) { - test('Latency $latency', () => fetcherTest(0x00a08293, latency: latency)); + test( + 'Latency $latency', + () => fetcherTest(0x00a08293, latency: latency), + timeout: Timeout(Duration(seconds: latency ~/ 10 + 30)), + ); } }); @@ -112,6 +120,7 @@ void main() { hasCompressed: true, isCompressed: true, ), + timeout: Timeout(Duration(seconds: latency ~/ 10 + 30)), ); } }); diff --git a/packages/river_hdl/test/core/instruction_aligner_test.dart b/packages/river_hdl/test/core/instruction_aligner_test.dart new file mode 100644 index 0000000..7ae5b6a --- /dev/null +++ b/packages/river_hdl/test/core/instruction_aligner_test.dart @@ -0,0 +1,123 @@ +import 'package:rohd/rohd.dart'; +import 'package:river_hdl/river_hdl.dart'; +import 'package:test/test.dart'; + +/// Unit tests for the variable-length instruction aligner: given a halfword +/// window, it must extract two back-to-back instructions of any 2/4-byte length +/// combination, with correct sizes, PCs (via size), and validity (boundary). +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + // Compressed (16-bit) halfword: low 2 bits != 0b11. e.g. c.addi = 0x0505. + // 32-bit halfword: low 2 bits == 0b11. e.g. addi low half ...0x13 (bits 1:0=11). + const comp = 0x4505; // c.li x10, 1 low bits 01 -> compressed + const comp2 = 0x4585; // c.li x11, 1 + // 32-bit instr 0x00100513 = addi x10,x0,1 -> low half 0x0513, high half 0x0010 + const w32lo = 0x0513; + const w32hi = 0x0010; + const w32 = 0x00100513; + const x32lo = 0x0593; // addi x11,x0,... low half + const x32hi = 0x0020; + const x32 = 0x00200593; + + /// Build the aligner with a 4-halfword window and drive it. + Future> align(List hwords, int validCount) async { + final halves = Logic(width: 64); + final vc = Logic(width: 3); + final a = InstructionAligner(halves, vc, laneCount: 4); + await a.build(); + var packed = 0; + for (var i = 0; i < 4; i++) { + packed |= (hwords[i] & 0xFFFF) << (16 * i); + } + halves.put(packed); + vc.put(validCount); + return { + 'instr0': a.instr0.value.toInt(), + 'size0': a.size0.value.toInt(), + 'comp0': a.compressed0.value.toInt(), + 'valid0': a.valid0.value.toInt(), + 'instr1': a.instr1.value.toInt(), + 'size1': a.size1.value.toInt(), + 'comp1': a.compressed1.value.toInt(), + 'valid1': a.valid1.value.toInt(), + }; + } + + test('compressed + compressed', () async { + final r = await align([comp, comp2, 0, 0], 2); + expect(r['instr0'], comp); + expect(r['size0'], 1); + expect(r['comp0'], 1); + expect(r['valid0'], 1); + expect(r['instr1'], comp2); + expect(r['size1'], 1); + expect(r['comp1'], 1); + expect(r['valid1'], 1); + }); + + test('compressed + 32-bit', () async { + final r = await align([comp, w32lo, w32hi, 0], 3); + expect(r['instr0'], comp); + expect(r['size0'], 1); + expect(r['valid0'], 1); + expect(r['instr1'], w32); // {hi, lo} at halfwords 1,2 + expect(r['size1'], 2); + expect(r['comp1'], 0); + expect(r['valid1'], 1); + }); + + test('32-bit + compressed', () async { + final r = await align([w32lo, w32hi, comp2, 0], 3); + expect(r['instr0'], w32); + expect(r['size0'], 2); + expect(r['comp0'], 0); + expect(r['valid0'], 1); + expect(r['instr1'], comp2); // halfword 2 + expect(r['size1'], 1); + expect(r['comp1'], 1); + expect(r['valid1'], 1); + }); + + test('32-bit + 32-bit', () async { + final r = await align([w32lo, w32hi, x32lo, x32hi], 4); + expect(r['instr0'], w32); + expect(r['size0'], 2); + expect(r['valid0'], 1); + expect(r['instr1'], x32); // halfwords 2,3 + expect(r['size1'], 2); + expect(r['valid1'], 1); + }); + + test( + 'boundary: only lane 0 valid (32-bit instr0, 2 halves, no room for i1)', + () async { + final r = await align([w32lo, w32hi, comp2, 0], 2); + expect(r['instr0'], w32); + expect(r['valid0'], 1); + expect(r['valid1'], 0); // only 2 halfwords -> instr1 not present + }, + ); + + test( + 'boundary: 32-bit instr0 straddles, only 1 half valid -> instr0 invalid', + () async { + final r = await align([w32lo, w32hi, 0, 0], 1); + expect(r['size0'], 2); + expect(r['valid0'], 0); // needs 2 halfwords, only 1 valid + expect(r['valid1'], 0); + }, + ); + + test( + 'boundary: compressed instr0 with 1 half valid -> instr0 valid, i1 not', + () async { + final r = await align([comp, 0, 0, 0], 1); + expect(r['instr0'], comp); + expect(r['valid0'], 1); + expect(r['valid1'], 0); + }, + ); +} diff --git a/packages/river_hdl/test/core/issue_queue_count_test.dart b/packages/river_hdl/test/core/issue_queue_count_test.dart new file mode 100644 index 0000000..127ab92 --- /dev/null +++ b/packages/river_hdl/test/core/issue_queue_count_test.dart @@ -0,0 +1,129 @@ +import 'dart:async'; + +import 'package:rohd/rohd.dart'; +import 'package:river_hdl/river_hdl.dart'; +import 'package:test/test.dart'; + +/// Direct unit test for the issue-queue occupancy `count`. Regression guard for +/// the bug where `count` was driven by scattered `count Const(0, width: w); + final iq = IssueQueue( + clk, + reset, + // slot 0: a ready ALU op + enqValid0: enqValid0, + enqTag0: z(7), + enqPsrc10: z(7), + enqPsrc20: z(7), + enqPdst0: z(7), + enqImm0: z(64), + enqPc0: z(64), + enqFunct0: z(7), + enqFuType0: Const(FuType.alu.index, width: 2), + enqWritesRd0: Const(1), + enqIsStore0: Const(0), + enqMemSize0: z(3), + enqBranchCond0: z(3), + enqIsJump0: Const(0), + enqIsJalr0: Const(0), + enqUseImm0: Const(1), + enqCsrOp0: z(3), + enqCsrAddr0: z(12), + enqSignExtend0: Const(0), + // slot 1: unused + enqValid1: Const(0), + enqTag1: z(7), + enqPsrc11: z(7), + enqPsrc21: z(7), + enqPdst1: z(7), + enqImm1: z(64), + enqPc1: z(64), + enqFunct1: z(7), + enqFuType1: Const(FuType.alu.index, width: 2), + enqWritesRd1: Const(0), + enqIsStore1: Const(0), + enqMemSize1: z(3), + enqBranchCond1: z(3), + enqIsJump1: Const(0), + enqIsJalr1: Const(0), + enqUseImm1: Const(0), + enqCsrOp1: z(3), + enqCsrAddr1: z(12), + enqSignExtend1: Const(0), + // operands: both sources ready (so each entry can dispatch immediately) + enqSrc1Value0: z(64), + enqSrc2Value0: z(64), + enqSrc1Ready0: Const(1), + enqSrc2Ready0: Const(1), + enqSrc1Value1: z(64), + enqSrc2Value1: z(64), + enqSrc1Ready1: Const(0), + enqSrc2Ready1: Const(0), + // no wakeups + wakeupValid0: Const(0), + wakeupTag0: z(7), + wakeupValue0: z(64), + wakeupValid1: Const(0), + wakeupTag1: z(7), + wakeupValue1: z(64), + // all FUs free + aluBusy0: Const(0), + aluBusy1: Const(0), + memBusy: Const(0), + branchBusy: Const(0), + csrBusy: Const(0), + flush: Const(0), + ); + await iq.build(); + + reset.inject(1); + enqValid0.inject(0); + Simulator.registerAction(15, () => reset.put(0)); + Simulator.setMaxSimTime(10000); + unawaited(Simulator.run()); + await clk.nextPosedge; + while (reset.value.toBool()) { + await clk.nextPosedge; + } + + // Enqueue ONLY when the IQ says it can accept (enqReady), exactly like the + // core's back-pressure. The conflicting-count bug under-counts on each + // enqueue+dispatch overlap, so `count` underflows, wraps to a huge value, + // and `enqReady` (= count < depth-1) sticks low. Then enqueue stops, the + // queue drains, and dispatch dies. The net-update count keeps enqReady + // correct, so dispatch sustains ~1/cycle. + enqValid0.inject(1); + var dispatches = 0; + const cycles = 40; + for (var i = 0; i < cycles; i++) { + await clk.nextPosedge; + final d = iq.dispatchAluValid0.value; + if (d.isValid && d.toBool()) dispatches++; + final er = iq.enqReady.value; + enqValid0.inject(er.isValid && er.toBool() ? 1 : 0); + } + await Simulator.endSimulation(); + await Simulator.simulationEnded; + + expect( + dispatches, + greaterThan(cycles - 8), + reason: 'IQ wedged: only $dispatches/$cycles dispatches (count bug)', + ); + }); +} diff --git a/packages/river_hdl/test/core/pipeline_test.dart b/packages/river_hdl/test/core/pipeline_test.dart index 37627f6..edd59b7 100644 --- a/packages/river_hdl/test/core/pipeline_test.dart +++ b/packages/river_hdl/test/core/pipeline_test.dart @@ -1,8 +1,7 @@ import 'dart:async'; import 'package:rohd/rohd.dart'; -import 'package:rohd_hcl/rohd_hcl.dart'; -import 'package:riscv/riscv.dart'; +import 'package:rohd_hcl/rohd_hcl.dart' hide DataPortInterface, DataPortGroup; import 'package:river/river.dart'; import 'package:river_hdl/river_hdl.dart'; import 'package:test/test.dart'; @@ -10,8 +9,8 @@ import 'package:test/test.dart'; Future pipelineTest( int instr, Map regStates, - Microcode microcode, - Mxlen mxlen, { + MicrocodeRom microcode, + RiscVMxlen mxlen, { Map initRegisters = const {}, int maxSimTime = 800, int cycleCount = 8, @@ -44,11 +43,15 @@ Future pipelineTest( final rs2Read = DataPortInterface(mxlen.size, 5); final rdWrite = DataPortInterface(mxlen.size, 5); + // ignore: unused_local_variable final mem = MemoryModel( clk, reset, [], - [memFetchRead, memExecRead], + [ + wrapReadForRegisterFile(memFetchRead), + wrapReadForRegisterFile(memExecRead), + ], readLatency: latency, storage: SparseMemoryStorage( addrWidth: mxlen.size, @@ -62,8 +65,8 @@ Future pipelineTest( final regs = RegisterFile( clk, reset, - [rdWrite], - [rs1Read, rs2Read], + [wrapWriteForRegisterFile(rdWrite)], + [wrapReadForRegisterFile(rs1Read), wrapReadForRegisterFile(rs2Read)], numEntries: 32, ); @@ -95,29 +98,38 @@ Future pipelineTest( await pipeline.build(); reset.inject(1); + enable.inject(0); - Simulator.registerAction(20, () { - reset.put(0); + Simulator.setMaxSimTime(2000 + maxSimTime * ((latency ~/ 36) + 1)); + unawaited(Simulator.run()); - for (final regState in initRegisters.entries) { - regs.setData( - LogicValue.ofInt(regState.key.value, 5), - LogicValue.ofInt(regState.value, mxlen.size), - ); - } + // Release reset + await clk.nextPosedge; + reset.put(0); - enable.put(1); - }); + // Write initial register values one per cycle + for (final regState in initRegisters.entries) { + rdWrite.en.inject(1); + rdWrite.addr.inject(LogicValue.ofInt(regState.key.value, 5)); + rdWrite.data.inject(LogicValue.ofInt(regState.value, mxlen.size)); + await clk.nextPosedge; + } + rdWrite.en.inject(0); - Simulator.setMaxSimTime(maxSimTime * ((latency ~/ 36) + 1)); - unawaited(Simulator.run()); + // Enable pipeline + enable.put(1); - for (var i = 0; i < cycleCount; i++) { + // Wait for pipeline done + for (var i = 0; i < 100; i++) { await clk.nextPosedge; + final d = pipeline.done.value; + if (d.isValid && d.toBool()) break; } + await Simulator.endSimulation(); await Simulator.simulationEnded; + expect(pipeline.done.value.isValid, isTrue); expect(pipeline.done.value.toBool(), isTrue); expect(pipeline.nextPc.value.toInt(), nextPc); @@ -135,7 +147,9 @@ void main() { }); group('RV32I', () { - final microcode = Microcode(Microcode.buildDecodeMap([rv32i])); + final microcode = MicrocodeRom( + RiscVIsaConfig(mxlen: RiscVMxlen.rv32, extensions: [rv32i]), + ); test( 'addi increments register', @@ -143,7 +157,7 @@ void main() { 0x00a08293, {Register.x5: 10}, microcode, - Mxlen.mxlen_32, + RiscVMxlen.rv32, ), ); @@ -153,7 +167,7 @@ void main() { 0x005303B3, {Register.x7: 16}, microcode, - Mxlen.mxlen_32, + RiscVMxlen.rv32, initRegisters: {Register.x5: 7, Register.x6: 9}, maxSimTime: 800, ), @@ -165,7 +179,7 @@ void main() { 0x00628463, {}, microcode, - Mxlen.mxlen_32, + RiscVMxlen.rv32, initRegisters: {Register.x5: 5, Register.x6: 5}, nextPc: 8, maxSimTime: 800, @@ -178,7 +192,7 @@ void main() { 0x00628463, {}, microcode, - Mxlen.mxlen_32, + RiscVMxlen.rv32, initRegisters: {Register.x5: 5, Register.x6: 7}, nextPc: 4, maxSimTime: 800, @@ -191,7 +205,7 @@ void main() { 0x100002EF, {Register.x5: 4}, microcode, - Mxlen.mxlen_32, + RiscVMxlen.rv32, nextPc: 0x100, maxSimTime: 800, ), @@ -203,7 +217,7 @@ void main() { 0x00010297, {Register.x5: 0x10000}, microcode, - Mxlen.mxlen_32, + RiscVMxlen.rv32, maxSimTime: 800, ), ); @@ -214,7 +228,7 @@ void main() { 0x00A22293, {Register.x5: 1}, microcode, - Mxlen.mxlen_32, + RiscVMxlen.rv32, initRegisters: {Register.x4: 5}, maxSimTime: 800, ), diff --git a/packages/river_hdl/test/core/pipelined_fetch_memory_test.dart b/packages/river_hdl/test/core/pipelined_fetch_memory_test.dart new file mode 100644 index 0000000..7ab2ee3 --- /dev/null +++ b/packages/river_hdl/test/core/pipelined_fetch_memory_test.dart @@ -0,0 +1,181 @@ +import 'dart:async'; + +import 'package:rohd/rohd.dart'; +import 'package:river_hdl/river_hdl.dart'; +import 'package:test/test.dart'; + +/// End-to-end: a real synthesizable [PipelinedFetchMemory] (registered-read, +/// multi-outstanding BRAM) feeding a [PipelinedFetchUnit] through one shared +/// [FetchReadInterface]. The program is loaded over the memory's write port +/// while fetch is disabled, then streamed. Proves the in-core downstream the +/// front-end needs works against the real engine. Returns (stream, cycles). +Future<(List<(int, int)>, int)> runRealMem( + List prog, { + required int count, + int readLatency = 1, + int maxOutstanding = 2, + int depth = 4, + bool useInit = false, +}) async { + await Simulator.reset(); + final clk = SimpleClockGenerator(20).clk; + final reset = Logic(); + final enable = Logic(); + final advance = Logic(); + final redirect = Logic(); + final redirectPcL = Logic(width: 32); + final writeEn = Logic(); + final writeAddr = Logic(width: 32); + final writeData = Logic(width: 32); + + final link = FetchReadInterface(32, 32); + final mem = PipelinedFetchMemory( + clk, + reset, + link, + writeEn: writeEn, + writeAddr: writeAddr, + writeData: writeData, + initWords: useInit ? prog : const [], + words: 64, + readLatency: readLatency, + ); + final fetcher = PipelinedFetchUnit( + clk, + reset, + enable, + Const(0, width: 32), + link, + advance: advance, + redirect: redirect, + redirectPc: redirectPcL, + depth: depth, + maxOutstanding: maxOutstanding, + ); + await mem.build(); + await fetcher.build(); + + reset.inject(1); + enable.inject(0); + advance.inject(0); + redirect.inject(0); + redirectPcL.inject(0); + writeEn.inject(0); + writeAddr.inject(0); + writeData.inject(0); + Simulator.setMaxSimTime(60000 + readLatency * 600); + unawaited(Simulator.run()); + + await clk.nextPosedge; + reset.inject(0); + await clk.nextPosedge; + + // Load the program over the write port (fetch still disabled), unless the + // memory was initialised as a ROM at reset. + if (!useInit) { + for (var i = 0; i < prog.length; i++) { + writeEn.inject(1); + writeAddr.inject(i * 4); + writeData.inject(prog[i]); + await clk.nextPosedge; + } + writeEn.inject(0); + } + enable.inject(1); + + final collected = <(int, int)>[]; + var cycles = 0; + var guard = 0; + while (collected.length < count && guard < 8000 + readLatency * 200) { + await clk.nextPosedge; + guard++; + cycles++; + final d = fetcher.done.value; + if (d.isValid && d.toBool()) { + collected.add(( + fetcher.pcOut.value.toInt(), + fetcher.result.value.toInt(), + )); + advance.inject(1); + } else { + advance.inject(0); + } + } + + await Simulator.endSimulation(); + await Simulator.simulationEnded; + return (collected, cycles); +} + +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + final seq = [for (var i = 0; i < 16; i++) (0x00000013 | ((i + 1) << 20))]; + + for (final readLatency in [1, 2]) { + test( + 'real mem: in-order stream at readLatency $readLatency', + () async { + final (got, _) = await runRealMem( + seq, + count: 12, + readLatency: readLatency, + maxOutstanding: readLatency + 1, + depth: 1 << (readLatency + 2).bitLength, + ); + expect(got.length, 12); + for (var i = 0; i < 12; i++) { + expect(got[i], ( + i * 4, + seq[i], + ), reason: 'instr $i at readLatency $readLatency'); + } + }, + timeout: Timeout(Duration(seconds: 40)), + ); + } + + // ROM init: contents loaded at reset (no write-port boot), the path the core + // uses for a tightly-coupled instruction memory. + test('real mem: ROM-initialised contents stream correctly', () async { + final (got, _) = await runRealMem( + seq, + count: 12, + readLatency: 1, + maxOutstanding: 2, + depth: 4, + useInit: true, + ); + expect(got.length, 12); + for (var i = 0; i < 12; i++) { + expect(got[i], (i * 4, seq[i]), reason: 'ROM-init instr $i'); + } + }); + + // The real BRAM has a read latency, but with enough outstanding the engine + // still streams ~1 instr/cycle (a single-outstanding port would pay the + // latency on every read). + test('real mem: sustains ~1 instr/cycle despite read latency', () async { + const count = 12; + const readLatency = 2; + final (got, cycles) = await runRealMem( + seq, + count: count, + readLatency: readLatency, + maxOutstanding: 3, + depth: 8, + ); + expect(got.length, count); + for (var i = 0; i < count; i++) { + expect(got[i], (i * 4, seq[i])); + } + // Single-outstanding would need ~count*(readLatency+1) = 36; assert well under. + expect( + cycles, + lessThan(count + readLatency + 8), + reason: 'did not sustain throughput (took $cycles cycles)', + ); + }); +} diff --git a/packages/river_hdl/test/core/pipelined_fetcher_test.dart b/packages/river_hdl/test/core/pipelined_fetcher_test.dart new file mode 100644 index 0000000..cd2a989 --- /dev/null +++ b/packages/river_hdl/test/core/pipelined_fetcher_test.dart @@ -0,0 +1,269 @@ +import 'dart:async'; + +import 'package:rohd/rohd.dart'; +import 'package:river_hdl/river_hdl.dart'; +import 'package:test/test.dart'; + +import 'pipelined_responder.dart'; + +/// Drives [PipelinedFetchUnit] (master) wired to [PipelinedReadResponder] +/// (slave, a real pipelined multi-outstanding memory) through one shared +/// [FetchReadInterface]. Free-running consumer: advance whenever a head is +/// delivered. Returns (deliveredStream, cyclesToCollect). +Future<(List<(int, int)>, int)> runPipelined( + Map mem, { + required int count, + int latency = 4, + int maxOutstanding = 4, + int depth = 8, + int? redirectAfter, + int? redirectPc, +}) async { + // Reset at entry so this harness can be called repeatedly within one test + // (the throughput benchmark sweeps several configs in a single test body). + await Simulator.reset(); + final clk = SimpleClockGenerator(20).clk; + final reset = Logic(); + final enable = Logic(); + final advance = Logic(); + final redirect = Logic(); + final redirectPcL = Logic(width: 32); + + final link = FetchReadInterface(32, 32); + final responder = PipelinedReadResponder( + clk, + reset, + link, + mem, + latency: latency, + maxOutstanding: maxOutstanding, + ); + final fetcher = PipelinedFetchUnit( + clk, + reset, + enable, + Const(0, width: 32), + link, + advance: advance, + redirect: redirect, + redirectPc: redirectPcL, + depth: depth, + maxOutstanding: maxOutstanding, + ); + await responder.build(); + await fetcher.build(); + + reset.inject(1); + enable.inject(0); + advance.inject(0); + redirect.inject(0); + redirectPcL.inject(0); + Simulator.registerAction(15, () { + reset.put(0); + enable.put(1); + }); + Simulator.setMaxSimTime(60000 + latency * 600); + unawaited(Simulator.run()); + + await clk.nextPosedge; + while (reset.value.toBool()) { + await clk.nextPosedge; + } + + final collected = <(int, int)>[]; + var cycles = 0; + var guard = 0; + while (collected.length < count && guard < 8000 + latency * 200) { + await clk.nextPosedge; + guard++; + cycles++; + if (redirectAfter != null && collected.length == redirectAfter) { + redirect.inject(1); + redirectPcL.inject(redirectPc!); + advance.inject(0); + await clk.nextPosedge; + cycles++; + redirect.inject(0); + redirectAfter = null; + continue; + } + final d = fetcher.done.value; + if (d.isValid && d.toBool()) { + collected.add(( + fetcher.pcOut.value.toInt(), + fetcher.result.value.toInt(), + )); + advance.inject(1); + } else { + advance.inject(0); + } + } + + await Simulator.endSimulation(); + await Simulator.simulationEnded; + return (collected, cycles); +} + +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + final seq = [for (var i = 0; i < 16; i++) (0x00000013 | ((i + 1) << 20))]; + final mem = {for (var i = 0; i < seq.length; i++) i * 4: seq[i]}; + + // Correctness: each instruction delivered with its PC, in order, across + // latencies and outstanding depths. + for (final latency in [0, 1, 2, 4, 8]) { + test( + 'pipelined fetch: in-order stream at latency $latency', + () async { + final (got, _) = await runPipelined( + mem, + count: 12, + latency: latency, + maxOutstanding: 4, + depth: 8, + ); + expect(got.length, 12); + for (var i = 0; i < 12; i++) { + expect(got[i], (i * 4, seq[i]), reason: 'instr $i lat $latency'); + } + }, + timeout: Timeout(Duration(seconds: 40 + latency * 2)), + ); + } + + // The point of the whole exercise: with enough outstanding reads, a multi- + // cycle fetch latency is hidden. At latency L with maxOutstanding >= L, the + // steady-state delivery is ~1 instr/cycle, so collecting N takes ~N+L cycles, + // NOT the N*(L+1) a single-outstanding fetcher needs. + test('pipelined fetch: hides latency (maxOutstanding >= latency)', () async { + const count = 12; + const latency = 4; + final (got, cycles) = await runPipelined( + mem, + count: count, + latency: latency, + maxOutstanding: 4, + depth: 8, + ); + expect(got.length, count); + for (var i = 0; i < count; i++) { + expect(got[i], (i * 4, seq[i])); + } + // Single-outstanding would need ~count*(latency+1) = 60; assert we are far + // below that, proving the reads pipelined. + expect( + cycles, + lessThan(count + latency + 8), + reason: 'latency not hidden (took $cycles cycles for $count instrs)', + ); + }); + + // maxOutstanding == 1 must reproduce the single-outstanding behaviour exactly + // (strict superset): still correct, just no latency hiding. + test( + 'pipelined fetch: maxOutstanding==1 is correct (single-outstanding)', + () async { + final (got, _) = await runPipelined( + mem, + count: 8, + latency: 3, + maxOutstanding: 1, + depth: 2, + ); + expect(got.length, 8); + for (var i = 0; i < 8; i++) { + expect(got[i], (i * 4, seq[i]), reason: 'single-outstanding instr $i'); + } + }, + ); + + // Quantify the fetchOutstanding knob: same engine, same pipelined memory, only + // maxOutstanding changes. At a fetch latency L, outstanding=1 needs ~N*(L+1) + // cycles (the FIFO drains between reads) while outstanding=L hides it to ~N+L. + test( + 'benchmark: fetchOutstanding hides fetch latency', + () async { + const count = 16; + final rows = []; + for (final latency in [1, 2, 4, 8]) { + final (g1, c1) = await runPipelined( + mem, + count: count, + latency: latency, + maxOutstanding: 1, + depth: 2, + ); + final (gN, cN) = await runPipelined( + mem, + count: count, + latency: latency, + maxOutstanding: latency, + depth: 1 << (latency + 1).bitLength, + ); + expect(g1.length, count); + expect(gN.length, count); + final speedup = (c1 / cN).toStringAsFixed(2); + rows.add( + 'latency=$latency: outstanding=1 -> $c1 cyc, ' + 'outstanding=$latency -> $cN cyc (${speedup}x)', + ); + // The knob must help (more so as latency grows) and never hurt. + expect( + cN, + lessThanOrEqualTo(c1), + reason: 'multi-outstanding slower at latency $latency', + ); + } + // ignore: avoid_print + print( + '\n=== fetch throughput vs fetchOutstanding (16 instrs) ===\n' + '${rows.join('\n')}\n', + ); + }, + timeout: Timeout(Duration(seconds: 90)), + ); + + // Redirect mid-stream: flush + drain the in-flight (now stale) responses, then + // deliver the resteered stream. The hard case for multi-outstanding (several + // stale responses must be dropped, not delivered). + for (final latency in [1, 4]) { + test( + 'pipelined fetch: redirect drains stale responses at latency $latency', + () async { + final tgt = [ + for (var i = 0; i < 8; i++) (0x00000093 | ((i + 1) << 20)), + ]; + final m = { + ...mem, + for (var i = 0; i < tgt.length; i++) 0x40 + i * 4: tgt[i], + }; + final (got, _) = await runPipelined( + m, + count: 7, + latency: latency, + maxOutstanding: 4, + depth: 8, + redirectAfter: 3, + redirectPc: 0x40, + ); + for (var i = 0; i < 3; i++) { + expect(got[i], ( + i * 4, + seq[i], + ), reason: 'pre-redirect $i lat $latency'); + } + for (var i = 3; i < got.length; i++) { + final j = i - 3; + expect(got[i], ( + 0x40 + j * 4, + tgt[j], + ), reason: 'post-redirect $j lat $latency'); + } + }, + timeout: Timeout(Duration(seconds: 40 + latency * 2)), + ); + } +} diff --git a/packages/river_hdl/test/core/pipelined_responder.dart b/packages/river_hdl/test/core/pipelined_responder.dart new file mode 100644 index 0000000..89e4a9f --- /dev/null +++ b/packages/river_hdl/test/core/pipelined_responder.dart @@ -0,0 +1,94 @@ +import 'package:rohd/rohd.dart'; +import 'package:river_hdl/river_hdl.dart'; + +/// Behavioral pipelined memory that honours [FetchReadInterface] from the SLAVE +/// side: fixed `latency`-cycle, in-order reads with up to `maxOutstanding` +/// requests in flight. This is the representative multiple-outstanding read port +/// the single-outstanding test models could not provide, so the multi-outstanding +/// fetch engine can be exercised against a real pipelined memory. +/// +/// `mem` maps byte address -> 32-bit word; unmapped reads return 0. Responses +/// come back exactly `latency` cycles after acceptance, one per accepted request, +/// in order. `reqReady` deasserts while `maxOutstanding` requests are in flight, +/// which is how back-pressure is exercised (set `maxOutstanding < latency`). +class PipelinedReadResponder extends Module { + PipelinedReadResponder( + Logic clk, + Logic reset, + FetchReadInterface port, + Map mem, { + int latency = 4, + int maxOutstanding = 8, + super.name = 'pipelined_read_responder', + }) : super(definitionName: 'PipelinedReadResponder') { + assert(latency >= 0, 'latency must be >= 0'); + assert(maxOutstanding >= 1, 'maxOutstanding must be >= 1'); + clk = addInput('clk', clk); + reset = addInput('reset', reset); + final aw = port.addrWidth; + final dw = port.dataWidth; + + port = port.clone() + ..connectIO( + this, + port, + // Slave view: request is an input; ready + response are outputs. + inputTags: {FetchReadGroup.request}, + outputTags: {FetchReadGroup.requestReady, FetchReadGroup.response}, + uniquify: (og) => 'port_$og', + ); + + Logic wordOf(Logic addr) { + Logic r = Const(0, width: dw); + for (final e in mem.entries) { + r = mux(addr.eq(Const(e.key, width: aw)), Const(e.value, width: dw), r); + } + return r; + } + + final cntW = (maxOutstanding + 2).bitLength; + final inflight = Logic(name: 'inflight', width: cntW); + final reqReady = inflight.lt(maxOutstanding).named('reqReadyInt'); + final accept = (port.reqValid & reqReady).named('accept'); + port.reqReady <= reqReady; + + if (latency == 0) { + // Same-cycle response: nothing is ever in flight. + port.rspValid <= accept; + port.rspData <= wordOf(port.reqAddr); + Sequential(clk, [inflight < 0]); + } else { + final validPipe = List.generate(latency, (i) => Logic(name: 'vp_$i')); + final addrPipe = List.generate( + latency, + (i) => Logic(name: 'ap_$i', width: aw), + ); + final retire = validPipe[latency - 1]; + port.rspValid <= retire; + port.rspData <= wordOf(addrPipe[latency - 1]); + + Sequential(clk, [ + If( + reset, + then: [ + inflight < 0, + for (final v in validPipe) v < 0, + for (final a in addrPipe) a < 0, + ], + orElse: [ + // Shift the {valid, addr} pipe; inject the accepted request at stage 0. + validPipe[0] < accept, + addrPipe[0] < port.reqAddr, + for (var i = 1; i < latency; i++) ...[ + validPipe[i] < validPipe[i - 1], + addrPipe[i] < addrPipe[i - 1], + ], + // One accept enters, one retire leaves: net update the counter. + inflight < + (inflight + accept.zeroExtend(cntW) - retire.zeroExtend(cntW)), + ], + ), + ]); + } + } +} diff --git a/packages/river_hdl/test/core/pipelined_responder_test.dart b/packages/river_hdl/test/core/pipelined_responder_test.dart new file mode 100644 index 0000000..ae057c3 --- /dev/null +++ b/packages/river_hdl/test/core/pipelined_responder_test.dart @@ -0,0 +1,146 @@ +import 'dart:async'; + +import 'package:rohd/rohd.dart'; +import 'package:river_hdl/river_hdl.dart'; +import 'package:test/test.dart'; + +import 'pipelined_responder.dart'; + +/// Drives [PipelinedReadResponder] with a free-running, hold-until-accepted +/// master: `reqValid` stays high, `reqAddr` advances only when the request is +/// accepted (`reqValid & reqReady`). Responses are in order, so the k-th +/// collected word must equal mem[k*4]. Returns (collectedWords, cyclesUsed, +/// sawBackpressure). +Future<(List, int, bool)> runResponder( + Map mem, { + required int count, + int latency = 4, + int maxOutstanding = 16, +}) async { + final clk = SimpleClockGenerator(20).clk; + final reset = Logic(); + final reqValid = Logic(); + final reqAddr = Logic(width: 32); + + final port = FetchReadInterface(32, 32); + port.reqValid <= reqValid; + port.reqAddr <= reqAddr; + + final dut = PipelinedReadResponder( + clk, + reset, + port, + mem, + latency: latency, + maxOutstanding: maxOutstanding, + ); + await dut.build(); + + reset.inject(1); + reqValid.inject(0); + reqAddr.inject(0); + Simulator.registerAction(15, () => reset.put(0)); + Simulator.setMaxSimTime(40000 + latency * 400); + unawaited(Simulator.run()); + + await clk.nextPosedge; + while (reset.value.toBool()) { + await clk.nextPosedge; + } + + reqValid.inject(1); + var curAddr = 0; + reqAddr.inject(curAddr); + final collected = []; + var cycles = 0; + var sawBackpressure = false; + var guard = 0; + while (collected.length < count && guard < 8000 + latency * 200) { + guard++; + cycles++; + // Settle: sample whether the upcoming posedge will accept the held request. + await clk.nextNegedge; + final ready = port.reqReady.value; + final willAccept = ready.isValid && ready.toBool(); + if (!willAccept) sawBackpressure = true; + await clk.nextPosedge; + final rv = port.rspValid.value; + if (rv.isValid && rv.toBool()) { + collected.add(port.rspData.value.toInt()); + } + if (willAccept) { + curAddr += 4; + reqAddr.inject(curAddr); + } + } + + await Simulator.endSimulation(); + await Simulator.simulationEnded; + return (collected, cycles, sawBackpressure); +} + +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + // 12 distinct words at 0x00, 0x04, ... + final seq = [for (var i = 0; i < 12; i++) (0x00000013 | ((i + 1) << 20))]; + final mem = {for (var i = 0; i < seq.length; i++) i * 4: seq[i]}; + + // Pipelined, no back-pressure (maxOutstanding >= latency): responses must be + // in order AND arrive ~1/cycle, so total cycles ~ latency + count (NOT the + // count*(latency+1) a single-outstanding port would take). + for (final latency in [0, 1, 2, 4, 8]) { + test( + 'pipelined: in-order + ~1/cycle throughput at latency $latency', + () async { + const count = 8; + final (got, cycles, sawBp) = await runResponder( + mem, + count: count, + latency: latency, + maxOutstanding: 16, + ); + expect(got.length, count); + for (var i = 0; i < count; i++) { + expect(got[i], seq[i], reason: 'word $i at latency $latency'); + } + // No back-pressure expected when maxOutstanding >> latency. + expect(sawBp, isFalse, reason: 'unexpected back-pressure'); + // Pipelined bound: a single-outstanding port would need + // count*(latency+1); assert we are far under that. + expect( + cycles, + lessThanOrEqualTo(count + latency + 4), + reason: 'not pipelined at latency $latency (took $cycles cycles)', + ); + }, + timeout: Timeout(Duration(seconds: 40 + latency * 2)), + ); + } + + // Back-pressure: maxOutstanding < latency forces reqReady low at times. The + // stream must still be correct and complete (no deadlock, no reorder). + test('back-pressure: maxOutstanding < latency stays correct', () async { + const count = 10; + final (got, cycles, sawBp) = await runResponder( + mem, + count: count, + latency: 6, + maxOutstanding: 2, + ); + expect(got.length, count); + for (var i = 0; i < count; i++) { + expect(got[i], seq[i], reason: 'word $i under back-pressure'); + } + expect(sawBp, isTrue, reason: 'cap=2 < latency=6 should back-pressure'); + // Capacity 2 over a 6-cycle pipe: throughput ~2/6, so noticeably slower + // than the unthrottled case but still far better than fully serial. + expect( + cycles, + greaterThan(count + 6 + 4), + reason: 'back-pressure should slow it vs the unthrottled bound', + ); + }); +} diff --git a/packages/river_hdl/test/core/prefetch_fetcher_test.dart b/packages/river_hdl/test/core/prefetch_fetcher_test.dart new file mode 100644 index 0000000..4c52d21 --- /dev/null +++ b/packages/river_hdl/test/core/prefetch_fetcher_test.dart @@ -0,0 +1,390 @@ +import 'dart:async'; + +import 'package:rohd/rohd.dart'; +import 'package:rohd_hcl/rohd_hcl.dart' hide DataPortInterface, DataPortGroup; +import 'package:river_hdl/river_hdl.dart'; +import 'package:test/test.dart'; + +/// Drives the prefetch fetcher as a free-running consumer (advance whenever a +/// head is delivered) and records the delivered (pc, instruction) stream. +Future> runPrefetch( + String memString, { + int count = 8, + int latency = 0, + int? redirectAfter, + int? redirectPc, +}) async { + final clk = SimpleClockGenerator(20).clk; + final reset = Logic(); + final enable = Logic(); + final advance = Logic(); + final redirect = Logic(); + final redirectPcL = Logic(width: 32); + + final memRead = DataPortInterface(32, 32); + final storage = SparseMemoryStorage( + addrWidth: 32, + dataWidth: 32, + alignAddress: (addr) => addr, + onInvalidRead: (addr, dataWidth) => + LogicValue.filled(dataWidth, LogicValue.zero), + ); + // ignore: unused_local_variable + final mem = MemoryModel( + clk, + reset, + [], + [wrapReadForRegisterFile(memRead, clk: clk, readLatency: latency)], + readLatency: latency, + storage: storage, + ); + + final fetcher = PrefetchFetchUnit( + clk, + reset, + enable, + Const(0, width: 32), + memRead, + advance: advance, + redirect: redirect, + redirectPc: redirectPcL, + ); + await fetcher.build(); + + reset.inject(1); + enable.inject(0); + advance.inject(0); + redirect.inject(0); + redirectPcL.inject(0); + + // Load AFTER reset releases: MemoryModel clears its storage while reset is + // asserted, so an earlier load would be wiped. + Simulator.registerAction(15, () { + reset.put(0); + enable.put(1); + storage.loadMemString(memString); + }); + + Simulator.setMaxSimTime(20000 + latency * 200); + unawaited(Simulator.run()); + + await clk.nextPosedge; + while (reset.value.toBool()) { + await clk.nextPosedge; + } + + final collected = <(int, int)>[]; + var guard = 0; + while (collected.length < count && guard < 4000 + latency * 100) { + await clk.nextPosedge; + guard++; + if (redirectAfter != null && collected.length == redirectAfter) { + // Fire a one-cycle redirect, then keep consuming. + redirect.inject(1); + redirectPcL.inject(redirectPc!); + advance.inject(0); + await clk.nextPosedge; + redirect.inject(0); + redirectAfter = null; // only once + continue; + } + final d = fetcher.done.value; + if (d.isValid && d.toBool()) { + collected.add(( + fetcher.pcOut.value.toInt(), + fetcher.result.value.toInt(), + )); + advance.inject(1); + } else { + advance.inject(0); + } + } + + await Simulator.endSimulation(); + await Simulator.simulationEnded; + return collected; +} + +String progAt(Map> blocks) { + final sb = StringBuffer(); + for (final entry in blocks.entries) { + sb.write('@${entry.key.toRadixString(16)}\n'); + for (final word in entry.value) { + for (var i = 0; i < 4; i++) { + sb.write(((word >> (i * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + sb.write('\n'); + } + return sb.toString(); +} + +/// Drives the prefetch fetcher against a GENERIC single-outstanding response- +/// PULSE read port, the contract the real MMU and AXI/TileLink adapters present +/// (NOT the level-held pipe of wrapReadForRegisterFile). Holding en+addr, the +/// responder waits `latency` cycles then asserts done&valid for exactly ONE +/// cycle with the word, then a one-cycle gap before it can launch the next read. +/// This is the interconnect-neutral portability test. `mem` is byteAddr->word. +Future> runPrefetchPulse( + Map mem, { + int count = 8, + int latency = 1, + int depth = 2, + int? redirectAfter, + int? redirectPc, +}) async { + final clk = SimpleClockGenerator(20).clk; + final reset = Logic(); + final enable = Logic(); + final advance = Logic(); + final redirect = Logic(); + final redirectPcL = Logic(width: 32); + final memRead = DataPortInterface(32, 32); + + Logic wordOf(Logic addr) { + Logic r = Const(0, width: 32); + for (final e in mem.entries) { + r = mux(addr.eq(Const(e.key, width: 32)), Const(e.value, width: 32), r); + } + return r; + } + + final st = Logic(name: 'rstate', width: 2); // 0 idle, 1 counting, 2 gap + final cnt = Logic(name: 'rcnt', width: 16); + final capAddr = Logic(name: 'rcap', width: 32); + final doneR = Logic(name: 'rdone'); + final validR = Logic(name: 'rvalid'); + final dataR = Logic(name: 'rdata', width: 32); + memRead.done <= doneR; + memRead.valid <= validR; + memRead.data <= dataR; + Sequential(clk, [ + If( + reset, + then: [st < 0, cnt < 0, capAddr < 0, doneR < 0, validR < 0, dataR < 0], + orElse: [ + doneR < 0, + validR < 0, + If.block([ + Iff(st.eq(0) & memRead.en, [ + capAddr < memRead.addr, + if (latency == 0) ...[ + doneR < 1, + validR < 1, + dataR < wordOf(memRead.addr), + st < 2, + ] else ...[ + cnt < Const(latency - 1, width: 16), + st < 1, + ], + ]), + Iff(st.eq(1), [ + If( + cnt.eq(0), + then: [doneR < 1, validR < 1, dataR < wordOf(capAddr), st < 2], + orElse: [cnt < cnt - 1], + ), + ]), + Iff(st.eq(2), [st < 0]), + ]), + ], + ), + ]); + + final fetcher = PrefetchFetchUnit( + clk, + reset, + enable, + Const(0, width: 32), + memRead, + advance: advance, + redirect: redirect, + redirectPc: redirectPcL, + depth: depth, + ); + await fetcher.build(); + + reset.inject(1); + enable.inject(0); + advance.inject(0); + redirect.inject(0); + redirectPcL.inject(0); + Simulator.registerAction(15, () { + reset.put(0); + enable.put(1); + }); + Simulator.setMaxSimTime(40000 + latency * 400); + unawaited(Simulator.run()); + await clk.nextPosedge; + while (reset.value.toBool()) { + await clk.nextPosedge; + } + final collected = <(int, int)>[]; + var guard = 0; + while (collected.length < count && guard < 8000 + latency * 200) { + await clk.nextPosedge; + guard++; + if (redirectAfter != null && collected.length == redirectAfter) { + redirect.inject(1); + redirectPcL.inject(redirectPc!); + advance.inject(0); + await clk.nextPosedge; + redirect.inject(0); + redirectAfter = null; + continue; + } + final d = fetcher.done.value; + if (d.isValid && d.toBool()) { + collected.add(( + fetcher.pcOut.value.toInt(), + fetcher.result.value.toInt(), + )); + advance.inject(1); + } else { + advance.inject(0); + } + } + await Simulator.endSimulation(); + await Simulator.simulationEnded; + return collected; +} + +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + // 8 distinct non-compressed words at 0x00, 0x04, ... + final seq = [for (var i = 0; i < 12; i++) (0x00000013 | ((i + 1) << 20))]; + + test('sequential stream delivers each instr with its PC', () async { + final got = await runPrefetch(progAt({0: seq}), count: 8); + expect(got.length, 8); + for (var i = 0; i < 8; i++) { + expect(got[i], (i * 4, seq[i]), reason: 'instr $i'); + } + }); + + // NOTE: only latency 0 is exercised here. The read engine holds `en` and waits + // for the bus to drop `valid` on an address change (the real MMU/Wishbone fetch + // contract). The MemoryModel's wrapReadForRegisterFile drives `valid` as a pipe + // keyed to `en` continuity (NOT to the address), which is only faithful to the + // real bus at latency 0 (valid = en, data combinational on addr). Higher + // latencies are covered by the in-pipeline test (core_prefetch_test) where the + // fetch port is the real MMU. See project_hdl_prefetch. + for (final latency in [0]) { + test( + 'sequential stream correct at latency $latency', + () async { + final got = await runPrefetch( + progAt({0: seq}), + count: 8, + latency: latency, + ); + expect(got.length, 8); + for (var i = 0; i < 8; i++) { + expect(got[i], (i * 4, seq[i]), reason: 'instr $i lat $latency'); + } + }, + timeout: Timeout(Duration(seconds: 30 + latency)), + ); + } + + test('redirect mid-stream resteers to the new PC', () async { + // Target block at 0x40 with distinct values. + final tgt = [for (var i = 0; i < 8; i++) (0x00000093 | ((i + 1) << 20))]; + final got = await runPrefetch( + progAt({0: seq, 0x40: tgt}), + count: 7, + redirectAfter: 3, + redirectPc: 0x40, + ); + // First 3 from the @0 stream. + for (var i = 0; i < 3; i++) { + expect(got[i], (i * 4, seq[i]), reason: 'pre-redirect $i'); + } + // Remaining from the @0x40 stream. + for (var i = 3; i < got.length; i++) { + final j = i - 3; + expect(got[i], (0x40 + j * 4, tgt[j]), reason: 'post-redirect $j'); + } + }); + + // ── Interconnect portability: the generic response-PULSE contract ────────── + // These exercise the read engine against a single-outstanding response-pulse + // port (the contract the real MMU and AXI/TileLink adapters present), across + // latencies, proving the fetcher is not tied to any one interconnect's timing. + final memMap = {for (var i = 0; i < seq.length; i++) i * 4: seq[i]}; + + for (final latency in [0, 1, 2, 4, 8]) { + test( + 'pulse port: sequential stream correct at latency $latency', + () async { + final got = await runPrefetchPulse(memMap, count: 8, latency: latency); + expect(got.length, 8); + for (var i = 0; i < 8; i++) { + expect(got[i], (i * 4, seq[i]), reason: 'instr $i lat $latency'); + } + }, + timeout: Timeout(Duration(seconds: 40 + latency * 2)), + ); + } + + // Deeper FIFO (power-of-two): correctness must hold at any depth (the depth + // is a buffering knob; it does not change which instructions are delivered). + for (final d in [4, 8]) { + test( + 'pulse port: depth $d delivers the correct stream', + () async { + final got = await runPrefetchPulse( + memMap, + count: 8, + latency: 3, + depth: d, + ); + expect(got.length, 8); + for (var i = 0; i < 8; i++) { + expect(got[i], (i * 4, seq[i]), reason: 'instr $i depth $d'); + } + }, + timeout: Timeout(Duration(seconds: 40)), + ); + } + + for (final latency in [1, 4]) { + test( + 'pulse port: redirect mid-stream at latency $latency', + () async { + final tgt = [ + for (var i = 0; i < 8; i++) (0x00000093 | ((i + 1) << 20)), + ]; + final mem = { + ...memMap, + for (var i = 0; i < tgt.length; i++) 0x40 + i * 4: tgt[i], + }; + final got = await runPrefetchPulse( + mem, + count: 7, + latency: latency, + redirectAfter: 3, + redirectPc: 0x40, + ); + for (var i = 0; i < 3; i++) { + expect(got[i], ( + i * 4, + seq[i], + ), reason: 'pre-redirect $i lat $latency'); + } + for (var i = 3; i < got.length; i++) { + final j = i - 3; + expect(got[i], ( + 0x40 + j * 4, + tgt[j], + ), reason: 'post-redirect $j lat $latency'); + } + }, + timeout: Timeout(Duration(seconds: 40 + latency * 2)), + ); + } +} diff --git a/packages/river_hdl/test/core/rename_test.dart b/packages/river_hdl/test/core/rename_test.dart new file mode 100644 index 0000000..008c501 --- /dev/null +++ b/packages/river_hdl/test/core/rename_test.dart @@ -0,0 +1,189 @@ +import 'dart:async'; + +import 'package:rohd/rohd.dart'; +import 'package:river_hdl/src/core/rename.dart'; +import 'package:test/test.dart'; + +/// Drives a [RegisterRenameTable] for speculative free-list rollback testing. +class _Harness { + final Logic clk; + final Logic reset = Logic(name: 'reset'); + final Logic rs1_0 = Logic(name: 'rs1_0', width: 5); + final Logic rs2_0 = Logic(name: 'rs2_0', width: 5); + final Logic rd_0 = Logic(name: 'rd_0', width: 5); + final Logic valid0 = Logic(name: 'valid0'); + final Logic writesRd0 = Logic(name: 'writesRd0'); + final Logic rs1_1 = Logic(name: 'rs1_1', width: 5); + final Logic rs2_1 = Logic(name: 'rs2_1', width: 5); + final Logic rd_1 = Logic(name: 'rd_1', width: 5); + final Logic valid1 = Logic(name: 'valid1'); + final Logic writesRd1 = Logic(name: 'writesRd1'); + final Logic freeValid0 = Logic(name: 'freeValid0'); + final Logic freeReg0 = Logic(name: 'freeReg0', width: 7); + final Logic freeValid1 = Logic(name: 'freeValid1'); + final Logic freeReg1 = Logic(name: 'freeReg1', width: 7); + final Logic commitValid0 = Logic(name: 'commitValid0'); + final Logic commitRd0 = Logic(name: 'commitRd0', width: 5); + final Logic commitPdst0 = Logic(name: 'commitPdst0', width: 7); + final Logic commitValid1 = Logic(name: 'commitValid1'); + final Logic commitRd1 = Logic(name: 'commitRd1', width: 5); + final Logic commitPdst1 = Logic(name: 'commitPdst1', width: 7); + final Logic flush = Logic(name: 'flush'); + late final RegisterRenameTable rt; + + _Harness(this.clk) { + rt = RegisterRenameTable( + clk, + reset, + rs1Arch0: rs1_0, + rs2Arch0: rs2_0, + rdArch0: rd_0, + valid0: valid0, + writesRd0: writesRd0, + rs1Arch1: rs1_1, + rs2Arch1: rs2_1, + rdArch1: rd_1, + valid1: valid1, + writesRd1: writesRd1, + freeValid0: freeValid0, + freeReg0: freeReg0, + freeValid1: freeValid1, + freeReg1: freeReg1, + commitValid0: commitValid0, + commitRd0: commitRd0, + commitPdst0: commitPdst0, + commitValid1: commitValid1, + commitRd1: commitRd1, + commitPdst1: commitPdst1, + flush: flush, + numPhysRegs: 96, + ); + } + + void idle() { + valid0.inject(0); + writesRd0.inject(0); + valid1.inject(0); + writesRd1.inject(0); + freeValid0.inject(0); + freeValid1.inject(0); + commitValid0.inject(0); + commitValid1.inject(0); + flush.inject(0); + for (final l in [ + rs1_0, + rs2_0, + rd_0, + rs1_1, + rs2_1, + rd_1, + commitRd0, + commitRd1, + ]) { + l.inject(0); + } + freeReg0.inject(0); + freeReg1.inject(0); + commitPdst0.inject(0); + commitPdst1.inject(0); + } + + /// Rename a single reg-writing instruction with destination [rd]. + void renameRd(int rd) { + valid0.inject(1); + writesRd0.inject(1); + rd_0.inject(rd); + rs1_0.inject(1); + rs2_0.inject(2); + valid1.inject(0); + writesRd1.inject(0); + } + + /// Commit a single reg-writing instruction (frees [oldPdst], maps [rd]->[pdst]). + void commitRd(int rd, int pdst, int oldPdst) { + commitValid0.inject(1); + commitRd0.inject(rd); + commitPdst0.inject(pdst); + freeValid0.inject(1); + freeReg0.inject(oldPdst); + } +} + +void main() { + tearDown(() async { + await Simulator.endSimulation(); + Simulator.reset(); + }); + + Future<_Harness> setup() async { + final clk = SimpleClockGenerator(10).clk; + final h = _Harness(clk); + h.idle(); + h.reset.inject(1); + await h.rt.build(); + Simulator.setMaxSimTime(100000); + unawaited(Simulator.run()); + await clk.nextPosedge; + await clk.nextPosedge; + h.reset.inject(0); + await clk.nextPosedge; + return h; + } + + test('flush with no commits reclaims all speculative allocations', () async { + final h = await setup(); + final clk = h.clk; + // pdst0 is combinational from freeHead; first free phys reg is 32. + h.renameRd(5); + await clk.nextNegedge; + expect(h.rt.pdst0.value.toInt(), 32, reason: 'first alloc'); + await clk.nextPosedge; // consume 32 for x5 + h.renameRd(6); + await clk.nextNegedge; + expect(h.rt.pdst0.value.toInt(), 33, reason: 'second alloc'); + await clk.nextPosedge; // consume 33 for x6 + // Flush (no commits): both speculative allocations must be reclaimed. + h.idle(); + h.flush.inject(1); + await clk.nextPosedge; + h.idle(); + h.renameRd(7); + await clk.nextNegedge; + expect( + h.rt.pdst0.value.toInt(), + 32, + reason: 'flush reclaimed 32 and 33; next alloc reuses 32', + ); + }); + + test( + 'flush after a commit keeps committed alloc, reclaims younger', + () async { + final h = await setup(); + final clk = h.clk; + h.renameRd(5); // x5 -> 32 + await clk.nextNegedge; + expect(h.rt.pdst0.value.toInt(), 32); + await clk.nextPosedge; + // Commit x5 (its alloc 32 becomes permanent), while renaming x6 -> 33. + h.idle(); + h.commitRd(5, 32, 5); // old mapping of x5 was phys 5 + h.renameRd(6); + await clk.nextNegedge; + expect(h.rt.pdst0.value.toInt(), 33); + await clk.nextPosedge; + // Flush: x5's 32 stays committed; x6's 33 is reclaimed. + h.idle(); + h.flush.inject(1); + await clk.nextPosedge; + h.idle(); + h.renameRd(7); + await clk.nextNegedge; + expect( + h.rt.pdst0.value.toInt(), + 33, + reason: 'next alloc reuses reclaimed 33, not 34', + ); + }, + ); +} diff --git a/packages/river_hdl/test/core/rvc_decode_test.dart b/packages/river_hdl/test/core/rvc_decode_test.dart new file mode 100644 index 0000000..52eeec4 --- /dev/null +++ b/packages/river_hdl/test/core/rvc_decode_test.dart @@ -0,0 +1,45 @@ +import 'package:river_hdl/river_hdl.dart'; +import 'package:test/test.dart'; + +import '../constants.dart'; + +void main() { + group('HDL compressed decode (pattern match)', () { + final config = kCpuConfigs['RC1.n']!; + final rom = MicrocodeRom(config.isa, encodings: kMicroOpTable); + + test('identifies c.j (0xbfcd)', () { + expect(rom.lookup(0xbfcd)?.mnemonic, 'c.j'); + }); + test('identifies c.addi (0x0285)', () { + expect(rom.lookup(0x0285)?.mnemonic, 'c.addi'); + }); + test('identifies c.lw (0x4040)', () { + expect(rom.lookup(0x4040)?.mnemonic, 'c.lw'); + }); + test('distinguishes c.mv (0x852e) from c.add (0x952e)', () { + expect(rom.lookup(0x852e)?.mnemonic, 'c.mv'); + expect(rom.lookup(0x952e)?.mnemonic, 'c.add'); + }); + test('CA arithmetic c.sub (0x8c05) / c.and (0x8c65)', () { + expect(rom.lookup(0x8c05)?.mnemonic, 'c.sub'); + expect(rom.lookup(0x8c65)?.mnemonic, 'c.and'); + }); + test('CB-arith c.srli (0x8005) / c.andi (0x987d)', () { + expect(rom.lookup(0x8005)?.mnemonic, 'c.srli'); + expect(rom.lookup(0x987d)?.mnemonic, 'c.andi'); + }); + test('CR jumps: c.jr (0x8082) / c.jalr (0x9082) / c.ebreak (0x9002)', () { + expect(rom.lookup(0x8082)?.mnemonic, 'c.jr'); + expect(rom.lookup(0x9082)?.mnemonic, 'c.jalr'); + expect(rom.lookup(0x9002)?.mnemonic, 'c.ebreak'); + }); + test('c.addi16sp (0x7139, rd=x2) vs c.lui (0x6285, rd=x10)', () { + // 0x7139 = addi sp,sp,-64 (won't fit c.addi's 6-bit imm); c.addi sp,sp,-16 + // (0x1141) is a separate, valid encoding. + expect(rom.lookup(0x7139)?.mnemonic, 'c.addi16sp'); + expect(rom.lookup(0x6285)?.mnemonic, 'c.lui'); + expect(rom.lookup(0x1141)?.mnemonic, 'c.addi'); + }); + }); +} diff --git a/packages/river_hdl/test/core_harness.dart b/packages/river_hdl/test/core_harness.dart new file mode 100644 index 0000000..cfba10d --- /dev/null +++ b/packages/river_hdl/test/core_harness.dart @@ -0,0 +1,164 @@ +import 'dart:async'; + +import 'package:rohd/rohd.dart'; +import 'package:rohd_hcl/rohd_hcl.dart' hide DataPortInterface, DataPortGroup; +import 'package:river/river.dart'; +import 'package:river_hdl/river_hdl.dart'; +import 'package:test/test.dart'; + +Future coreTest( + String memString, + Map regStates, + RiverCoreConfig config, { + Map memStates = const {}, + Map initRegisters = const {}, + int nextPc = 4, + int latency = 0, + int memLatency = 0, +}) async { + final clk = SimpleClockGenerator(20).clk; + final reset = Logic(); + + final addrWidth = config.mxlen.size; + final wbConfig = WishboneConfig( + addressWidth: addrWidth, + dataWidth: config.mxlen.size, + selWidth: config.mxlen.size ~/ 8, + ); + + // Drives the OoO physical-regfile backdoor seed: while high, a regWritePort + // write also lands in the OoO prf so initRegisters reaches the OoO read path. + final prfSeedMode = Logic(name: 'prfSeedMode'); + + final core = RiverCore(config, busConfig: wbConfig, prfSeedMode: prfSeedMode); + + core.input('clk').srcConnection! <= clk; + core.input('reset').srcConnection! <= reset; + + await core.build(); + + final storage = SparseMemoryStorage( + addrWidth: addrWidth, + dataWidth: config.mxlen.size, + alignAddress: (addr) => addr, + onInvalidRead: (addr, dataWidth) => + LogicValue.filled(dataWidth, LogicValue.zero), + ); + + // Bridge Wishbone master to MemoryModel + final memRead = DataPortInterface(config.mxlen.size, addrWidth); + final memWrite = DataPortInterface(config.mxlen.size, addrWidth); + + // ignore: unused_local_variable + final mem = MemoryModel( + clk, + reset, + [wrapWriteForRegisterFile(memWrite)], + [wrapReadForRegisterFile(memRead, clk: clk, readLatency: memLatency)], + readLatency: memLatency, + storage: storage, + ); + + final wbCyc = core.output('dataBus_CYC'); + final wbStb = core.output('dataBus_STB'); + final wbWe = core.output('dataBus_WE'); + final wbAdr = core.output('dataBus_ADR'); + final wbDatMosi = core.output('dataBus_DAT_MOSI'); + + memRead.en <= wbCyc & wbStb & ~wbWe; + memRead.addr <= wbAdr; + memWrite.en <= wbCyc & wbStb & wbWe; + memWrite.addr <= wbAdr; + memWrite.data <= wbDatMosi; + + // wbAck honors the read port's latency: for reads, only acknowledge when the + // slave actually has data ready (memRead.valid, `done` asserts immediately on + // `en`, it only means the request was accepted). Writes are combinational, so + // a one-cycle ack is correct. + final wbAckReg = Logic(name: 'wbAck'); + final readyForAck = wbWe | memRead.valid; + Sequential(clk, [ + If( + reset, + then: [wbAckReg < 0], + orElse: [ + If( + wbCyc & wbStb & ~wbAckReg & readyForAck, + then: [wbAckReg < 1], + orElse: [wbAckReg < 0], + ), + ], + ), + ]); + // While `seedGate` is high we starve the data-bus acknowledge so the fetcher + // stalls on its first read and the pipeline cannot retire anything. This lets + // us backdoor-seed the register file one entry per clock edge (the regfile has + // a single write port and clears all entries while `reset` is asserted, so the + // seed must happen post-reset, with the core held) before instructions run. + final seedGate = Logic(name: 'seedGate'); + core.input('dataBus_ACK').srcConnection! <= wbAckReg & ~seedGate; + core.input('dataBus_DAT_MISO').srcConnection! <= memRead.data; + + reset.inject(1); + seedGate.inject(initRegisters.isNotEmpty ? 1 : 0); + // High through the seed window; the prf write is additionally gated by + // regWritePort.en (in core.dart) so it only lands on an actual seed write. + prfSeedMode.inject(initRegisters.isNotEmpty ? 1 : 0); + + Simulator.registerAction(20, () { + reset.put(0); + storage.loadMemString(memString); + }); + + Simulator.setMaxSimTime(100000); + unawaited(Simulator.run()); + + await clk.nextPosedge; + + // Seed the register file one entry per clock edge (single write port). The + // core is held by `seedGate` (no bus acks), so none of these writes races a + // pipeline read-back. + for (final regState in initRegisters.entries) { + core.regWritePort.en.inject(1); + core.regWritePort.addr.inject(LogicValue.ofInt(regState.key.value, 5)); + core.regWritePort.data.inject( + LogicValue.ofInt(regState.value, config.mxlen.size), + ); + await clk.nextPosedge; + } + + // Disable register write port and release the core to run. + core.regWritePort.en.inject(0); + seedGate.inject(0); + prfSeedMode.inject(0); + + while (reset.value.toBool()) { + await clk.nextPosedge; + } + + for (var i = 0; i < 5000; i++) { + await clk.nextPosedge; + final pc = core.pipeline.nextPc.value; + if (pc.isValid && pc.toInt() == nextPc) break; + } + + await Simulator.endSimulation(); + await Simulator.simulationEnded; + + expect(core.pipeline.done.value.toBool(), isTrue); + expect(core.pipeline.nextPc.value.toInt(), nextPc); + + for (final regState in regStates.entries) { + final value = core.regs.getData(LogicValue.ofInt(regState.key.value, 5))!; + expect(value.toInt(), regState.value, reason: '${regState.key}=$value'); + } + + for (final memState in memStates.entries) { + expect( + storage + .getData(LogicValue.ofInt(memState.key, config.mxlen.size))! + .toInt(), + memState.value, + ); + } +} diff --git a/packages/river_hdl/test/core_test.dart b/packages/river_hdl/test/core_test.dart deleted file mode 100644 index c35ccc6..0000000 --- a/packages/river_hdl/test/core_test.dart +++ /dev/null @@ -1,165 +0,0 @@ -import 'dart:async'; - -import 'package:rohd/rohd.dart'; -import 'package:rohd_bridge/rohd_bridge.dart'; -import 'package:rohd_hcl/rohd_hcl.dart'; -import 'package:riscv/riscv.dart'; -import 'package:river/river.dart'; -import 'package:river_hdl/river_hdl.dart'; -import 'package:test/test.dart'; -import 'constants.dart'; - -void coreTest( - String memString, - Map regStates, - RiverCore config, { - Map memStates = const {}, - Map initRegisters = const {}, - int nextPc = 4, - int latency = 0, - int memLatency = 0, -}) async { - final clk = SimpleClockGenerator(20).clk; - final reset = Logic(); - - final addrWidth = config.mmu.blocks[0].size.bitLength; - - final memRead = DataPortInterface(config.mxlen.size, addrWidth); - final memWrite = DataPortInterface(config.mxlen.size, addrWidth); - - final mmioRead = MmioReadInterface(config.mxlen.size, addrWidth); - final mmioWrite = MmioWriteInterface(config.mxlen.size, addrWidth); - - memRead.en <= mmioRead.en; - memRead.addr <= mmioRead.addr; - mmioRead.data <= memRead.data; - mmioRead.done <= memRead.done; - mmioRead.valid <= memRead.valid; - - memWrite.en <= mmioWrite.en; - memWrite.addr <= mmioWrite.addr; - memWrite.data <= mmioWrite.data; - mmioWrite.done <= memWrite.done; - mmioWrite.valid <= memWrite.valid; - - final storage = SparseMemoryStorage( - addrWidth: addrWidth, - dataWidth: config.mxlen.size, - alignAddress: (addr) => addr, - onInvalidRead: (addr, dataWidth) => - LogicValue.filled(dataWidth, LogicValue.zero), - ); - - final mem = MemoryModel( - clk, - reset, - [memWrite], - [memRead], - readLatency: latency, - storage: storage, - ); - - final core = RiverCoreIP(config); - - mmioRead.en <= - (core.interface('mmioRead0').interface as MmioReadInterface).en; - mmioRead.addr <= - (core.interface('mmioRead0').interface as MmioReadInterface).addr; - (core.interface('mmioRead0').interface as MmioReadInterface).data <= - mmioRead.data; - (core.interface('mmioRead0').interface as MmioReadInterface).done <= - mmioRead.done; - (core.interface('mmioRead0').interface as MmioReadInterface).valid <= - mmioRead.valid; - - mmioWrite.en <= - (core.interface('mmioWrite0').interface as MmioWriteInterface).en; - mmioWrite.addr <= - (core.interface('mmioWrite0').interface as MmioWriteInterface).addr; - mmioWrite.data <= - (core.interface('mmioWrite0').interface as MmioWriteInterface).data; - (core.interface('mmioWrite0').interface as MmioWriteInterface).done <= - mmioWrite.done; - (core.interface('mmioWrite0').interface as MmioWriteInterface).valid <= - mmioWrite.valid; - - core.input('clk').srcConnection! <= clk; - core.input('reset').srcConnection! <= reset; - - await core.build(); - - reset.inject(1); - - Simulator.registerAction(20, () { - reset.put(0); - - for (final regState in initRegisters.entries) { - core.regs.setData( - LogicValue.ofInt(regState.key.value, 5), - LogicValue.ofInt(regState.value, config.mxlen.size), - ); - } - - storage.loadMemString(memString); - }); - - //Simulator.setMaxSimTime(1200000); - unawaited(Simulator.run()); - - await clk.nextPosedge; - - while (reset.value.toBool()) { - await clk.nextPosedge; - } - - while (core.pipeline.nextPc.value.toInt() != nextPc) { - await clk.nextPosedge; - } - - await Simulator.endSimulation(); - await Simulator.simulationEnded; - - expect(core.pipeline.done.value.toBool(), isTrue); - expect(core.pipeline.nextPc.value.toInt(), nextPc); - - for (final regState in regStates.entries) { - final value = core.regs.getData(LogicValue.ofInt(regState.key.value, 5))!; - expect(value.toInt(), regState.value, reason: '${regState.key}=$value'); - } - - for (final memState in memStates.entries) { - expect( - storage - .getData(LogicValue.ofInt(memState.key, config.mxlen.size))! - .toInt(), - memState.value, - ); - } -} - -void main() { - tearDown(() async { - await Simulator.reset(); - }); - - cpuTests('RV32I', (config) { - test( - 'Small program', - () => coreTest( - '''@${config.resetVector.toRadixString(16)} -93 00 80 3E 13 81 00 7D 93 01 81 C1 13 82 01 83 -93 02 82 3E 13 00 00 00 -''', - { - Register.x1: 0x3E8, - Register.x2: 0xBB8, - Register.x3: 0x7D0, - Register.x4: 0, - Register.x5: 0x3E8, - }, - config, - nextPc: 0x18, - ), - ); - }); -} diff --git a/packages/river_hdl/test/csr/rv32_inorder_test.dart b/packages/river_hdl/test/csr/rv32_inorder_test.dart new file mode 100644 index 0000000..03844bb --- /dev/null +++ b/packages/river_hdl/test/csr/rv32_inorder_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'csr'; + const mxlen = RiscVMxlen.rv32; + const uarch = Uarch.inOrder; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/csr/rv32_ooo_dual_test.dart b/packages/river_hdl/test/csr/rv32_ooo_dual_test.dart new file mode 100644 index 0000000..9a68c8a --- /dev/null +++ b/packages/river_hdl/test/csr/rv32_ooo_dual_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'csr'; + const mxlen = RiscVMxlen.rv32; + const uarch = Uarch.oooDual; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/csr/rv32_ooo_test.dart b/packages/river_hdl/test/csr/rv32_ooo_test.dart new file mode 100644 index 0000000..8b10bfb --- /dev/null +++ b/packages/river_hdl/test/csr/rv32_ooo_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'csr'; + const mxlen = RiscVMxlen.rv32; + const uarch = Uarch.ooo; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/csr/rv64_inorder_microcode_test.dart b/packages/river_hdl/test/csr/rv64_inorder_microcode_test.dart new file mode 100644 index 0000000..61c863d --- /dev/null +++ b/packages/river_hdl/test/csr/rv64_inorder_microcode_test.dart @@ -0,0 +1,22 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +/// In-order MICROCODE path (DynamicExecutionUnit + microcode ROM, +/// MicrocodeMode.full) for the 'csr' category, validated against the emulator +/// golden. This is the area-first path rc1-s (creek) uses on small FPGAs. Split +/// per-category so dart test parallelizes across isolates (one big file +/// accumulates heap across builds and times out - see project_parity / +/// feedback_test_parallelism). +void main() { + const category = 'csr'; + const mxlen = RiscVMxlen.rv64; + const uarch = Uarch.inOrder; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)} (microcode)', + matrixConfig(mxlen, uarch, category, microcodeMode: MicrocodeMode.full), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/csr/rv64_inorder_test.dart b/packages/river_hdl/test/csr/rv64_inorder_test.dart new file mode 100644 index 0000000..848c599 --- /dev/null +++ b/packages/river_hdl/test/csr/rv64_inorder_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'csr'; + const mxlen = RiscVMxlen.rv64; + const uarch = Uarch.inOrder; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/csr/rv64_ooo_dual_test.dart b/packages/river_hdl/test/csr/rv64_ooo_dual_test.dart new file mode 100644 index 0000000..b5d6cba --- /dev/null +++ b/packages/river_hdl/test/csr/rv64_ooo_dual_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'csr'; + const mxlen = RiscVMxlen.rv64; + const uarch = Uarch.oooDual; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/csr/rv64_ooo_test.dart b/packages/river_hdl/test/csr/rv64_ooo_test.dart new file mode 100644 index 0000000..f9bacd8 --- /dev/null +++ b/packages/river_hdl/test/csr/rv64_ooo_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'csr'; + const mxlen = RiscVMxlen.rv64; + const uarch = Uarch.ooo; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/d/rv64_inorder_test.dart b/packages/river_hdl/test/d/rv64_inorder_test.dart new file mode 100644 index 0000000..4d707f7 --- /dev/null +++ b/packages/river_hdl/test/d/rv64_inorder_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'd'; + const mxlen = RiscVMxlen.rv64; + const uarch = Uarch.inOrder; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/dbg_elab_test.dart b/packages/river_hdl/test/dbg_elab_test.dart new file mode 100644 index 0000000..7a894a7 --- /dev/null +++ b/packages/river_hdl/test/dbg_elab_test.dart @@ -0,0 +1,14 @@ +import 'package:river/river.dart'; +import 'package:river_hdl/river_hdl.dart'; +import 'package:test/test.dart'; + +void main() { + test('RiverDebugSubsystem elaborates', () async { + final cfg = WishboneConfig(addressWidth: 64, dataWidth: 64, selWidth: 8); + final sub = RiverDebugSubsystem(cfg, xlen: 64); + await sub.build(); + final sv = sub.generateSynth(); + expect(sv.contains('RiverDebugModule'), isTrue); + expect(sv.contains('SbaWishboneAdapter'), isTrue); + }); +} diff --git a/packages/river_hdl/test/debug/debug_core_test.dart b/packages/river_hdl/test/debug/debug_core_test.dart new file mode 100644 index 0000000..bd2059f --- /dev/null +++ b/packages/river_hdl/test/debug/debug_core_test.dart @@ -0,0 +1,379 @@ +import 'dart:async'; + +import 'package:rohd/rohd.dart'; +import 'package:rohd_hcl/rohd_hcl.dart' hide DataPortInterface, DataPortGroup; +import 'package:river/river.dart'; +import 'package:river_hdl/river_hdl.dart'; +import 'package:test/test.dart'; + +/// Wires a real [RiverCore] (with debug enabled) to a [RiverDebugModule] and a +/// memory model, then drives the chain over JTAG the way OpenOCD would. This is +/// the integration counterpart to the isolated debug_module_test: it proves the +/// Debug Module actually halts and resumes the live core. +class DebugRig { + final RiverCore core; + final RiverDebugModule dbg; + final Logic clk; + final Logic tck, tms, tdi; + final Logic sbaRdata, sbaAck; + final MemoryStorage storage; + final int xlen; + bool _acked = false; + + DebugRig( + this.core, + this.dbg, + this.clk, + this.tck, + this.tms, + this.tdi, + this.sbaRdata, + this.sbaAck, + this.storage, + this.xlen, + ); + + Future _tick() async { + await clk.nextPosedge; + final req = dbg.sbaReq.value.isValid ? dbg.sbaReq.value.toInt() : 0; + if (req == 1 && !_acked) { + final bytes = xlen ~/ 8; + final addr = dbg.sbaAddr.value.toInt(); + final off = addr % bytes; + final aligned = LogicValue.ofInt(addr - off, xlen); + final zero = LogicValue.filled(xlen, LogicValue.zero); + if (dbg.sbaWe.value.toInt() == 1) { + storage.setData(aligned, dbg.sbaWdata.value); + } + final rd = (storage.getData(aligned) ?? zero).toBigInt() >> (off * 8); + sbaRdata.inject(LogicValue.ofBigInt(rd, xlen)); + sbaAck.inject(1); + _acked = true; + } else { + sbaAck.inject(0); + _acked = false; + } + } + + Future _clk(int tmsv, [int tdiv = 0]) async { + tms.inject(tmsv); + tdi.inject(tdiv); + tck.inject(1); + await _tick(); + tck.inject(0); + await _tick(); + } + + Future idle(int n) async { + for (var i = 0; i < n; i++) { + await _clk(0); + } + } + + Future resetTap() async { + for (var i = 0; i < 5; i++) { + await _clk(1); + } + await _clk(0); + } + + Future scanDr(int bits, int value) async { + await _clk(1); + await _clk(0); + await _clk(0); + var captured = 0; + for (var i = 0; i < bits; i++) { + // Sample combinational TDO before the clock that shifts it. + if (dbg.tdo.value.toInt() == 1) captured |= 1 << i; + await _clk(i == bits - 1 ? 1 : 0, (value >> i) & 1); + } + await _clk(1); + await _clk(0); + return captured; + } + + Future scanIr(int bits, int value) async { + await _clk(1); + await _clk(1); + await _clk(0); + await _clk(0); + var captured = 0; + for (var i = 0; i < bits; i++) { + // Sample combinational TDO before the clock that shifts it. + if (dbg.tdo.value.toInt() == 1) captured |= 1 << i; + await _clk(i == bits - 1 ? 1 : 0, (value >> i) & 1); + } + await _clk(1); + await _clk(0); + return captured; + } + + Future dmWrite(int addr, int data) => + scanDr(41, (addr << 34) | ((data & 0xFFFFFFFF) << 2) | 2); + + Future dmRead(int addr) async { + await scanDr(41, (addr << 34) | 1); + final captured = await scanDr(41, 0); + return (captured >> 2) & 0xFFFFFFFF; + } +} + +void main() { + test('Debug Module halts and resumes the live core', () async { + await Simulator.reset(); + const xlen = 64; + final clk = SimpleClockGenerator(10).clk; + final reset = Logic(name: 'reset'); + + final coreConfig = RiverCoreConfigV1.small( + interrupts: [], + // Distinctive mhartid so the abstract CSR read below is decisive: the old + // fall-through read 0 for any CSR; the borrowed-port read returns 0x42. + hartId: 0x42, + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + clock: const HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ), + resetVector: 0, + ); + final wbConfig = WishboneConfig( + addressWidth: xlen, + dataWidth: xlen, + selWidth: xlen ~/ 8, + ); + + final storage = SparseMemoryStorage( + addrWidth: xlen, + dataWidth: xlen, + alignAddress: (addr) => addr, + onInvalidRead: (addr, dataWidth) => + LogicValue.filled(dataWidth, LogicValue.zero), + ); + // Fill low memory with pairs of NOPs (addi x0,x0,0 == 0x13) so a running + // core marches its PC forward word by word. + for (var a = 0; a < 0x400; a += 8) { + storage.setData( + LogicValue.ofInt(a, xlen), + LogicValue.ofInt(0x0000001300000013, xlen), + ); + } + + final core = RiverCore(coreConfig, busConfig: wbConfig, withDebug: true); + core.input('clk').srcConnection! <= clk; + // Hart reset = external reset OR the DM's ndmreset (driven after the DM). + final coreReset = Logic(name: 'coreReset'); + core.input('reset').srcConnection! <= coreReset; + await core.build(); + + final wb = core.interface('dataBus').interface as WishboneInterface; + final memRead = DataPortInterface(xlen, xlen); + final memWrite = DataPortInterface(xlen, xlen); + // ignore: unused_local_variable + final mem = MemoryModel( + clk, + reset, + [wrapWriteForRegisterFile(memWrite)], + [wrapReadForRegisterFile(memRead)], + storage: storage, + ); + memRead.en <= wb.cyc & wb.stb & ~wb.we; + memRead.addr <= wb.adr; + memWrite.en <= wb.cyc & wb.stb & wb.we; + memWrite.addr <= wb.adr; + memWrite.data <= wb.datMosi; + final wbAck = Logic(name: 'wbAck'); + Sequential(clk, [ + If( + reset, + then: [wbAck < 0], + orElse: [ + If(wb.cyc & wb.stb & ~wbAck, then: [wbAck < 1], orElse: [wbAck < 0]), + ], + ), + ]); + wb.ack <= wbAck; + wb.datMiso <= memRead.data; + + final tck = Logic(name: 'tck'); + final tms = Logic(name: 'tms'); + final tdi = Logic(name: 'tdi'); + final trstN = Logic(name: 'trst_n'); + final sbaRdata = Logic(name: 'sba_rdata', width: xlen); + final sbaAck = Logic(name: 'sba_ack'); + final dbg = RiverDebugModule( + clk, + reset, + tck, + tms, + tdi, + trstN, + hartHalted: core.output('debug_halted'), + regRdata: core.output('debug_reg_rdata'), + regReady: core.output('debug_reg_ready'), + sbaRdata: sbaRdata, + sbaAck: sbaAck, + xlen: xlen, + idcode: 0x10000001, + ); + await dbg.build(); + core.input('debug_halt_req').srcConnection! <= dbg.haltReq; + core.input('debug_resume_req').srcConnection! <= dbg.resumeReq; + core.input('debug_reg_read').srcConnection! <= dbg.regRead; + core.input('debug_reg_write').srcConnection! <= dbg.regWrite; + core.input('debug_reg_addr').srcConnection! <= dbg.regAddr; + core.input('debug_reg_wdata').srcConnection! <= dbg.regWdata; + coreReset <= reset | dbg.ndmreset; + + reset.inject(1); + tck.inject(0); + tms.inject(0); + tdi.inject(0); + trstN.inject(1); + sbaRdata.inject(0); + sbaAck.inject(0); + Simulator.setMaxSimTime(500000000); + unawaited(Simulator.run()); + await clk.nextPosedge; + reset.inject(0); + // Let the core run a while so its PC is marching forward. + for (var i = 0; i < 40; i++) { + await clk.nextPosedge; + } + + final rig = DebugRig( + core, + dbg, + clk, + tck, + tms, + tdi, + sbaRdata, + sbaAck, + storage, + xlen, + ); + await rig.resetTap(); + await rig.scanIr(5, 0x11); + + // Halt the hart. + await rig.dmWrite(0x10, (1 << 31) | 1); // dmcontrol: haltreq | dmactive + await rig.idle(8); + final dmHalted = await rig.dmRead(0x11); + expect((dmHalted >> 9) & 1, 1, reason: 'allhalted set after haltreq'); + expect(core.output('debug_halted').value.toInt(), 1); + + // PC must be frozen while halted. + final pcAtHalt = core.pipeline.nextPc.value.toInt(); + for (var i = 0; i < 30; i++) { + await clk.nextPosedge; + } + expect( + core.pipeline.nextPc.value.toInt(), + pcAtHalt, + reason: 'PC must not advance while halted', + ); + + // Resume and confirm the core runs again. + await rig.dmWrite(0x10, (1 << 30) | 1); // resumereq | dmactive + await rig.idle(8); + expect( + core.output('debug_halted').value.toInt(), + 0, + reason: 'halt clears on resume', + ); + final dmRun = await rig.dmRead(0x11); + expect((dmRun >> 9) & 1, 0, reason: 'allhalted clears after resume'); + + // ---- Abstract command: write a GPR, read it back, read dpc ---- + await rig.dmWrite(0x10, (1 << 31) | 1); // halt again + await rig.idle(8); + + // command = access-register, aarsize=3 (64-bit), transfer, write, x6. + const writeX6 = (3 << 20) | (1 << 17) | (1 << 16) | 0x1006; + const readX6 = (3 << 20) | (1 << 17) | 0x1006; + await rig.dmWrite(0x04, 0x12345678); // data0 (low 32) + await rig.dmWrite(0x05, 0xDEADBEEF); // data1 (high 32) + await rig.dmWrite(0x17, writeX6); + await rig.idle(6); + expect( + core.regs.getData(LogicValue.ofInt(6, 5))!.toBigInt(), + BigInt.parse('DEADBEEF12345678', radix: 16), + reason: 'abstract command wrote x6', + ); + + // Read it back into data0/data1. + await rig.dmWrite(0x17, readX6); + await rig.idle(6); + expect(await rig.dmRead(0x04), 0x12345678, reason: 'x6 low readback'); + expect(await rig.dmRead(0x05), 0xDEADBEEF, reason: 'x6 high readback'); + + // dpc (CSR 0x7b1) reads the PC captured at halt. + final dpc = core.output('debug_dpc').value.toBigInt(); + const readDpc = (3 << 20) | (1 << 17) | 0x7b1; + await rig.dmWrite(0x17, readDpc); + await rig.idle(6); + expect( + await rig.dmRead(0x04), + (dpc & BigInt.from(0xFFFFFFFF)).toInt(), + reason: 'dpc low matches the latched halt PC', + ); + + // A general CSR (mhartid, 0xF14) read over the abstract command: the Debug + // Module borrows the frozen CSR read port. Before this path existed any + // non-dpc/dcsr/misa CSR fell through to the GPR port and read 0; now it + // returns the real value (config hartId = 0x42). + const readMhartid = (3 << 20) | (1 << 17) | 0xF14; + await rig.dmWrite(0x17, readMhartid); + await rig.idle(6); + expect( + await rig.dmRead(0x04), + 0x42, + reason: 'mhartid read over JTAG returns the real CSR value, not 0', + ); + + // misa (0x301) still served by its dedicated constant path. + const readMisa = (3 << 20) | (1 << 17) | 0x301; + await rig.dmWrite(0x17, readMisa); + await rig.idle(6); + expect( + await rig.dmRead(0x04), + coreConfig.isa.misaValue & 0xFFFFFFFF, + reason: 'misa low word still served over JTAG', + ); + + // ---- ndmreset: reset the hart over JTAG ---- + // x6 currently holds 0xDEADBEEF12345678 (written above). Setting + // dmcontrol.ndmreset (bit 1) drives the hart into reset, clearing its + // register file, while leaving the Debug Module alive. + await rig.dmWrite(0x10, (1 << 1) | 1); // ndmreset | dmactive + await rig.idle(6); + expect( + (await rig.dmRead(0x10) >> 1) & 1, + 1, + reason: 'dmcontrol reads back ndmreset asserted', + ); + expect( + core.regs.getData(LogicValue.ofInt(6, 5))!.toBigInt(), + BigInt.zero, + reason: 'ndmreset reset the hart, clearing x6', + ); + + // Release ndmreset; the DM stayed alive throughout (still reads dmactive). + await rig.dmWrite(0x10, 1); // dmactive only + await rig.idle(4); + expect( + (await rig.dmRead(0x10) >> 1) & 1, + 0, + reason: 'dmcontrol reads back ndmreset released', + ); + + await Simulator.endSimulation(); + await Simulator.simulationEnded; + }); +} diff --git a/packages/river_hdl/test/debug/debug_full_config_test.dart b/packages/river_hdl/test/debug/debug_full_config_test.dart new file mode 100644 index 0000000..e8060cf --- /dev/null +++ b/packages/river_hdl/test/debug/debug_full_config_test.dart @@ -0,0 +1,327 @@ +import 'dart:async'; + +import 'package:rohd/rohd.dart'; +import 'package:rohd_hcl/rohd_hcl.dart' hide DataPortInterface, DataPortGroup; +import 'package:river/river.dart'; +import 'package:river_hdl/river_hdl.dart'; +import 'package:test/test.dart'; + +/// Reproduces river_sim's remote_bitbang setup IN-PROCESS (no socket): the full +/// `rc1-s` core config (small + Sv39 paging) with `withDebug`, the debug module +/// wired both ways, and a free-running simulator. If the bidirectional debug +/// feedback plus this config makes the simulator hang, this test times out and +/// pins the bug deterministically (the live socket path is hard to observe). +/// Builds the full rc1-s system (core + memory + debug module, wired both ways) +/// exactly like river_sim's remote_bitbang path, and returns the core. +Future _buildFull(Logic clk, Logic reset) async { + const xlen = 64; + final coreConfig = RiverCoreConfigV1.small( + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + clock: const HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ), + resetVector: 0, + ); + final wbConfig = WishboneConfig( + addressWidth: xlen, + dataWidth: xlen, + selWidth: xlen ~/ 8, + ); + final storage = SparseMemoryStorage( + addrWidth: xlen, + dataWidth: xlen, + alignAddress: (addr) => addr, + onInvalidRead: (addr, dataWidth) => + LogicValue.filled(dataWidth, LogicValue.zero), + ); + for (var a = 0; a < 0x400; a += 8) { + storage.setData( + LogicValue.ofInt(a, xlen), + LogicValue.ofInt(0x0000001300000013, xlen), + ); + } + final core = RiverCore(coreConfig, busConfig: wbConfig, withDebug: true); + core.input('clk').srcConnection! <= clk; + core.input('reset').srcConnection! <= reset; + await core.build(); + final wb = core.interface('dataBus').interface as WishboneInterface; + final memRead = DataPortInterface(xlen, xlen); + final memWrite = DataPortInterface(xlen, xlen); + // ignore: unused_local_variable + final mem = MemoryModel( + clk, + reset, + [wrapWriteForRegisterFile(memWrite)], + [wrapReadForRegisterFile(memRead)], + storage: storage, + ); + memRead.en <= wb.cyc & wb.stb & ~wb.we; + memRead.addr <= wb.adr; + memWrite.en <= wb.cyc & wb.stb & wb.we; + memWrite.addr <= wb.adr; + memWrite.data <= wb.datMosi; + final wbAck = Logic(name: 'wbAck'); + Sequential(clk, [ + If( + reset, + then: [wbAck < 0], + orElse: [ + If(wb.cyc & wb.stb & ~wbAck, then: [wbAck < 1], orElse: [wbAck < 0]), + ], + ), + ]); + wb.ack <= wbAck; + wb.datMiso <= memRead.data; + final tck = Logic(name: 'tck'); + final tms = Logic(name: 'tms'); + final tdi = Logic(name: 'tdi'); + final trstN = Logic(name: 'trst_n'); + final sbaRdata = Logic(name: 'sba_rdata', width: xlen); + final sbaAck = Logic(name: 'sba_ack'); + final dbg = RiverDebugModule( + clk, + reset, + tck, + tms, + tdi, + trstN, + hartHalted: core.output('debug_halted'), + regRdata: core.output('debug_reg_rdata'), + regReady: core.output('debug_reg_ready'), + sbaRdata: sbaRdata, + sbaAck: sbaAck, + xlen: xlen, + idcode: 0x10000001, + ); + await dbg.build(); + core.input('debug_halt_req').srcConnection! <= dbg.haltReq; + core.input('debug_resume_req').srcConnection! <= dbg.resumeReq; + core.input('debug_reg_read').srcConnection! <= dbg.regRead; + core.input('debug_reg_write').srcConnection! <= dbg.regWrite; + core.input('debug_reg_addr').srcConnection! <= dbg.regAddr; + core.input('debug_reg_wdata').srcConnection! <= dbg.regWdata; + tck.inject(0); + tms.inject(0); + tdi.inject(0); + trstN.inject(1); + sbaRdata.inject(0); + sbaAck.inject(0); + return core; +} + +void main() { + test( + 'full rc1-s config + debug wiring advances the clock (no settle hang)', + () async { + await Simulator.reset(); + const xlen = 64; + final clk = SimpleClockGenerator(20).clk; + final reset = Logic(name: 'reset'); + + // Mirror river_sim's rc1-s: small core WITH Sv39 in the paging modes. + final coreConfig = RiverCoreConfigV1.small( + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + clock: const HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ), + resetVector: 0, + ); + final wbConfig = WishboneConfig( + addressWidth: xlen, + dataWidth: xlen, + selWidth: xlen ~/ 8, + ); + + final storage = SparseMemoryStorage( + addrWidth: xlen, + dataWidth: xlen, + alignAddress: (addr) => addr, + onInvalidRead: (addr, dataWidth) => + LogicValue.filled(dataWidth, LogicValue.zero), + ); + for (var a = 0; a < 0x400; a += 8) { + storage.setData( + LogicValue.ofInt(a, xlen), + LogicValue.ofInt(0x0000001300000013, xlen), + ); + } + + final core = RiverCore(coreConfig, busConfig: wbConfig, withDebug: true); + core.input('clk').srcConnection! <= clk; + core.input('reset').srcConnection! <= reset; + await core.build(); + + final wb = core.interface('dataBus').interface as WishboneInterface; + final memRead = DataPortInterface(xlen, xlen); + final memWrite = DataPortInterface(xlen, xlen); + // ignore: unused_local_variable + final mem = MemoryModel( + clk, + reset, + [wrapWriteForRegisterFile(memWrite)], + [wrapReadForRegisterFile(memRead)], + storage: storage, + ); + memRead.en <= wb.cyc & wb.stb & ~wb.we; + memRead.addr <= wb.adr; + memWrite.en <= wb.cyc & wb.stb & wb.we; + memWrite.addr <= wb.adr; + memWrite.data <= wb.datMosi; + final wbAck = Logic(name: 'wbAck'); + Sequential(clk, [ + If( + reset, + then: [wbAck < 0], + orElse: [ + If( + wb.cyc & wb.stb & ~wbAck, + then: [wbAck < 1], + orElse: [wbAck < 0], + ), + ], + ), + ]); + wb.ack <= wbAck; + wb.datMiso <= memRead.data; + + final tck = Logic(name: 'tck'); + final tms = Logic(name: 'tms'); + final tdi = Logic(name: 'tdi'); + final trstN = Logic(name: 'trst_n'); + final sbaRdata = Logic(name: 'sba_rdata', width: xlen); + final sbaAck = Logic(name: 'sba_ack'); + final dbg = RiverDebugModule( + clk, + reset, + tck, + tms, + tdi, + trstN, + hartHalted: core.output('debug_halted'), + regRdata: core.output('debug_reg_rdata'), + regReady: core.output('debug_reg_ready'), + sbaRdata: sbaRdata, + sbaAck: sbaAck, + xlen: xlen, + idcode: 0x10000001, + ); + await dbg.build(); + core.input('debug_halt_req').srcConnection! <= dbg.haltReq; + core.input('debug_resume_req').srcConnection! <= dbg.resumeReq; + core.input('debug_reg_read').srcConnection! <= dbg.regRead; + core.input('debug_reg_write').srcConnection! <= dbg.regWrite; + core.input('debug_reg_addr').srcConnection! <= dbg.regAddr; + core.input('debug_reg_wdata').srcConnection! <= dbg.regWdata; + + reset.inject(1); + tck.inject(0); + tms.inject(0); + tdi.inject(0); + trstN.inject(1); + sbaRdata.inject(0); + sbaAck.inject(0); + + Simulator.setMaxSimTime(200000); + unawaited(Simulator.run()); + await clk.nextPosedge; + reset.inject(0); + + // Free-run the clock like river_sim's loop. This proves the full rc1-s + // config plus the bidirectional debug wiring settles and advances (it does). + // NOTE: the live remote_bitbang socket can NOT be driven from this same + // isolate: `Simulator.run()` starves socket/timer awaits, and a hand-pumped + // `Simulator.tick()` loop deadlocks with the full core. The socket bridge + // needs the simulation in a separate isolate (see project_debug_jtag). + for (var i = 0; i < 100; i++) { + await clk.nextPosedge; + } + + expect( + core.pipeline.nextPc.value.isValid, + isTrue, + reason: 'full config + debug wiring advanced 100 cycles', + ); + + await Simulator.endSimulation(); + await Simulator.simulationEnded; + }, + timeout: const Timeout(Duration(seconds: 60)), + ); + + test( + 'rbb run loop (tick + periodic yield) advances core AND services I/O', + () async { + // This is exactly river_sim's remote_bitbang loop: hand-step the simulator + // with `Simulator.tick()` and yield to the event loop every `yieldEvery` + // ticks. It must (a) advance the full core and (b) let a concurrent async + // task (the JTAG socket) make progress. `Simulator.run()` fails (b); a + // per-tick yield is far too slow on the full core; per-N is the sweet spot. + await Simulator.reset(); + final clk = SimpleClockGenerator(20).clk; + final reset = Logic(name: 'reset'); + final core = await _buildFull(clk, reset); + reset.inject(1); + Simulator.setMaxSimTime(2000000); + + // A gentle background task (like a socket server waiting for data), NOT a + // tight timer loop. It must get serviced while the sim advances. + var ioTurns = 0; + var running = true; + unawaited(() async { + while (running) { + await Future.delayed(const Duration(milliseconds: 5)); + ioTurns++; + } + }()); + + const yieldEvery = 64; + var cycles = 0; + var prevClk = 0; + var tickCount = 0; + await Future(() {}); + while (cycles < 100 && Simulator.hasStepsRemaining()) { + await Simulator.tick(); + // Deassert reset exactly once (river_sim does this via a t=20 registered + // action; injecting every tick re-propagates reset and is pathologically + // slow). + if (Simulator.time >= 20 && + reset.value.isValid && + reset.value.toBool()) { + reset.inject(0); + } + final c = (clk.value.isValid && clk.value.toBool()) ? 1 : 0; + if (c == 1 && prevClk == 0 && !reset.value.toBool()) cycles++; + prevClk = c; + if (++tickCount % yieldEvery == 0) { + await Future.delayed(Duration.zero); + } + } + running = false; + + expect(cycles, 100, reason: 'rbb loop advanced the full core'); + expect( + ioTurns, + greaterThan(0), + reason: 'concurrent async (the JTAG socket) was serviced, not starved', + ); + expect(core.pipeline.nextPc.value.isValid, isTrue); + + Simulator.endSimulation(); + }, + timeout: const Timeout(Duration(seconds: 60)), + ); +} diff --git a/packages/river_hdl/test/debug/debug_module_test.dart b/packages/river_hdl/test/debug/debug_module_test.dart new file mode 100644 index 0000000..4080780 --- /dev/null +++ b/packages/river_hdl/test/debug/debug_module_test.dart @@ -0,0 +1,219 @@ +import 'dart:async'; + +import 'package:rohd/rohd.dart'; +import 'package:river_hdl/src/core/debug.dart'; +import 'package:test/test.dart'; + +/// Drives the RTL debug module exactly as a JTAG adapter (OpenOCD bitbang) +/// would: it injects TCK/TMS/TDI pins, steps the system clock so the module's +/// edge-detected TAP advances, and services the System Bus Access port against +/// a plain memory map (standing in for the sim's storage). +class JtagHost { + final RiverDebugModule dut; + final Logic clk; + final Logic tck; + final Logic tms; + final Logic tdi; + final Logic sbaRdata; + final Logic sbaAck; + final Map mem; + bool _acked = false; + + JtagHost( + this.dut, + this.clk, + this.tck, + this.tms, + this.tdi, + this.sbaRdata, + this.sbaAck, + this.mem, + ); + + Future _tick() async { + await clk.nextPosedge; + final req = dut.sbaReq.value.isValid ? dut.sbaReq.value.toInt() : 0; + if (req == 1 && !_acked) { + final we = dut.sbaWe.value.toInt(); + final addr = dut.sbaAddr.value.toInt(); + if (we == 1) { + mem[addr] = dut.sbaWdata.value.toInt(); + } + sbaRdata.inject(mem[addr] ?? 0); + sbaAck.inject(1); + _acked = true; + } else { + sbaAck.inject(0); + _acked = false; + } + } + + Future _clk(int tmsv, [int tdiv = 0]) async { + tms.inject(tmsv); + tdi.inject(tdiv); + tck.inject(1); + await _tick(); + tck.inject(0); + await _tick(); + } + + Future idle(int n) async { + for (var i = 0; i < n; i++) { + await _clk(0); + } + } + + Future resetTap() async { + for (var i = 0; i < 5; i++) { + await _clk(1); + } + await _clk(0); + } + + Future scanDr(int bits, int value) async { + await _clk(1); // -> Select-DR + await _clk(0); // -> Capture-DR + await _clk(0); // -> Shift-DR + var captured = 0; + for (var i = 0; i < bits; i++) { + final last = i == bits - 1; + // TDO is combinational (the bit about to shift out); sample it BEFORE the + // clock that shifts it, matching the JTAG / OpenOCD convention. + if (dut.tdo.value.toInt() == 1) captured |= 1 << i; + await _clk(last ? 1 : 0, (value >> i) & 1); + } + await _clk(1); // Exit1-DR -> Update-DR + await _clk(0); // -> Run-Test/Idle + return captured; + } + + Future scanIr(int bits, int value) async { + await _clk(1); // -> Select-DR + await _clk(1); // -> Select-IR + await _clk(0); // -> Capture-IR + await _clk(0); // -> Shift-IR + var captured = 0; + for (var i = 0; i < bits; i++) { + final last = i == bits - 1; + // TDO is combinational (the bit about to shift out); sample it BEFORE the + // clock that shifts it, matching the JTAG / OpenOCD convention. + if (dut.tdo.value.toInt() == 1) captured |= 1 << i; + await _clk(last ? 1 : 0, (value >> i) & 1); + } + await _clk(1); // -> Update-IR + await _clk(0); // -> Run-Test/Idle + return captured; + } + + Future dmWrite(int addr, int data) => + scanDr(41, (addr << 34) | ((data & 0xFFFFFFFF) << 2) | 2); + + Future dmRead(int addr) async { + await scanDr(41, (addr << 34) | 1); + final captured = await scanDr(41, 0); + return (captured >> 2) & 0xFFFFFFFF; + } +} + +void main() { + group('RiverDebugModule (TAP/DTM/DM/SBA over JTAG)', () { + late Logic clk, reset, tck, tms, tdi, trstN, sbaRdata, sbaAck; + late RiverDebugModule dut; + late JtagHost host; + late Map mem; + + Future boot({Logic? hartHalted}) async { + await Simulator.reset(); + clk = SimpleClockGenerator(10).clk; + reset = Logic(name: 'reset'); + tck = Logic(name: 'tck'); + tms = Logic(name: 'tms'); + tdi = Logic(name: 'tdi'); + trstN = Logic(name: 'trst_n'); + sbaRdata = Logic(name: 'sba_rdata', width: 64); + sbaAck = Logic(name: 'sba_ack'); + mem = {}; + dut = RiverDebugModule( + clk, + reset, + tck, + tms, + tdi, + trstN, + hartHalted: hartHalted, + sbaRdata: sbaRdata, + sbaAck: sbaAck, + xlen: 64, + idcode: 0x10000001, + ); + await dut.build(); + reset.inject(1); + tck.inject(0); + tms.inject(0); + tdi.inject(0); + trstN.inject(1); + sbaRdata.inject(0); + sbaAck.inject(0); + Simulator.setMaxSimTime(50000000); + unawaited(Simulator.run()); + await clk.nextPosedge; + reset.inject(0); + await clk.nextPosedge; + host = JtagHost(dut, clk, tck, tms, tdi, sbaRdata, sbaAck, mem); + } + + tearDown(() async { + await Simulator.endSimulation(); + await Simulator.simulationEnded; + }); + + test('reads IDCODE', () async { + await boot(); + await host.resetTap(); + expect(await host.scanDr(32, 0), 0x10000001); + }); + + test('dmstatus reports version 0.13.2 and running', () async { + await boot(); + await host.resetTap(); + await host.scanIr(5, 0x11); + final dmstatus = await host.dmRead(0x11); + expect(dmstatus & 0xF, 2, reason: 'debug spec version field'); + expect((dmstatus >> 9) & 1, 0, reason: 'allhalted == 0 when running'); + expect((dmstatus >> 11) & 1, 1, reason: 'allrunning == 1'); + }); + + test('dmstatus reflects a halted hart', () async { + final halted = Logic(name: 'halted_tie'); + await boot(hartHalted: halted); + halted.inject(1); + await host.resetTap(); + await host.scanIr(5, 0x11); + final dmstatus = await host.dmRead(0x11); + expect((dmstatus >> 9) & 1, 1, reason: 'allhalted == 1'); + expect((dmstatus >> 8) & 1, 1, reason: 'anyhalted == 1'); + }); + + test('system bus access: write then read back memory', () async { + await boot(); + await host.resetTap(); + await host.scanIr(5, 0x11); + + // Write phase (sbreadonaddr off): set address, then write data0. + await host.dmWrite(0x39, 0x40); // sbaddress0 = 0x40 + await host.dmWrite(0x3c, 0xCAFEBABE); // sbdata0 -> bus write + await host.idle(4); // let the bus access drain + expect(mem[0x40], 0xCAFEBABE, reason: 'SBA wrote through to memory'); + + // Read phase: enable sbreadonaddr, write the address to trigger a read, + // then read sbdata0 back. + await host.dmWrite( + 0x38, + (2 << 17) | (1 << 20), + ); // sbaccess=32b, readonaddr + await host.dmWrite(0x39, 0x40); + await host.idle(4); + expect(await host.dmRead(0x3c), 0xCAFEBABE); + }); + }); +} diff --git a/packages/river_hdl/test/debug/debug_pump_test.dart b/packages/river_hdl/test/debug/debug_pump_test.dart new file mode 100644 index 0000000..d9b1748 --- /dev/null +++ b/packages/river_hdl/test/debug/debug_pump_test.dart @@ -0,0 +1,144 @@ +import 'package:river_hdl/river_hdl.dart'; +import 'package:test/test.dart'; + +/// Unit tests for [ResumePump]'s resume-aware clocking, using a mock core so the +/// loop logic is exercised without building any RTL (fast). The mock counts +/// `advanceOneClock` calls and reports "halted" via a programmable predicate, so +/// each test scripts exactly when the core self-halts. +void main() { + test( + 'no resume edge: a running core advances exactly one clock per pump', + () async { + // Core is running and stays running (never halted, no edge). Each pump must + // advance exactly one clock - no free-run. + final mock = _Mock(haltsAfter: null, startHalted: false); + final pump = mock.makePump(1000000); + for (var i = 0; i < 5; i++) { + await pump.pump(); + } + expect(mock.clocks, 5, reason: 'one clock per bit when never halted'); + }, + ); + + test( + 'post-reset running never triggers free-run even after many pumps', + () async { + // The dummy-firmware case: running from reset, never halted. Must NOT spin + // the budget (the bug the redesign fixes). + final mock = _Mock(haltsAfter: null, startHalted: false); + final pump = mock.makePump(1000000); + for (var i = 0; i < 20; i++) { + await pump.pump(); + } + expect( + mock.clocks, + 20, + reason: 'no edge -> no free-run -> no budget spin', + ); + }, + ); + + test('resume edge free-runs to self-halt', () async { + // Core starts halted; the first pump observes the running transition (the + // mock flips to running once pumped) and free-runs until it self-halts. + final mock = _Mock(haltsAfter: 7, startHalted: true); + final pump = mock.makePump(1000000); + // First pump: advanceOneClock makes the mock "resumed" (running), the pump + // sees was-halted && now-running -> free-run until clock 7 self-halts. + await pump.pump(); + expect(mock.halted, isTrue, reason: 'free-run reached the self-halt'); + expect(mock.clocks, 7, reason: 'ran exactly to the ebreak (clock 7)'); + expect(pump.wasHalted, isTrue); + }); + + test('non-self-halting resume falls back at the budget (no wedge)', () async { + // Resume onto a program with no ebreak: the free-run must stop at the budget + // and hand control back, not spin forever. + final mock = _Mock(haltsAfter: null, startHalted: true); + final pump = mock.makePump(500); + await pump.pump(); + // 1 clock for the pump's own advance (the resume edge) + 500 free-run. + expect(mock.clocks, 501, reason: 'free-run bounded by the budget'); + expect(pump.wasHalted, isFalse, reason: 'still running after the budget'); + // After the budget it is one-clock-per-bit again (no fresh edge: it was + // already running at the end of the last pump). + await pump.pump(); + expect( + mock.clocks, + 502, + reason: 'no re-trigger; back to one clock per bit', + ); + }); + + test('halt then resume across pumps is a single edge', () async { + // Running -> debugger halts -> debugger resumes onto a self-halting program. + final mock = _Mock(haltsAfter: null, startHalted: false); + final pump = mock.makePump(1000000); + await pump.pump(); // running, one clock + expect(mock.clocks, 1); + + // Debugger halts the core. + mock.forceHalt(); + await pump.pump(); // observes halted; one clock, no edge + expect(pump.wasHalted, isTrue); + + // Debugger resumes onto a program that self-halts after 4 clocks. + mock.resumeSelfHaltingAfter(4); + await pump.pump(); // edge -> free-run to self-halt + expect(mock.halted, isTrue); + expect(pump.wasHalted, isTrue); + }); +} + +/// Mock core driving a [ResumePump]. Halt state is scripted so tests can place +/// the self-halt at a precise clock. +class _Mock { + _Mock({required this.haltsAfter, required this.startHalted}) + : _halted = startHalted; + + /// Clocks-since-resume at which the core self-halts (null = never). + int? haltsAfter; + final bool startHalted; + + int clocks = 0; + int _clocksSinceResume = 0; + bool _halted; + bool _forcedHalt = false; + + bool get halted => _halted; + + ResumePump makePump(int resumeBudget) => ResumePump( + advanceOneClock: _advance, + coreHalted: () => _halted, + resumeBudget: resumeBudget, + yieldEvery: 64, + initiallyHalted: startHalted, + ); + + Future _advance() async { + clocks++; + // The first clock after being halted is the resume: the core starts running. + if (_halted && !_forcedHalt) { + _halted = false; + _clocksSinceResume = 0; + } + if (!_halted) { + _clocksSinceResume++; + if (haltsAfter != null && _clocksSinceResume >= haltsAfter!) { + _halted = true; + } + } + } + + /// Debugger halt: the core is halted and stays halted until a resume is set up. + void forceHalt() { + _halted = true; + _forcedHalt = true; + } + + /// Debugger resume onto a program that self-halts after [n] clocks. + void resumeSelfHaltingAfter(int n) { + _forcedHalt = false; + haltsAfter = n; + } +} diff --git a/packages/river_hdl/test/debug/ebreak_debug_halt_test.dart b/packages/river_hdl/test/debug/ebreak_debug_halt_test.dart new file mode 100644 index 0000000..1997c2e --- /dev/null +++ b/packages/river_hdl/test/debug/ebreak_debug_halt_test.dart @@ -0,0 +1,172 @@ +import 'dart:async'; +import 'package:rohd/rohd.dart'; +import 'package:rohd_hcl/rohd_hcl.dart' hide DataPortInterface, DataPortGroup; +import 'package:river/river.dart'; +import 'package:river_hdl/river_hdl.dart'; +import 'package:test/test.dart'; + +// Drives a withDebug core directly (no JTAG): halt, set dcsr.ebreakm, resume +// into `li a0,0x42 ; ebreak ; j _start`, and assert the core self-halts at the +// ebreak (debug_halted=1, dpc=4, a0=0x42). +void main() { + tearDown(() async => Simulator.reset()); + + test( + 'ebreak with dcsr.ebreakm enters debug', + timeout: Timeout(Duration(seconds: 120)), + () async { + final config = RiverCoreConfigV1.small( + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + interrupts: [], + clock: const HarborClockConfig( + name: 't', + rate: HarborFixedClockRate(10000), + ), + ); + final aw = config.mxlen.size; + final clk = SimpleClockGenerator(20).clk; + final reset = Logic(); + final wbConfig = WishboneConfig( + addressWidth: aw, + dataWidth: aw, + selWidth: aw ~/ 8, + ); + final core = RiverCore(config, busConfig: wbConfig, withDebug: true); + core.input('clk').srcConnection! <= clk; + core.input('reset').srcConnection! <= reset; + await core.build(); + + final storage = SparseMemoryStorage( + addrWidth: aw, + dataWidth: aw, + alignAddress: (a) => a, + onInvalidRead: (a, w) => LogicValue.filled(w, LogicValue.zero), + ); + final memRead = DataPortInterface(aw, aw); + final memWrite = DataPortInterface(aw, aw); + // ignore: unused_local_variable + final mem = MemoryModel( + clk, + reset, + [wrapWriteForRegisterFile(memWrite)], + [wrapReadForRegisterFile(memRead)], + storage: storage, + ); + final wbCyc = core.output('dataBus_CYC'), + wbStb = core.output('dataBus_STB'); + final wbWe = core.output('dataBus_WE'), + wbAdr = core.output('dataBus_ADR'); + memRead.en <= wbCyc & wbStb & ~wbWe; + memRead.addr <= wbAdr; + memWrite.en <= wbCyc & wbStb & wbWe; + memWrite.addr <= wbAdr; + memWrite.data <= core.output('dataBus_DAT_MOSI'); + final wbAckReg = Logic(); + Sequential(clk, [ + If( + reset, + then: [wbAckReg < 0], + orElse: [ + If( + wbCyc & wbStb & ~wbAckReg & (wbWe | memRead.valid), + then: [wbAckReg < 1], + orElse: [wbAckReg < 0], + ), + ], + ), + ]); + core.input('dataBus_ACK').srcConnection! <= wbAckReg; + core.input('dataBus_DAT_MISO').srcConnection! <= memRead.data; + + // debug port drivers + final dHalt = Logic(), + dResume = Logic(), + dRegRead = Logic(), + dRegWrite = Logic(); + final dRegAddr = Logic(width: 16), dRegWdata = Logic(width: aw); + core.input('debug_halt_req').srcConnection! <= dHalt; + core.input('debug_resume_req').srcConnection! <= dResume; + core.input('debug_reg_read').srcConnection! <= dRegRead; + core.input('debug_reg_write').srcConnection! <= dRegWrite; + core.input('debug_reg_addr').srcConnection! <= dRegAddr; + core.input('debug_reg_wdata').srcConnection! <= dRegWdata; + for (final s in [dHalt, dResume, dRegRead, dRegWrite]) { + s.inject(0); + } + dRegAddr.inject(0); + dRegWdata.inject(0); + reset.inject(1); + + // Program at 0: li a0,0x42 ; ebreak ; j _start + Simulator.registerAction(20, () { + reset.put(0); + storage.setData( + LogicValue.ofInt(0, aw), + LogicValue.ofBigInt(BigInt.parse('0010007304200513', radix: 16), aw), + ); + storage.setData( + LogicValue.ofInt(8, aw), + LogicValue.ofBigInt(BigInt.parse('00000013ff9ff06f', radix: 16), aw), + ); + }); + + final halted = core.output('debug_halted'); + final dpc = core.output('debug_dpc'); + unawaited(Simulator.run()); + // let it come out of reset and run a bit + for (var i = 0; i < 6; i++) { + await clk.nextPosedge; + } + // halt + dHalt.inject(1); + await clk.nextPosedge; + dHalt.inject(0); + for (var i = 0; i < 4; i++) { + await clk.nextPosedge; + } + expect( + halted.value.toInt(), + 1, + reason: 'core should be halted by haltreq', + ); + // write dcsr.ebreakm (0xb000) and dpc=0 + dRegWrite.inject(1); + dRegAddr.inject(0x7b0); + dRegWdata.inject(0xb000); + await clk.nextPosedge; + dRegAddr.inject(0x7b1); + dRegWdata.inject(0); + await clk.nextPosedge; + dRegWrite.inject(0); + await clk.nextPosedge; + // resume + dResume.inject(1); + await clk.nextPosedge; + dResume.inject(0); + // run; expect self-halt on ebreak within N cycles + var sawHalt = false; + for (var i = 0; i < 60; i++) { + await clk.nextPosedge; + if (halted.value.isValid && halted.value.toInt() == 1) { + sawHalt = true; + break; + } + } + final a0 = core.regs.getData(LogicValue.ofInt(10, 5)); + await Simulator.endSimulation(); + expect( + sawHalt, + true, + reason: 'ebreak (ebreakm set) should re-enter debug', + ); + // dpc latches the ebreak PC (0x4) and a0 holds the value set before it. + expect(dpc.value.toInt(), 0x4); + expect(a0!.toInt(), 0x42); + }, + ); +} diff --git a/packages/river_hdl/test/debug/ebreak_trap_probe_test.dart b/packages/river_hdl/test/debug/ebreak_trap_probe_test.dart new file mode 100644 index 0000000..e2018a5 --- /dev/null +++ b/packages/river_hdl/test/debug/ebreak_trap_probe_test.dart @@ -0,0 +1,44 @@ +import 'package:rohd/rohd.dart'; +import 'package:river/river.dart'; +import 'package:test/test.dart'; +import '../core_harness.dart'; + +// Diagnostic: does the in-order core trap on ebreak (cause 3) like ecall? +// Mirrors core_trap_return_test's ecall case, swapping ecall (73 00 00 00) +// for ebreak (73 00 10 00). Same handler bumps mepc past it and mret resumes. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + final config = RiverCoreConfigV1.small( + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + interrupts: [], + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + ); + + test( + 'ebreak traps to mtvec, mret resumes after ebreak', + timeout: Timeout(Duration(seconds: 200)), + () { + return coreTest( + '@0\n' + '73 10 55 30 73 00 10 00 93 05 50 05 13 00 00 00 ' + '13 00 00 00 13 00 00 00 13 00 00 00 73 26 10 34 ' + '13 06 46 00 73 10 16 34 73 00 20 30\n', + {Register.x11: 0x55, Register.x12: 0x8}, + config, + initRegisters: {Register.x10: 0x1c}, + nextPc: 0xc, + ); + }, + ); +} diff --git a/packages/river_hdl/test/debug/jtag_tunnel_dm_test.dart b/packages/river_hdl/test/debug/jtag_tunnel_dm_test.dart new file mode 100644 index 0000000..ccc7423 --- /dev/null +++ b/packages/river_hdl/test/debug/jtag_tunnel_dm_test.dart @@ -0,0 +1,272 @@ +import 'dart:async'; + +import 'package:rohd/rohd.dart'; +import 'package:river_hdl/src/core/debug.dart'; +import 'package:river_hdl/src/core/jtag_bscan_tunnel.dart'; +import 'package:test/test.dart'; + +/// Drives the [JtagBscanTunnel] + a real [RiverDebugModule] exactly as +/// riscv-openocd would over the ECP5 `JTAGG` ER1 user register: it builds the +/// SiFive NESTED_TAP tunnel frame (sel + width + payload + idle), strobes the +/// ER1 Capture/Shift/Update signals the JTAGG primitive would emit, and recovers +/// the inner TAP's TDO from `jtdo1`. The frame layout is taken verbatim from +/// OpenOCD's `riscv_add_bscan_tunneled_scan` so this validates the tunnel +/// framing against the authoritative protocol, not against our own assumptions. +class Er1Host { + final Logic clk, jtck, jtdi, jshift, jupdate, jce1, jrstn, jtdo1; + final RiverDebugModule dut; + final Logic sbaRdata, sbaAck; + final Map mem; + bool _acked = false; + + Er1Host( + this.clk, + this.jtck, + this.jtdi, + this.jshift, + this.jupdate, + this.jce1, + this.jrstn, + this.jtdo1, + this.dut, + this.sbaRdata, + this.sbaAck, + this.mem, + ); + + /// Service the DM's single-outstanding System Bus Access port against [mem]. + void _serviceSba() { + final req = dut.sbaReq.value.isValid ? dut.sbaReq.value.toInt() : 0; + if (req == 1 && !_acked) { + final we = dut.sbaWe.value.toInt(); + final addr = dut.sbaAddr.value.toInt(); + if (we == 1) { + mem[addr] = dut.sbaWdata.value.toInt(); + } + sbaRdata.inject(mem[addr] ?? 0); + sbaAck.inject(1); + _acked = true; + } else { + sbaAck.inject(0); + _acked = false; + } + } + + Future _settle() async { + // Let the system clock sample the JTAG-domain levels (edge detect) and + // service SBA so DM bus accesses can drain. + await clk.nextPosedge; + _serviceSba(); + await clk.nextPosedge; + _serviceSba(); + } + + /// One ER1 TCK pulse with the given shift/update strobes and TDI; returns the + /// jtdo1 value sampled just before the shifting edge (JTAG TDO convention). + Future _pulse({ + required int shift, + required int update, + required int tdi, + int ce1 = 1, + }) async { + jce1.inject(ce1); + jshift.inject(shift); + jupdate.inject(update); + jtdi.inject(tdi); + await _settle(); + final tdo = jtdo1.value.isValid ? jtdo1.value.toInt() : 0; + jtck.inject(1); + await _settle(); + jtck.inject(0); + await _settle(); + return tdo; + } + + /// Scan a NESTED_TAP tunnel frame: sel (1=DR,0=IR), width N, payload of N+1 + /// bits. Returns the N+1 jtdo1 samples taken over the payload window. + Future tunnelScan(int sel, int n, int payload) async { + final frame = []; + frame.add(sel & 1); + for (var i = 0; i < 7; i++) { + frame.add((n >> i) & 1); // width, LSB first + } + for (var i = 0; i < n + 1; i++) { + frame.add((payload >> i) & 1); // payload (N+1, LSB first) + } + frame.addAll([0, 0, 0]); // idle + + // Outer Capture-DR (jce1=1, jshift=0): inner TAP is NOT clocked. + await _pulse(shift: 0, update: 0, tdi: 0); + + // Outer Shift-DR: shift the whole frame, sample jtdo1 each bit. + final payloadStart = 8; + var captured = 0; + for (var i = 0; i < frame.length; i++) { + final tdo = await _pulse(shift: 1, update: 0, tdi: frame[i]); + if (i >= payloadStart && i <= payloadStart + n) { + if (tdo == 1) captured |= 1 << (i - payloadStart); + } + } + + // Outer Update-DR. + await _pulse(shift: 0, update: 1, tdi: 0); + await _pulse(shift: 0, update: 0, tdi: 0); + return captured; + } + + Future tapReset() async { + jrstn.inject(0); + await _settle(); + jrstn.inject(1); + await _settle(); + } + + /// Inner IR scan (sel=0): set the inner DM TAP instruction (irWidth=5). + Future innerIr(int ir) => tunnelScan(0, 5, ir); + + /// Inner DR scan (sel=1) of [n] bits; returns the inner TAP's TDO with the + /// 1-TCK skew removed (OpenOCD right-shifts the captured field by 1). + Future innerDr(int n, int value) async { + final raw = await tunnelScan(1, n, value); + return (raw >> 1) & ((1 << n) - 1); + } + + Future idleFrames(int n) async { + for (var i = 0; i < n; i++) { + await _pulse(shift: 0, update: 0, tdi: 0, ce1: 0); + } + } + + Future dmiWrite(int addr, int data) => + innerDr(41, (addr << 34) | ((data & 0xFFFFFFFF) << 2) | 2); + + Future dmiRead(int addr) async { + await innerDr(41, (addr << 34) | 1); + final captured = await innerDr(41, 0); + return (captured >> 2) & 0xFFFFFFFF; + } +} + +void main() { + group('JtagBscanTunnel + RiverDebugModule (NESTED_TAP over ER1)', () { + late Logic clk, reset, sbaRdata, sbaAck; + late JtagBscanTunnel tunnel; + late RiverDebugModule dm; + late Er1Host host; + late Map mem; + late Logic jtck, jtdi, jshift, jupdate, jce1, jrstn; + + Future boot() async { + await Simulator.reset(); + clk = SimpleClockGenerator(10).clk; + reset = Logic(name: 'reset'); + jtck = Logic(name: 'jtck'); + jtdi = Logic(name: 'jtdi'); + jshift = Logic(name: 'jshift'); + jupdate = Logic(name: 'jupdate'); + jce1 = Logic(name: 'jce1'); + jrstn = Logic(name: 'jrstn'); + sbaRdata = Logic(name: 'sba_rdata', width: 64); + sbaAck = Logic(name: 'sba_ack'); + mem = {}; + + tunnel = JtagBscanTunnel(maxScanBits: 64); + tunnel.input('clk').srcConnection! <= clk; + tunnel.input('reset').srcConnection! <= reset; + tunnel.input('jtck').srcConnection! <= jtck; + tunnel.input('jtdi').srcConnection! <= jtdi; + tunnel.input('jshift').srcConnection! <= jshift; + tunnel.input('jupdate').srcConnection! <= jupdate; + tunnel.input('jce1').srcConnection! <= jce1; + tunnel.input('jrstn').srcConnection! <= jrstn; + + dm = RiverDebugModule( + clk, + reset, + tunnel.output('inner_tck'), + tunnel.output('inner_tms'), + tunnel.output('inner_tdi'), + tunnel.output('inner_trst_n'), + sbaRdata: sbaRdata, + sbaAck: sbaAck, + xlen: 64, + idcode: 0x10000001, + ); + tunnel.input('inner_tdo').srcConnection! <= dm.tdo; + + await tunnel.build(); + await dm.build(); + reset.inject(1); + jtck.inject(0); + jtdi.inject(0); + jshift.inject(0); + jupdate.inject(0); + jce1.inject(0); + jrstn.inject(1); + sbaRdata.inject(0); + sbaAck.inject(0); + Simulator.setMaxSimTime(200000000); + unawaited(Simulator.run()); + await clk.nextPosedge; + reset.inject(0); + await clk.nextPosedge; + host = Er1Host( + clk, + jtck, + jtdi, + jshift, + jupdate, + jce1, + jrstn, + tunnel.output('jtdo1'), + dm, + sbaRdata, + sbaAck, + mem, + ); + } + + tearDown(() async { + await Simulator.endSimulation(); + await Simulator.simulationEnded; + }); + + test('tunneled IDCODE read returns 0x10000001', () async { + await boot(); + await host.tapReset(); + // Inner IR defaults to IDCODE after TAP reset. Inner DR scan, N=32. + final raw = await host.tunnelScan(1, 32, 0); + // OpenOCD compensates the 1-TCK skew by right-shifting the captured field. + final idcode = (raw >> 1) & 0xFFFFFFFF; + expect(idcode, 0x10000001); + }); + + test( + 'tunneled inner-IR scan + dmstatus reads version 0.13.2 / running', + () async { + await boot(); + await host.tapReset(); + await host.innerIr(0x11); // inner IR <- DMI + final dmstatus = await host.dmiRead(0x11); + expect(dmstatus & 0xF, 2, reason: 'debug spec version field'); + expect((dmstatus >> 11) & 1, 1, reason: 'allrunning == 1'); + }, + ); + + test('tunneled SBA: write then read back memory', () async { + await boot(); + await host.tapReset(); + await host.innerIr(0x11); // inner IR <- DMI + + await host.dmiWrite(0x39, 0x40); // sbaddress0 = 0x40 + await host.dmiWrite(0x3c, 0xCAFEBABE); // sbdata0 -> bus write + await host.idleFrames(4); // let the bus access drain + expect(mem[0x40], 0xCAFEBABE, reason: 'SBA wrote through to memory'); + + await host.dmiWrite(0x38, (2 << 17) | (1 << 20)); // 32b, readonaddr + await host.dmiWrite(0x39, 0x40); // triggers a read + await host.idleFrames(4); + expect(await host.dmiRead(0x3c), 0xCAFEBABE); + }); + }); +} diff --git a/packages/river_hdl/test/debug/sim_pump_test.dart b/packages/river_hdl/test/debug/sim_pump_test.dart new file mode 100644 index 0000000..d22f62a --- /dev/null +++ b/packages/river_hdl/test/debug/sim_pump_test.dart @@ -0,0 +1,74 @@ +import 'dart:async'; + +import 'package:rohd/rohd.dart'; +import 'package:test/test.dart'; + +/// Validates the manual `Simulator.tick()` pump that river_sim's +/// remote_bitbang mode uses instead of a free-running `Simulator.run()`. +/// +/// The pump must (a) advance the clock so the design runs, and (b) yield to the +/// Dart event loop each tick so concurrent async work (the JTAG socket) is +/// serviced. A free-running `Simulator.run()` chains ticks via microtasks and +/// starves I/O; the pump below breaks that with a zero-duration timer. +void main() { + test( + 'Simulator.tick() pump advances a clocked counter and yields to I/O', + () async { + await Simulator.reset(); + final clk = SimpleClockGenerator(20).clk; + final reset = Logic(name: 'reset'); + final count = Logic(name: 'count', width: 16); + Sequential(clk, [ + If(reset, then: [count < 0], orElse: [count < count + 1]), + ]); + + reset.inject(1); + + // A concurrent task that only makes progress if the pump yields to the + // event loop (real timers), standing in for the socket read loop. + var concurrentTicks = 0; + var running = true; + unawaited(() async { + while (running) { + await Future.delayed(Duration.zero); + concurrentTicks++; + } + }()); + + // Manual pump: NO Simulator.run(). + var prevClk = 0; + var cycles = 0; + for (var i = 0; i < 400 && cycles < 20; i++) { + await Simulator.tick(); + if (i == 1) reset.inject(0); + final c = (clk.value.isValid && clk.value.toBool()) ? 1 : 0; + if (c == 1 && prevClk == 0) cycles++; + prevClk = c; + await Future.delayed(Duration.zero); + } + running = false; + + expect( + cycles, + greaterThanOrEqualTo(20), + reason: 'the pump must advance the clock', + ); + expect( + count.value.toInt(), + greaterThanOrEqualTo(18), + reason: 'the clocked counter must increment under the pump', + ); + // ~1 concurrent turn per pump iteration (loop runs ~40 iterations for 20 + // cycles), so a healthy count near `cycles` proves I/O is not starved. + expect( + concurrentTicks, + greaterThanOrEqualTo(20), + reason: 'concurrent async work must run (I/O is not starved)', + ); + + // NOTE: with a hand-pumped simulator there is no `Simulator.run()` loop, so + // `await Simulator.simulationEnded` would hang. Just stop pumping. + Simulator.endSimulation(); + }, + ); +} diff --git a/packages/river_hdl/test/decode/amo_decode_test.dart b/packages/river_hdl/test/decode/amo_decode_test.dart new file mode 100644 index 0000000..36ec969 --- /dev/null +++ b/packages/river_hdl/test/decode/amo_decode_test.dart @@ -0,0 +1,55 @@ +import 'package:river/river.dart'; +import 'package:test/test.dart'; + +/// Atomic (A) decode regression: every AMO/LR/SC decodes at its SPEC encoding, +/// where the funct7 field (inst[31:25]) = funct5<<2 (aq=rl=0). Guards the fix for +/// the systematic Harbor bug where atomic funct7 values were funct5<<3 - which made +/// amoxor/amoor/amomin mis-decode (e.g. amoxor.w -> lr.w) and amomax/amominu/amomaxu +/// undecodable (funct7 > 0x7F). Only amoadd (funct5=0) was accidentally correct. +void main() { + final config = RiverCoreConfigV1.macro( + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + interrupts: [], + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + ); + + // funct5 -> mnemonic stem (RISC-V A spec). funct3 selects .w (0x2) / .d (0x3). + const funct5 = { + 0x00: 'amoadd', + 0x01: 'amoswap', + 0x02: 'lr', + 0x03: 'sc', + 0x04: 'amoxor', + 0x08: 'amoor', + 0x0C: 'amoand', + 0x10: 'amomin', + 0x14: 'amomax', + 0x18: 'amominu', + 0x1C: 'amomaxu', + }; + + for (final width in const [(0x2, 'w'), (0x3, 'd')]) { + test('atomics decode at spec encodings (.${width.$2})', () { + for (final e in funct5.entries) { + // funct7 = funct5<<2 (aq=rl=0); opcode AMO = 0x2F; rs2=rs1=rd=0. + final instr = ((e.key << 2) << 25) | (width.$1 << 12) | 0x2F; + final op = config.isa.findOperation(instr); + expect( + op?.mnemonic, + '${e.value}.${width.$2}', + reason: + 'funct5=0x${e.key.toRadixString(16)} instr=' + '0x${instr.toRadixString(16)} should be ${e.value}.${width.$2}', + ); + } + }); + } +} diff --git a/packages/river_hdl/test/decode/rtype_decode_audit_test.dart b/packages/river_hdl/test/decode/rtype_decode_audit_test.dart new file mode 100644 index 0000000..7bc171c --- /dev/null +++ b/packages/river_hdl/test/decode/rtype_decode_audit_test.dart @@ -0,0 +1,147 @@ +import 'package:river/river.dart'; +import 'package:test/test.dart'; + +/// Decode-correctness audit for funct7-bearing R-type ops (base OP 0x33, OP-32 +/// 0x3B, M extension) at SPEC encodings. Same bug class as the AMO funct7 bug +/// (project_amo_funct7_bug): catches any op whose funct7/funct3 in Harbor doesn't +/// match the real RISC-V encoding, which would silently mis-decode real code. +void main() { + final config = RiverCoreConfigV1.macro( + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + interrupts: [], + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + ); + + // (opcode, funct3, funct7, rs2, mnemonic). rs1=rd=0. + int enc(int opcode, int f3, int f7, int rs2) => + (f7 << 25) | (rs2 << 20) | (f3 << 12) | opcode; + + // OP-FP (0x53) ops: funct7-distinguished arithmetic, plus a couple rs2-coded + // fcvt pairs (same funct7, differ only by rs2 - exercises rs2 disambiguation). + final fpCases = <(int, int, int, int, String)>[ + (0x53, 0x0, 0x00, 0, 'fadd.s'), (0x53, 0x0, 0x01, 0, 'fadd.d'), + (0x53, 0x0, 0x04, 0, 'fsub.s'), (0x53, 0x0, 0x05, 0, 'fsub.d'), + (0x53, 0x0, 0x08, 0, 'fmul.s'), (0x53, 0x0, 0x09, 0, 'fmul.d'), + (0x53, 0x0, 0x0C, 0, 'fdiv.s'), (0x53, 0x0, 0x0D, 0, 'fdiv.d'), + (0x53, 0x0, 0x10, 0, 'fsgnj.s'), (0x53, 0x1, 0x10, 0, 'fsgnjn.s'), + (0x53, 0x0, 0x14, 0, 'fmin.s'), (0x53, 0x1, 0x14, 0, 'fmax.s'), + (0x53, 0x2, 0x50, 0, 'feq.s'), (0x53, 0x1, 0x50, 0, 'flt.s'), + (0x53, 0x0, 0x50, 0, 'fle.s'), + (0x53, 0x0, 0x60, 0, 'fcvt.w.s'), (0x53, 0x0, 0x68, 0, 'fcvt.s.w'), + // NOTE: the rs2-coded fcvt variants (fcvt.wu/l/lu .s/.d, fcvt.s.wu/l/lu) are + // NOT yet defined as Harbor decode ops, and the defined ones lack an rs2 + // matchMask, so a real fcvt.wu.s (rs2=1) currently mis-decodes to fcvt.w.s. + // Decode-completion is a separate task - see project_fcvt_decode_gap. + ]; + + final cases = <(int, int, int, String)>[ + // base OP (0x33) + (0x33, 0x0, 0x00, 'add'), (0x33, 0x0, 0x20, 'sub'), + (0x33, 0x1, 0x00, 'sll'), (0x33, 0x2, 0x00, 'slt'), + (0x33, 0x3, 0x00, 'sltu'), (0x33, 0x4, 0x00, 'xor'), + (0x33, 0x5, 0x00, 'srl'), (0x33, 0x5, 0x20, 'sra'), + (0x33, 0x6, 0x00, 'or'), (0x33, 0x7, 0x00, 'and'), + // M extension (0x33, funct7=0x01) + (0x33, 0x0, 0x01, 'mul'), (0x33, 0x1, 0x01, 'mulh'), + (0x33, 0x2, 0x01, 'mulhsu'), (0x33, 0x3, 0x01, 'mulhu'), + (0x33, 0x4, 0x01, 'div'), (0x33, 0x5, 0x01, 'divu'), + (0x33, 0x6, 0x01, 'rem'), (0x33, 0x7, 0x01, 'remu'), + // OP-32 (0x3B, RV64) + (0x3B, 0x0, 0x00, 'addw'), (0x3B, 0x0, 0x20, 'subw'), + (0x3B, 0x1, 0x00, 'sllw'), (0x3B, 0x5, 0x00, 'srlw'), + (0x3B, 0x5, 0x20, 'sraw'), + // M64 (0x3B, funct7=0x01) + (0x3B, 0x0, 0x01, 'mulw'), (0x3B, 0x4, 0x01, 'divw'), + (0x3B, 0x5, 0x01, 'divuw'), (0x3B, 0x6, 0x01, 'remw'), + (0x3B, 0x7, 0x01, 'remuw'), + ]; + + test('R-type / M ops decode at spec encodings', () { + final fails = []; + for (final (op, f3, f7, want) in cases) { + final got = config.isa.findOperation(enc(op, f3, f7, 0))?.mnemonic; + if (got != want) { + fails.add( + '$want (op=0x${op.toRadixString(16)} f3=$f3 ' + 'f7=0x${f7.toRadixString(16)}) -> ${got ?? "NULL"}', + ); + } + } + expect(fails, isEmpty, reason: 'mis-decoded: ${fails.join("; ")}'); + }); + + test('OP-FP (F/D) ops decode at spec encodings', () { + final fails = []; + for (final (op, f3, f7, rs2, want) in fpCases) { + final got = config.isa.findOperation(enc(op, f3, f7, rs2))?.mnemonic; + if (got != want) { + fails.add( + '$want (f3=$f3 f7=0x${f7.toRadixString(16)} rs2=$rs2) ' + '-> ${got ?? "NULL"}', + ); + } + } + expect(fails, isEmpty, reason: 'mis-decoded: ${fails.join("; ")}'); + }); + + // SYSTEM (0x73) privileged ops. sret/wfi share funct7=0x08 and differ only in + // rs2 (sret=2, wfi=5); without an rs2 matchMask wfi mis-decoded to sret (a real + // OS-idle crash). Guards that fix plus the other SYSTEM ops. + test('SYSTEM privileged ops decode at spec encodings (wfi != sret)', () { + // (opcode, funct3, funct7, rs2, mnemonic) + final sysCases = <(int, int, int, int, String)>[ + (0x73, 0x0, 0x00, 0, 'ecall'), + (0x73, 0x0, 0x00, 1, 'ebreak'), + (0x73, 0x0, 0x08, 2, 'sret'), + (0x73, 0x0, 0x18, 2, 'mret'), + (0x73, 0x0, 0x08, 5, 'wfi'), // was mis-decoding to sret + ]; + final fails = []; + for (final (op, f3, f7, rs2, want) in sysCases) { + final got = config.isa.findOperation(enc(op, f3, f7, rs2))?.mnemonic; + if (got != want) { + fails.add( + '$want (f7=0x${f7.toRadixString(16)} rs2=$rs2) ' + '-> ${got ?? "NULL"}', + ); + } + } + expect(fails, isEmpty, reason: 'mis-decoded: ${fails.join("; ")}'); + }); + + // FMA (R4-type): opcode picks the op (fmadd/fmsub/fnmsub/fnmadd), fmt[26:25] + // picks single (0) vs double (1). rs3/rs2/rs1/rm/rd carry registers. + test('FMA R4-type ops decode at spec encodings (fmt picks s/d)', () { + int enc4(int opcode, int fmt) => + (0 << 27) | (fmt << 25) | (0 << 20) | (0 << 15) | (0 << 12) | opcode; + final fmaCases = <(int, int, String)>[ + (0x43, 0, 'fmadd.s'), + (0x47, 0, 'fmsub.s'), + (0x4B, 0, 'fnmsub.s'), + (0x4F, 0, 'fnmadd.s'), + (0x43, 1, 'fmadd.d'), + (0x47, 1, 'fmsub.d'), + (0x4B, 1, 'fnmsub.d'), + (0x4F, 1, 'fnmadd.d'), + ]; + final fails = []; + for (final (op, fmt, want) in fmaCases) { + final got = config.isa.findOperation(enc4(op, fmt))?.mnemonic; + if (got != want) { + fails.add( + '$want (op=0x${op.toRadixString(16)} fmt=$fmt) ' + '-> ${got ?? "NULL"}', + ); + } + } + expect(fails, isEmpty, reason: 'mis-decoded: ${fails.join("; ")}'); + }); +} diff --git a/packages/river_hdl/test/decode/rvc_decode_test.dart b/packages/river_hdl/test/decode/rvc_decode_test.dart new file mode 100644 index 0000000..d873887 --- /dev/null +++ b/packages/river_hdl/test/decode/rvc_decode_test.dart @@ -0,0 +1,78 @@ +import 'package:river/river.dart'; +import 'package:test/test.dart'; + +/// RV32C/RV64C decode regression: overlap-prone ops resolve distinctly, the full +/// op set is present, and the per-instruction scrambled immediates decode per the +/// RISC-V C-extension spec. Guards the fixes that closed project_rvc_audit (the +/// c.mv/c.add and c.jr/c.jalr/c.ebreak overlaps, the ~12 once-missing ops, and the +/// per-instruction sign-extended/scrambled immediates). +void main() { + final config = RiverCoreConfigV1.macro( + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + interrupts: [], + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + ); + + RiscVOperation? decode(int instr) { + final opcode = instr & 0x3; + final funct3 = (instr >> 13) & 0x7; + for (final ext in config.extensions) { + final op = ext.findOperation(opcode, funct3: funct3, instruction: instr); + if (op != null) return op; + } + return null; + } + + test('RVC overlap + once-missing ops resolve distinctly', () { + final cases = { + 0x8082: 'c.jr', // inst12=0, rs2=0 (NOT shadowed by c.mv) + 0x852E: 'c.mv', // inst12=0, rs2!=0 + 0x9082: 'c.jalr', // inst12=1, rs1!=0, rs2=0 (NOT shadowed by c.add) + 0x9002: 'c.ebreak', // inst12=1, rs1=0, rs2=0 + 0x952E: 'c.add', // inst12=1, rs2!=0 + 0x8091: 'c.srli', + 0x8511: 'c.srai', + 0x8911: 'c.andi', + 0x8D0D: 'c.sub', + 0x8D2D: 'c.xor', + 0x8D4D: 'c.or', + 0x8D6D: 'c.and', + }; + for (final e in cases.entries) { + expect( + decode(e.key)?.mnemonic, + e.value, + reason: '0x${e.key.toRadixString(16)} should decode to ${e.value}', + ); + } + }); + + test('RVC per-instruction scrambled immediates (known answers)', () { + // [kind, instrWord, expectedImm] + final cases = <(RvcImm, int, int)>[ + (RvcImm.ciAddi, 0x0014, 5), // +5 + (RvcImm.ciAddi, 0x107C, -1), // sign-extended -1 + (RvcImm.ciLui, 0x0004, 4096), // imm<<12 + (RvcImm.ciLui, 0x1000, -131072), // sign-extended from bit17 + (RvcImm.ciAddi16sp, 0x0040, 16), + (RvcImm.ciLwsp, 0x0004, 64), + (RvcImm.cssSwsp, 0x0200, 4), + (RvcImm.ciwAddi4spn, 0x0080, 64), + ]; + for (final (kind, word, want) in cases) { + expect( + decodeRvcImm(kind, word), + want, + reason: '$kind of 0x${word.toRadixString(16)} should be $want', + ); + } + }); +} diff --git a/packages/river_hdl/test/device_parse_test.dart b/packages/river_hdl/test/device_parse_test.dart new file mode 100644 index 0000000..5271001 --- /dev/null +++ b/packages/river_hdl/test/device_parse_test.dart @@ -0,0 +1,253 @@ +import 'package:river_hdl/river_hdl.dart'; +import 'package:test/test.dart'; + +void main() { + group('Device.parse - legacy device forms', () { + test('type:addr', () { + final d = Device.parse('uart:0x10000000'); + expect(d.type, 'uart'); + expect(d.name, 'uart'); + expect(d.address, 0x10000000); + expect(d.size, isNull); + expect(d.effectiveSize, 0x1000); // uart class default + }); + + test('type:addr:compat', () { + final d = Device.parse('uart:0x10000000:ns16550a'); + expect(d.type, 'uart'); + expect(d.address, 0x10000000); + expect(d.compatible, 'ns16550a'); + expect(d.board, isNull); + }); + + test('name=type:addr:compat', () { + final d = Device.parse('myuart=uart:0x10000000:ns16550a'); + expect(d.name, 'myuart'); + expect(d.type, 'uart'); + expect(d.address, 0x10000000); + expect(d.compatible, 'ns16550a'); + }); + + test('clint with class-default size', () { + final d = Device.parse('clint:0x02000000'); + expect(d.type, 'clint'); + expect(d.effectiveSize, 0x10000); + }); + }); + + group('Device.parse - memory-backed forms', () { + test('sram addr:size', () { + final d = Device.parse('sram:0x08000000:64K'); + expect(d.type, 'sram'); + expect(d.address, 0x08000000); + expect(d.size, 64 * 1024); + expect(d.isMemoryBacked, isTrue); + }); + + test('flash addr:size:board', () { + final d = Device.parse('flash:0x20000000:16M:arty-s7'); + expect(d.type, 'flash'); + expect(d.address, 0x20000000); + expect(d.size, 16 * 1024 * 1024); + expect(d.board, 'arty-s7'); + expect(d.flashBoard, isNotNull); + }); + + test('second bare number becomes size', () { + final d = Device.parse('sram:0x08000000:65536'); + expect(d.address, 0x08000000); + expect(d.size, 65536); + }); + + test('dram addr:size:board (no params)', () { + final d = Device.parse('dram:0x80000000:128M:arty-s7-x8'); + expect(d.type, 'dram'); + expect(d.address, 0x80000000); + expect(d.size, 128 * 1024 * 1024); + expect(d.board, 'arty-s7-x8'); + expect(d.ddrBoard, isNotNull); + expect(d.params, isNull); + }); + }); + + group('Device.parse - params', () { + test('dram with ddr clock params', () { + final d = Device.parse( + 'dram:0x80000000:128M:arty-s7-x8:ddr3fast=true,clockfreq=200000000', + ); + expect(d.board, 'arty-s7-x8'); + expect(d.params, isNotNull); + expect(d.params!.ddr3Fast, isTrue); + expect(d.params!.clockFreq, 200000000); + }); + + test('dram tuning params still parse (back-compat)', () { + final d = Device.parse( + 'dram:0x80000000:128M:arty-s7-x8:cmdslot=2,wrshift=-1,readretry=6', + ); + expect(d.params!.cmdSlot, 2); + expect(d.params!.wrShift, -1); // negative int + expect(d.params!.readRetry, 6); + }); + + test('usb-dfu with mode', () { + final d = Device.parse('usb-dfu:0x0C000000:mode=software'); + expect(d.type, 'usb-dfu'); + expect(d.address, 0x0C000000); + expect(d.params!.mode, 'software'); + }); + + test('flash-firmware offset + path (addr is the flash offset)', () { + final d = Device.parse('flash-firmware:0x100000:path=weir-fsbl.bin'); + expect(d.type, 'flash-firmware'); + expect(d.address, 0x100000); + expect(d.params!.path, 'weir-fsbl.bin'); + }); + }); + + group('Device.parse - addressless', () { + test('debug-jtag is type only', () { + final d = Device.parse('debug-jtag'); + expect(d.type, 'debug-jtag'); + expect(d.address, isNull); + expect(d.size, isNull); + expect(d.board, isNull); + expect(d.params, isNull); + }); + }); + + group('Device.parse - validation', () { + test('memory-backed type without size throws', () { + expect(() => Device.parse('sram:0x08000000'), throwsFormatException); + }); + + test('memory-backed type without address throws', () { + expect(() => Device.parse('dram'), throwsFormatException); + }); + + test('unknown dram board throws', () { + expect( + () => Device.parse('dram:0x80000000:128M:no-such-board'), + throwsA(isA()), + ); + }); + + test('dram size mismatch against the part throws', () { + expect( + () => Device.parse('dram:0x80000000:64M:arty-s7-x8'), + throwsA(isA()), + ); + }); + + test('bad usb-dfu mode throws', () { + expect( + () => Device.parse('usb-dfu:0x0C000000:mode=bogus'), + throwsFormatException, + ); + }); + + test('unknown param key throws', () { + expect( + () => Device.parse('dram:0x80000000:128M:arty-s7-x8:nonsense=1'), + throwsFormatException, + ); + }); + + test('a bare word in the board slot is treated as a board name', () { + // `mode` (no '=') is not a param; on a dram it is read as a board name, + // which is unknown -> ArgumentError. This is why params always need '='. + expect( + () => Device.parse('dram:0x80000000:128M:mode'), + throwsA(isA()), + ); + }); + }); + + group('DDR clock-tree agreement (buildSoC validation)', () { + test('two dram controllers disagreeing on ddr3fast throws', () { + final config = RiverGenIpConfig( + name: 'two_dram', + cores: const ['rc1-s'], + devices: [ + Device.parse('dram:0x80000000:128M:arty-s7-x8:ddr3fast=true'), + Device.parse('dram:0x90000000:128M:arty-s7-x8:ddr3fast=false'), + Device.parse('uart:0x10000000:ns16550a'), + ], + ); + // The validation is the first line of buildSoC, so it rejects before any + // heavy elaboration. + expect(config.buildSoC(), throwsA(isA())); + }); + + test('two dram controllers disagreeing on clockfreq throws', () { + final config = RiverGenIpConfig( + name: 'two_dram', + cores: const ['rc1-s'], + devices: [ + Device.parse('dram:0x80000000:128M:arty-s7-x8:clockfreq=200000000'), + Device.parse('dram:0x90000000:128M:arty-s7-x8:clockfreq=333333333'), + Device.parse('uart:0x10000000:ns16550a'), + ], + ); + expect(config.buildSoC(), throwsA(isA())); + }); + }); + + group('--board (HarborBoard wiring)', () { + RiverGenIpConfig cfg() => RiverGenIpConfig( + name: 'b', + cores: const ['rc1-s'], + boardName: 'arty-s7-50', + devices: [Device.parse('uart:0x10000000:ns16550a')], + ); + + test('board synthesises the target when --target is unset', () { + final t = cfg().effectiveTarget; + expect(t, isA()); + final f = t as FpgaTarget; + expect(f.vendor, 'spartan7'); // openXc7 board -> spartan7 target path + expect(f.device, 'xc7s50'); + expect(f.package, 'csga324'); + }); + + test('explicit --target wins over the board target', () { + final config = RiverGenIpConfig( + name: 'b', + cores: const ['rc1-s'], + boardName: 'arty-s7-50', + target: Target.parse('ecp5:lfe5u-25f:CSFBGA285'), + devices: [Device.parse('uart:0x10000000:ns16550a')], + ); + expect((config.effectiveTarget as FpgaTarget).vendor, 'ecp5'); + }); + + test('board catalog uart_tx binds to the uart device port', () { + final tx = cfg().effectivePins.firstWhere( + (p) => p.externalName == 'uart_tx', + ); + expect(tx.isDevicePin, isTrue); + expect(tx.deviceName, 'uart'); + expect(tx.portName, 'tx'); + }); + + test('board catalog clk is a simple (non-device) pin in fpgaPinMap', () { + final config = cfg(); + final clk = config.effectivePins.firstWhere( + (p) => p.externalName == 'clk', + ); + expect(clk.isDevicePin, isFalse); + expect(config.fpgaPinMap['clk'], startsWith('R2')); + }); + + test('explicit --pin overrides the board catalog entry', () { + final config = RiverGenIpConfig( + name: 'b', + cores: const ['rc1-s'], + boardName: 'arty-s7-50', + pins: [PinAssignment.parse('clk=Z99')], + devices: [Device.parse('uart:0x10000000:ns16550a')], + ); + expect(config.fpgaPinMap['clk'], 'Z99'); + }); + }); +} diff --git a/packages/river_hdl/test/fd/rv32_inorder_test.dart b/packages/river_hdl/test/fd/rv32_inorder_test.dart new file mode 100644 index 0000000..e7fc9be --- /dev/null +++ b/packages/river_hdl/test/fd/rv32_inorder_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'fd'; + const mxlen = RiscVMxlen.rv32; + const uarch = Uarch.inOrder; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/fd/rv64_inorder_test.dart b/packages/river_hdl/test/fd/rv64_inorder_test.dart new file mode 100644 index 0000000..dbcd603 --- /dev/null +++ b/packages/river_hdl/test/fd/rv64_inorder_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'fd'; + const mxlen = RiscVMxlen.rv64; + const uarch = Uarch.inOrder; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/fetch/core_multifetch_test.dart b/packages/river_hdl/test/fetch/core_multifetch_test.dart new file mode 100644 index 0000000..4ee4612 --- /dev/null +++ b/packages/river_hdl/test/fetch/core_multifetch_test.dart @@ -0,0 +1,212 @@ +import 'dart:async'; + +import 'package:rohd/rohd.dart'; +import 'package:rohd_hcl/rohd_hcl.dart' hide DataPortInterface, DataPortGroup; +import 'package:river/river.dart'; +import 'package:river_hdl/river_hdl.dart'; +import 'package:test/test.dart'; + +/// Increment 4 integration: drive the core's EXPOSED multiple-outstanding fetch +/// port (fetchReq_*/fetchRsp_*) from an external pipelined fetch memory, and +/// confirm (a) it executes correctly and (b) it hides fetch latency in-core, +/// recovering toward the alloc-cadence floor where the single-outstanding +/// prefetch fetcher sags. The external memory drives the handshake (async +/// pattern); the core makes no latency assumption. +void main() { + RiverCoreConfig mk({int fetchOutstanding = 1}) => RiverCoreConfig( + clock: HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ), + mxlen: RiscVMxlen.rv64, + extensions: [rv64i, rv32i, rvM, rvZicsr, rvZifencei], + interrupts: const [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + executionMode: ExecutionMode.outOfOrder, + speculativeFetch: true, + prefetchFetch: true, + prefetchDepth: fetchOutstanding > 1 ? 8 : 2, + fetchOutstanding: fetchOutstanding, + ); + + int iimm(int imm, int rs1, int f3, int rd) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x13; + + // 24 independent addi then a self-loop terminator (jal x0, 0) so the sim + // settles at nextPc once the 24th commits. + final program = [ + for (var i = 0; i < 24; i++) iimm((i & 0x3F) + 1, 0, 0x0, (i % 30) + 1), + 0x0000006F, // jal x0, 0 + ]; + const nextPc = 24 * 4; + + String memString(List words) { + final sb = StringBuffer('@0\n'); + for (final w in words) { + for (var b = 0; b < 4; b++) { + sb.write(((w >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + return sb.toString(); + } + + /// Run [config]. When [fetchLatency] != null the core's exposed fetch port is + /// driven by an external [PipelinedFetchMemory] at that read latency; else + /// fetch goes over the bus at [busLatency]. Returns cycles to reach nextPc. + Future run( + RiverCoreConfig config, { + int busLatency = 0, + int? fetchLatency, + }) async { + await Simulator.reset(); + final clk = SimpleClockGenerator(20).clk; + final reset = Logic(); + final aw = config.mxlen.size; + final wbConfig = WishboneConfig( + addressWidth: aw, + dataWidth: aw, + selWidth: aw ~/ 8, + ); + final core = RiverCore(config, busConfig: wbConfig); + core.input('clk').srcConnection! <= clk; + core.input('reset').srcConnection! <= reset; + + // External pipelined fetch memory on the exposed port (async-pattern). + if (fetchLatency != null) { + final link = FetchReadInterface(32, aw); + link.reqValid <= core.output('fetchReq_valid'); + link.reqAddr <= core.output('fetchReq_addr'); + core.input('fetchReq_ready').srcConnection! <= link.reqReady; + core.input('fetchRsp_valid').srcConnection! <= link.rspValid; + core.input('fetchRsp_data').srcConnection! <= link.rspData; + PipelinedFetchMemory( + clk, + reset, + link, + initWords: program, + words: 64, + readLatency: fetchLatency, + ); + } + + await core.build(); + + final storage = SparseMemoryStorage( + addrWidth: aw, + dataWidth: aw, + alignAddress: (addr) => addr, + onInvalidRead: (addr, dataWidth) => + LogicValue.filled(dataWidth, LogicValue.zero), + ); + final memRead = DataPortInterface(aw, aw); + final memWrite = DataPortInterface(aw, aw); + // ignore: unused_local_variable + final mem = MemoryModel( + clk, + reset, + [wrapWriteForRegisterFile(memWrite)], + [wrapReadForRegisterFile(memRead, clk: clk, readLatency: busLatency)], + readLatency: busLatency, + storage: storage, + ); + final wbCyc = core.output('dataBus_CYC'); + final wbStb = core.output('dataBus_STB'); + final wbWe = core.output('dataBus_WE'); + final wbAdr = core.output('dataBus_ADR'); + final wbDatMosi = core.output('dataBus_DAT_MOSI'); + memRead.en <= wbCyc & wbStb & ~wbWe; + memRead.addr <= wbAdr; + memWrite.en <= wbCyc & wbStb & wbWe; + memWrite.addr <= wbAdr; + memWrite.data <= wbDatMosi; + final wbAckReg = Logic(name: 'wbAck'); + final readyForAck = wbWe | memRead.valid; + Sequential(clk, [ + If( + reset, + then: [wbAckReg < 0], + orElse: [ + If( + wbCyc & wbStb & ~wbAckReg & readyForAck, + then: [wbAckReg < 1], + orElse: [wbAckReg < 0], + ), + ], + ), + ]); + core.input('dataBus_ACK').srcConnection! <= wbAckReg; + core.input('dataBus_DAT_MISO').srcConnection! <= memRead.data; + + reset.inject(1); + Simulator.registerAction(20, () { + reset.put(0); + storage.loadMemString(memString(program)); + }); + Simulator.setMaxSimTime(2000000); + unawaited(Simulator.run()); + await clk.nextPosedge; + while (reset.value.toBool()) { + await clk.nextPosedge; + } + var cycles = 0; + var reached = false; + for (var i = 0; i < 20000; i++) { + await clk.nextPosedge; + cycles++; + final pc = core.pipeline.nextPc.value; + if (pc.isValid && pc.toInt() == nextPc) { + reached = true; + break; + } + } + await Simulator.endSimulation(); + await Simulator.simulationEnded; + expect(reached, isTrue, reason: 'core did not reach nextPc'); + return cycles; + } + + tearDown(() async { + await Simulator.reset(); + }); + + // Correctness first: the exposed-port + external-memory path executes the + // program and reaches nextPc. + test( + 'multi-outstanding fetch executes correctly via the exposed port', + () async { + final c = await run(mk(fetchOutstanding: 3), fetchLatency: 2); + expect(c, greaterThan(0)); + }, + timeout: Timeout(Duration(seconds: 120)), + ); + + // In-core win: at a fetch latency, multi-outstanding (external pipelined + // memory) should beat the single-outstanding prefetch fetcher over the bus at + // the same latency, recovering toward the alloc floor. + test( + 'multi-outstanding fetch hides latency in-core', + () async { + const lat = 4; + final single = await run(mk(), busLatency: lat); // prefetch over bus + final multi = await run(mk(fetchOutstanding: 5), fetchLatency: lat); + // ignore: avoid_print + print( + '\n=== in-core fetch latency $lat: single-outstanding=$single cyc, ' + 'multi-outstanding=$multi cyc (${(single / multi).toStringAsFixed(2)}x) ===\n', + ); + expect( + multi, + lessThan(single), + reason: 'multi-outstanding should hide fetch latency in-core', + ); + }, + timeout: Timeout(Duration(seconds: 200)), + ); +} diff --git a/packages/river_hdl/test/fetch/core_prefetch_test.dart b/packages/river_hdl/test/fetch/core_prefetch_test.dart new file mode 100644 index 0000000..2c26189 --- /dev/null +++ b/packages/river_hdl/test/fetch/core_prefetch_test.dart @@ -0,0 +1,175 @@ +import 'package:river/river.dart'; +import 'package:rohd/rohd.dart'; +import 'package:test/test.dart'; + +import '../core_harness.dart'; + +/// Increment 2 of the prefetch fetcher: PrefetchFetchUnit wired into the +/// single-issue speculative OoO front-end (RiverCoreConfig.prefetchFetch = true). +/// This is the FAITHFUL test environment, the fetch port is the real MMU, whose +/// valid/done behave like the bus the read engine targets (unlike the standalone +/// unit test's MemoryModel). Re-runs representative speculative programs and +/// checks the architectural result matches the classic-fetcher runs in +/// core_ooo_test. See project_hdl_prefetch. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + RiverCoreConfig prefetchConfig() => RiverCoreConfig( + clock: HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ), + mxlen: RiscVMxlen.rv32, + extensions: [rv32i, rvZicsr, rvZifencei, rvM], + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv32, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + executionMode: ExecutionMode.outOfOrder, + commitWidth: IssueWidth.dual, + speculativeFetch: true, + prefetchFetch: true, + ); + + int iimm(int imm, int rs1, int f3, int rd) => + (imm << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x13; + int r(int f7, int rs2, int rs1, int f3, int rd) => + (f7 << 25) | (rs2 << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x33; + int b(int imm, int rs2, int rs1, int f3) => + (((imm >> 12) & 0x1) << 31) | + (((imm >> 5) & 0x3F) << 25) | + (rs2 << 20) | + (rs1 << 15) | + (f3 << 12) | + (((imm >> 1) & 0xF) << 8) | + (((imm >> 11) & 0x1) << 7) | + 0x63; + int jal(int imm, int rd) => + (((imm >> 20) & 0x1) << 31) | + (((imm >> 1) & 0x3FF) << 21) | + (((imm >> 11) & 0x1) << 20) | + (((imm >> 12) & 0xFF) << 12) | + (rd << 7) | + 0x6F; + String prog(List words) { + final sb = StringBuffer('@0\n'); + for (final w in words) { + for (var i = 0; i < 4; i++) { + sb.write(((w >> (i * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + return '$sb\n'; + } + + test( + 'prefetch: straight-line RAW chain forwards in-flight operands', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + iimm(1, 0, 0x0, 1), + iimm(1, 1, 0x0, 2), + iimm(1, 2, 0x0, 3), + iimm(1, 3, 0x0, 4), + iimm(1, 4, 0x0, 5), + ...List.filled(8, 0x00000013), + ]), + { + Register.x1: 1, + Register.x2: 2, + Register.x3: 3, + Register.x4: 4, + Register.x5: 5, + }, + prefetchConfig(), + nextPc: 0x34, + ), + ); + + test( + 'prefetch: speculative overlaps a multi-cycle mul with a backlog', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + iimm(6, 0, 0x0, 1), + iimm(7, 0, 0x0, 2), + r(0x01, 2, 1, 0x0, 3), // mul x3 = 42 (multi-cycle) + iimm(1, 1, 0x0, 4), + iimm(2, 1, 0x0, 5), + iimm(3, 1, 0x0, 6), + iimm(4, 1, 0x0, 7), + ...List.filled(8, 0x00000013), + ]), + { + Register.x1: 6, + Register.x2: 7, + Register.x3: 42, + Register.x4: 7, + Register.x5: 8, + Register.x6: 9, + Register.x7: 10, + }, + prefetchConfig(), + nextPc: 0x3C, + ), + ); + + test( + 'prefetch: counted loop (backward branch redirects)', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + iimm(3, 0, 0x0, 1), // 0x00 addi x1,x0,3 + iimm(0, 0, 0x0, 2), // 0x04 addi x2,x0,0 + iimm(1, 2, 0x0, 2), // 0x08 addi x2,x2,1 <- target + iimm(-1, 1, 0x0, 1), // 0x0C addi x1,x1,-1 + b(-8, 0, 1, 0x1), // 0x10 bne x1,x0,-8 + ...List.filled(11, 0x00000013), + ]), + {Register.x1: 0, Register.x2: 3}, + prefetchConfig(), + nextPc: 0x3C, + ), + ); + + test( + 'prefetch: taken branch redirects past the skipped instruction', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + iimm(5, 0, 0x0, 1), + iimm(5, 0, 0x0, 2), + b(8, 2, 1, 0x0), // beq taken -> 0x10 + iimm(99, 0, 0x0, 3), // SKIPPED + iimm(7, 0, 0x0, 4), // target @0x10 + ...List.filled(8, 0x00000013), + ]), + {Register.x1: 5, Register.x2: 5, Register.x3: 0, Register.x4: 7}, + prefetchConfig(), + nextPc: 0x34, + ), + ); + + test( + 'prefetch: JAL redirects and writes the link register', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + iimm(5, 0, 0x0, 1), // 0x00 + jal(8, 3), // 0x04 jal x3,+8 -> link 0x08, jump 0x0C + iimm(99, 0, 0x0, 4), // 0x08 SKIPPED + iimm(7, 0, 0x0, 2), // 0x0C target + ...List.filled(8, 0x00000013), + ]), + {Register.x1: 5, Register.x2: 7, Register.x3: 0x08, Register.x4: 0}, + prefetchConfig(), + nextPc: 0x30, + ), + ); +} diff --git a/packages/river_hdl/test/fpvector/core_fp_test.dart b/packages/river_hdl/test/fpvector/core_fp_test.dart new file mode 100644 index 0000000..4f01efc --- /dev/null +++ b/packages/river_hdl/test/fpvector/core_fp_test.dart @@ -0,0 +1,619 @@ +import 'package:rohd/rohd.dart'; +import 'package:river/river.dart'; +import 'package:test/test.dart'; +import '../core_harness.dart'; + +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + // F/D phase 1: the FP register file + load/store routing. flw loads a word + // into an FP register; fsw stores it back. A round-trip through memory proves + // the value went into (and came out of) the FP regfile (not the int one). + group('RC1.fd - F/D load/store (RV64)', () { + final config = RiverCoreConfig( + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + mxlen: RiscVMxlen.rv64, + extensions: [ + rv64i, + rv32i, + rvZicsr, + rvZifencei, + rvM, + rvA, + rvPriv, + rvF, + rvD, + rvFExtra, + rvDExtra, + ], + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + ); + + int iimm(int imm, int rs1, int f3, int rd) => + (imm << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x13; + int s(int imm, int rs2, int rs1, int f3, int op) => + (((imm >> 5) & 0x7F) << 25) | + (rs2 << 20) | + (rs1 << 15) | + (f3 << 12) | + ((imm & 0x1F) << 7) | + op; + int flw(int imm, int rs1, int rd) => + (imm << 20) | (rs1 << 15) | (0x2 << 12) | (rd << 7) | 0x07; + int fld(int imm, int rs1, int rd) => + (imm << 20) | (rs1 << 15) | (0x3 << 12) | (rd << 7) | 0x07; + int lui(int imm20, int rd) => (imm20 << 12) | (rd << 7) | 0x37; + int fop(int f7, int rs2, int rs1, int rm, int rd) => + (f7 << 25) | (rs2 << 20) | (rs1 << 15) | (rm << 12) | (rd << 7) | 0x53; + // R4-type FMA: rs3[31:27] | fmt[26:25] | rs2 | rs1 | rm | rd | opcode. + int fop4(int opcode, int rs3, int rs2, int rs1, int rd, {int fmt = 0}) => + (rs3 << 27) | + (fmt << 25) | + (rs2 << 20) | + (rs1 << 15) | + (rd << 7) | + opcode; + String prog(List words) { + final sb = StringBuffer('@0\n'); + for (final w in words) { + for (var b = 0; b < 4; b++) { + sb.write(((w >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + return '$sb\n'; + } + + test( + 'flw into FP reg, fsw back (round-trip via memory)', + timeout: Timeout(Duration(seconds: 300)), + () => coreTest( + prog([ + iimm(0x100, 0, 0x0, 10), // addi x10, x0, 0x100 (src) + iimm(0x200, 0, 0x0, 11), // addi x11, x0, 0x200 (dst) + iimm(0x7B, 0, 0x0, 5), // addi x5, x0, 0x7B + s(0, 5, 10, 0x2, 0x23), // sw x5, 0(x10) -> mem[0x100] = 0x7B + flw(0, 10, 1), // flw f1, 0(x10) -> f1 = 0x7B + s(0, 1, 11, 0x2, 0x27), // fsw f1, 0(x11) -> mem[0x200] = 0x7B + 0x00000013, // nop (halt target) + ]), + {Register.x10: 0x100, Register.x11: 0x200}, + config, + nextPc: 0x18, + memStates: {0x200: 0x7B}, + ), + ); + + test( + 'fadd.s / fsub.s / fmul.s (1.0, 2.0)', + timeout: Timeout(Duration(seconds: 300)), + () => coreTest( + prog([ + lui(0x3F800, 5), // x5 = 0x3F800000 (1.0f) + iimm(0x100, 0, 0x0, 10), // x10 = 0x100 + s(0, 5, 10, 0x2, 0x23), // sw x5, 0(x10) + flw(0, 10, 1), // flw f1, 0(x10) -> f1 = 1.0 + lui(0x40000, 6), // x6 = 0x40000000 (2.0f) + iimm(0x110, 0, 0x0, 11), // x11 = 0x110 + s(0, 6, 11, 0x2, 0x23), // sw x6, 0(x11) + flw(0, 11, 2), // flw f2, 0(x11) -> f2 = 2.0 + fop(0x00, 2, 1, 0, 3), // fadd.s f3, f1, f2 -> 3.0 + fop(0x08, 2, 2, 0, 4), // fmul.s f4, f2, f2 -> 4.0 + fop(0x04, 1, 2, 0, 5), // fsub.s f5, f2, f1 -> 1.0 + iimm(0x120, 0, 0x0, 12), // x12 = 0x120 + s(0, 3, 12, 0x2, 0x27), // fsw f3, 0(x12) -> mem = 3.0 + iimm(0x130, 0, 0x0, 13), // x13 = 0x130 + s(0, 4, 13, 0x2, 0x27), // fsw f4, 0(x13) -> mem = 4.0 + iimm(0x140, 0, 0x0, 14), // x14 = 0x140 + s(0, 5, 14, 0x2, 0x27), // fsw f5, 0(x14) -> mem = 1.0 + 0x00000013, // nop (halt target) + ]), + const {}, + config, + nextPc: 0x44, + memStates: { + 0x120: 0x40400000, // 3.0f + 0x130: 0x40800000, // 4.0f + 0x140: 0x3F800000, // 1.0f + }, + ), + ); + + test( + 'fsqrt.s (sqrt(4.0) = 2.0)', + timeout: Timeout(Duration(seconds: 300)), + () => coreTest( + prog([ + lui(0x40800, 5), // x5 = 0x40800000 (4.0f) + iimm(0x100, 0, 0x0, 10), // x10 = 0x100 + s(0, 5, 10, 0x2, 0x23), // sw x5, 0(x10) + flw(0, 10, 4), // flw f4, 0(x10) -> f4 = 4.0 + fop(0x2C, 0, 4, 0, 6), // fsqrt.s f6, f4 -> 2.0 + iimm(0x120, 0, 0x0, 12), // x12 = 0x120 + s(0, 6, 12, 0x2, 0x27), // fsw f6, 0(x12) -> mem = 2.0 + 0x00000013, // nop (halt target) + ]), + const {}, + config, + nextPc: 0x1C, + memStates: {0x120: 0x40000000}, // 2.0f + ), + ); + + // FP compares (feq/flt/fle) write 0/1 to an integer reg. The false case is + // verified by addi+7 (0+7=7) so it isn't confused with uninitialized 0 mem. + test( + 'feq.s / flt.s / fle.s (1.0 vs 2.0)', + timeout: Timeout(Duration(seconds: 300)), + () => coreTest( + prog([ + lui(0x3F800, 5), // x5 = 1.0f bits + iimm(0x100, 0, 0x0, 10), // x10 = 0x100 + s(0, 5, 10, 0x2, 0x23), // sw x5, 0(x10) + flw(0, 10, 1), // f1 = 1.0 + lui(0x40000, 6), // x6 = 2.0f bits + iimm(0x110, 0, 0x0, 11), // x11 = 0x110 + s(0, 6, 11, 0x2, 0x23), // sw x6, 0(x11) + flw(0, 11, 2), // f2 = 2.0 + fop(0x50, 1, 1, 0x2, 20), // feq.s x20, f1, f1 -> 1 + fop(0x50, 2, 1, 0x1, 21), // flt.s x21, f1, f2 -> 1 + fop(0x50, 1, 2, 0x1, 23), // flt.s x23, f2, f1 -> 0 + iimm(7, 23, 0x0, 24), // addi x24, x23, 7 -> 7 (proves x23==0) + iimm(0x120, 0, 0x0, 12), + s(0, 20, 12, 0x2, 0x23), // sw x20 -> 0x120 (1) + iimm(0x130, 0, 0x0, 13), + s(0, 21, 13, 0x2, 0x23), // sw x21 -> 0x130 (1) + iimm(0x140, 0, 0x0, 14), + s(0, 24, 14, 0x2, 0x23), // sw x24 -> 0x140 (7) + 0x00000013, // nop (halt target) + ]), + const {}, + config, + nextPc: 0x48, + memStates: {0x120: 1, 0x130: 1, 0x140: 7}, + ), + ); + + // fcvt int<->float (RTZ, matching the emulator golden model which truncates + // toward zero via Dart .toInt()). fcvt.s.w f7=0x68, fcvt.w.s f7=0x60. + test( + 'fcvt.s.w / fcvt.w.s (int<->float + truncation)', + timeout: Timeout(Duration(seconds: 300)), + () => coreTest( + prog([ + iimm(5, 0, 0x0, 5), // x5 = 5 + fop(0x68, 0, 5, 0, 1), // fcvt.s.w f1, x5 -> 5.0f + iimm(0x100, 0, 0x0, 10), + s(0, 1, 10, 0x2, 0x27), // fsw f1 -> 0x40A00000 + fop(0x60, 0, 1, 0, 6), // fcvt.w.s x6, f1 -> 5 + iimm(0x110, 0, 0x0, 11), + s(0, 6, 11, 0x2, 0x23), // sw x6 -> 5 + lui(0x40300, 7), // x7 = 2.75f bits + iimm(0x120, 0, 0x0, 12), + s(0, 7, 12, 0x2, 0x23), // sw x7, 0(x12) + flw(0, 12, 3), // flw f3 = 2.75f + fop(0x60, 0, 3, 1, 8), // fcvt.w.s x8, f3 (rm=1 RTZ) -> 2 + iimm(0x130, 0, 0x0, 13), + s(0, 8, 13, 0x2, 0x23), // sw x8 -> 2 + 0x00000013, // nop (halt target) + ]), + const {}, + config, + nextPc: 0x38, + memStates: {0x100: 0x40A00000, 0x110: 5, 0x130: 2}, + ), + ); + + // fcvt precision converts (single<->double) + int<->double. + test( + 'fcvt.d.s / fcvt.s.d / fcvt.w.d / fcvt.d.w', + timeout: Timeout(Duration(seconds: 300)), + () => coreTest( + prog([ + iimm(5, 0, 0x0, 5), // x5 = 5 + fop(0x68, 0, 5, 0, 1), // fcvt.s.w f1, x5 -> 5.0f + fop(0x21, 0, 1, 0, 4), // fcvt.d.s f4, f1 -> 5.0d + iimm(0x100, 0, 0x0, 10), + s(0, 4, 10, 0x3, 0x27), // fsd f4 -> 5.0d + fop(0x20, 1, 4, 0, 5), // fcvt.s.d f5, f4 -> 5.0f + iimm(0x110, 0, 0x0, 11), + s(0, 5, 11, 0x2, 0x27), // fsw f5 -> 0x40A00000 + fop(0x61, 0, 4, 0, 9), // fcvt.w.d x9, f4 -> 5 + iimm(0x120, 0, 0x0, 12), + s(0, 9, 12, 0x2, 0x23), // sw x9 -> 5 + fop(0x69, 0, 5, 0, 6), // fcvt.d.w f6, x5 -> 5.0d + iimm(0x130, 0, 0x0, 13), + s(0, 6, 13, 0x3, 0x27), // fsd f6 -> 5.0d + 0x00000013, // nop (halt target) + ]), + const {}, + config, + nextPc: 0x38, + memStates: { + 0x100: 0x4014000000000000, // 5.0d + 0x110: 0x40A00000, // 5.0f + 0x120: 5, + 0x130: 0x4014000000000000, // 5.0d + }, + ), + ); + + // fdiv.s multi-cycle Newton-Raphson (reuses one mul+add over ~10 cycles). + // Divisor 2.0 -> reciprocal seed is exact, so 6/2=3.0 and 7/2=3.5 are + // bit-exact. Inexact quotients (e.g. 1/3) are ~1 ULP off, the divider is + // functional, not bit-exact (no remainder-correction step), as chosen. + test( + 'fdiv.s (6.0/2.0=3.0, 7.0/2.0=3.5)', + timeout: Timeout(Duration(seconds: 180)), + () => coreTest( + prog([ + lui(0x40C00, 5), // x5 = 6.0f + iimm(0x100, 0, 0x0, 10), + s(0, 5, 10, 0x2, 0x23), // sw x5 + flw(0, 10, 1), // f1 = 6.0 + lui(0x40000, 6), // x6 = 2.0f + iimm(0x110, 0, 0x0, 11), + s(0, 6, 11, 0x2, 0x23), + flw(0, 11, 2), // f2 = 2.0 + fop(0x0C, 2, 1, 0, 3), // fdiv.s f3, f1, f2 -> 3.0 + iimm(0x120, 0, 0x0, 12), + s(0, 3, 12, 0x2, 0x27), // fsw f3 -> 0x40400000 + lui(0x40E00, 7), // x7 = 7.0f + iimm(0x130, 0, 0x0, 13), + s(0, 7, 13, 0x2, 0x23), + flw(0, 13, 4), // f4 = 7.0 + fop(0x0C, 2, 4, 0, 5), // fdiv.s f5, f4, f2 -> 3.5 + iimm(0x140, 0, 0x0, 14), + s(0, 5, 14, 0x2, 0x27), // fsw f5 -> 0x40600000 + 0x00000013, // nop (halt target) + ]), + const {}, + config, + nextPc: 0x48, + memStates: {0x120: 0x40400000, 0x140: 0x40600000}, + ), + ); + + // Double-precision: operands placed directly in memory (the harness keys + // each address as a 64-bit slot, so instruction-based dword construction is + // unreliable; placing the 8 bytes in the memString avoids that). + test( + 'fadd.d / fmul.d (1.0, 2.0 doubles from memory)', + timeout: Timeout(Duration(seconds: 300)), + () => coreTest( + '${prog([ + iimm(0x100, 0, 0x0, 10), // x10 = 0x100 + iimm(0x110, 0, 0x0, 11), // x11 = 0x110 + fld(0, 10, 1), // fld f1, 0(x10) -> 1.0 + fld(0, 11, 2), // fld f2, 0(x11) -> 2.0 + fop(0x01, 2, 1, 0, 3), // fadd.d f3, f1, f2 -> 3.0 + fop(0x09, 2, 2, 0, 4), // fmul.d f4, f2, f2 -> 4.0 + iimm(0x120, 0, 0x0, 12), // x12 = 0x120 + s(0, 3, 12, 0x3, 0x27), // fsd f3, 0(x12) + iimm(0x130, 0, 0x0, 13), // x13 = 0x130 + s(0, 4, 13, 0x3, 0x27), // fsd f4, 0(x13) + 0x00000013, // nop (halt target) + ])}@100\n00 00 00 00 00 00 f0 3f\n@110\n00 00 00 00 00 00 00 40\n', + const {}, + config, + nextPc: 0x28, + memStates: { + 0x120: 0x4008000000000000, // 3.0d + 0x130: 0x4010000000000000, // 4.0d + }, + ), + ); + + // Sign-injection, min/max, classify and raw move (single precision). + // f1 = 1.0 (0x3F800000), f2 = -2.0 (0xC0000000). + // fsgnj.s -> |f1| with sign(f2) = -1.0 (0xBF800000) + // fsgnjn.s -> |f1| with ~sign(f2) = 1.0 (0x3F800000) + // fsgnjx.s -> |f1| with sign(f1)^sign(f2) = -1.0 (0xBF800000) + // fmin.s -> -2.0 (0xC0000000) + // fmax.s -> 1.0 (0x3F800000) + // fclass.s(f1) -> +normal = bit6 = 0x40 + // fclass.s(f2) -> -normal = bit1 = 0x02 + // fmv.x.w(f1) -> raw bits 0x3F800000 + test( + 'fsgnj/fmin/fmax/fclass/fmv.x.w (single)', + timeout: Timeout(Duration(seconds: 300)), + () => coreTest( + prog([ + lui(0x3F800, 5), // x5 = 1.0f bits + iimm(0x100, 0, 0x0, 10), + s(0, 5, 10, 0x2, 0x23), + flw(0, 10, 1), // f1 = 1.0 + lui(0xC0000, 6), // x6 = -2.0f bits (0xC0000000) + iimm(0x110, 0, 0x0, 11), + s(0, 6, 11, 0x2, 0x23), + flw(0, 11, 2), // f2 = -2.0 + fop(0x10, 2, 1, 0x0, 3), // fsgnj.s f3 + fop(0x10, 2, 1, 0x1, 4), // fsgnjn.s f4 + fop(0x10, 2, 1, 0x2, 5), // fsgnjx.s f5 + fop(0x14, 2, 1, 0x0, 6), // fmin.s f6 + fop(0x14, 2, 1, 0x1, 7), // fmax.s f7 + fop(0x70, 0, 1, 0x1, 8), // fclass.s x8, f1 + fop(0x70, 0, 2, 0x1, 9), // fclass.s x9, f2 + fop(0x70, 0, 1, 0x0, 18), // fmv.x.w x18, f1 + iimm(0x120, 0, 0x0, 12), + s(0, 3, 12, 0x2, 0x27), // fsw f3 -> 0xBF800000 + iimm(0x130, 0, 0x0, 13), + s(0, 4, 13, 0x2, 0x27), // fsw f4 -> 0x3F800000 + iimm(0x140, 0, 0x0, 14), + s(0, 5, 14, 0x2, 0x27), // fsw f5 -> 0xBF800000 + iimm(0x150, 0, 0x0, 15), + s(0, 6, 15, 0x2, 0x27), // fsw f6 -> 0xC0000000 + iimm(0x160, 0, 0x0, 16), + s(0, 7, 16, 0x2, 0x27), // fsw f7 -> 0x3F800000 + iimm(0x170, 0, 0x0, 17), + s(0, 8, 17, 0x2, 0x23), // sw x8 -> 0x40 + iimm(0x180, 0, 0x0, 19), + s(0, 9, 19, 0x2, 0x23), // sw x9 -> 0x02 + iimm(0x190, 0, 0x0, 20), + s(0, 18, 20, 0x2, 0x23), // sw x18 -> 0x3F800000 + 0x00000013, // nop (halt target) + ]), + const {}, + config, + nextPc: 0x80, + memStates: { + 0x120: 0xBF800000, + 0x130: 0x3F800000, + 0x140: 0xBF800000, + 0x150: 0xC0000000, + 0x160: 0x3F800000, + 0x170: 0x40, + 0x180: 0x02, + 0x190: 0x3F800000, + }, + ), + ); + + // Sign-injection, min/max, classify (double precision). Operands placed in + // memory: f1 = 1.0d (0x3FF0000000000000), f2 = -2.0d (0xC000000000000000). + // fsgnj.d -> -1.0d (0xBFF0000000000000) + // fsgnjn.d -> 1.0d (0x3FF0000000000000) + // fsgnjx.d -> -1.0d (0xBFF0000000000000) + // fmin.d -> -2.0d (0xC000000000000000) + // fmax.d -> 1.0d (0x3FF0000000000000) + // fclass.d(f1) -> +normal = 0x40 ; fclass.d(f2) -> -normal = 0x02 + test( + 'fsgnj/fmin/fmax/fclass (double)', + timeout: Timeout(Duration(seconds: 300)), + () => coreTest( + '${prog([ + iimm(0x100, 0, 0x0, 10), + iimm(0x110, 0, 0x0, 11), + fld(0, 10, 1), // f1 = 1.0d + fld(0, 11, 2), // f2 = -2.0d + fop(0x11, 2, 1, 0x0, 3), // fsgnj.d f3 + fop(0x11, 2, 1, 0x1, 4), // fsgnjn.d f4 + fop(0x11, 2, 1, 0x2, 5), // fsgnjx.d f5 + fop(0x15, 2, 1, 0x0, 6), // fmin.d f6 + fop(0x15, 2, 1, 0x1, 7), // fmax.d f7 + fop(0x71, 0, 1, 0x1, 8), // fclass.d x8, f1 + fop(0x71, 0, 2, 0x1, 9), // fclass.d x9, f2 + iimm(0x120, 0, 0x0, 12), + s(0, 3, 12, 0x3, 0x27), // fsd f3 + iimm(0x130, 0, 0x0, 13), + s(0, 4, 13, 0x3, 0x27), // fsd f4 + iimm(0x140, 0, 0x0, 14), + s(0, 5, 14, 0x3, 0x27), // fsd f5 + iimm(0x150, 0, 0x0, 15), + s(0, 6, 15, 0x3, 0x27), // fsd f6 + iimm(0x160, 0, 0x0, 16), + s(0, 7, 16, 0x3, 0x27), // fsd f7 + iimm(0x170, 0, 0x0, 17), + s(0, 8, 17, 0x2, 0x23), // sw x8 + iimm(0x180, 0, 0x0, 19), + s(0, 9, 19, 0x2, 0x23), // sw x9 + 0x00000013, // nop (halt target) + ])}@100\n00 00 00 00 00 00 f0 3f\n@110\n00 00 00 00 00 00 00 c0\n', + const {}, + config, + nextPc: 0x64, + memStates: { + 0x120: 0xBFF0000000000000, + 0x130: 0x3FF0000000000000, + 0x140: 0xBFF0000000000000, + 0x150: 0xC000000000000000, + 0x160: 0x3FF0000000000000, + 0x170: 0x40, + 0x180: 0x02, + }, + ), + ); + + // 64-bit conversions (fcvt.l.s/.s.l/.l.d/.d.l), selected by rs2==2. + // fcvt.l.s: f7=0x60 rs2=2 ; fcvt.s.l: f7=0x68 rs2=2 + // fcvt.l.d: f7=0x61 rs2=2 ; fcvt.d.l: f7=0x69 rs2=2 + // Use a value > 2^31 to prove the 64-bit (not 32-bit) path: 0x1_0000_0000 + // (2^32) as a double round-trips int64<->f64; and 5 round-trips int64<->f32. + test( + 'fcvt.l.s / fcvt.s.l / fcvt.l.d / fcvt.d.l (signed 64-bit)', + timeout: Timeout(Duration(seconds: 300)), + () => coreTest( + prog([ + iimm(5, 0, 0x0, 5), // x5 = 5 + fop(0x68, 2, 5, 0, 1), // fcvt.s.l f1, x5 -> 5.0f + iimm(0x100, 0, 0x0, 10), + s(0, 1, 10, 0x2, 0x27), // fsw f1 -> 0x40A00000 + fop(0x60, 2, 1, 0, 6), // fcvt.l.s x6, f1 -> 5 + iimm(0x110, 0, 0x0, 11), + s(0, 6, 11, 0x2, 0x23), // sw x6 -> 5 + fop(0x69, 2, 5, 0, 2), // fcvt.d.l f2, x5 -> 5.0d + iimm(0x120, 0, 0x0, 12), + s(0, 2, 12, 0x3, 0x27), // fsd f2 -> 5.0d + fop(0x61, 2, 2, 0, 7), // fcvt.l.d x7, f2 -> 5 + iimm(0x130, 0, 0x0, 13), + s(0, 7, 13, 0x2, 0x23), // sw x7 -> 5 + 0x00000013, // nop (halt target) + ]), + const {}, + config, + nextPc: 0x34, + memStates: { + 0x100: 0x40A00000, // 5.0f + 0x110: 5, + 0x120: 0x4014000000000000, // 5.0d + 0x130: 5, + }, + ), + ); + + // Unsigned fcvt (rs2 bit0 set): fcvt.s.wu/.s.lu interpret the source as + // unsigned; fcvt.wu.s/.lu.s clamp a negative float to 0. Values stay in + // range (saturation at >= 2^w is a documented follow-up). + // x5 = -1 (low32 = 0xFFFFFFFF, full = u64 max), x6 = -5. + // fcvt.s.wu f1, x5 -> 4294967296.0f (unsigned 0xFFFFFFFF, NOT -1.0) + // fcvt.s.w f2, x6 -> -5.0f ; fcvt.wu.s x7, f2 -> 0 (neg clamp) + // fcvt.s.lu f3, x5 -> 1.8e19f (u64 max) ; fcvt.lu.s x8, f2 -> 0 + test( + 'fcvt unsigned: s.wu / wu.s / s.lu / lu.s (rs2 bit0)', + timeout: Timeout(Duration(seconds: 300)), + () => coreTest( + prog([ + iimm(0xFFF, 0, 0x0, 5), // x5 = -1 + iimm(0xFFB, 0, 0x0, 6), // x6 = -5 + fop(0x68, 1, 5, 0, 1), // fcvt.s.wu f1, x5 -> 4294967296.0f + iimm(0x100, 0, 0x0, 10), + s(0, 1, 10, 0x2, 0x27), // fsw f1 -> 0x4F800000 + fop(0x68, 0, 6, 0, 2), // fcvt.s.w f2, x6 -> -5.0f + fop(0x60, 1, 2, 0, 7), // fcvt.wu.s x7, f2 -> 0 + iimm(0x110, 0, 0x0, 11), + s(0, 7, 11, 0x2, 0x23), // sw x7 -> 0 + fop(0x68, 3, 5, 0, 3), // fcvt.s.lu f3, x5 -> 1.8e19f + iimm(0x120, 0, 0x0, 12), + s(0, 3, 12, 0x2, 0x27), // fsw f3 -> 0x5F800000 + fop(0x60, 3, 2, 0, 8), // fcvt.lu.s x8, f2 -> 0 + iimm(0x130, 0, 0x0, 13), + s(0, 8, 13, 0x2, 0x23), // sw x8 -> 0 + 0x00000013, // nop (halt target) + ]), + const {}, + config, + nextPc: 0x3C, + memStates: { + 0x100: 0x4F800000, // 2^32 as f32 (unsigned 0xFFFFFFFF rounds up) + 0x110: 0, // fcvt.wu.s(-5.0) clamps to 0 + 0x120: 0x5F800000, // 2^64 as f32 (u64 max) + 0x130: 0, // fcvt.lu.s(-5.0) clamps to 0 + }, + ), + ); + + // Fused multiply-add (R4-type). a=2, b=3, c=4 (built via fcvt.s.w): + // fmadd = a*b + c = 10.0 (0x41200000) + // fmsub = a*b - c = 2.0 (0x40000000) + // fnmsub = -(a*b)+ c = -2.0 (0xC0000000) + // fnmadd = -(a*b)- c = -10.0 (0xC1200000) + test( + 'FMA: fmadd.s / fmsub.s / fnmsub.s / fnmadd.s', + timeout: Timeout(Duration(seconds: 300)), + () => coreTest( + prog([ + iimm(2, 0, 0x0, 5), iimm(3, 0, 0x0, 6), iimm(4, 0, 0x0, 7), + fop(0x68, 0, 5, 0, 1), // f1 = 2.0 + fop(0x68, 0, 6, 0, 2), // f2 = 3.0 + fop(0x68, 0, 7, 0, 3), // f3 = 4.0 + fop4(0x43, 3, 2, 1, 8), // fmadd.s f8 -> 10.0 + iimm(0x100, 0, 0x0, 10), + s(0, 8, 10, 0x2, 0x27), + fop4(0x47, 3, 2, 1, 9), // fmsub.s f9 -> 2.0 + iimm(0x110, 0, 0x0, 11), + s(0, 9, 11, 0x2, 0x27), + fop4(0x4B, 3, 2, 1, 12), // fnmsub.s f12 -> -2.0 + iimm(0x120, 0, 0x0, 13), + s(0, 12, 13, 0x2, 0x27), + fop4(0x4F, 3, 2, 1, 14), // fnmadd.s f14 -> -10.0 + iimm(0x130, 0, 0x0, 15), + s(0, 14, 15, 0x2, 0x27), + 0x00000013, // nop (halt target) + ]), + const {}, + config, + nextPc: 0x48, + memStates: { + 0x100: 0x41200000, // 10.0 + 0x110: 0x40000000, // 2.0 + 0x120: 0xC0000000, // -2.0 + 0x130: 0xC1200000, // -10.0 + }, + ), + ); + + // Double-precision FMA: a=2, b=3, c=4 via fcvt.d.w. fmadd.d -> 10.0d. + test( + 'FMA double: fmadd.d (fmt=1)', + timeout: Timeout(Duration(seconds: 300)), + () => coreTest( + prog([ + iimm(2, 0, 0x0, 5), iimm(3, 0, 0x0, 6), iimm(4, 0, 0x0, 7), + fop(0x69, 0, 5, 0, 1), // fcvt.d.w f1 = 2.0d + fop(0x69, 0, 6, 0, 2), // fcvt.d.w f2 = 3.0d + fop(0x69, 0, 7, 0, 3), // fcvt.d.w f3 = 4.0d + fop4(0x43, 3, 2, 1, 8, fmt: 1), // fmadd.d f8 -> 10.0d + iimm(0x100, 0, 0x0, 10), + s(0, 8, 10, 0x3, 0x27), // fsd f8 -> 10.0d + 0x00000013, // nop + ]), + const {}, + config, + nextPc: 0x24, + memStates: { + 0x100: 0x4024000000000000, // 10.0d + }, + ), + ); + + // fcvt.w.s rounding modes + saturation. f1 = 2.5f (0x40200000): + // rm=0 RNE -> 2 (ties to even), rm=3 RUP -> 3. + // f2 = 2^31 (0x4F000000) overflows signed-32 -> saturates to 0x7FFFFFFF. + test( + 'fcvt.w.s rm rounding (2.5) + saturation (2^31)', + timeout: Timeout(Duration(seconds: 300)), + () => coreTest( + prog([ + lui(0x40200, 5), // x5 = 2.5f bits + iimm(0x100, 0, 0x0, 10), + s(0, 5, 10, 0x2, 0x23), // mem[0x100] = 2.5f + flw(0, 10, 1), // f1 = 2.5f + fop(0x60, 0, 1, 0, 6), // fcvt.w.s rm=0 RNE -> 2 + iimm(0x110, 0, 0x0, 11), + s(0, 6, 11, 0x2, 0x23), + fop(0x60, 0, 1, 3, 7), // fcvt.w.s rm=3 RUP -> 3 + iimm(0x120, 0, 0x0, 12), + s(0, 7, 12, 0x2, 0x23), + lui(0x4F000, 13), // x13 = 2^31 f32 bits + iimm(0x130, 0, 0x0, 14), + s(0, 13, 14, 0x2, 0x23), // mem[0x130] = 2^31 bits + flw(0, 14, 2), // f2 = 2^31 + fop(0x60, 0, 2, 1, 8), // fcvt.w.s saturates -> 0x7FFFFFFF + iimm(0x140, 0, 0x0, 15), + s(0, 8, 15, 0x2, 0x23), + 0x00000013, // nop + ]), + const {}, + config, + nextPc: 0x44, + memStates: { + 0x110: 2, // RNE(2.5) -> 2 + 0x120: 3, // RUP(2.5) -> 3 + 0x140: 0x7FFFFFFF, // 2^31 saturates + }, + ), + ); + }); +} diff --git a/packages/river_hdl/test/fpvector/core_vector_test.dart b/packages/river_hdl/test/fpvector/core_vector_test.dart new file mode 100644 index 0000000..bf1bc5f --- /dev/null +++ b/packages/river_hdl/test/fpvector/core_vector_test.dart @@ -0,0 +1,565 @@ +import 'dart:typed_data'; + +import 'package:river/river.dart'; +import 'package:rohd/rohd.dart'; +import 'package:test/test.dart'; + +import '../core_harness.dart'; + +/// Vector (V extension) datapath bring-up. The HDL had no vector support; this +/// builds it incrementally against Harbor's rv_v op set, mirroring the +/// emulator's vector engine. See project_vector / project_parity in memory. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + RiverCoreConfig vecConfig() => RiverCoreConfig( + clock: HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ), + mxlen: RiscVMxlen.rv64, + extensions: [rv64i, rv32i, rvZicsr, rvZifencei, rvV], + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + vlen: 128, + ); + + // Same as vecConfig but with Zvfh (SEW=16 half-precision vector FP). Only the + // FP16 test uses this so the rest of the suite skips the extra FP16 lane units. + RiverCoreConfig vecConfigZvfh() => RiverCoreConfig( + clock: HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ), + mxlen: RiscVMxlen.rv64, + extensions: [rv64i, rv32i, rvZicsr, rvZifencei, rvV, rvZvfh], + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + vlen: 128, + ); + + int iimm(int imm, int rs1, int f3, int rd) => + (imm << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x13; + // vsetvli rd, rs1, vtypei (opcode 0x57, funct3=7 OPCFG; vtypei in bits[30:20]) + int vsetvli(int vtypei, int rs1, int rd) => + (vtypei << 20) | (rs1 << 15) | (0x7 << 12) | (rd << 7) | 0x57; + // vle32.v vd, (rs1): opcode 0x07, width(funct3)=6, vm=1, lumop=0. + int vle32(int rs1, int vd) => + (1 << 25) | (rs1 << 15) | (0x6 << 12) | (vd << 7) | 0x07; + // vse32.v vs3, (rs1): opcode 0x27, width=6, vm=1. + int vse32(int rs1, int vs3) => + (1 << 25) | (rs1 << 15) | (0x6 << 12) | (vs3 << 7) | 0x27; + // OPIVV integer op vd, vs2, vs1: opcode 0x57, funct3=0, vm=1, given funct6. + int vopivv(int funct6, int vs2, int vs1, int vd) => + (funct6 << 26) | (1 << 25) | (vs2 << 20) | (vs1 << 15) | (vd << 7) | 0x57; + // OPFVV FP op vd, vs2, vs1: funct3=1, vm=1, given funct6 (add=0, mul=0x24). + int vopfvv(int funct6, int vs2, int vs1, int vd) => + (funct6 << 26) | + (1 << 25) | + (vs2 << 20) | + (vs1 << 15) | + (0x1 << 12) | + (vd << 7) | + 0x57; + int vaddvv(int vs2, int vs1, int vd) => vopivv(0x00, vs2, vs1, vd); + // vadd.vx vd, vs2, rs1: funct3=4 (OPIVX), funct6=0, vm=1. + int vaddvx(int vs2, int rs1, int vd) => + (1 << 25) | (vs2 << 20) | (rs1 << 15) | (0x4 << 12) | (vd << 7) | 0x57; + // vadd.vi vd, vs2, imm5: funct3=3 (OPIVI), funct6=0, vm=1. + int vaddvi(int vs2, int imm5, int vd) => + (1 << 25) | + (vs2 << 20) | + ((imm5 & 0x1F) << 15) | + (0x3 << 12) | + (vd << 7) | + 0x57; + String prog(List words) { + final sb = StringBuffer('@0\n'); + for (final w in words) { + for (var b = 0; b < 4; b++) { + sb.write(((w >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + return '$sb\n'; + } + + // Milestone 1: vsetvli sets vl = min(AVL, VLMAX) and writes it to rd. + // e32,m1 with VLEN=128 -> VLMAX = 128/32 = 4. AVL=8 -> vl=4. + // Milestone 1: vsetvli computes vl = min(AVL, VLMAX) into rd. + test( + 'vsetvli computes vl into rd (e32,m1, VLEN=128 -> vl=4)', + timeout: Timeout(Duration(seconds: 120)), + () => coreTest( + prog([ + iimm(8, 0, 0x0, 2), // addi x2, x0, 8 (AVL = 8) + vsetvli(0x10, 2, 1), // vsetvli x1, x2, e32,m1 -> x1 = vl = 4 + 0x00000013, // nop (halt target) + ]), + {Register.x1: 4, Register.x2: 8}, + vecConfig(), + nextPc: 0x0C, + ), + ); + + // vsetvli with rs1=x0 (and rd!=x0) sets vl = VLMAX (not 0). The old code read + // AVL from x0 = 0 and produced vl=0; the spec says rs1=x0 means "give me VLMAX". + test( + 'vsetvli rs1=x0 sets vl=VLMAX (e32,m1 -> 4)', + timeout: Timeout(Duration(seconds: 120)), + () => coreTest( + prog([ + vsetvli(0x10, 0, 1), // vsetvli x1, x0, e32,m1 -> vl = VLMAX = 4 + 0x00000013, // nop (halt target) + ]), + {Register.x1: 4}, + vecConfig(), + nextPc: 0x08, + ), + ); + + // Fractional LMUL: e32,mf2 (VLEN=128) -> VLMAX = (128/32)/2 = 2. The old code + // shifted left by vlmul=7 giving a bogus huge VLMAX; now it shifts right. + test( + 'vsetvli fractional LMUL mf2 (e32,mf2 -> vl=2)', + timeout: Timeout(Duration(seconds: 120)), + () => coreTest( + prog([ + iimm(8, 0, 0x0, 2), // addi x2, x0, 8 (AVL = 8) + vsetvli(0x17, 2, 1), // vsetvli x1, x2, e32,mf2 -> vl = min(8, 2) = 2 + 0x00000013, // nop (halt target) + ]), + {Register.x1: 2, Register.x2: 8}, + vecConfig(), + nextPc: 0x0C, + ), + ); + + // Milestone 2a: vle32.v / vse32.v round-trip through the vector register file + // (loads the low mxlen-wide chunk of a vreg). Proves the vreg file + vector + // load/store path without needing element arithmetic. + test( + 'vle32.v + vse32.v round-trip through a vreg', + timeout: Timeout(Duration(seconds: 120)), + () => coreTest( + '${prog([ + iimm(0x100, 0, 0x0, 10), // addi x10, x0, 0x100 (src) + iimm(0x200, 0, 0x0, 11), // addi x11, x0, 0x200 (dst) + vle32(10, 1), // vle32.v v1, (x10) v1 = mem[0x100] + vse32(11, 1), // vse32.v v1, (x11) mem[0x200] = v1 + 0x00000013, // nop (halt target) + ])}@100\nbe ba fe ca ef be ad de\n', + {Register.x10: 0x100, Register.x11: 0x200}, + vecConfig(), + nextPc: 0x14, + memStates: {0x200: 0xDEADBEEFCAFEBABE}, + ), + ); + + // Milestone 2b: vadd.vv element-wise add (SEW=32). Load two vregs, add, store. + // v1=[10,20], v2=[100,200] -> v3=[110,220]; stored low 64 = 220<<32 | 110. + test( + 'vadd.vv element-wise add (e32: [10,20]+[100,200]=[110,220])', + timeout: Timeout(Duration(seconds: 120)), + () => coreTest( + '${prog([ + iimm(0x100, 0, 0x0, 10), // x10 = 0x100 (v1 src) + iimm(0x110, 0, 0x0, 11), // x11 = 0x110 (v2 src) + iimm(0x200, 0, 0x0, 12), // x12 = 0x200 (dst) + vle32(10, 1), // v1 = [10, 20] + vle32(11, 2), // v2 = [100, 200] + vaddvv(1, 2, 3), // v3 = v1 + v2 = [110, 220] + vse32(12, 3), // mem[0x200] = v3 + 0x00000013, // nop (halt target) + ])}@100\n0a 00 00 00 14 00 00 00\n@110\n64 00 00 00 c8 00 00 00\n', + const {}, + vecConfig(), + nextPc: 0x20, + memStates: {0x200: 0x000000DC0000006E}, // [110, 220] + ), + ); + + // Milestone 2c: the rest of OPIVV integer arithmetic, vsub (per-lane borrow) + // and vxor (full-width bitwise). v1=[100,200], v2=[10,20]. + test( + 'vsub.vv / vxor.vv (e32)', + timeout: Timeout(Duration(seconds: 120)), + () => coreTest( + '${prog([ + iimm(0x100, 0, 0x0, 10), // v1 src + iimm(0x110, 0, 0x0, 11), // v2 src + iimm(0x200, 0, 0x0, 12), // vsub dst + iimm(0x210, 0, 0x0, 13), // vxor dst + vle32(10, 1), // v1 = [100, 200] + vle32(11, 2), // v2 = [10, 20] + vopivv(0x02, 1, 2, 3), // vsub.vv v3, v1, v2 -> [90, 180] + vopivv(0x0B, 1, 2, 4), // vxor.vv v4, v1, v2 -> [110, 220] + vse32(12, 3), + vse32(13, 4), + 0x00000013, // nop (halt target) + ])}@100\n64 00 00 00 c8 00 00 00\n@110\n0a 00 00 00 14 00 00 00\n', + const {}, + vecConfig(), + nextPc: 0x2C, + memStates: { + 0x200: 0x000000B40000005A, // vsub: [90, 180] + 0x210: 0x000000DC0000006E, // vxor: [110, 220] + }, + ), + ); + + // Milestone 2e: LMUL=2 grouping. vsetvli e32,m2 (VLEN=128) -> VLMAX=8, AVL=8 + // -> vl=8. vadd.vv with LMUL=2 spans two consecutive vregs: v6=v2+v4 and + // v7=v3+v5. The harness vle/vse only touch the low 64 bits (2 e32 lanes) per + // reg, so observing v7's store proves the register-index loop ran the second + // register (without grouping v7 would keep its loaded [5,6]). + test( + 'vadd.vv LMUL=2 spans two vregs (v6=v2+v4, v7=v3+v5)', + timeout: Timeout(Duration(seconds: 120)), + () => coreTest( + '${prog([ + iimm(0x100, 0, 0x0, 10), // v2 src low [1,2] + iimm(0x108, 0, 0x0, 11), // v3 src low [5,6] + iimm(0x110, 0, 0x0, 12), // v4 src low [10,20] + iimm(0x118, 0, 0x0, 13), // v5 src low [50,60] + iimm(8, 0, 0x0, 14), // x14 = AVL = 8 + iimm(0x200, 0, 0x0, 15), // v6 dst + iimm(0x208, 0, 0x0, 16), // v7 dst + vle32(10, 2), // v2 = [1, 2] + vle32(11, 3), // v3 = [5, 6] + vle32(12, 4), // v4 = [10, 20] + vle32(13, 5), // v5 = [50, 60] + vsetvli(0x11, 14, 1), // vsetvli x1, x14, e32,m2 -> x1 = vl = 8 + vaddvv(2, 4, 6), // vadd.vv v6, v2, v4 (LMUL=2) + vse32(15, 6), // mem[0x200] = v6 = [11, 22] + vse32(16, 7), // mem[0x208] = v7 = [55, 66] + 0x00000013, // nop (halt target) + ])}@100\n01 00 00 00 02 00 00 00 05 00 00 00 06 00 00 00 0a 00 00 00 14 00 00 00 32 00 00 00 3c 00 00 00\n', + const {Register.x1: 8}, + vecConfig(), + nextPc: 0x3C, + memStates: { + 0x200: 0x000000160000000B, // v6 = [11, 22] + 0x208: 0x0000004200000037, // v7 = [55, 66] + }, + ), + ); + + // Milestone 2g: LMUL=2 group load/store. One vle32.v (m2) fills v2,v3 from + // 32 contiguous bytes; one vse32.v (m2) writes both back. Round-trips all 8 + // e32 elements across the two-register group in single instructions. + test( + 'vle32.v + vse32.v LMUL=2 group round-trip (v2,v3)', + timeout: Timeout(Duration(seconds: 120)), + () => coreTest( + '${prog([ + iimm(0x100, 0, 0x0, 10), // src + iimm(0x200, 0, 0x0, 11), // dst + iimm(8, 0, 0x0, 12), // AVL = 8 + vsetvli(0x11, 12, 1), // e32, m2 -> vl = 8 + vle32(10, 2), // v2,v3 = mem[0x100..0x11F] + vse32(11, 2), // mem[0x200..0x21F] = v2,v3 + 0x00000013, // nop + ])}@100\n11 00 00 00 22 00 00 00 33 00 00 00 44 00 00 00 55 00 00 00 66 00 00 00 77 00 00 00 88 00 00 00\n', + const {Register.x1: 8}, + vecConfig(), + nextPc: 0x18, + memStates: { + 0x200: 0x0000002200000011, // v2 low + 0x208: 0x0000004400000033, // v2 high + 0x210: 0x0000006600000055, // v3 low + 0x218: 0x0000008800000077, // v3 high + }, + ), + ); + + // Milestone 2f: LMUL=2 grouping for FP. vfadd.vv at e32,m2 spans v6=v2+v4 and + // v7=v3+v5. Floats: v2=[1.0,2.0], v3=[5.0,6.0], v4=[10.0,20.0], v5=[50.0,60.0] + // -> v6=[11.0,22.0], v7=[55.0,66.0]. IEEE-754 single bit patterns. + int f32(double d) { + final bd = ByteData(4)..setFloat32(0, d); + return bd.getUint32(0); + } + + test( + 'vfadd.vv LMUL=2 spans two vregs (v6=v2+v4, v7=v3+v5)', + timeout: Timeout(Duration(seconds: 120)), + () => coreTest( + '${prog([ + iimm(0x100, 0, 0x0, 10), // v2 src [1.0, 2.0] + iimm(0x108, 0, 0x0, 11), // v3 src [5.0, 6.0] + iimm(0x110, 0, 0x0, 12), // v4 src [10.0, 20.0] + iimm(0x118, 0, 0x0, 13), // v5 src [50.0, 60.0] + iimm(8, 0, 0x0, 14), // x14 = AVL = 8 + iimm(0x200, 0, 0x0, 15), // v6 dst + iimm(0x208, 0, 0x0, 16), // v7 dst + vle32(10, 2), + vle32(11, 3), + vle32(12, 4), + vle32(13, 5), + vsetvli(0x11, 14, 1), // e32, m2 -> vl = 8 + vopfvv(0x00, 2, 4, 6), // vfadd.vv v6, v2, v4 (LMUL=2) + vse32(15, 6), // mem[0x200] = v6 = [11.0, 22.0] + vse32(16, 7), // mem[0x208] = v7 = [55.0, 66.0] + 0x00000013, // nop + ])}@100\n' + '${[1.0, 2.0, 5.0, 6.0, 10.0, 20.0, 50.0, 60.0].map((d) { + final v = f32(d); + return List.generate(4, (b) => ((v >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')).join(' '); + }).join(' ')}\n', + const {Register.x1: 8}, + vecConfig(), + nextPc: 0x3C, + memStates: { + 0x200: (f32(22.0) << 32) | f32(11.0), // v6 = [11.0, 22.0] + 0x208: (f32(66.0) << 32) | f32(55.0), // v7 = [55.0, 66.0] + }, + ), + ); + + // Milestone 2d: vadd.vx (scalar broadcast) and vadd.vi (immediate broadcast). + // v1=[100,200]; +x5(=5) -> [105,205]; +imm(3) -> [103,203]. + test( + 'vadd.vx / vadd.vi (scalar + immediate operands)', + timeout: Timeout(Duration(seconds: 120)), + () => coreTest( + '${prog([ + iimm(0x100, 0, 0x0, 10), // v1 src + iimm(5, 0, 0x0, 5), // x5 = 5 (scalar) + iimm(0x200, 0, 0x0, 12), // .vx dst + iimm(0x210, 0, 0x0, 13), // .vi dst + vle32(10, 1), // v1 = [100, 200] + vaddvx(1, 5, 2), // vadd.vx v2, v1, x5 -> [105, 205] + vaddvi(1, 3, 3), // vadd.vi v3, v1, 3 -> [103, 203] + vse32(12, 2), + vse32(13, 3), + 0x00000013, // nop (halt target) + ])}@100\n64 00 00 00 c8 00 00 00\n', + const {}, + vecConfig(), + nextPc: 0x28, + memStates: { + 0x200: 0x000000CD00000069, // [105, 205] + 0x210: 0x000000CB00000067, // [103, 203] + }, + ), + ); + + // Milestone 3: vfadd.vv / vfmul.vv, per-32-bit-lane FP via the ROHD-HCL units. + // v1=[1.0,2.0], v2=[3.0,4.0]; add -> [4.0,6.0]; mul -> [3.0,8.0]. + test( + 'vfadd.vv / vfmul.vv (e32 float lanes)', + timeout: Timeout(Duration(seconds: 180)), + () => coreTest( + '${prog([ + iimm(0x100, 0, 0x0, 10), // v1 src + iimm(0x110, 0, 0x0, 11), // v2 src + iimm(0x200, 0, 0x0, 12), // vfadd dst + iimm(0x210, 0, 0x0, 13), // vfmul dst + vle32(10, 1), // v1 = [1.0, 2.0] + vle32(11, 2), // v2 = [3.0, 4.0] + vopfvv(0x00, 1, 2, 3), // vfadd.vv v3, v1, v2 -> [4.0, 6.0] + vopfvv(0x24, 1, 2, 4), // vfmul.vv v4, v1, v2 -> [3.0, 8.0] + vse32(12, 3), + vse32(13, 4), + 0x00000013, // nop (halt target) + ])}@100\n00 00 80 3f 00 00 00 40\n@110\n00 00 40 40 00 00 80 40\n', + const {}, + vecConfig(), + nextPc: 0x2C, + memStates: { + 0x200: 0x40C0000040800000, // [4.0, 6.0] + 0x210: 0x4100000040400000, // [3.0, 8.0] + }, + ), + ); + + // Milestone 4 (polish): SEW-generic arithmetic driven by vsetvli's vtype. + // vsetvli e32, then vadd with byte-overflowing values: [200,100]+[100,200]= + // [300,300]. At SEW=8 (wrong) the low bytes would wrap to [44,44]; at SEW=32 + // (set by vsetvli) the 32-bit lanes give [300,300], proving vtype drives SEW. + test( + 'SEW-generic: vsetvli e32 makes vadd use 32-bit lanes (300, not 44)', + timeout: Timeout(Duration(seconds: 120)), + () => coreTest( + '${prog([ + iimm(0x100, 0, 0x0, 10), // v1 src + iimm(0x110, 0, 0x0, 11), // v2 src + iimm(0x200, 0, 0x0, 12), // dst + iimm(4, 0, 0x0, 1), // x1 = AVL + vsetvli(0x10, 1, 0), // vsetvli x0, x1, e32 -> _vtype = e32 + vle32(10, 1), // v1 = [200, 100] + vle32(11, 2), // v2 = [100, 200] + vaddvv(1, 2, 3), // v3 = v1 + v2 = [300, 300] (32-bit lanes) + vse32(12, 3), + 0x00000013, // nop (halt target) + ])}@100\nc8 00 00 00 64 00 00 00\n@110\n64 00 00 00 c8 00 00 00\n', + const {}, + vecConfig(), + nextPc: 0x28, + memStates: {0x200: 0x0000012C0000012C}, // [300, 300] + ), + ); + + // Milestone 4b (polish): full-VLEN load/store, the whole 128-bit vreg (both + // 64-bit chunks), not just the low chunk. Round-trip 4 e32 elements. + test( + 'vle32.v + vse32.v full-VLEN round-trip (4 elements / 128 bits)', + timeout: Timeout(Duration(seconds: 120)), + () => coreTest( + '${prog([ + iimm(0x100, 0, 0x0, 10), // src + iimm(0x200, 0, 0x0, 11), // dst + vle32(10, 1), // v1 = mem[0x100..0x10F] (128 bits) + vse32(11, 1), // mem[0x200..0x20F] = v1 + 0x00000013, // nop (halt target) + ])}@100\n11 11 11 11 22 22 22 22 33 33 33 33 44 44 44 44\n', + {Register.x10: 0x100, Register.x11: 0x200}, + vecConfig(), + nextPc: 0x14, + memStates: { + 0x200: 0x2222222211111111, // chunk0: elements 0,1 + 0x208: 0x4444444433333333, // chunk1: elements 2,3 + }, + ), + ); + + // Milestone 4c (polish): vl/tail. vsetvli e32 with AVL=2 -> vl=2, so vadd + // writes only lanes 0,1 (=v1+v2) and leaves lanes 2,3 (the tail) undisturbed + //, i.e. the preloaded v3 values survive. + test( + 'vl/tail: vadd with vl=2 leaves the tail (lanes 2,3) undisturbed', + timeout: Timeout(Duration(seconds: 120)), + () => coreTest( + '${prog([ + iimm(0x120, 0, 0x0, 9), // x9 = v3 preload src + iimm(0x100, 0, 0x0, 10), // x10 = v1 src + iimm(0x110, 0, 0x0, 11), // x11 = v2 src + iimm(0x200, 0, 0x0, 12), // x12 = dst + iimm(2, 0, 0x0, 1), // x1 = AVL = 2 + vle32(9, 3), // v3 = [AAAA0001..AAAA0004] (preload) + vsetvli(0x10, 1, 0), // vsetvli x0, x1, e32 -> vl=2 + vle32(10, 1), // v1 = [10,20,30,40] + vle32(11, 2), // v2 = [1,2,3,4] + vaddvv(1, 2, 3), // v3: lanes 0,1 = v1+v2; lanes 2,3 undisturbed + vse32(12, 3), // store full v3 + 0x00000013, // nop (halt target) + ])}@100\n0a 00 00 00 14 00 00 00 1e 00 00 00 28 00 00 00\n' + '@110\n01 00 00 00 02 00 00 00 03 00 00 00 04 00 00 00\n' + '@120\n01 00 aa aa 02 00 aa aa 03 00 aa aa 04 00 aa aa\n', + const {}, + vecConfig(), + nextPc: 0x2C, + memStates: { + 0x200: 0x000000160000000B, // [11, 22] (active lanes) + 0x208: 0xAAAA0004AAAA0003, // [AAAA0003, AAAA0004] (tail kept) + }, + ), + ); + + // Milestone 4d (polish): FP ops respect vl/tail too. vsetvli e32 AVL=2; + // vfadd lanes 0,1 = v1+v2 (1+10=11, 2+20=22), lanes 2,3 keep preloaded v3. + test( + 'vl/tail: vfadd with vl=2 leaves the FP tail undisturbed', + timeout: Timeout(Duration(seconds: 180)), + () => coreTest( + '${prog([ + iimm(0x120, 0, 0x0, 9), // x9 = v3 preload + iimm(0x100, 0, 0x0, 10), // x10 = v1 + iimm(0x110, 0, 0x0, 11), // x11 = v2 + iimm(0x200, 0, 0x0, 12), // x12 = dst + iimm(2, 0, 0x0, 1), // x1 = AVL = 2 + vle32(9, 3), // v3 = [100,200,300,400] + vsetvli(0x10, 1, 0), // vl=2 + vle32(10, 1), // v1 = [1,2,3,4] + vle32(11, 2), // v2 = [10,20,30,40] + vopfvv(0x00, 1, 2, 3), // vfadd.vv v3, v1, v2 (vl=2) + vse32(12, 3), + 0x00000013, // nop (halt target) + ])}@100\n00 00 80 3f 00 00 00 40 00 00 40 40 00 00 80 40\n' + '@110\n00 00 20 41 00 00 a0 41 00 00 f0 41 00 00 20 42\n' + '@120\n00 00 c8 42 00 00 48 43 00 00 96 43 00 00 c8 43\n', + const {}, + vecConfig(), + nextPc: 0x2C, + memStates: { + 0x200: 0x41B0000041300000, // [11.0, 22.0] (active) + 0x208: 0x43C8000043960000, // [300.0, 400.0] (tail kept) + }, + ), + ); + + // Milestone 4e: vector FP at SEW=64 (FP64 lanes). vsetvli e64 makes vfadd.vv + // operate on 2x 64-bit lanes. v1=[1.0d,2.0d], v2=[3.0d,4.0d] -> [4.0d,6.0d]. + test( + 'vfadd.vv at SEW=64 (FP64 lanes)', + timeout: Timeout(Duration(seconds: 180)), + () => coreTest( + '${prog([ + iimm(0x100, 0, 0x0, 10), + iimm(0x110, 0, 0x0, 11), + iimm(0x200, 0, 0x0, 12), + iimm(2, 0, 0x0, 1), // x1 = AVL = 2 + vsetvli(0x18, 1, 0), // e64 -> vl = min(2, VLMAX=2) = 2 + vle32(10, 1), // v1 = [1.0d, 2.0d] (full 128b) + vle32(11, 2), // v2 = [3.0d, 4.0d] + vopfvv(0x00, 1, 2, 3), // vfadd.vv v3, v1, v2 -> [4.0d, 6.0d] + vse32(12, 3), + 0x00000013, // nop (halt target) + ])}@100\n00 00 00 00 00 00 f0 3f 00 00 00 00 00 00 00 40\n' + '@110\n00 00 00 00 00 00 08 40 00 00 00 00 00 00 10 40\n', + const {}, + vecConfig(), + nextPc: 0x24, + memStates: { + 0x200: 0x4010000000000000, // 4.0d (lane 0) + 0x208: 0x4018000000000000, // 6.0d (lane 1) + }, + ), + ); + + // Milestone 4f: Zvfh vector FP at SEW=16 (FP16 half-precision lanes). vsetvli + // e16 makes vfadd.vv operate on 8x 16-bit lanes. Half bit patterns: 1.0=0x3C00, + // 2.0=0x4000, 3.0=0x4200, 4.0=0x4400, 6.0=0x4600. v1=[1,2,1,2], v2=[3,4,3,4] + // -> v3=[4,6,4,6]. Uses vecConfigZvfh (the only core that builds FP16 units). + test( + 'vfadd.vv at SEW=16 (FP16 lanes, Zvfh)', + timeout: Timeout(Duration(seconds: 180)), + () => coreTest( + '${prog([ + iimm(0x100, 0, 0x0, 10), + iimm(0x110, 0, 0x0, 11), + iimm(0x200, 0, 0x0, 12), + iimm(8, 0, 0x0, 1), // x1 = AVL = 8 (VLMAX = 128/16 = 8) + vsetvli(0x08, 1, 0), // e16, m1 -> vl = 8 + vle32(10, 1), // v1 (low 4 lanes = [1.0,2.0,1.0,2.0]) + vle32(11, 2), // v2 (low 4 lanes = [3.0,4.0,3.0,4.0]) + vopfvv(0x00, 1, 2, 3), // vfadd.vv v3, v1, v2 -> [4.0,6.0,4.0,6.0] + vse32(12, 3), + 0x00000013, // nop (halt target) + ])}@100\n00 3c 00 40 00 3c 00 40 00 00 00 00 00 00 00 00\n' + '@110\n00 42 00 44 00 42 00 44 00 00 00 00 00 00 00 00\n', + const {Register.x1: 8}, // AVL; vsetvli rd=x0 discards vl + vecConfigZvfh(), + nextPc: 0x24, + memStates: { + // lanes [4.0, 6.0, 4.0, 6.0] = 0x4400,0x4600,0x4400,0x4600 packed LE. + 0x200: 0x4600440046004400, + }, + ), + ); +} diff --git a/packages/river_hdl/test/golden/rv32_inorder_test.dart b/packages/river_hdl/test/golden/rv32_inorder_test.dart new file mode 100644 index 0000000..d86ab88 --- /dev/null +++ b/packages/river_hdl/test/golden/rv32_inorder_test.dart @@ -0,0 +1,14 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_golden_vectors.dart'; +import '../matrix_harness.dart'; + +void main() { + const mxlen = RiscVMxlen.rv32; + runGolden( + 'golden: rv32 inorder', + matrixConfig(mxlen, Uarch.inOrder, 'm'), + inOrderGolden(mxlen), + ); +} diff --git a/packages/river_hdl/test/golden/rv32_ooo_test.dart b/packages/river_hdl/test/golden/rv32_ooo_test.dart new file mode 100644 index 0000000..72c4dfa --- /dev/null +++ b/packages/river_hdl/test/golden/rv32_ooo_test.dart @@ -0,0 +1,14 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_golden_vectors.dart'; +import '../matrix_harness.dart'; + +void main() { + const mxlen = RiscVMxlen.rv32; + runGolden( + 'golden: branch rv32 ooo', + matrixConfig(mxlen, Uarch.ooo, 'branch'), + branchGolden(mxlen), + ); +} diff --git a/packages/river_hdl/test/golden/rv64_inorder_test.dart b/packages/river_hdl/test/golden/rv64_inorder_test.dart new file mode 100644 index 0000000..d232c69 --- /dev/null +++ b/packages/river_hdl/test/golden/rv64_inorder_test.dart @@ -0,0 +1,15 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_golden_vectors.dart'; +import '../matrix_harness.dart'; + +void main() { + const mxlen = RiscVMxlen.rv64; + // Config carries base + M (covers arith/shift/mul/memory/lui golden vectors). + runGolden( + 'golden: rv64 inorder', + matrixConfig(mxlen, Uarch.inOrder, 'm'), + inOrderGolden(mxlen), + ); +} diff --git a/packages/river_hdl/test/golden/rv64_ooo_test.dart b/packages/river_hdl/test/golden/rv64_ooo_test.dart new file mode 100644 index 0000000..6e9417f --- /dev/null +++ b/packages/river_hdl/test/golden/rv64_ooo_test.dart @@ -0,0 +1,15 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_golden_vectors.dart'; +import '../matrix_harness.dart'; + +void main() { + const mxlen = RiscVMxlen.rv64; + // Branch vectors need a predictor -> OoO+btfn config. + runGolden( + 'golden: branch rv64 ooo', + matrixConfig(mxlen, Uarch.ooo, 'branch'), + branchGolden(mxlen), + ); +} diff --git a/packages/river_hdl/test/heimdall-river.cfg b/packages/river_hdl/test/heimdall-river.cfg new file mode 100644 index 0000000..97d1cc5 --- /dev/null +++ b/packages/river_hdl/test/heimdall-river.cfg @@ -0,0 +1,19 @@ +# OpenOCD config for Heimdall's openocd-spawn transport driving river_sim +# --remote-bitbang. Heimdall appends tcl_port/bindto/init itself and drives +# halt/reg over Tcl RPC, so this file must NOT declare tcl_port/init/halt. +adapter driver remote_bitbang +adapter speed 1000 +# Force IPv4. "localhost" can resolve to ::1 first; OpenOCD's remote_bitbang +# then mis-handles the IPv4 fallback and dies with "Bad file descriptor". The +# sim's JtagRemote binds IPv4 loopback only, so connect there directly. +remote_bitbang host 127.0.0.1 +remote_bitbang port 44901 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME + +gdb_port disabled +telnet_port disabled diff --git a/packages/river_hdl/test/hypervisor/core_gstage_ufault_test.dart b/packages/river_hdl/test/hypervisor/core_gstage_ufault_test.dart new file mode 100644 index 0000000..7275a49 --- /dev/null +++ b/packages/river_hdl/test/hypervisor/core_gstage_ufault_test.dart @@ -0,0 +1,111 @@ +import 'package:rohd/rohd.dart'; +import 'package:river/river.dart'; +import 'package:test/test.dart'; +import '../core_harness.dart'; + +/// H3 corner: every G-stage *leaf* must be user-accessible. Here the data page's +/// G-leaf has U=0, so the HLV must take a guest page fault and trap to mtvec. +/// The handler sets x5=0x5AD, proving the fault propagated (and exercising the +/// HLV fault -> trap path). +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + final config = RiverCoreConfig( + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + mxlen: RiscVMxlen.rv64, + extensions: [rv64i, rv32i, rvZicsr, rvZifencei, rvPriv, rvH], + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + ); + + int csrw(int csr, int rs1) => (csr << 20) | (rs1 << 15) | (0x1 << 12) | 0x73; + int addi(int rd, int rs1, int imm) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (rd << 7) | 0x13; + int csrr(int csr, int rd) => (csr << 20) | (0x2 << 12) | (rd << 7) | 0x73; + int slli(int rd, int rs1, int sh) => + (sh << 20) | (rs1 << 15) | (0x1 << 12) | (rd << 7) | 0x13; + int orr(int rd, int rs1, int rs2) => + (rs2 << 20) | (rs1 << 15) | (0x6 << 12) | (rd << 7) | 0x33; + int lui(int rd, int imm20) => (imm20 << 12) | (rd << 7) | 0x37; + int hlvw(int rd, int rs1) => + (0x34 << 25) | (rs1 << 15) | (0x4 << 12) | (rd << 7) | 0x73; + const jalLoop = 0x0000006F; // jal x0, 0 -> branch to self + + String words(List ws) { + final sb = StringBuffer(); + for (final w in ws) { + for (var b = 0; b < 4; b++) { + sb.write(((w >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + return sb.toString().trimRight(); + } + + String pte(int v) { + final sb = StringBuffer(); + for (var b = 0; b < 8; b++) { + sb.write(((v >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + return sb.toString().trimRight(); + } + + test( + 'HLV faults when the G-stage leaf is not user-accessible', + timeout: Timeout(Duration(seconds: 180)), + () { + final prog = words([ + csrw(0x280, 10), // 0 csrw vsatp, a0 + addi(14, 0, 0x50), //1 + addi(15, 0, 1), // 2 + slli(15, 15, 63), //3 + orr(14, 14, 15), // 4 x14 = hgatp + csrw(0x680, 14), // 5 csrw hgatp, x14 + addi(6, 0, 0x40), // 6 x6 = 0x40 (mtvec handler) + csrw(0x305, 6), // 7 csrw mtvec, x6 + lui(13, 0x20), // 8 x13 = 0x20000 + hlvw( + 11, + 13, + ), // 9 hlv.w a1, (a3) -> G-leaf U=0 -> page fault -> mtvec + 0x00000013, // 10 nop (0x28, skipped by trap) + 0x00000013, + 0x00000013, + 0x00000013, + 0x00000013, + 0x00000013, // 11-15 fill + csrr(0x342, 5), // 16 @0x40 handler: x5 = mcause (== 21 guest load PF) + jalLoop, // 17 @0x44 loop + ]); + return coreTest( + '@0\n$prog\n' + '@10000\n${pte(0x4401)}\n' + '@11000\n${pte(0x4801)}\n' + '@12100\n${pte(0xC00F)}\n' + '@40000\n${pte(0xCAFEF00D)}\n' + '@50000\n${pte(0x14401)}\n' + '@51000\n${pte(0x14801)}\n' + '@52080\n${pte(0x401F)}\n' + '@52088\n${pte(0x441F)}\n' + '@52090\n${pte(0x481F)}\n' + '@52180\n${pte(0x1000F)}\n', // data-page G-leaf: V|R|W|X but U=0 + {Register.x5: 21}, // mcause == loadGuestPageFault (G-stage fault) + config, + initRegisters: {Register.x10: 0x8000000000000010}, + nextPc: 0x44, + ); + }, + ); +} diff --git a/packages/river_hdl/test/hypervisor/core_hlv_test.dart b/packages/river_hdl/test/hypervisor/core_hlv_test.dart new file mode 100644 index 0000000..8cd5635 --- /dev/null +++ b/packages/river_hdl/test/hypervisor/core_hlv_test.dart @@ -0,0 +1,101 @@ +import 'package:rohd/rohd.dart'; +import 'package:river/river.dart'; +import 'package:test/test.dart'; +import '../core_harness.dart'; + +/// H2: HLV (hypervisor virtual load). From M-mode (virt=0), HLV.W must access +/// guest memory through the guest two-stage translation (vsatp + hgatp), not HS +/// satp, proving the per-access `memGuest` routing works. Reuses the two-stage +/// page tables: gva 0x20000 -VS-> gpa 0x30000 -G-> host 0x40000 (where the data +/// lives). A plain load couldn't reach it; only an HLV that routes to the guest +/// tables returns 0xCAFEF00D. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + final config = RiverCoreConfig( + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + mxlen: RiscVMxlen.rv64, + extensions: [rv64i, rv32i, rvZicsr, rvZifencei, rvPriv, rvH], + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + ); + + int csrw(int csr, int rs1) => (csr << 20) | (rs1 << 15) | (0x1 << 12) | 0x73; + int addi(int rd, int rs1, int imm) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (rd << 7) | 0x13; + int slli(int rd, int rs1, int sh) => + (sh << 20) | (rs1 << 15) | (0x1 << 12) | (rd << 7) | 0x13; + int orr(int rd, int rs1, int rs2) => + (rs2 << 20) | (rs1 << 15) | (0x6 << 12) | (rd << 7) | 0x33; + int lui(int rd, int imm20) => (imm20 << 12) | (rd << 7) | 0x37; + // HLV.W rd, (rs1): SYSTEM, funct7=0x34, funct3=4, rs2=0. + int hlvw(int rd, int rs1) => + (0x34 << 25) | (0 << 20) | (rs1 << 15) | (0x4 << 12) | (rd << 7) | 0x73; + + String words(List ws) { + final sb = StringBuffer(); + for (final w in ws) { + for (var b = 0; b < 4; b++) { + sb.write(((w >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + return sb.toString().trimRight(); + } + + String pte(int v) { + final sb = StringBuffer(); + for (var b = 0; b < 8; b++) { + sb.write(((v >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + return sb.toString().trimRight(); + } + + test( + 'HLV.W reads guest memory via two-stage translation from M-mode', + timeout: Timeout(Duration(seconds: 180)), + () { + final prog = words([ + csrw(0x280, 10), // 0 csrw vsatp, a0 (Sv39 | gpa-root PPN 0x10) + addi(14, 0, 0x50), //1 x14 = 0x50 + addi(15, 0, 1), // 2 x15 = 1 + slli(15, 15, 63), //3 x15 = 1<<63 + orr(14, 14, 15), //4 x14 = hgatp (Sv39 | host-root PPN 0x50) + csrw(0x680, 14), //5 csrw hgatp, x14 + lui(13, 0x20), // 6 x13 = 0x20000 (guest virtual) + hlvw(11, 13), // 7 hlv.w a1, (a3) -> two-stage translate + load + 0x00000013, // 8 nop + ]); + return coreTest( + '@0\n$prog\n' + '@10000\n${pte(0x4401)}\n' + '@11000\n${pte(0x4801)}\n' + '@12100\n${pte(0xC00F)}\n' + '@40000\n${pte(0xCAFEF00D)}\n' + '@50000\n${pte(0x14401)}\n' + '@51000\n${pte(0x14801)}\n' + '@52080\n${pte(0x401F)}\n' + '@52088\n${pte(0x441F)}\n' + '@52090\n${pte(0x481F)}\n' + '@52180\n${pte(0x1001F)}\n', + // HLV.W is signed; 0xCAFEF00D has bit 31 set -> sign-extended to 64 bits. + {Register.x11: 0xFFFFFFFFCAFEF00D}, + config, + initRegisters: {Register.x10: 0x8000000000000010}, + nextPc: 0x24, + ); + }, + ); +} diff --git a/packages/river_hdl/test/hypervisor/core_hsv_test.dart b/packages/river_hdl/test/hypervisor/core_hsv_test.dart new file mode 100644 index 0000000..8322c7f --- /dev/null +++ b/packages/river_hdl/test/hypervisor/core_hsv_test.dart @@ -0,0 +1,100 @@ +import 'package:rohd/rohd.dart'; +import 'package:river/river.dart'; +import 'package:test/test.dart'; +import '../core_harness.dart'; + +/// H2: HSV (hypervisor virtual store). From M-mode, HSV.W must store to guest +/// memory through the guest two-stage translation. Reuses the two-stage tables: +/// gva 0x20000 -VS-> gpa 0x30000 -G-> host 0x40000. After HSV.W of 0x5A5 to the +/// guest address, host physical 0x40000 must hold 0x5A5. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + final config = RiverCoreConfig( + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + mxlen: RiscVMxlen.rv64, + extensions: [rv64i, rv32i, rvZicsr, rvZifencei, rvPriv, rvH], + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + ); + + int csrw(int csr, int rs1) => (csr << 20) | (rs1 << 15) | (0x1 << 12) | 0x73; + int addi(int rd, int rs1, int imm) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (rd << 7) | 0x13; + int slli(int rd, int rs1, int sh) => + (sh << 20) | (rs1 << 15) | (0x1 << 12) | (rd << 7) | 0x13; + int orr(int rd, int rs1, int rs2) => + (rs2 << 20) | (rs1 << 15) | (0x6 << 12) | (rd << 7) | 0x33; + int lui(int rd, int imm20) => (imm20 << 12) | (rd << 7) | 0x37; + // HSV.W rs2, (rs1): SYSTEM, funct7=0x35, funct3=4. + int hsvw(int rs1, int rs2) => + (0x35 << 25) | (rs2 << 20) | (rs1 << 15) | (0x4 << 12) | 0x73; + + String words(List ws) { + final sb = StringBuffer(); + for (final w in ws) { + for (var b = 0; b < 4; b++) { + sb.write(((w >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + return sb.toString().trimRight(); + } + + String pte(int v) { + final sb = StringBuffer(); + for (var b = 0; b < 8; b++) { + sb.write(((v >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + return sb.toString().trimRight(); + } + + test( + 'HSV.W stores guest memory via two-stage translation from M-mode', + timeout: Timeout(Duration(seconds: 180)), + () { + final prog = words([ + csrw(0x280, 10), // 0 csrw vsatp, a0 + addi(14, 0, 0x50), //1 + addi(15, 0, 1), // 2 + slli(15, 15, 63), //3 + orr(14, 14, 15), //4 x14 = hgatp + csrw(0x680, 14), //5 csrw hgatp, x14 + lui(13, 0x20), // 6 x13 = 0x20000 (guest virtual) + addi(12, 0, 0x5A5), //7 x12 = 0x5A5 (store data) + hsvw(13, 12), // 8 hsv.w a2, (a3) + 0x00000013, // 9 nop + ]); + return coreTest( + '@0\n$prog\n' + '@10000\n${pte(0x4401)}\n' + '@11000\n${pte(0x4801)}\n' + '@12100\n${pte(0xC00F)}\n' + '@40000\n${pte(0x0)}\n' + '@50000\n${pte(0x14401)}\n' + '@51000\n${pte(0x14801)}\n' + '@52080\n${pte(0x401F)}\n' + '@52088\n${pte(0x441F)}\n' + '@52090\n${pte(0x481F)}\n' + '@52180\n${pte(0x1001F)}\n', + const {}, + config, + initRegisters: {Register.x10: 0x8000000000000010}, + memStates: {0x40000: 0x5A5}, + nextPc: 0x28, + ); + }, + ); +} diff --git a/packages/river_hdl/test/hypervisor/core_hypervisor_test.dart b/packages/river_hdl/test/hypervisor/core_hypervisor_test.dart new file mode 100644 index 0000000..1053880 --- /dev/null +++ b/packages/river_hdl/test/hypervisor/core_hypervisor_test.dart @@ -0,0 +1,71 @@ +import 'package:rohd/rohd.dart'; +import 'package:river/river.dart'; +import 'package:test/test.dart'; +import '../core_harness.dart'; + +/// Hypervisor (H) phase. H0: the H + VS-shadow CSRs exist and are read/write +/// when the config has H (gated on hasHypervisor). See project_hypervisor. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + // RV64 + supervisor + hypervisor. H virtualizes S, so supervisor is required. + final config = RiverCoreConfig( + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + mxlen: RiscVMxlen.rv64, + extensions: [rv64i, rv32i, rvZicsr, rvZifencei, rvPriv, rvH], + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + ); + + // csrrw x0, csr, rs1 (write csr = rs1); csrrs rd, csr, x0 (read csr -> rd). + int csrw(int csr, int rs1) => + (csr << 20) | (rs1 << 15) | (0x1 << 12) | (0 << 7) | 0x73; + int csrr(int csr, int rd) => + (csr << 20) | (0 << 15) | (0x2 << 12) | (rd << 7) | 0x73; + int iimm(int imm, int rs1, int f3, int rd) => + (imm << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x13; + String prog(List words) { + final sb = StringBuffer('@0\n'); + for (final w in words) { + for (var b = 0; b < 4; b++) { + sb.write(((w >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + return '$sb\n'; + } + + // H0: hgatp (0x680) and hstatus (0x600) round-trip via csrw/csrr. + // a0 (x10) is preloaded; csrw writes it, csrr reads it back into a reg. + test( + 'H CSRs read/write (hgatp, hstatus)', + timeout: Timeout(Duration(seconds: 300)), + () { + return coreTest( + prog([ + csrw(0x680, 10), // csrw hgatp, a0 (a0 = 0x123) + csrr(0x680, 11), // csrr a1, hgatp -> a1 = 0x123 + iimm(0x55, 0, 0x0, 12), // x12 = 0x55 + csrw(0x600, 12), // csrw hstatus, x12 + csrr(0x600, 13), // csrr a3, hstatus -> a3 = 0x55 + 0x00000013, // nop (halt target) + ]), + {Register.x11: 0x123, Register.x13: 0x55}, + config, + initRegisters: {Register.x10: 0x123}, + nextPc: 0x14, + ); + }, + ); +} diff --git a/packages/river_hdl/test/hypervisor/core_virt_test.dart b/packages/river_hdl/test/hypervisor/core_virt_test.dart new file mode 100644 index 0000000..ea04bfb --- /dev/null +++ b/packages/river_hdl/test/hypervisor/core_virt_test.dart @@ -0,0 +1,128 @@ +import 'dart:async'; +import 'package:rohd/rohd.dart'; +import 'package:rohd_hcl/rohd_hcl.dart' hide DataPortInterface, DataPortGroup; +import 'package:river/river.dart'; +import 'package:river_hdl/river_hdl.dart'; +import 'package:test/test.dart'; + +/// H1: the V (virtualization) bit transitions on MRET. With mstatus.MPV=1 and +/// MPP=S, an MRET must enter (mode=S, virt=1). +void main() { + tearDown(() async => Simulator.reset()); + + final config = RiverCoreConfig( + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + mxlen: RiscVMxlen.rv64, + extensions: [rv64i, rv32i, rvZicsr, rvZifencei, rvPriv, rvH], + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + ); + + test( + 'MRET with MPV=1, MPP=S enters virt mode', + timeout: Timeout(Duration(seconds: 300)), + () async { + final clk = SimpleClockGenerator(20).clk; + final reset = Logic(); + final aw = config.mxlen.size; + final wbConfig = WishboneConfig( + addressWidth: aw, + dataWidth: config.mxlen.size, + selWidth: config.mxlen.size ~/ 8, + ); + final core = RiverCore(config, busConfig: wbConfig); + core.input('clk').srcConnection! <= clk; + core.input('reset').srcConnection! <= reset; + await core.build(); + final storage = SparseMemoryStorage( + addrWidth: aw, + dataWidth: config.mxlen.size, + alignAddress: (a) => a, + onInvalidRead: (a, w) => LogicValue.filled(w, LogicValue.zero), + ); + final memRead = DataPortInterface(config.mxlen.size, aw); + final memWrite = DataPortInterface(config.mxlen.size, aw); + // ignore: unused_local_variable + final mem = MemoryModel( + clk, + reset, + [wrapWriteForRegisterFile(memWrite)], + [wrapReadForRegisterFile(memRead, clk: clk, readLatency: 0)], + readLatency: 0, + storage: storage, + ); + final cyc = core.output('dataBus_CYC'), + stb = core.output('dataBus_STB'), + we = core.output('dataBus_WE'), + adr = core.output('dataBus_ADR'), + dat = core.output('dataBus_DAT_MOSI'); + memRead.en <= cyc & stb & ~we; + memRead.addr <= adr; + memWrite.en <= cyc & stb & we; + memWrite.addr <= adr; + memWrite.data <= dat; + final ack = Logic(name: 'wbAck'); + final ready = we | memRead.valid; + Sequential(clk, [ + If( + reset, + then: [ack < 0], + orElse: [ + If(cyc & stb & ~ack & ready, then: [ack < 1], orElse: [ack < 0]), + ], + ), + ]); + core.input('dataBus_ACK').srcConnection! <= ack; + core.input('dataBus_DAT_MISO').srcConnection! <= memRead.data; + + reset.inject(1); + Simulator.registerAction(20, () { + reset.put(0); + core.regWritePort.en.inject(1); + core.regWritePort.addr.inject(LogicValue.ofInt(Register.x11.value, 5)); + // mstatus: MPP=S (1<<11) | MPV (1<<39) + core.regWritePort.data.inject( + LogicValue.ofInt(0x8000000800, config.mxlen.size), + ); + // addi x10,x0,0x10 ; csrw mepc,x10 ; csrw mstatus,x11 ; mret ; @0x10 addi x12,x0,0x55 + storage.loadMemString( + '@0\n13 05 00 01 73 10 15 34 73 90 05 30 73 00 20 30 13 06 50 05\n', + ); + }); + Simulator.setMaxSimTime(200000); + unawaited(Simulator.run()); + await clk.nextPosedge; + core.regWritePort.en.inject(0); + while (reset.value.toBool()) { + await clk.nextPosedge; + } + for (var i = 0; i < 5000; i++) { + await clk.nextPosedge; + final pc = core.pipeline.nextPc.value; + if (pc.isValid && pc.toInt() == 0x14) break; + } + await Simulator.endSimulation(); + await Simulator.simulationEnded; + + expect(core.pipeline.nextPc.value.toInt(), 0x14); + final virt = core.output('virt').value; + expect(virt.isValid, isTrue, reason: 'virt is X'); + expect(virt.toInt(), 1, reason: 'MRET should have entered virt mode'); + final x12 = core.regs.getData(LogicValue.ofInt(Register.x12.value, 5))!; + expect( + x12.toInt(), + 0x55, + reason: 'instruction after MRET should execute', + ); + }, + ); +} diff --git a/packages/river_hdl/test/hypervisor/core_vsmode_csr_test.dart b/packages/river_hdl/test/hypervisor/core_vsmode_csr_test.dart new file mode 100644 index 0000000..2f8c5cd --- /dev/null +++ b/packages/river_hdl/test/hypervisor/core_vsmode_csr_test.dart @@ -0,0 +1,90 @@ +import 'package:rohd/rohd.dart'; +import 'package:river/river.dart'; +import 'package:test/test.dart'; +import '../core_harness.dart'; + +/// H4 (CSR redirect): in VS-mode (virt=1) a supervisor-CSR access redirects to +/// the VS shadow. A VS-mode `csrw satp` must land in vsatp, verified by reading +/// vsatp back directly (x5) and via the redirected `csrr satp` (x6); both equal +/// the written value, which is impossible without the redirect (vsatp would +/// stay 0). Flow: MRET into VS-mode, then the three CSR ops, then loop. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + final config = RiverCoreConfig( + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + mxlen: RiscVMxlen.rv64, + extensions: [rv64i, rv32i, rvZicsr, rvZifencei, rvPriv, rvH], + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + ); + + int csrw(int csr, int rs1) => (csr << 20) | (rs1 << 15) | (0x1 << 12) | 0x73; + int csrr(int csr, int rd) => (csr << 20) | (0x2 << 12) | (rd << 7) | 0x73; + int addi(int rd, int rs1, int imm) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (rd << 7) | 0x13; + int slli(int rd, int rs1, int sh) => + (sh << 20) | (rs1 << 15) | (0x1 << 12) | (rd << 7) | 0x13; + int orr(int rd, int rs1, int rs2) => + (rs2 << 20) | (rs1 << 15) | (0x6 << 12) | (rd << 7) | 0x33; + const jalLoop = 0x0000006F; + + String words(List ws) { + final sb = StringBuffer(); + for (final w in ws) { + for (var b = 0; b < 4; b++) { + sb.write(((w >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + return sb.toString().trimRight(); + } + + test( + 'VS-mode csrw satp redirects to vsatp', + timeout: Timeout(Duration(seconds: 180)), + () { + final prog = words([ + addi(11, 0, 0x24), // 0 x11 = 0x24 (VS code address) + csrw(0x341, 11), // 1 csrw mepc, x11 + addi(12, 0, 1), // 2 + slli(12, 12, 11), // 3 x12 = 0x800 (MPP=S) + addi(13, 0, 1), // 4 + slli(13, 13, 39), // 5 x13 = MPV + orr(12, 12, 13), // 6 x12 = 0x8000000800 + csrw(0x300, 12), // 7 csrw mstatus, x12 + 0x30200073, // 8 @0x20 mret -> VS-mode (S, virt=1), pc=0x24 + csrw(0x180, 10), // 9 @0x24 VS: csrw satp,a0 -> redirects to vsatp + csrr( + 0x280, + 5, + ), // 10 @0x28 csrr x5, vsatp (direct: 0x280 not redirected) + csrr(0x180, 6), // 11 @0x2c csrr x6, satp (redirects to vsatp) + jalLoop, // 12 @0x30 loop + ]); + return coreTest( + '@0\n$prog\n', + { + Register.x5: + 0x8000000000000042, // vsatp received the VS-mode satp write + Register.x6: + 0x8000000000000042, // VS-mode csrr satp redirects to vsatp + }, + config, + initRegisters: {Register.x10: 0x8000000000000042}, + nextPc: 0x30, + ); + }, + ); +} diff --git a/packages/river_hdl/test/hypervisor/core_vsmode_ecall_test.dart b/packages/river_hdl/test/hypervisor/core_vsmode_ecall_test.dart new file mode 100644 index 0000000..2f327fe --- /dev/null +++ b/packages/river_hdl/test/hypervisor/core_vsmode_ecall_test.dart @@ -0,0 +1,83 @@ +import 'package:rohd/rohd.dart'; +import 'package:river/river.dart'; +import 'package:test/test.dart'; +import '../core_harness.dart'; + +/// H4 (trap virtualization, first step): an ecall taken in VS-mode must trap to +/// M (mtvec) cleanly. MRET into VS-mode, ecall, handler sets x5=0x5AD. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + final config = RiverCoreConfig( + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + mxlen: RiscVMxlen.rv64, + extensions: [rv64i, rv32i, rvZicsr, rvZifencei, rvPriv, rvH], + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + ); + + int csrw(int csr, int rs1) => (csr << 20) | (rs1 << 15) | (0x1 << 12) | 0x73; + int addi(int rd, int rs1, int imm) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (rd << 7) | 0x13; + int slli(int rd, int rs1, int sh) => + (sh << 20) | (rs1 << 15) | (0x1 << 12) | (rd << 7) | 0x13; + int orr(int rd, int rs1, int rs2) => + (rs2 << 20) | (rs1 << 15) | (0x6 << 12) | (rd << 7) | 0x33; + const ecall = 0x00000073; + const jalLoop = 0x0000006F; + + String words(List ws) { + final sb = StringBuffer(); + for (final w in ws) { + for (var b = 0; b < 4; b++) { + sb.write(((w >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + return sb.toString().trimRight(); + } + + test( + 'ecall in VS-mode traps to mtvec', + timeout: Timeout(Duration(seconds: 180)), + () { + final prog = words([ + addi(11, 0, 0x2c), // 0 x11 = 0x2c (VS code) + csrw(0x341, 11), // 1 csrw mepc, x11 + addi(12, 0, 1), // 2 + slli(12, 12, 11), // 3 x12 = 0x800 (MPP=S) + addi(13, 0, 1), // 4 + slli(13, 13, 39), // 5 x13 = MPV + orr(12, 12, 13), // 6 x12 = 0x8000000800 + csrw(0x300, 12), // 7 csrw mstatus, x12 + addi(14, 0, 0x40), // 8 x14 = 0x40 (mtvec) + csrw(0x305, 14), // 9 csrw mtvec, x14 + 0x30200073, // 10 @0x28 mret -> VS-mode, pc=0x2c + ecall, // 11 @0x2c VS ecall -> trap to mtvec + 0x00000013, // 12 @0x30 (skipped) + 0x00000013, // 13 @0x34 + 0x00000013, // 14 @0x38 + 0x00000013, // 15 @0x3c + addi(5, 0, 0x5AD), // 16 @0x40 handler: x5 = 0x5AD + jalLoop, // 17 @0x44 loop + ]); + return coreTest( + '@0\n$prog\n', + {Register.x5: 0x5AD}, + config, + nextPc: 0x44, + ); + }, + ); +} diff --git a/packages/river_hdl/test/hypervisor/core_vsmode_trapdeleg_test.dart b/packages/river_hdl/test/hypervisor/core_vsmode_trapdeleg_test.dart new file mode 100644 index 0000000..ed58f44 --- /dev/null +++ b/packages/river_hdl/test/hypervisor/core_vsmode_trapdeleg_test.dart @@ -0,0 +1,100 @@ +import 'package:rohd/rohd.dart'; +import 'package:river/river.dart'; +import 'package:test/test.dart'; +import '../core_harness.dart'; + +/// H4 (trap delegation to VS-mode): a trap taken in VS-mode whose cause is +/// delegated by BOTH medeleg (M->HS) and hedeleg (HS->VS) must trap to vstvec +/// (staying virtualized), not to stvec. vstvec and stvec point at distinct +/// handlers; reaching the vstvec handler (x5=0x111) proves the VS delegation. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + final config = RiverCoreConfig( + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + mxlen: RiscVMxlen.rv64, + extensions: [rv64i, rv32i, rvZicsr, rvZifencei, rvPriv, rvH], + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + ); + + int csrw(int csr, int rs1) => (csr << 20) | (rs1 << 15) | (0x1 << 12) | 0x73; + int csrr(int csr, int rd) => (csr << 20) | (0x2 << 12) | (rd << 7) | 0x73; + int addi(int rd, int rs1, int imm) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (rd << 7) | 0x13; + int slli(int rd, int rs1, int sh) => + (sh << 20) | (rs1 << 15) | (0x1 << 12) | (rd << 7) | 0x13; + int orr(int rd, int rs1, int rs2) => + (rs2 << 20) | (rs1 << 15) | (0x6 << 12) | (rd << 7) | 0x33; + const ecall = 0x00000073; + const jalLoop = 0x0000006F; + const nop = 0x00000013; + + String words(List ws) { + final sb = StringBuffer(); + for (final w in ws) { + for (var b = 0; b < 4; b++) { + sb.write(((w >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + return sb.toString().trimRight(); + } + + test( + 'VS-mode trap delegates to vstvec (hedeleg)', + timeout: Timeout(Duration(seconds: 200)), + () { + final prog = words([ + addi( + 10, + 0, + 0x400, + ), // 0 x10 = 1<<10 (delegate cause-10 = ecall-from-VS) + csrw(0x302, 10), // 1 csrw medeleg, x10 (M->HS) + csrw(0x602, 10), // 2 csrw hedeleg, x10 (HS->VS) + addi(11, 0, 0x60), // 3 x11 = 0x60 (vstvec handler) + csrw(0x205, 11), // 4 csrw vstvec, x11 + addi(12, 0, 0x70), // 5 x12 = 0x70 (stvec handler) + csrw(0x105, 12), // 6 csrw stvec, x12 + addi(13, 0, 0x40), // 7 x13 = 0x40 (mepc = VS code) + csrw(0x341, 13), // 8 csrw mepc, x13 + addi(14, 0, 1), // 9 + slli(14, 14, 11), // 10 x14 = 0x800 (MPP=S) + addi(15, 0, 1), // 11 + slli(15, 15, 39), // 12 x15 = MPV + orr(14, 14, 15), // 13 x14 = 0x8000000800 + csrw(0x300, 14), // 14 csrw mstatus, x14 + 0x30200073, // 15 @0x3c mret -> VS-mode, pc=0x40 + ecall, // 16 @0x40 VS ecall -> delegated to VS (vstvec=0x60) + nop, nop, nop, nop, nop, nop, nop, // 17-23 @0x44..0x5c filler + // VS handler: read the cause via csrr scause (redirects to vscause in + // VS-mode), proves the trap landed in VS *and* vscause = ecallVS (10). + csrr(0x142, 5), // 24 @0x60 x5 = vscause (== 10) + jalLoop, // 25 @0x64 loop + nop, nop, // 26-27 @0x68,0x6c + addi(5, 0, 0x222), // 28 @0x70 HS handler (must NOT run): x5 = 0x222 + jalLoop, // 29 @0x74 loop + ]); + return coreTest( + '@0\n$prog\n', + { + Register.x5: 10, + }, // vscause == ecallVS: reached VS handler with right cause + config, + nextPc: 0x64, + ); + }, + ); +} diff --git a/packages/river_hdl/test/hypervisor/core_vsmode_virtinst_test.dart b/packages/river_hdl/test/hypervisor/core_vsmode_virtinst_test.dart new file mode 100644 index 0000000..77123b7 --- /dev/null +++ b/packages/river_hdl/test/hypervisor/core_vsmode_virtinst_test.dart @@ -0,0 +1,152 @@ +import 'package:rohd/rohd.dart'; +import 'package:river/river.dart'; +import 'package:test/test.dart'; +import '../core_harness.dart'; + +/// H4 (trap virtualization): VS-mode access to an HS-only hypervisor CSR raises +/// a virtual-instruction exception (cause 22). MRET into VS-mode, `csrr hstatus` +/// must trap to mtvec; the handler reads mcause and confirms it is 22. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + final config = RiverCoreConfig( + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + mxlen: RiscVMxlen.rv64, + extensions: [rv64i, rv32i, rvZicsr, rvZifencei, rvPriv, rvH], + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + ); + + int csrw(int csr, int rs1) => (csr << 20) | (rs1 << 15) | (0x1 << 12) | 0x73; + int csrr(int csr, int rd) => (csr << 20) | (0x2 << 12) | (rd << 7) | 0x73; + int addi(int rd, int rs1, int imm) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (rd << 7) | 0x13; + int slli(int rd, int rs1, int sh) => + (sh << 20) | (rs1 << 15) | (0x1 << 12) | (rd << 7) | 0x13; + int orr(int rd, int rs1, int rs2) => + (rs2 << 20) | (rs1 << 15) | (0x6 << 12) | (rd << 7) | 0x33; + const jalLoop = 0x0000006F; + + String words(List ws) { + final sb = StringBuffer(); + for (final w in ws) { + for (var b = 0; b < 4; b++) { + sb.write(((w >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + return sb.toString().trimRight(); + } + + final stateenConfig = RiverCoreConfig( + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + mxlen: RiscVMxlen.rv64, + extensions: [ + rv64i, + rv32i, + rvZicsr, + rvZifencei, + rvPriv, + rvH, + rvSmstateen, + rvSsstateen, + ], + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + ); + + // VS-mode sstateen access that mstateen0.SE0 permits but hstateen0.SE0 blocks + // (hstateen0 resets to 0) must raise virtual-instruction, not illegal. The + // exec catches it before the CSR access, so the VS redirect never applies. + test( + 'VS-mode csrr sstateen0 (hstateen blocks) raises virtual-instruction (22)', + timeout: Timeout(Duration(seconds: 180)), + () { + final prog = words([ + addi(11, 0, 0x38), // 0 x11 = 0x38 (VS code) + csrw(0x341, 11), // 1 csrw mepc, x11 + addi(12, 0, 1), // 2 + slli(12, 12, 11), // 3 MPP=S + addi(13, 0, 1), // 4 + slli(13, 13, 39), // 5 MPV + orr(12, 12, 13), // 6 x12 = 0x8000000800 + csrw(0x300, 12), // 7 csrw mstatus, x12 + addi(14, 0, 0x4c), // 8 x14 = 0x4c (mtvec) + csrw(0x305, 14), // 9 csrw mtvec, x14 + addi(15, 0, 1), // 10 + slli(15, 15, 63), // 11 x15 = 1<<63 (mstateen0.SE0) + csrw(0x30c, 15), // 12 csrw mstateen0, x15 (SE0=1; hstateen0 SE0=0) + 0x30200073, // 13 @0x34 mret -> VS-mode + csrr(0x10c, 6), // 14 @0x38 VS: csrr x6, sstateen0 -> virtual-instr + 0x00000013, // 15 @0x3c (skipped) + 0x00000013, // 16 @0x40 + 0x00000013, // 17 @0x44 + 0x00000013, // 18 @0x48 + csrr(0x342, 5), // 19 @0x4c handler: x5 = mcause + jalLoop, // 20 @0x50 loop + ]); + return coreTest( + '@0\n$prog\n', + {Register.x5: 22}, // mcause == virtual-instruction + stateenConfig, + nextPc: 0x50, + ); + }, + ); + + test( + 'VS-mode csrr hstatus raises virtual-instruction (cause 22)', + timeout: Timeout(Duration(seconds: 180)), + () { + final prog = words([ + addi(11, 0, 0x2c), // 0 x11 = 0x2c (VS code) + csrw(0x341, 11), // 1 csrw mepc, x11 + addi(12, 0, 1), // 2 + slli(12, 12, 11), // 3 MPP=S + addi(13, 0, 1), // 4 + slli(13, 13, 39), // 5 MPV + orr(12, 12, 13), // 6 x12 = 0x8000000800 + csrw(0x300, 12), // 7 csrw mstatus, x12 + addi(14, 0, 0x40), // 8 x14 = 0x40 (mtvec) + csrw(0x305, 14), // 9 csrw mtvec, x14 + 0x30200073, // 10 @0x28 mret -> VS-mode + csrr( + 0x600, + 6, + ), // 11 @0x2c VS: csrr x6, hstatus -> virtual-instruction + 0x00000013, // 12 @0x30 (skipped) + 0x00000013, // 13 @0x34 + 0x00000013, // 14 @0x38 + 0x00000013, // 15 @0x3c + csrr(0x342, 5), // 16 @0x40 handler: x5 = mcause + jalLoop, // 17 @0x44 loop + ]); + return coreTest( + '@0\n$prog\n', + {Register.x5: 22}, // mcause == virtual-instruction + config, + nextPc: 0x44, + ); + }, + ); +} diff --git a/packages/river_hdl/test/hypervisor/core_vsstage_test.dart b/packages/river_hdl/test/hypervisor/core_vsstage_test.dart new file mode 100644 index 0000000..8d1e2c4 --- /dev/null +++ b/packages/river_hdl/test/hypervisor/core_vsstage_test.dart @@ -0,0 +1,91 @@ +import 'package:rohd/rohd.dart'; +import 'package:river/river.dart'; +import 'package:test/test.dart'; +import '../core_harness.dart'; + +/// H3 (groundwork): guest VS-stage translation. With virt=1 (entered via MRET), +/// data accesses translate through vsatp instead of HS satp; the G-stage is +/// identity (bare hgatp). A load from guest-virtual 0x20000 must reach physical +/// 0x30000 via the vsatp page table, proving the V-bit routes to the VS-stage. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + final config = RiverCoreConfig( + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + mxlen: RiscVMxlen.rv64, + extensions: [rv64i, rv32i, rvZicsr, rvZifencei, rvPriv, rvH], + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + ); + + int csrw(int csr, int rs1) => (csr << 20) | (rs1 << 15) | (0x1 << 12) | 0x73; + int addi(int rd, int rs1, int imm) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (0x0 << 12) | (rd << 7) | 0x13; + int slli(int rd, int rs1, int sh) => + (sh << 20) | (rs1 << 15) | (0x1 << 12) | (rd << 7) | 0x13; + int orr(int rd, int rs1, int rs2) => + (rs2 << 20) | (rs1 << 15) | (0x6 << 12) | (rd << 7) | 0x33; + int lui(int rd, int imm20) => (imm20 << 12) | (rd << 7) | 0x37; + int ld(int rd, int rs1, int imm) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (0x3 << 12) | (rd << 7) | 0x03; + const mret = 0x30200073; + + String prog(List words) { + final sb = StringBuffer('@0\n'); + for (final w in words) { + for (var b = 0; b < 4; b++) { + sb.write(((w >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + return '$sb\n'; + } + + // a0(x10)=vsatp value (Sv39|root 0x10) preloaded. Build mstatus (MPP=S|MPV) + // and mepc=0x28 in-program, MRET into VS-mode, then translate a load. + test( + 'VS-stage translates guest load 0x20000 -> 0x30000', + timeout: Timeout(Duration(seconds: 120)), + () { + return coreTest( + // NOTE: MPV (bit 39) is built with two slli<32 shifts, slli with + // shamt>=32 currently hangs the in-order decoder (separate RV64 gap). + '${prog([ + csrw(0x280, 10), // 0x00 csrw vsatp, a0 + addi(11, 0, 0x2c), // 0x04 a1 = 0x2c (mepc target) + csrw(0x341, 11), // 0x08 csrw mepc, a1 + addi(12, 0, 1), // 0x0c a2 = 1 + slli(12, 12, 11), // 0x10 a2 = 0x800 (MPP=S) + addi(13, 0, 1), // 0x14 a3 = 1 + slli(13, 13, 20), // 0x18 a3 = 0x100000 + slli(13, 13, 19), // 0x1c a3 = 1<<39 (MPV) + orr(12, 12, 13), // 0x20 a2 = 0x8000000800 + csrw(0x300, 12), // 0x24 csrw mstatus, a2 + mret, // 0x28 -> VS-mode (S, virt=1), pc=0x2c + lui(13, 0x20), // 0x2c a3 = 0x20000 (guest virtual) + ld(14, 13, 0), // 0x30 a4 = *(translate(0x20000)) + 0x00000013, // 0x34 nop + ]).trimRight()}\n' + '@10000\n01 44 00 00 00 00 00 00\n' + '@11000\n01 48 00 00 00 00 00 00\n' + '@12100\n0F C0 00 00 00 00 00 00\n' + '@30000\n0D F0 FE CA 00 00 00 00\n', + {Register.x14: 0xCAFEF00D}, + config, + initRegisters: {Register.x10: 0x8000000000000010}, + nextPc: 0x38, + ); + }, + ); +} diff --git a/packages/river_hdl/test/interconnect/core_interconnect_test.dart b/packages/river_hdl/test/interconnect/core_interconnect_test.dart new file mode 100644 index 0000000..d38aeb6 --- /dev/null +++ b/packages/river_hdl/test/interconnect/core_interconnect_test.dart @@ -0,0 +1,322 @@ +import 'dart:async'; + +import 'package:rohd/rohd.dart'; +import 'package:rohd_hcl/rohd_hcl.dart' hide DataPortInterface, DataPortGroup; +import 'package:river/river.dart'; +import 'package:river_hdl/river_hdl.dart'; +import 'package:test/test.dart'; + +/// Multi-interconnect support: the River core emits a Wishbone master; Harbor's +/// bridges convert it to AXI4 or TileLink. These tests run a real program with +/// the core's bus routed through each interconnect (via the Harbor bridges) into +/// a memory slave, and check the architectural result is identical, proving the +/// core works over Wishbone, AXI4, and TileLink. See project_hdl_prefetch / +/// Harbor bus infra. +enum Interconnect { wishbone, axi4, tilelink } + +/// Wire a Wishbone MASTER interface `wb` to a MemoryModel-backed slave. +void wishboneMemorySlave( + WishboneInterface wb, + Logic clk, + Logic reset, + SparseMemoryStorage storage, + int dataWidth, + int addrWidth, +) { + final memRead = DataPortInterface(dataWidth, addrWidth); + final memWrite = DataPortInterface(dataWidth, addrWidth); + // ignore: unused_local_variable + final mem = MemoryModel( + clk, + reset, + [wrapWriteForRegisterFile(memWrite)], + [wrapReadForRegisterFile(memRead, clk: clk, readLatency: 0)], + readLatency: 0, + storage: storage, + ); + memRead.en <= wb.cyc & wb.stb & ~wb.we; + memRead.addr <= wb.adr; + memWrite.en <= wb.cyc & wb.stb & wb.we; + memWrite.addr <= wb.adr; + memWrite.data <= wb.datMosi; + final ackReg = Logic(name: 'slaveAck'); + final readyForAck = wb.we | memRead.valid; + Sequential(clk, [ + If( + reset, + then: [ackReg < 0], + orElse: [ + If( + wb.cyc & wb.stb & ~ackReg & readyForAck, + then: [ackReg < 1], + orElse: [ackReg < 0], + ), + ], + ), + ]); + wb.ack <= ackReg; + wb.datMiso <= memRead.data; +} + +Future interconnectTest( + String memString, + Map regStates, + RiverCoreConfig config, + Interconnect ic, { + Map memStates = const {}, + int nextPc = 4, +}) async { + final clk = SimpleClockGenerator(20).clk; + final reset = Logic(); + final addrWidth = config.mxlen.size; + final dataWidth = config.mxlen.size; + final wbConfig = WishboneConfig( + addressWidth: addrWidth, + dataWidth: dataWidth, + selWidth: dataWidth ~/ 8, + ); + final core = RiverCore(config, busConfig: wbConfig); + core.input('clk').srcConnection! <= clk; + core.input('reset').srcConnection! <= reset; + await core.build(); + + final storage = SparseMemoryStorage( + addrWidth: addrWidth, + dataWidth: dataWidth, + alignAddress: (addr) => addr, + onInvalidRead: (addr, w) => LogicValue.filled(w, LogicValue.zero), + ); + + // Reconstruct the core's Wishbone master from its exposed ports. + final coreWb = WishboneInterface(wbConfig); + coreWb.cyc <= core.output('dataBus_CYC'); + coreWb.stb <= core.output('dataBus_STB'); + coreWb.we <= core.output('dataBus_WE'); + coreWb.adr <= core.output('dataBus_ADR'); + coreWb.datMosi <= core.output('dataBus_DAT_MOSI'); + coreWb.sel <= core.output('dataBus_SEL'); + core.input('dataBus_ACK').srcConnection! <= coreWb.ack; + core.input('dataBus_DAT_MISO').srcConnection! <= coreWb.datMiso; + + switch (ic) { + case Interconnect.wishbone: + wishboneMemorySlave(coreWb, clk, reset, storage, dataWidth, addrWidth); + case Interconnect.tilelink: + // core WB -> TileLink -> WB memory (round-trip through both TL bridges). + final tlConfig = TileLinkConfig( + addressWidth: addrWidth, + dataWidth: dataWidth, + ); + final tl = TileLinkInterface(tlConfig); + WishboneToTileLinkBridge(coreWb, tl); + final memWb = WishboneInterface(wbConfig); + TileLinkToWishboneBridge(tl, memWb); + wishboneMemorySlave(memWb, clk, reset, storage, dataWidth, addrWidth); + case Interconnect.axi4: + // core WB -> AXI4 -> AXI4 memory slave. + // user/sideband channels are unused by the bridge; keep them 0-width + // (rohd_hcl caps *userWidth at 16). + final axiRead = Axi4ReadInterface( + addrWidth: addrWidth, + dataWidth: dataWidth, + aruserWidth: 0, + ruserWidth: 0, + ); + final axiWrite = Axi4WriteInterface( + addrWidth: addrWidth, + dataWidth: dataWidth, + awuserWidth: 0, + wuserWidth: 0, + buserWidth: 0, + ); + WishboneToAxi4Bridge(coreWb, axiRead, axiWrite); + _axi4MemorySlave( + axiRead, + axiWrite, + clk, + reset, + storage, + dataWidth, + addrWidth, + ); + } + + reset.inject(1); + Simulator.registerAction(20, () { + reset.put(0); + storage.loadMemString(memString); + }); + Simulator.setMaxSimTime(100000); + unawaited(Simulator.run()); + await clk.nextPosedge; + while (reset.value.toBool()) { + await clk.nextPosedge; + } + for (var i = 0; i < 5000; i++) { + await clk.nextPosedge; + final pc = core.pipeline.nextPc.value; + if (pc.isValid && pc.toInt() == nextPc) break; + } + await Simulator.endSimulation(); + await Simulator.simulationEnded; + + for (final regState in regStates.entries) { + final value = core.regs.getData(LogicValue.ofInt(regState.key.value, 5))!; + expect(value.toInt(), regState.value, reason: '${regState.key}=$value'); + } + for (final memState in memStates.entries) { + expect( + storage.getData(LogicValue.ofInt(memState.key, dataWidth))!.toInt(), + memState.value, + ); + } +} + +/// A minimal single-beat AXI4 memory slave backed by a MemoryModel. +void _axi4MemorySlave( + Axi4ReadInterface axiRead, + Axi4WriteInterface axiWrite, + Logic clk, + Logic reset, + SparseMemoryStorage storage, + int dataWidth, + int addrWidth, +) { + final memRead = DataPortInterface(dataWidth, addrWidth); + final memWrite = DataPortInterface(dataWidth, addrWidth); + // ignore: unused_local_variable + final mem = MemoryModel( + clk, + reset, + [wrapWriteForRegisterFile(memWrite)], + [wrapReadForRegisterFile(memRead, clk: clk, readLatency: 0)], + readLatency: 0, + storage: storage, + ); + + // Read channel: always ready to accept AR; one-cycle later return R. + axiRead.arReady <= Const(1); + memRead.en <= axiRead.arValid; + memRead.addr <= axiRead.arAddr.getRange(0, addrWidth); + final rValidReg = Logic(name: 'axiRValid'); + final rDataReg = Logic(name: 'axiRData', width: dataWidth); + Sequential(clk, [ + If( + reset, + then: [rValidReg < 0, rDataReg < 0], + orElse: [ + // Pulse R the cycle after a valid read request (latency-0 memory). + rValidReg < (axiRead.arValid & ~(rValidReg & axiRead.rReady)), + rDataReg < memRead.data, + ], + ), + ]); + axiRead.rValid <= rValidReg; + axiRead.rData <= rDataReg.zeroExtend(axiRead.dataWidth); + if (axiRead.rResp != null) axiRead.rResp! <= Const(0, width: 2); + if (axiRead.rId != null) axiRead.rId! <= Const(0, width: axiRead.idWidth); + if (axiRead.rLast != null) axiRead.rLast! <= Const(1); + + // Write channel: accept AW+W, commit, then B. + axiWrite.awReady <= Const(1); + axiWrite.wReady <= Const(1); + final doWrite = axiWrite.awValid & axiWrite.wValid; + memWrite.en <= doWrite; + memWrite.addr <= axiWrite.awAddr.getRange(0, addrWidth); + memWrite.data <= axiWrite.wData.getRange(0, dataWidth); + final bValidReg = Logic(name: 'axiBValid'); + Sequential(clk, [ + If( + reset, + then: [bValidReg < 0], + orElse: [bValidReg < (doWrite & ~(bValidReg & axiWrite.bReady))], + ), + ]); + axiWrite.bValid <= bValidReg; + if (axiWrite.bResp != null) axiWrite.bResp! <= Const(0, width: 2); + if (axiWrite.bId != null) axiWrite.bId! <= Const(0, width: axiWrite.idWidth); +} + +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + RiverCoreConfig cfg() => RiverCoreConfig( + clock: HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ), + mxlen: RiscVMxlen.rv32, + extensions: [rv32i, rvZicsr, rvZifencei], + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv32, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + executionMode: ExecutionMode.inOrder, + ); + + // A store + load + register ops: exercises bus READ (fetch + load) and WRITE + // (store) over the interconnect. sw x5,0(x10); lw x6,0(x10). + // addi x10,x0,0x100 ; addi x5,x0,0x123 ; sw x5,0(x10) ; + // nop nop ; lw x6,0(x10) ; nop tail + int iimm(int imm, int rs1, int f3, int rd) => + (imm << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x13; + int s(int imm, int rs2, int rs1, int f3) => + (((imm >> 5) & 0x7F) << 25) | + (rs2 << 20) | + (rs1 << 15) | + (f3 << 12) | + ((imm & 0x1F) << 7) | + 0x23; + int lw(int imm, int rs1, int rd) => + (imm << 20) | (rs1 << 15) | (0x2 << 12) | (rd << 7) | 0x03; + String prog(List words) { + final sb = StringBuffer('@0\n'); + for (final w in words) { + for (var i = 0; i < 4; i++) { + sb.write(((w >> (i * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + return '$sb\n'; + } + + final program = prog([ + iimm(0x100, 0, 0x0, 10), + iimm(0x123, 0, 0x0, 5), + s(0, 5, 10, 0x2), + 0x00000013, + 0x00000013, + lw(0, 10, 6), + ...List.filled(6, 0x00000013), + ]); + final expectedRegs = { + Register.x10: 0x100, + Register.x5: 0x123, + Register.x6: 0x123, + }; + const expectedNextPc = 0x2C; + final expectedMem = {0x100: 0x123}; + + for (final ic in Interconnect.values) { + test( + 'core runs over ${ic.name} interconnect', + timeout: Timeout(Duration(seconds: 60)), + () async { + await interconnectTest( + program, + expectedRegs, + cfg(), + ic, + nextPc: expectedNextPc, + memStates: expectedMem, + ); + }, + ); + } +} diff --git a/packages/river_hdl/test/interconnect/creek_boot_uart_test.dart b/packages/river_hdl/test/interconnect/creek_boot_uart_test.dart new file mode 100644 index 0000000..ebcdf8f --- /dev/null +++ b/packages/river_hdl/test/interconnect/creek_boot_uart_test.dart @@ -0,0 +1,134 @@ +// Boots the exact creek SoC gateware (rc1-s core + maskrom hello program + +// SRAM + ns16550a UART + wishbone fabric) in a ROHD simulation with a +// passthrough clock and external reset (NO target, so the EHXPLLL/POR/LOCK +// path is deliberately out of the picture). This partitions the "dead silent +// on OrangeCrab" bug: if the banner decodes out of uart_tx here, the gateware +// logic is correct and the silence is the physical PLL clock path. If it does +// NOT, the bug is in the core/maskrom/SRAM/UART/bus logic. +import 'dart:async'; + +import 'package:rohd/rohd.dart'; +import 'package:river_hdl/river_hdl.dart'; +import 'package:test/test.dart'; + +void main() { + // NOTE: this boots the full SoC and runs ~27k cycles of the microcode core, + // which the interpreted ROHD simulator cannot push fast enough (>15 min). The + // fast, definitive integration proof is the Verilator harness driven by + // `bin/gen_sim_sv.dart` (see that file): it streams "Hello from River!" out of + // uart_tx in ~0.1s. The two silicon fixes this exercised are locked in by fast + // unit tests: river_adl li zero-extension, mmu sub-word load lane-shift, and + // harbor sram SEL byte-store. Kept here, skipped, to document the flow. + test( + 'creek hello banner streams out of uart_tx (logic-only, no PLL)', + skip: + 'too slow for ROHD sim; use the Verilator harness (bin/gen_sim_sv.dart)', + () async { + // Small clock so the baked UART divisor (clockHz / 115200) is tiny and the + // banner streams in a few thousand sim cycles. The logic under test is + // identical to the 24 MHz build; only the divisor immediate differs. + const clockHz = 1152000; // divisor = 1152000 / 115200 = 10 + const divisor = clockHz ~/ 115200; + + final config = RiverGenIpConfig( + name: 'creek_v1', + cores: const ['rc1-s'], + clockFrequency: clockHz, + oscFrequency: clockHz, // equal -> passthrough clock in sim + devices: [ + Device.parse('flash:0x20000000:16M'), + Device.parse('sram:0x80000000:32K'), + Device.parse('clint:0x02000000'), + Device.parse('plic:0x04000000'), + Device.parse('uart:0x10000000:ns16550a'), + ], + // Expose uart tx/rx at the top so the testbench can read them. The + // FPGA pin names are irrelevant with no target. + pins: [ + PinAssignment.parse('uart_tx=uart@tx:N17'), + PinAssignment.parse('uart_rx=uart@rx:M18'), + ], + // no target -> sim passthrough clock + real external reset pin + bootProgram: 'hello', + ); + + final soc = await config.buildSoC(); + + final clk = SimpleClockGenerator(10).clk; + final reset = Logic(name: 'reset'); + + soc.input('clk').srcConnection! <= clk; + soc.input('reset').srcConnection! <= reset; + // UART RX idle-high so the receive engine stays quiet. + soc.input('uart_rx').srcConnection! <= Const(1); + + await soc.build(); + + final tx = soc.output('uart_tx'); + + reset.inject(1); + Simulator.setMaxSimTime(20000000); + unawaited(Simulator.run()); + + // Hold reset a few cycles, then release. + for (var i = 0; i < 8; i++) { + await clk.nextPosedge; + } + reset.inject(0); + + // Decode the 8N1 serial stream on uart_tx. Sample once per sysclk; on a + // falling edge (start bit) wait 1.5 bit-periods to land mid-bit0, then read + // 8 data bits LSB-first spaced one bit-period apart. + final received = []; + final sb = StringBuffer(); + var prev = 1; + const maxCycles = 200000; + for (var cycle = 0; cycle < maxCycles; cycle++) { + await clk.nextPosedge; + final cur = tx.value.isValid ? tx.value.toInt() : 1; + if (prev == 1 && cur == 0) { + // Start bit detected. Advance to the middle of bit 0. + for (var w = 0; w < divisor + divisor ~/ 2; w++) { + await clk.nextPosedge; + cycle++; + } + var byte = 0; + for (var b = 0; b < 8; b++) { + final bit = tx.value.isValid ? tx.value.toInt() & 1 : 1; + byte |= bit << b; + for (var w = 0; w < divisor; w++) { + await clk.nextPosedge; + cycle++; + } + } + received.add(byte); + if (byte >= 0x20 && byte < 0x7f) { + sb.writeCharCode(byte); + } else { + sb.write('[${byte.toRadixString(16).padLeft(2, '0')}]'); + } + prev = tx.value.isValid ? tx.value.toInt() : 1; + // Stop once we have enough to recognize the banner. + if (received.length >= 19) break; + continue; + } + prev = cur; + } + + await Simulator.endSimulation(); + await Simulator.simulationEnded; + + // ignore: avoid_print + print('UART bytes (${received.length}): $sb'); + + final text = String.fromCharCodes( + received.where((b) => b >= 0x20 && b < 0x7f), + ); + expect( + text, + contains('Hello from River!'), + reason: 'decoded uart_tx stream was: $sb', + ); + }, + ); +} diff --git a/packages/river_hdl/test/interconnect/creek_ddrlevel_train_hang_test.dart b/packages/river_hdl/test/interconnect/creek_ddrlevel_train_hang_test.dart new file mode 100644 index 0000000..b224dc7 --- /dev/null +++ b/packages/river_hdl/test/interconnect/creek_ddrlevel_train_hang_test.dart @@ -0,0 +1,397 @@ +// Reproduces (or refutes) the OrangeCrab DDR train-control read HANG in a FULL +// creek SoC ROHD simulation, with full wishbone-bus visibility. +// +// On hardware the creek `ddrlevel` firmware prints its UART self-test +// `12345678` then HANGS on the FIRST train-control STATUS read (`lw` at +// 0x88000018). The controller-only sim (ddr_train_soc_test.dart) acks a +// hand-built `lui` program fine, but that test reproduces a hang only with a +// DELIBERATELY naive `lui` that sign-extends bit 31. The real firmware does NOT +// use raw `lui`: RiverDdrLevel builds the STATUS address with `li(regStatus)`, +// and `li` (river_adl instruction_set.dart) already zero-extends bit-31 +// addresses on RV64. So the open question this test answers definitively is: +// does the ACTUAL ddrlevel firmware, in the SAME full SoC the hardware uses, +// reproduce the hang? +// +// This test boots the FULL creek SoC (rc1-s core + SRAM + flash + clint + plic +// + ns16550a UART + the OrangeCrab DDR3 controller WITH the train-control +// window, all on the wishbone fabric) with `--boot-program ddrlevel`, a +// passthrough clock and an external reset (no PLL/target). It taps the core's +// data-bus master and logs the FIRST access into the train-control window +// [0x88000000, 0x88001000): the exact ADR presented (sign-extended or not), +// whether CYC&STB assert, and whether any slave ACKs. That single logged line +// is the smoking gun that resolves the contradiction. +import 'dart:async'; + +import 'package:river/river.dart' show HarborClockConfig, HarborFixedClockRate; +import 'package:river_maskrom/river_maskrom.dart' show RiverDdrLevel; +import 'package:rohd/rohd.dart'; +import 'package:river_hdl/river_hdl.dart'; +import 'package:test/test.dart'; + +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + // FAST, default-suite guard (no sim): the firmware must build the train- + // control STATUS address 0x88000018 as a ZERO-extended positive RV64 value, + // not a sign-extended `lui`. This is the load-bearing fact that resolves the + // hardware-hang contradiction without paying for the multi-minute full-SoC + // sim below: `li(0x88000018)` already applies the slli32/srli32 zero-extend + // (river_adl instruction_set.dart), so the bus sees 0x0000000088000018 (which + // the DDR slave's [base, base+size+trainCtrlSize) decode routes and ctrlAcks), + // NOT 0xFFFFFFFF88000018 (which no slave decodes -> the only sign-ext hang). + test( + 'ddrlevel materializes the 0x88000018 STATUS address zero-extended ' + '(not a sign-extended lui) - the train-control hang precondition', + () async { + final coreClock = HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(1152000), + ); + // rc1-s is the creek core; reuse genip's exact ISA build for it. + final config = RiverGenIpConfig( + name: 'creek_v1', + cores: const ['rc1-s'], + clockFrequency: 1152000, + oscFrequency: 1152000, + devices: [ + Device.parse('dram:0x80000000:128M:orangecrab'), + Device.parse('uart:0x10000000:ns16550a'), + ], + ); + final coreConfig = config.buildCoreConfig(coreClock, 'rc1-s', hartId: 0); + + final fw = RiverDdrLevel( + isa: coreConfig.isa, + uartBase: 0x10000000, + dramBase: 0x80000000, + trainCtrlBase: 0x88000000, // dramBase + 128M + clockHz: 1152000, + ); + await fw.build(); + final bin = fw.generateBinary(); + final words = []; + for (var i = 0; i + 3 < bin.length; i += 4) { + words.add( + bin[i] | (bin[i + 1] << 8) | (bin[i + 2] << 16) | (bin[i + 3] << 24), + ); + } + + // Find the `li(0x88000018)` -> `lw` sequence: a `LUI rd, 0x88000` whose + // i+1=ADDI(+24), i+2=SLLI 32, i+3=SRLI 32 (the zero-extension), i+4=LOAD. + // The presence of the SLLI32/SRLI32 pair proves the address is corrected. + var foundStatusLoad = false; + for (var i = 0; i + 4 < words.length; i++) { + final lui = words[i]; + if ((lui & 0x7f) != 0x37) continue; // LUI + if (((lui >> 12) & 0xfffff) != 0x88000) continue; // imm 0x88000 + final addi = words[i + 1]; + final slli = words[i + 2]; + final srli = words[i + 3]; + final load = words[i + 4]; + final isAddi24 = + (addi & 0x7f) == 0x13 && + ((addi >> 12) & 0x7) == 0 && + ((addi >> 20) & 0xfff) == 24; + final isSlli32 = + (slli & 0x7f) == 0x13 && + ((slli >> 12) & 0x7) == 1 && + ((slli >> 20) & 0x3f) == 32; + final isSrli32 = + (srli & 0x7f) == 0x13 && + ((srli >> 12) & 0x7) == 5 && + ((srli >> 20) & 0x3f) == 32; + final isLoad = (load & 0x7f) == 0x03; // LW/LD + if (isAddi24 && isSlli32 && isSrli32 && isLoad) { + foundStatusLoad = true; + break; + } + } + + // There must be NO bare `lui` of the STATUS address feeding a load directly + // without the zero-extension (that would be the sign-extension hang). + var foundNakedSignExt = false; + for (var i = 0; i + 1 < words.length; i++) { + final lui = words[i]; + if ((lui & 0x7f) != 0x37) continue; + if (((lui >> 12) & 0xfffff) != 0x88000) continue; + final rd = (lui >> 7) & 0x1f; + final addi = words[i + 1]; + final next2 = i + 2 < words.length ? words[i + 2] : 0; + // lui rd,0x88000 ; addi rd,rd,24 ; (no slli/srli between) + final isAddi24Same = + (addi & 0x7f) == 0x13 && + ((addi >> 7) & 0x1f) == rd && + ((addi >> 15) & 0x1f) == rd && + ((addi >> 20) & 0xfff) == 24; + final next2IsLoadOfRd = + (next2 & 0x7f) == 0x03 && ((next2 >> 15) & 0x1f) == rd; + if (isAddi24Same && next2IsLoadOfRd) foundNakedSignExt = true; + } + + expect( + foundStatusLoad, + isTrue, + reason: + 'ddrlevel must build 0x88000018 with the slli32/srli32 ' + 'zero-extension before the STATUS lw (the lui sign-extension fix)', + ); + expect( + foundNakedSignExt, + isFalse, + reason: + 'ddrlevel must NOT load STATUS from a naked sign-extended lui ' + '(that is the only address-construction hang mechanism)', + ); + }, + ); + + // The hardware creek/orangecrab map (devices.nix base + orangecrab override), + // collapsed to the single-clock passthrough form so the ROHD sim is tractable + // (osc == core => no CDC; the DDR control window is served on the bus clock + // regardless, so the control-read path under test is identical). + // + // dram 0x80000000 : 128M : orangecrab -> trainCtrlBase 0x88000000 + // sram 0x08000000 : 32K + // flash 0x20000000 : 16M + // clint 0x02000000, plic 0x04000000, uart 0x10000000 ns16550a + // + // trainCtrlBase = dramBase + dramSize = 0x80000000 + 0x08000000 = 0x88000000, + // STATUS (reg3) at 0x88000018 - the exact address the hardware hangs on, with + // bit 31 set (the case that would expose an RV64 lui sign-extension trap). + // + // Small clock so the baked UART divisor (clockHz / 115200) is tiny and the + // self-test streams in a few thousand sim cycles. The logic under test is + // identical to the 48 MHz build; only the divisor immediate differs. + const clockHz = 1152000; // divisor = 10 + const divisor = clockHz ~/ 115200; + const trainCtrlLo = 0x88000000; + const trainCtrlHi = 0x88001000; + const statusAddr = 0x88000018; + + test( + 'creek ddrlevel: full-SoC wishbone visibility at the first train-control ' + 'read (resolves the hardware hang contradiction)', + // The microcode core is slow under the interpreted ROHD simulator. We only + // need to reach the FIRST train-control access (right after the 12345678 + // self-test print), which is a few thousand cycles, not the full 640-combo + // sweep. Budgeted accordingly; kept runnable but not in the default fast + // suite (mirrors the sibling banner test's rationale). + timeout: const Timeout(Duration(minutes: 20)), + skip: + 'slow under interpreted ROHD sim; run explicitly to reproduce/refute ' + 'the train-control hang (dart test ' + 'test/interconnect/creek_ddrlevel_train_hang_test.dart)', + () async { + final config = RiverGenIpConfig( + name: 'creek_v1', + cores: const ['rc1-s'], + clockFrequency: clockHz, + oscFrequency: clockHz, // equal -> passthrough clock, single domain + devices: [ + Device.parse('flash:0x20000000:16M'), + Device.parse('sram:0x08000000:32K'), + Device.parse('dram:0x80000000:128M:orangecrab'), + Device.parse('clint:0x02000000'), + Device.parse('plic:0x04000000'), + Device.parse('uart:0x10000000:ns16550a'), + ], + pins: [ + PinAssignment.parse('uart_tx=uart@tx:N17'), + PinAssignment.parse('uart_rx=uart@rx:M18'), + ], + bootProgram: 'ddrlevel', + ); + + final soc = await config.buildSoC(); + + final clk = SimpleClockGenerator(10).clk; + final reset = Logic(name: 'reset'); + + soc.input('clk').srcConnection! <= clk; + soc.input('reset').srcConnection! <= reset; + soc.input('uart_rx').srcConnection! <= Const(1); + + await soc.build(); + + final tx = soc.output('uart_tx'); + + // Tap the core's data-bus wishbone master. Inside a built SoC these ports + // are already connected to the WishboneDecoder, so we OBSERVE them (the + // fabric drives ACK back into the core). These are exactly the signals the + // hardware decoder sees, so an ADR/ACK mismatch here is the hardware bug. + final core = soc.masters.first as RiverCore; + final adr = core.output('dataBus_ADR'); + final cyc = core.output('dataBus_CYC'); + final stb = core.output('dataBus_STB'); + final we = core.output('dataBus_WE'); + final ack = core.input('dataBus_ACK'); + + int? readv(Logic l) => l.value.isValid ? l.value.toInt() : null; + String hex(int? v) => + v == null ? 'X' : '0x${v.toRadixString(16).padLeft(16, '0')}'; + + reset.inject(1); + Simulator.setMaxSimTime(2000000000); + unawaited(Simulator.run()); + + for (var i = 0; i < 8; i++) { + await clk.nextPosedge; + } + reset.inject(0); + + // --- UART decode (liveness proof: 12345678 must emit) --------------- + final received = []; + final sb = StringBuffer(); + var prev = 1; + + // --- Wishbone watch (the smoking gun) ------------------------------- + // Log the FIRST access whose ADR lands in [0x88000000, 0x88001000), and + // the ADR of the access right after the 12345678 print. Also count how + // many cycles the core then waits without an ack. + var sawSelfTest = false; + var firstCtrlLogged = false; + var firstPostPrintLogged = false; + var ctrlAckSeen = false; + var ctrlWaitCycles = 0; + int? prevAdr; + + const maxCycles = 4000000; + var emittedDiag = false; + + for (var cycle = 0; cycle < maxCycles; cycle++) { + await clk.nextPosedge; + + // Wishbone observation, every cycle. + final a = readv(adr); + final c = readv(cyc) ?? 0; + final s = readv(stb) ?? 0; + final w = readv(we) ?? 0; + final k = readv(ack) ?? 0; + + // The access right after the self-test print: log the first distinct + // bus address presented once 12345678 has streamed. + if (sawSelfTest && !firstPostPrintLogged && c == 1 && s == 1) { + if (a != prevAdr) { + // ignore: avoid_print + print( + 'POST-PRINT first bus access: ADR=${hex(a)} ' + 'CYC=$c STB=$s WE=$w ACK=$k', + ); + firstPostPrintLogged = true; + } + } + + // First train-control-window access. + final inCtrl = a != null && a >= trainCtrlLo && a < trainCtrlHi; + // Also catch the sign-extended form 0xFFFFFFFF_88000018 explicitly. + final lowMatchesStatus = a != null && (a & 0xFFFFFFFF) == statusAddr; + if (!firstCtrlLogged && + c == 1 && + s == 1 && + (inCtrl || lowMatchesStatus)) { + final low32 = (a & 0xFFFFFFFF).toRadixString(16); + // ignore: avoid_print + print( + 'FIRST train-control access @cycle $cycle: ' + 'ADR=${hex(a)} (low32=0x$low32) ' + 'CYC=$c STB=$s WE=$w ACK=$k ' + 'inWindow=$inCtrl signExtended=${a > 0xFFFFFFFF}', + ); + firstCtrlLogged = true; + } + if (firstCtrlLogged && !ctrlAckSeen) { + if (k == 1) { + ctrlAckSeen = true; + // ignore: avoid_print + print( + 'train-control access ACKED after $ctrlWaitCycles wait ' + 'cycles: ADR=${hex(a)} ACK=$k', + ); + } else if (c == 1 && s == 1) { + ctrlWaitCycles++; + } + } + if (c == 1 && s == 1) prevAdr = a; + + // UART decode (sample once per sysclk; mid-bit on falling edge). + final cur = tx.value.isValid ? tx.value.toInt() : 1; + if (prev == 1 && cur == 0) { + for (var x = 0; x < divisor + divisor ~/ 2; x++) { + await clk.nextPosedge; + cycle++; + } + var byte = 0; + for (var b = 0; b < 8; b++) { + final bit = tx.value.isValid ? tx.value.toInt() & 1 : 1; + byte |= bit << b; + for (var x = 0; x < divisor; x++) { + await clk.nextPosedge; + cycle++; + } + } + received.add(byte); + if (byte >= 0x20 && byte < 0x7f) { + sb.writeCharCode(byte); + } else { + sb.write('[${byte.toRadixString(16).padLeft(2, '0')}]'); + } + final text = String.fromCharCodes( + received.where((b) => b >= 0x20 && b < 0x7f), + ); + if (text.contains('12345678')) sawSelfTest = true; + // DIAG only prints if the STATUS read returned (control read acked). + if (text.contains('DIAG')) emittedDiag = true; + prev = tx.value.isValid ? tx.value.toInt() : 1; + // Stop early once we have the verdict either way: DIAG means the + // control read acked (no hang); a logged control access that never + // acks for a long stretch means the hang reproduced. + if (emittedDiag) break; + if (firstCtrlLogged && ctrlWaitCycles > 2000) break; + continue; + } + prev = cur; + + if (firstCtrlLogged && ctrlWaitCycles > 2000) break; + } + + await Simulator.endSimulation(); + await Simulator.simulationEnded; + + // ignore: avoid_print + print('UART bytes (${received.length}): $sb'); + // ignore: avoid_print + print( + 'summary: selfTest=$sawSelfTest firstCtrlLogged=$firstCtrlLogged ' + 'ctrlAckSeen=$ctrlAckSeen ctrlWaitCycles=$ctrlWaitCycles ' + 'emittedDiag=$emittedDiag', + ); + + // Liveness: the core must at least reach the self-test print. + final text = String.fromCharCodes( + received.where((b) => b >= 0x20 && b < 0x7f), + ); + expect( + text, + contains('12345678'), + reason: 'core must emit the 12345678 self-test (decoded: $sb)', + ); + + // The definitive question: did the train-control STATUS read ack? + // If DIAG emits or the control access acked, the full-SoC RTL does NOT + // reproduce the hang (the control plane is correct, so the hardware hang + // is a silicon/analog/config effect needing board instrumentation). If + // the control access never acked, the hang reproduced and the logged ADR + // above pinpoints the mechanism. + expect( + ctrlAckSeen || emittedDiag, + isTrue, + reason: + 'train-control STATUS read at 0x88000018 never acked: the ' + 'hardware hang reproduced in full-SoC RTL. See the logged FIRST ' + 'train-control access ADR/CYC/STB/ACK above for the mechanism.', + ); + }, + ); +} diff --git a/packages/river_hdl/test/interconnect/ddr_train_soc_test.dart b/packages/river_hdl/test/interconnect/ddr_train_soc_test.dart new file mode 100644 index 0000000..0a82f0e --- /dev/null +++ b/packages/river_hdl/test/interconnect/ddr_train_soc_test.dart @@ -0,0 +1,328 @@ +import 'dart:async'; + +import 'package:rohd/rohd.dart'; +import 'package:rohd_hcl/rohd_hcl.dart' hide DataPortInterface, DataPortGroup; +import 'package:river/river.dart'; +import 'package:river_hdl/river_hdl.dart'; +import 'package:test/test.dart'; + +import '../matrix_encoders.dart'; + +/// End-to-end: the River CPU drives the opt-in DDR read-training MMIO window. +/// A program writes RDTAP_TARGET + pulses CTL.SET, then polls STATUS until the +/// reported current tap reaches the target, proving the CPU -> bus -> control +/// register -> Ecp5DelayController path works as a whole SoC fragment. The DDR +/// array itself is never touched (its PHY is an analog blackbox); code/data +/// live in a separate memory slave. See project_ddr_training. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + /// Result of a CPU tap-walk run: the PC the core reached and the tap it read + /// back (null when the program ran away / never wrote the result register). + /// + /// Builds the SoC fragment (core + trainable DDR controller + code/data + /// memory), runs [program], and returns where the PC landed plus x1. + /// + /// [ddrBase] is the controller's array base; the control window then lives at + /// [ddrBase] + arraySize. The DRAM array span is a power of two + /// (HarborDdrConfig.orangeCrab => 128 MB), so the control window's address has + /// bit 31 set whenever [ddrBase] is 0x80000000 (the real OrangeCrab map), the + /// case that exposes the RV64 `lui` sign-extension trap. + /// + /// The address decode mirrors the genip SoC: the DDR slave owns + /// `[ddrBase, ddrBase + arraySize + trainCtrlSize)` (the same range the + /// Harbor WishboneDecoder derives from the controller's device-tree `reg`), + /// and the low code/data memory owns everything below. The decode itself is + /// the same unsigned `gte/lt` compare the real WishboneDecoder uses, so a + /// no-ack/hang here is a faithful reproduction of the fabric-level behavior. + Future<({int? reachedPc, int? tap})> runTapWalk({ + required int ddrBase, + required List program, + required int haltPc, + int maxCycles = 8000, + }) async { + const mxlen = RiscVMxlen.rv64; + final config = RiverCoreConfig( + clock: const HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ), + mxlen: mxlen, + extensions: [rv64i, rv32i, rvZicsr, rvZifencei, rvPriv], + interrupts: const [], + mmu: HarborMmuConfig( + mxlen: mxlen, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + ); + + final clk = SimpleClockGenerator(20).clk; + final reset = Logic(name: 'reset'); + final aw = mxlen.size; + final dw = mxlen.size; + final wbConfig = WishboneConfig( + addressWidth: aw, + dataWidth: dw, + selWidth: dw ~/ 8, + ); + + final core = RiverCore(config, busConfig: wbConfig); + core.input('clk').srcConnection! <= clk; + core.input('reset').srcConnection! <= reset; + + const ddrConfig = HarborDdrConfig.orangeCrab(); + final ddr = HarborDdrController( + config: ddrConfig, + baseAddress: ddrBase, + busAddressWidth: aw, + ); + ddr.input('clk').srcConnection! <= clk; + ddr.input('reset').srcConnection! <= reset; + + await core.build(); + await ddr.build(); + + // Core Wishbone master. + final wbCyc = core.output('dataBus_CYC'); + final wbStb = core.output('dataBus_STB'); + final wbWe = core.output('dataBus_WE'); + final wbAdr = core.output('dataBus_ADR'); + final wbDatMosi = core.output('dataBus_DAT_MOSI'); + + // Address decode the genip way: the DDR slave owns its declared bus range + // (array + train-control window), the same range the Harbor WishboneDecoder + // derives from the controller's device-tree `reg`. The compare is the same + // unsigned `gte/lt` the real decoder uses (WishboneDecoder.hit_i), so a high + // (bit-31-set) control address that the core sign-extends will miss this + // window exactly as it misses the fabric decoder on hardware. + final ctrlLo = ddrBase + ddrConfig.size; + // The committed clk90 DDR controller has no train-control window, so this + // whole SoC fragment no longer applies; the tests below are skipped. Use a + // nominal window size purely so the (skipped) helper still compiles. + const trainCtrlSize = 0x1000; + final ctrlHi = ctrlLo + trainCtrlSize; + final ctrlSel = + wbAdr.gte(Const(ctrlLo, width: aw)) & + wbAdr.lt(Const(ctrlHi, width: aw)); + + // Code/data memory slave: everything below the DDR array base. + final storage = SparseMemoryStorage( + addrWidth: aw, + dataWidth: dw, + alignAddress: (addr) => addr, + onInvalidRead: (addr, w) => LogicValue.filled(w, LogicValue.zero), + ); + final memRead = DataPortInterface(dw, aw); + final memWrite = DataPortInterface(dw, aw); + // The code/data memory owns everything the control window does not. Code + // always lives in the low region (below the control window), so a plain + // ~ctrlSel keeps the original low-window behavior and, in the high-window + // case, still serves instruction fetch at low addresses. A control access + // that the core sign-extends to a high address has bit 31 set and is NOT in + // the control window, so it lands here on ~ctrlSel - but its address is + // 0xFFFFFFFF_88.. which no real storage backs, and (critically) the + // sign-extended store address never matches the control window, so the + // DELAY controller is never reached. To make the HANG observable rather + // than silently served by this catch-all memory, restrict the memory slave + // to the genuine low region [0, ctrlLo): a high sign-extended access then + // selects NEITHER slave and no ack returns. + final memSel = wbAdr.lt(Const(ctrlLo, width: aw)); + // ignore: unused_local_variable + final mem = MemoryModel( + clk, + reset, + [wrapWriteForRegisterFile(memWrite)], + [wrapReadForRegisterFile(memRead, clk: clk, readLatency: 0)], + readLatency: 0, + storage: storage, + ); + memRead.en <= wbCyc & wbStb & ~wbWe & memSel; + memRead.addr <= wbAdr; + memWrite.en <= wbCyc & wbStb & wbWe & memSel; + memWrite.addr <= wbAdr; + memWrite.data <= wbDatMosi; + + final memAck = Logic(name: 'memAck'); + final memReady = wbWe | memRead.valid; + Sequential(clk, [ + If( + reset, + then: [memAck < 0], + orElse: [ + If( + wbCyc & wbStb & memSel & ~memAck & memReady, + then: [memAck < 1], + orElse: [memAck < 0], + ), + ], + ), + ]); + + // DDR control slave - drive its bus from the master. The slave address is + // window-relative (control offset above the array): the decoder subtracts + // the slave's range start, so present `wbAdr - ctrlLo` (== array-relative + // control offset 0x00..) low bits, matching what the controller decodes. + final ctrlOff = + (wbAdr - Const(ctrlLo, width: aw)) + Const(ddrConfig.size, width: aw); + ddr.input('bus_CYC').srcConnection! <= wbCyc & ctrlSel; + ddr.input('bus_STB').srcConnection! <= wbStb & ctrlSel; + ddr.input('bus_WE').srcConnection! <= wbWe; + ddr.input('bus_ADR').srcConnection! <= + ctrlOff.getRange(0, ddr.input('bus_ADR').width); + ddr.input('bus_DAT_MOSI').srcConnection! <= + wbDatMosi.getRange(0, ddr.input('bus_DAT_MOSI').width); + ddr.input('bus_SEL').srcConnection! <= + Const(0, width: ddr.input('bus_SEL').width); + final ddrAck = ddr.output('bus_ACK'); + final ddrMiso = ddr.output('bus_DAT_MISO'); + + // Merge the two slaves back onto the master. A control access that misses + // the window (sign-extended high address) selects NEITHER slave, so no ack + // is ever returned and the CPU stalls - the hardware control-window hang. + core.input('dataBus_ACK').srcConnection! <= mux(ctrlSel, ddrAck, memAck); + core.input('dataBus_DAT_MISO').srcConnection! <= + mux(ctrlSel, ddrMiso.zeroExtend(dw), memRead.data); + + String memString(List ws) { + final sb = StringBuffer(); + for (final w in ws) { + for (var b = 0; b < 4; b++) { + sb.write(((w >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + return sb.toString().trimRight(); + } + + reset.inject(1); + Simulator.registerAction(20, () { + reset.put(0); + storage.loadMemString(memString(program)); + }); + Simulator.setMaxSimTime(2000000); + unawaited(Simulator.run()); + + await clk.nextPosedge; + while (reset.value.toBool()) { + await clk.nextPosedge; + } + var reached = false; + for (var i = 0; i < maxCycles; i++) { + await clk.nextPosedge; + final pc = core.pipeline.nextPc.value; + if (pc.isValid && pc.toInt() == haltPc) { + reached = true; + break; + } + } + + await Simulator.endSimulation(); + await Simulator.simulationEnded; + + final pc = core.pipeline.nextPc.value; + final reachedPc = reached && pc.isValid ? pc.toInt() : null; + final x1v = core.regs.getData(LogicValue.ofInt(1, 5)); + final tap = (x1v != null && x1v.isValid) ? x1v.toInt() : null; + return (reachedPc: reachedPc, tap: tap); + } + + /// Tap-walk program. [baseSetup] builds the control-window base into x10 + /// (its length in instructions shifts every later PC), then the body writes + /// RDTAP_TARGET, pulses CTL.SET, and polls STATUS until currentTap == target. + /// x1 ends holding the trained tap. + ({List program, int haltPc}) tapWalkProgram(List baseSetup) { + const target = 12; + final body = [ + iimm(target, 0, 0x0, 11), // addi x11, x0, 12 + store(0x00, 11, 10, 0x2), // sw x11, 0x00(x10) RDTAP_TARGET = 12 + iimm(1, 0, 0x0, 11), // addi x11, x0, 1 + store(0x08, 11, 10, 0x2), // sw x11, 0x08(x10) CTL = SET + // loop: x12 = (STATUS >> 1) & 0x7F; if x12 != 12 goto loop + load(0x18, 10, 0x2, 12), // lw x12, 0x18(x10) STATUS + iimm(1, 12, 0x5, 12), // srli x12, x12, 1 + iimm(0x7F, 12, 0x7, 12), // andi x12, x12, 0x7F + iimm(target, 0, 0x0, 13), // addi x13, x0, 12 + branch(-16, 13, 12, 0x1), // bne x12, x13, loop + rtype(0x00, 0, 12, 0x0, 1), // add x1, x12, x0 -> x1 = tap + nop, + ]; + final program = [...baseSetup, ...body]; + final haltPc = (program.length - 1) * 4; + return (program: program, haltPc: haltPc); + } + + test('CPU walks the DDR read tap through the MMIO control window ' + '(low window, base 0)', () async { + // Array base 0; control window at 0x08000000 (the 128MB boundary, bit 31 + // clear). lui builds the base directly with no sign extension. + final p = tapWalkProgram([ + lui(0x08000, 10), // x10 = 0x08000000 (control window base) + ]); + final r = await runTapWalk( + ddrBase: 0, + program: p.program, + haltPc: p.haltPc, + ); + expect(r.reachedPc, p.haltPc, reason: 'program should reach the halt nop'); + expect(r.tap, 12, reason: 'CPU read the trained tap back as ${r.tap}'); + }, skip: 'committed clk90 DDR has no train-control MMIO window'); + + test('high control window (base 0x80000000): naive lui sign-extends and the ' + 'control access misses the window -> CPU hangs (hardware repro)', () async { + // dramBase = 0x80000000, control window at 0x88000000 (bit 31 SET). On RV64 + // `lui 0x88000` loads 0x88000000 then SIGN-EXTENDS bit 31, so x10 becomes + // 0xFFFFFFFF_88000000 and the store/load address is 0xFFFFFFFF_88000018, + // which is NOT inside [0x80000000, 0x88001000). No slave decodes it, no ack + // returns, and the CPU stalls forever on the first control store - exactly + // the OrangeCrab control-window hang. This is a CORE/firmware address-math + // trap, not an interconnect routing bug (the decode range already includes + // the train-control window via trainCtrlSize, and the unsigned gte/lt + // compare handles bit 31 fine - proven by the corrected-address case below). + final p = tapWalkProgram([ + lui(0x88000, 10), // x10 = 0xFFFFFFFF88000000 (sign-extended!) + ]); + // The stall is permanent (no ack ever returns), so a short budget proves + // it: a healthy run reaches the control window and walks 12 taps in ~150 + // cycles, so 600 cycles with the PC never reaching halt is a confirmed hang. + final r = await runTapWalk( + ddrBase: 0x80000000, + program: p.program, + haltPc: p.haltPc, + maxCycles: 600, + ); + expect( + r.reachedPc, + isNull, + reason: + 'sign-extended high control address must hang (no ack), ' + 'reproducing the hardware control-window hang', + ); + }, skip: 'committed clk90 DDR has no train-control MMIO window'); + + test('high control window (base 0x80000000): sign-extension-corrected base ' + 'reaches the window -> tap walk completes (SoC path is clean)', () async { + // The fix is in the ADDRESS MATH, not the HDL: clear the sign-extended upper + // 32 bits after lui (slli 32 then srli 32) so x10 holds the true + // 0x0000000088000000. The same decode + interconnect that hung above now + // routes the control access correctly and the tap walk completes, proving + // the SoC-level control plane (decode range, ack, delay controller) is X- + // clean and bit-31-correct - the only defect was the naive lui. + final p = tapWalkProgram([ + lui(0x88000, 10), // x10 = 0xFFFFFFFF88000000 + iimm(32, 10, 0x1, 10), // slli x10, x10, 32 -> 0x8800000000000000 + iimm(32, 10, 0x5, 10), // srli x10, x10, 32 -> 0x0000000088000000 + ]); + final r = await runTapWalk( + ddrBase: 0x80000000, + program: p.program, + haltPc: p.haltPc, + ); + expect(r.reachedPc, p.haltPc, reason: 'program should reach the halt nop'); + expect(r.tap, 12, reason: 'CPU read the trained tap back as ${r.tap}'); + }, skip: 'committed clk90 DDR has no train-control MMIO window'); +} diff --git a/packages/river_hdl/test/interconnect/soc_test.dart b/packages/river_hdl/test/interconnect/soc_test.dart new file mode 100644 index 0000000..339c4b0 --- /dev/null +++ b/packages/river_hdl/test/interconnect/soc_test.dart @@ -0,0 +1,147 @@ +import 'package:river/river.dart'; +import 'package:river_hdl/river_hdl.dart'; +import 'package:test/test.dart'; + +void main() { + group('DTS generation', () { + test('generates valid DTS for RV32 core', () { + final sysclk = HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ); + + final coreConfig = RiverCoreConfigV1.nano( + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv32, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + interrupts: [], + clock: sysclk, + resetVector: 0x20000000, + ); + + final cpus = [ + HarborCpu( + hartId: coreConfig.hartId, + isa: coreConfig.isa.implementsString, + clockFrequency: 48000000, + ), + ]; + + final generator = HarborDeviceTreeGenerator( + model: 'Stream V1', + compatible: 'midstall,stream-v1', + cpus: cpus, + ); + + final dts = generator.generate(); + + expect(dts, contains('/dts-v1/')); + expect(dts, contains('cpus')); + expect(dts, contains('riscv')); + }); + + test('generates DTS with MMU type for RV64', () { + final sysclk = HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ); + + final coreConfig = RiverCoreConfigV1.small( + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + hasSupervisorUserMemory: true, + hasMakeExecutableReadable: true, + ), + interrupts: [], + clock: sysclk, + resetVector: 0x80000000, + ); + + final cpus = [ + HarborCpu( + hartId: coreConfig.hartId, + isa: coreConfig.isa.implementsString, + clockFrequency: 48000000, + mmu: 'riscv,sv39', + ), + ]; + + final generator = HarborDeviceTreeGenerator( + model: 'Creek V1', + compatible: 'midstall,creek-v1', + cpus: cpus, + ); + + final dts = generator.generate(); + + expect(dts, contains('/dts-v1/')); + expect(dts, contains('cpus')); + expect(dts, contains('sv39')); + }); + }); + + group('GenIP peripheral mapping', () { + test('maps compatible strings to Harbor peripherals', () { + final supported = [ + 'river,sram', + 'river,flash', + 'ns16550a', + 'riscv,clint0', + 'riscv,plic0', + ]; + + final mappings = { + 'river,sram': true, + 'river,flash': true, + 'ns16550a': true, + 'riscv,clint0': true, + 'riscv,plic0': true, + 'river,gpio': false, + 'river,dram': false, + 'unknown,device': false, + }; + + for (final entry in mappings.entries) { + expect( + supported.contains(entry.key), + entry.value, + reason: '${entry.key} mapping', + ); + } + }); + + test( + 'a flash memory region builds a real XIP SPI controller, not SRAM', + () async { + final config = RiverGenIpConfig( + name: 'flash_test_soc', + cores: const ['rc1-n'], + clockFrequency: 48000000, + oscFrequency: 48000000, + devices: [ + Device.parse('flash:0x20000000:16M'), + Device.parse('sram:0x80000000:64K'), + Device.parse('uart:0x10000000:ns16550a'), + ], + ); + final soc = await config.buildSoC(); + await soc.build(); + final sv = soc.generateSynth(); + // The flash region is the XIP SPI controller (HarborSpiFlashController), + // which a maskrom/Weir BIOS executes in place. The SRAM region stays SRAM. + expect( + sv, + contains('HarborSpiFlashController'), + reason: 'flash must be a real XIP SPI flash controller', + ); + expect(sv, contains('HarborSram'), reason: 'sram region stays SRAM'); + }, + ); + }); +} diff --git a/packages/river_hdl/test/loadstore/rv32_inorder_test.dart b/packages/river_hdl/test/loadstore/rv32_inorder_test.dart new file mode 100644 index 0000000..ef0e5e5 --- /dev/null +++ b/packages/river_hdl/test/loadstore/rv32_inorder_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'loadstore'; + const mxlen = RiscVMxlen.rv32; + const uarch = Uarch.inOrder; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/loadstore/rv64_inorder_microcode_test.dart b/packages/river_hdl/test/loadstore/rv64_inorder_microcode_test.dart new file mode 100644 index 0000000..95f43f1 --- /dev/null +++ b/packages/river_hdl/test/loadstore/rv64_inorder_microcode_test.dart @@ -0,0 +1,22 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +/// In-order MICROCODE path (DynamicExecutionUnit + microcode ROM, +/// MicrocodeMode.full) for the 'loadstore' category, validated against the emulator +/// golden. This is the area-first path rc1-s (creek) uses on small FPGAs. Split +/// per-category so dart test parallelizes across isolates (one big file +/// accumulates heap across builds and times out - see project_parity / +/// feedback_test_parallelism). +void main() { + const category = 'loadstore'; + const mxlen = RiscVMxlen.rv64; + const uarch = Uarch.inOrder; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)} (microcode)', + matrixConfig(mxlen, uarch, category, microcodeMode: MicrocodeMode.full), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/loadstore/rv64_inorder_test.dart b/packages/river_hdl/test/loadstore/rv64_inorder_test.dart new file mode 100644 index 0000000..589f242 --- /dev/null +++ b/packages/river_hdl/test/loadstore/rv64_inorder_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'loadstore'; + const mxlen = RiscVMxlen.rv64; + const uarch = Uarch.inOrder; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/lsq/core_lsq_dual_test.dart b/packages/river_hdl/test/lsq/core_lsq_dual_test.dart new file mode 100644 index 0000000..0f1d5a6 --- /dev/null +++ b/packages/river_hdl/test/lsq/core_lsq_dual_test.dart @@ -0,0 +1,142 @@ +import 'package:river/river.dart'; +import 'package:rohd/rohd.dart'; +import 'package:test/test.dart'; + +import '../core_harness.dart'; + +/// LSQ Phase 4: memory ops co-dispatch in dual-issue slot 1. With a load-store +/// queue, the slot-1 eligibility predicate no longer forbids memory ops, they +/// still leave the issue queue one at a time (single mem port) and execute in +/// program order, so the queue sees them in order and store→load forwarding +/// covers intra-bundle aliasing. See project_hdl_lsq / project_hdl_dualdispatch. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + RiverCoreConfig dualLsqConfig() => RiverCoreConfig( + clock: HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ), + mxlen: RiscVMxlen.rv32, + extensions: [rv32i, rvZicsr, rvZifencei], + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv32, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + executionMode: ExecutionMode.outOfOrder, + speculativeFetch: true, + issueWidth: IssueWidth.dual, + loadStoreQueue: LoadStoreQueue.forwarding, + ); + + int iimm(int imm, int rs1, int f3, int rd) => + (imm << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x13; + int s(int imm, int rs2, int rs1, int f3) => + (((imm >> 5) & 0x7F) << 25) | + (rs2 << 20) | + (rs1 << 15) | + (f3 << 12) | + ((imm & 0x1F) << 7) | + 0x23; + int lw(int imm, int rs1, int rd) => + (imm << 20) | (rs1 << 15) | (0x2 << 12) | (rd << 7) | 0x03; + String prog(List words) { + final sb = StringBuffer('@0\n'); + for (final w in words) { + for (var i = 0; i < 4; i++) { + sb.write(((w >> (i * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + return '$sb\n'; + } + + // Bundles place a memory op in slot 1 (pc+4): a store co-dispatches with an + // ALU op, then a load co-dispatches with an ALU op, and the load forwards. + // 0x00 addi x10,x0,0x100 | 0x04 addi x5,x0,0x123 (ALU,ALU) + // 0x08 addi x6,x0,0x55 | 0x0C sw x5,0(x10) (ALU, STORE-in-slot1) + // 0x10 addi x9,x0,0x77 | 0x14 lw x7,0(x10) (ALU, LOAD-in-slot1) + // 0x18 addi x8,x0,0x66 | 0x1C nop + test( + 'dual+LSQ: memory ops co-dispatch in slot 1', + timeout: Timeout(Duration(seconds: 90)), + () => coreTest( + prog([ + iimm(0x100, 0, 0x0, 10), + iimm(0x123, 0, 0x0, 5), + iimm(0x55, 0, 0x0, 6), + s(0, 5, 10, 0x2), // sw x5, 0(x10) (slot 1) + iimm(0x77, 0, 0x0, 9), + lw(0, 10, 7), // lw x7, 0(x10) (slot 1) -> 0x123 + iimm(0x66, 0, 0x0, 8), + ...List.filled(9, 0x00000013), + ]), + { + Register.x10: 0x100, + Register.x5: 0x123, + Register.x6: 0x55, + Register.x9: 0x77, + Register.x7: 0x123, + Register.x8: 0x66, + }, + dualLsqConfig(), + nextPc: 0x40, + memStates: {0x100: 0x123}, + ), + ); + + // Two stores in one bundle (slot0+slot1 both stores) both reach memory: the + // slot-1 store is held one commit cycle so the store queue's commit pointer + // tracks each store (a pair retiring together would otherwise under-count). + // (A load+load bundle still deadlocks, see project_hdl_lsq; WIP.) + test( + 'dual+LSQ: two stores in one bundle both drain', + timeout: Timeout(Duration(seconds: 90)), + () => coreTest( + prog([ + iimm(0x100, 0, 0x0, 10), + iimm(0x200, 0, 0x0, 11), + iimm(0xAA, 0, 0x0, 5), + iimm(0xBB, 0, 0x0, 6), + s(0, 5, 10, 0x2), // sw x5,0(x10) (bundle: store+store) + s(0, 6, 11, 0x2), // sw x6,0(x11) + ...List.filled(10, 0x00000013), + ]), + {Register.x10: 0x100, Register.x11: 0x200}, + dualLsqConfig(), + nextPc: 0x40, + memStates: {0x100: 0xAA, 0x200: 0xBB}, + ), + ); + + // A run mixing store and load bundles: the store pair co-dispatches; the load + // pair falls back to single dispatch (load+load co-dispatch is disabled) and + // still reads back the correct values. + test( + 'dual+LSQ: store and load bundles read back', + timeout: Timeout(Duration(seconds: 90)), + () => coreTest( + prog([ + iimm(0x100, 0, 0x0, 10), + iimm(0x200, 0, 0x0, 11), + iimm(0xAA, 0, 0x0, 5), + iimm(0xBB, 0, 0x0, 6), + s(0, 5, 10, 0x2), + s(0, 6, 11, 0x2), + lw(0, 10, 7), // -> 0xAA + lw(0, 11, 8), // -> 0xBB + ...List.filled(10, 0x00000013), + ]), + {Register.x7: 0xAA, Register.x8: 0xBB}, + dualLsqConfig(), + nextPc: 0x44, + memStates: {0x100: 0xAA, 0x200: 0xBB}, + ), + ); +} diff --git a/packages/river_hdl/test/lsq/core_lsq_fwd_test.dart b/packages/river_hdl/test/lsq/core_lsq_fwd_test.dart new file mode 100644 index 0000000..4fc86b4 --- /dev/null +++ b/packages/river_hdl/test/lsq/core_lsq_fwd_test.dart @@ -0,0 +1,152 @@ +import 'package:river/river.dart'; +import 'package:rohd/rohd.dart'; +import 'package:test/test.dart'; + +import '../core_harness.dart'; + +/// Load-store queue Phase 2: store→load forwarding. A load whose address is +/// covered by an in-queue store takes the value directly (no bus, no waiting for +/// the store to drain); a non-aliasing load reads the bus immediately; the +/// youngest aliasing store wins. See project_hdl_lsq. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + RiverCoreConfig fwdConfig() => RiverCoreConfig( + clock: HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ), + mxlen: RiscVMxlen.rv32, + extensions: [rv32i, rvZicsr, rvZifencei], + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv32, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + executionMode: ExecutionMode.outOfOrder, + speculativeFetch: true, + loadStoreQueue: LoadStoreQueue.forwarding, + ); + + int iimm(int imm, int rs1, int f3, int rd) => + (imm << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x13; + int s(int imm, int rs2, int rs1, int f3) => + (((imm >> 5) & 0x7F) << 25) | + (rs2 << 20) | + (rs1 << 15) | + (f3 << 12) | + ((imm & 0x1F) << 7) | + 0x23; + int lw(int imm, int rs1, int rd) => + (imm << 20) | (rs1 << 15) | (0x2 << 12) | (rd << 7) | 0x03; + String prog(List words) { + final sb = StringBuffer('@0\n'); + for (final w in words) { + for (var i = 0; i < 4; i++) { + sb.write(((w >> (i * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + return '$sb\n'; + } + + // Store then load the same address: the load FORWARDS from the queue (the + // store has not drained yet, memLatency 2, so a bus read would be stale). + test( + 'fwd: store then load same address forwards', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + iimm(0x100, 0, 0x0, 10), // addi x10, x0, 0x100 + iimm(0x123, 0, 0x0, 5), // addi x5, x0, 0x123 + s(0, 5, 10, 0x2), // sw x5, 0(x10) + lw(0, 10, 6), // lw x6, 0(x10) -> 0x123 (forwarded) + ...List.filled(8, 0x00000013), + ]), + {Register.x10: 0x100, Register.x5: 0x123, Register.x6: 0x123}, + fwdConfig(), + nextPc: 0x20, + memStates: {0x100: 0x123}, + memLatency: 2, + ), + ); + + // Two stores to the SAME address, then a load: the YOUNGEST store's value is + // forwarded. + test( + 'fwd: youngest aliasing store wins', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + iimm(0x100, 0, 0x0, 10), // addi x10, x0, 0x100 + iimm(0xAA, 0, 0x0, 5), // addi x5, x0, 0xAA + iimm(0xBB, 0, 0x0, 6), // addi x6, x0, 0xBB + s(0, 5, 10, 0x2), // sw x5, 0(x10) (older) + s(0, 6, 10, 0x2), // sw x6, 0(x10) (younger) + lw(0, 10, 7), // lw x7, 0(x10) -> 0xBB (youngest) + ...List.filled(8, 0x00000013), + ]), + {Register.x10: 0x100, Register.x7: 0xBB}, + fwdConfig(), + nextPc: 0x2C, + memStates: {0x100: 0xBB}, + memLatency: 2, + ), + ); + + // Non-aliasing load reads the bus immediately (no forward, no wait): store to + // 0x100, load from preloaded 0x200. + test( + 'fwd: non-aliasing load reads memory', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + '${prog([ + iimm(0x100, 0, 0x0, 10), // addi x10, x0, 0x100 + iimm(0x200, 0, 0x0, 11), // addi x11, x0, 0x200 + iimm(0x123, 0, 0x0, 5), // addi x5, x0, 0x123 + s(0, 5, 10, 0x2), // sw x5, 0(x10) mem[0x100]=0x123 + lw(0, 11, 7), // lw x7, 0(x11) -> 0xDEAD (from memory) + ...List.filled(8, 0x00000013), + ])}@200\nad de 00 00\n', + {Register.x10: 0x100, Register.x7: 0xDEAD}, + fwdConfig(), + nextPc: 0x28, + memStates: {0x100: 0x123}, + memLatency: 2, + ), + ); + + // Two stores to different addresses, two loads: each load forwards from its + // own store with no waiting (memLatency 0, like the other OoO memory tests). + test( + 'fwd: two stores, two loads each forward', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + iimm(0x100, 0, 0x0, 10), // addi x10, x0, 0x100 + iimm(0x200, 0, 0x0, 11), // addi x11, x0, 0x200 + iimm(0xAA, 0, 0x0, 5), // addi x5, x0, 0xAA + iimm(0xBB, 0, 0x0, 6), // addi x6, x0, 0xBB + s(0, 5, 10, 0x2), // sw x5, 0(x10) mem[0x100]=0xAA + s(0, 6, 11, 0x2), // sw x6, 0(x11) mem[0x200]=0xBB + lw(0, 10, 7), // lw x7, 0(x10) -> 0xAA + lw(0, 11, 8), // lw x8, 0(x11) -> 0xBB + ...List.filled(10, 0x00000013), + ]), + { + Register.x10: 0x100, + Register.x11: 0x200, + Register.x7: 0xAA, + Register.x8: 0xBB, + }, + fwdConfig(), + nextPc: 0x44, + memStates: {0x100: 0xAA, 0x200: 0xBB}, + ), + ); +} diff --git a/packages/river_hdl/test/lsq/core_lsq_spec_test.dart b/packages/river_hdl/test/lsq/core_lsq_spec_test.dart new file mode 100644 index 0000000..19d26b0 --- /dev/null +++ b/packages/river_hdl/test/lsq/core_lsq_spec_test.dart @@ -0,0 +1,128 @@ +import 'package:river/river.dart'; +import 'package:rohd/rohd.dart'; +import 'package:test/test.dart'; + +import '../core_harness.dart'; + +/// LSQ Phase 3: speculative loads + disambiguation/replay. Loads may execute +/// ahead of a not-ready older store; a load queue records them, and when the +/// store resolves its address it CAMs the queue, a younger aliasing load that +/// read too early triggers a replay (re-fetch from after the store). See +/// project_hdl_lsq. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + RiverCoreConfig specConfig() => RiverCoreConfig( + clock: HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ), + mxlen: RiscVMxlen.rv32, + extensions: [rv32i, rvM, rvZicsr, rvZifencei], + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv32, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + executionMode: ExecutionMode.outOfOrder, + speculativeFetch: true, + loadStoreQueue: LoadStoreQueue.speculative, + ); + + int iimm(int imm, int rs1, int f3, int rd) => + (imm << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x13; + int r(int f7, int rs2, int rs1, int f3, int rd) => + (f7 << 25) | (rs2 << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x33; + int s(int imm, int rs2, int rs1, int f3) => + (((imm >> 5) & 0x7F) << 25) | + (rs2 << 20) | + (rs1 << 15) | + (f3 << 12) | + ((imm & 0x1F) << 7) | + 0x23; + int lw(int imm, int rs1, int rd) => + (imm << 20) | (rs1 << 15) | (0x2 << 12) | (rd << 7) | 0x03; + String prog(List words) { + final sb = StringBuffer('@0\n'); + for (final w in words) { + for (var i = 0; i < 4; i++) { + sb.write(((w >> (i * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + return '$sb\n'; + } + + // Store then two loads of the same address: both forward / read the store. + test( + 'spec: store then two loads same address', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + iimm(0x100, 0, 0x0, 10), + iimm(0xAA, 0, 0x0, 5), + s(0, 5, 10, 0x2), + lw(0, 10, 7), + lw(0, 10, 8), + ...List.filled(10, 0x00000013), + ]), + {Register.x7: 0xAA, Register.x8: 0xAA}, + specConfig(), + nextPc: 0x3C, + memStates: {0x100: 0xAA}, + ), + ); + + // Two stores, two loads to distinct addresses. + test( + 'spec: two stores, two loads distinct addresses', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + iimm(0x100, 0, 0x0, 10), + iimm(0x200, 0, 0x0, 11), + iimm(0xAA, 0, 0x0, 5), + iimm(0xBB, 0, 0x0, 6), + s(0, 5, 10, 0x2), + s(0, 6, 11, 0x2), + lw(0, 10, 7), + lw(0, 11, 8), + ...List.filled(10, 0x00000013), + ]), + {Register.x7: 0xAA, Register.x8: 0xBB}, + specConfig(), + nextPc: 0x44, + memStates: {0x100: 0xAA, 0x200: 0xBB}, + ), + ); + + // DISAMBIGUATION REPLAY: the store's data comes from a multi-cycle mul, so the + // store is not ready when the load (whose address is ready early) executes. + // The load speculatively reads 0x100 (stale), the mul resolves, the store + // executes and CAMs the load queue → violation → replay → the load re-reads + // the stored value (42). Without the replay it would keep the stale 0. + test( + 'spec: load bypasses slow store, replays on violation', + timeout: Timeout(Duration(seconds: 90)), + () => coreTest( + prog([ + iimm(0x100, 0, 0x0, 10), // addi x10, x0, 0x100 + iimm(7, 0, 0x0, 1), // addi x1, x0, 7 + iimm(6, 0, 0x0, 4), // addi x4, x0, 6 + r(0x01, 4, 1, 0x0, 5), // mul x5, x1, x4 -> 42 (multi-cycle) + s(0, 5, 10, 0x2), // sw x5, 0(x10) (data x5 late -> store not ready) + lw(0, 10, 6), // lw x6, 0(x10) bypasses; replays -> 42 + ...List.filled(10, 0x00000013), + ]), + {Register.x10: 0x100, Register.x5: 42, Register.x6: 42}, + specConfig(), + nextPc: 0x40, + memStates: {0x100: 42}, + ), + ); +} diff --git a/packages/river_hdl/test/lsq/core_lsq_test.dart b/packages/river_hdl/test/lsq/core_lsq_test.dart new file mode 100644 index 0000000..e0fdc06 --- /dev/null +++ b/packages/river_hdl/test/lsq/core_lsq_test.dart @@ -0,0 +1,139 @@ +import 'package:river/river.dart'; +import 'package:rohd/rohd.dart'; +import 'package:test/test.dart'; + +import '../core_harness.dart'; + +/// Load-store queue (Phase 1: storeQueue mode). Stores buffer in the queue and +/// drain to memory in program order at commit; a load waits for the queue to +/// drain before reading the bus, so a load right after a same-address store sees +/// the stored value with NO separation nops (the case that needs a store- +/// visibility gap without an LSQ). See project_hdl_lsq. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + RiverCoreConfig lsqConfig() => RiverCoreConfig( + clock: HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ), + mxlen: RiscVMxlen.rv32, + extensions: [rv32i, rvZicsr, rvZifencei], + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv32, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + executionMode: ExecutionMode.outOfOrder, + speculativeFetch: true, + loadStoreQueue: LoadStoreQueue.storeQueue, + ); + + int iimm(int imm, int rs1, int f3, int rd) => + (imm << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x13; + int s(int imm, int rs2, int rs1, int f3) => + (((imm >> 5) & 0x7F) << 25) | + (rs2 << 20) | + (rs1 << 15) | + (f3 << 12) | + ((imm & 0x1F) << 7) | + 0x23; + int lw(int imm, int rs1, int rd) => + (imm << 20) | (rs1 << 15) | (0x2 << 12) | (rd << 7) | 0x03; + String prog(List words) { + final sb = StringBuffer('@0\n'); + for (final w in words) { + for (var i = 0; i < 4; i++) { + sb.write(((w >> (i * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + return '$sb\n'; + } + + // Store then load the SAME address with no separation nops. The load must + // wait for the store to drain, then read 0x123, not stale memory. + test( + 'LSQ: store then load same address (no visibility gap)', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + iimm(0x100, 0, 0x0, 10), // addi x10, x0, 0x100 (base addr) + iimm(0x123, 0, 0x0, 5), // addi x5, x0, 0x123 (value) + s(0, 5, 10, 0x2), // sw x5, 0(x10) mem[0x100]=0x123 + lw(0, 10, 6), // lw x6, 0(x10) x6 = 0x123 (waits for drain) + ...List.filled(8, 0x00000013), // nop tail + ]), + {Register.x10: 0x100, Register.x5: 0x123, Register.x6: 0x123}, + lsqConfig(), + nextPc: 0x20, + memStates: {0x100: 0x123}, + memLatency: 2, + ), + ); + + // Store then two loads of the same address: both loads wait for the queue to + // drain and read the stored value (exercises the background drain feeding two + // consecutive dependent loads). + test( + 'LSQ: store then two loads of the same address', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + iimm(0x100, 0, 0x0, 10), // addi x10, x0, 0x100 + iimm(0xAA, 0, 0x0, 5), // addi x5, x0, 0xAA + s(0, 5, 10, 0x2), // sw x5, 0(x10) mem[0x100]=0xAA + lw(0, 10, 7), // lw x7, 0(x10) x7 = 0xAA + lw(0, 10, 8), // lw x8, 0(x10) x8 = 0xAA + ...List.filled(10, 0x00000013), // nop tail + ]), + { + Register.x10: 0x100, + Register.x5: 0xAA, + Register.x7: 0xAA, + Register.x8: 0xAA, + }, + lsqConfig(), + nextPc: 0x3C, + memStates: {0x100: 0xAA}, + memLatency: 2, + ), + ); + + // Two stores to different addresses, then a load of each back. Both stores + // drain in program order in the background; each load waits for the queue to + // empty and reads its value. (memLatency 0 like the other OoO memory tests, + // a long store-drain stall lets the speculative front-end run off the end of + // this tiny program, an artifact of the nop-tail harness, not the core.) + test( + 'LSQ: two stores, two loads (different addresses)', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + iimm(0x100, 0, 0x0, 10), // addi x10, x0, 0x100 + iimm(0x200, 0, 0x0, 11), // addi x11, x0, 0x200 + iimm(0xAA, 0, 0x0, 5), // addi x5, x0, 0xAA + iimm(0xBB, 0, 0x0, 6), // addi x6, x0, 0xBB + s(0, 5, 10, 0x2), // sw x5, 0(x10) mem[0x100]=0xAA + s(0, 6, 11, 0x2), // sw x6, 0(x11) mem[0x200]=0xBB + lw(0, 10, 7), // lw x7, 0(x10) x7 = 0xAA + lw(0, 11, 8), // lw x8, 0(x11) x8 = 0xBB + ...List.filled(10, 0x00000013), // nop tail + ]), + { + Register.x10: 0x100, + Register.x11: 0x200, + Register.x7: 0xAA, + Register.x8: 0xBB, + }, + lsqConfig(), + nextPc: 0x44, + memStates: {0x100: 0xAA, 0x200: 0xBB}, + ), + ); +} diff --git a/packages/river_hdl/test/m/iterative_divider_test.dart b/packages/river_hdl/test/m/iterative_divider_test.dart new file mode 100644 index 0000000..c64dee4 --- /dev/null +++ b/packages/river_hdl/test/m/iterative_divider_test.dart @@ -0,0 +1,173 @@ +import 'dart:async'; + +import 'package:rohd/rohd.dart'; +import 'package:river_hdl/src/core/iterative_divider.dart'; +import 'package:test/test.dart'; + +/// Build one [IterativeDivider] of [width] bits, settled out of reset, plus the +/// input nets so a test can drive many vectors through it back to back. +class _Harness { + final int width; + final Logic clk; + final Logic reset; + final Logic start; + final Logic dividend; + final Logic divisor; + final IterativeDivider dut; + + _Harness._( + this.width, + this.clk, + this.reset, + this.start, + this.dividend, + this.divisor, + this.dut, + ); + + static Future<_Harness> make(int width) async { + final clk = SimpleClockGenerator(10).clk; + final reset = Logic(name: 'reset'); + final start = Logic(name: 'start'); + final dividend = Logic(name: 'dividend', width: width); + final divisor = Logic(name: 'divisor', width: width); + final dut = IterativeDivider( + clk, + reset, + start, + dividend, + divisor, + width: width, + ); + reset.inject(1); + start.inject(0); + dividend.inject(0); + divisor.inject(LogicValue.ofInt(1, width)); + await dut.build(); + Simulator.setMaxSimTime(50000000); + unawaited(Simulator.run()); + await clk.nextPosedge; + await clk.nextPosedge; + reset.inject(0); + await clk.nextPosedge; + return _Harness._(width, clk, reset, start, dividend, divisor, dut); + } + + /// Drive one division and return (quotient, remainder). Divisor must be >= 1. + Future<(BigInt, BigInt)> div(BigInt a, BigInt b) async { + dividend.inject(LogicValue.ofBigInt(a, width)); + divisor.inject(LogicValue.ofBigInt(b, width)); + start.inject(1); + // Wait for done (latency ~ width + a few cycles; cap generously). + var guard = 0; + while (!dut.done.value.toBool()) { + await clk.nextPosedge; + if (++guard > width + 16) { + fail('divider did not assert done within ${width + 16} cycles'); + } + } + final q = dut.quotient.value.toBigInt(); + final r = dut.remainder.value.toBigInt(); + // Release and let the core return to idle before the next vector. + start.inject(0); + await clk.nextPosedge; + return (q, r); + } +} + +/// Reference unsigned quotient/remainder (BigInt is truncating toward zero, and +/// both operands are non-negative here, so this is unsigned div/mod). +(BigInt, BigInt) _ref(BigInt a, BigInt b) => (a ~/ b, a % b); + +Future _check(_Harness h, BigInt a, BigInt b) async { + final (q, r) = await h.div(a, b); + final (eq, er) = _ref(a, b); + expect(q, eq, reason: 'quotient $a / $b (w=${h.width})'); + expect(r, er, reason: 'remainder $a % $b (w=${h.width})'); +} + +void main() { + tearDown(() async { + await Simulator.endSimulation(); + Simulator.reset(); + }); + + test('width=8 exhaustive-ish (edge a x edge/all b)', () async { + final h = await _Harness.make(8); + const aVals = [0, 1, 2, 7, 99, 127, 128, 200, 254, 255]; + for (final a in aVals) { + for (var b = 1; b <= 255; b++) { + await _check(h, BigInt.from(a), BigInt.from(b)); + } + } + }); + + test('width=32 edge cross product + pseudorandom', () async { + final h = await _Harness.make(32); + final max = (BigInt.one << 32) - BigInt.one; + final edges = [ + BigInt.zero, + BigInt.one, + BigInt.two, + BigInt.from(7), + BigInt.from(1000000), + BigInt.from(0x7FFFFFFF), + BigInt.from(0x80000000), + max, + ]; + for (final a in edges) { + for (final b in edges) { + if (b == BigInt.zero) continue; + await _check(h, a, b); + } + } + // Deterministic LCG sweep (no Math.random for reproducibility). + var s = 0x12345678; + int next() { + s = (s * 1103515245 + 12345) & 0x7FFFFFFF; + return s; + } + + for (var i = 0; i < 200; i++) { + final a = BigInt.from(next()) << 1 | BigInt.from(next() & 1); + final b = BigInt.from((next() % 0xFFFFFFFF) + 1); + await _check(h, a & max, b & max); + } + }); + + test('width=64 edge cross product + pseudorandom', () async { + final h = await _Harness.make(64); + final max = (BigInt.one << 64) - BigInt.one; + final edges = [ + BigInt.zero, + BigInt.one, + BigInt.two, + BigInt.from(7), + BigInt.parse('0x7FFFFFFFFFFFFFFF'), + BigInt.parse('0x8000000000000000'), + BigInt.parse('0xFFFFFFFF00000000'), + max, + ]; + for (final a in edges) { + for (final b in edges) { + if (b == BigInt.zero) continue; + await _check(h, a, b); + } + } + var s = BigInt.from(0xCAFEBABE); + final m64 = (BigInt.one << 64) - BigInt.one; + BigInt next() { + s = + (s * BigInt.from(6364136223846793005) + + BigInt.from(1442695040888963407)) & + m64; + return s; + } + + for (var i = 0; i < 200; i++) { + final a = next(); + final b = (next() & m64) | BigInt.one; // ensure non-zero + await _check(h, a, b); + } + }); +} diff --git a/packages/river_hdl/test/m/iterative_multiplier_test.dart b/packages/river_hdl/test/m/iterative_multiplier_test.dart new file mode 100644 index 0000000..4ed7c5e --- /dev/null +++ b/packages/river_hdl/test/m/iterative_multiplier_test.dart @@ -0,0 +1,176 @@ +import 'dart:async'; + +import 'package:rohd/rohd.dart'; +import 'package:river_hdl/src/core/iterative_multiplier.dart'; +import 'package:test/test.dart'; + +/// Build one [IterativeMultiplier] settled out of reset, plus the input nets so +/// a test can drive many vectors through it back to back. +class _Harness { + final int width; + final int radix; + final Logic clk; + final Logic reset; + final Logic start; + final Logic a; + final Logic b; + final IterativeMultiplier dut; + + _Harness._( + this.width, + this.radix, + this.clk, + this.reset, + this.start, + this.a, + this.b, + this.dut, + ); + + static Future<_Harness> make(int width, int radix) async { + final clk = SimpleClockGenerator(10).clk; + final reset = Logic(name: 'reset'); + final start = Logic(name: 'start'); + final a = Logic(name: 'a', width: width); + final b = Logic(name: 'b', width: width); + final dut = IterativeMultiplier( + clk, + reset, + start, + a, + b, + width: width, + radix: radix, + ); + reset.inject(1); + start.inject(0); + a.inject(0); + b.inject(0); + await dut.build(); + Simulator.setMaxSimTime(50000000); + unawaited(Simulator.run()); + await clk.nextPosedge; + await clk.nextPosedge; + reset.inject(0); + await clk.nextPosedge; + return _Harness._(width, radix, clk, reset, start, a, b, dut); + } + + /// Drive one multiply and return the full 2*width-bit unsigned product. + Future mul(BigInt x, BigInt y) async { + a.inject(LogicValue.ofBigInt(x, width)); + b.inject(LogicValue.ofBigInt(y, width)); + start.inject(1); + var guard = 0; + while (!dut.done.value.toBool()) { + await clk.nextPosedge; + if (++guard > width + 16) { + fail('multiplier did not assert done within ${width + 16} cycles'); + } + } + final p = dut.product.value.toBigInt(); + start.inject(0); + await clk.nextPosedge; + return p; + } +} + +Future _check(_Harness h, BigInt x, BigInt y) async { + final p = await h.mul(x, y); + expect(p, x * y, reason: 'product $x * $y (w=${h.width}, radix=${h.radix})'); +} + +void main() { + tearDown(() async { + await Simulator.endSimulation(); + Simulator.reset(); + }); + + test('width=8 radix=4 exhaustive', () async { + final h = await _Harness.make(8, 4); + for (var a = 0; a < 256; a++) { + for (var b = 0; b < 256; b++) { + await _check(h, BigInt.from(a), BigInt.from(b)); + } + } + }); + + test('width=16 radix=8 edge + sweep', () async { + final h = await _Harness.make(16, 8); + final max = (BigInt.one << 16) - BigInt.one; + final edges = [ + BigInt.zero, + BigInt.one, + BigInt.two, + BigInt.from(0x7FFF), + BigInt.from(0x8000), + BigInt.from(0xFFFE), + max, + ]; + for (final a in edges) { + for (final b in edges) { + await _check(h, a, b); + } + } + }); + + test('width=32 radix=16 edge + pseudorandom', () async { + final h = await _Harness.make(32, 16); + final max = (BigInt.one << 32) - BigInt.one; + final edges = [ + BigInt.zero, + BigInt.one, + BigInt.from(0x7FFFFFFF), + BigInt.from(0x80000000), + max, + ]; + for (final a in edges) { + for (final b in edges) { + await _check(h, a, b); + } + } + var s = 0x12345678; + int next() { + s = (s * 1103515245 + 12345) & 0x7FFFFFFF; + return s; + } + + for (var i = 0; i < 200; i++) { + final a = (BigInt.from(next()) << 1 | BigInt.from(next() & 1)) & max; + final b = (BigInt.from(next()) << 1 | BigInt.from(next() & 1)) & max; + await _check(h, a, b); + } + }); + + test('width=64 radix=16 edge + pseudorandom', () async { + final h = await _Harness.make(64, 16); + final m64 = (BigInt.one << 64) - BigInt.one; + final edges = [ + BigInt.zero, + BigInt.one, + BigInt.two, + BigInt.parse('0x7FFFFFFFFFFFFFFF'), + BigInt.parse('0x8000000000000000'), + BigInt.parse('0xFFFFFFFF00000000'), + BigInt.parse('0x00000000FFFFFFFF'), + m64, + ]; + for (final a in edges) { + for (final b in edges) { + await _check(h, a, b); + } + } + var s = BigInt.from(0xCAFEBABE); + BigInt next() { + s = + (s * BigInt.from(6364136223846793005) + + BigInt.from(1442695040888963407)) & + m64; + return s; + } + + for (var i = 0; i < 200; i++) { + await _check(h, next(), next()); + } + }); +} diff --git a/packages/river_hdl/test/m/microcode_alu_test.dart b/packages/river_hdl/test/m/microcode_alu_test.dart new file mode 100644 index 0000000..69a0cbb --- /dev/null +++ b/packages/river_hdl/test/m/microcode_alu_test.dart @@ -0,0 +1,148 @@ +import 'package:river/river.dart'; +import 'package:river_hdl/river_hdl.dart'; +import 'package:rohd/rohd.dart'; +import 'package:test/test.dart'; + +/// Golden test for the shared MicrocodeAlu (Phase 1 of the microcode exec +/// rewrite). Drives every integer ALU funct over a battery of operand pairs and +/// checks the result against a Dart 64-bit golden, so the shared datapath is +/// proven bit-for-bit before the exec is rewritten to use it. See +/// project_microcode_exec_rewrite. +void main() { + const m = 0xFFFFFFFFFFFFFFFF; // 64-bit mask + + // 64-bit golden for each MicroOpAluFunct, computed with Dart's native 64-bit + // (wrapping) int arithmetic. signExt32 sign-extends a 32-bit value. + int signExt32(int v) { + v &= 0xFFFFFFFF; + return (v & 0x80000000) != 0 ? v | (m << 32) : v; + } + + int golden(int funct, int a, int b) { + switch (funct) { + case MicroOpAluFunct.add: + return (a + b) & m; + case MicroOpAluFunct.sub: + return (a - b) & m; + case MicroOpAluFunct.and: + return a & b; + case MicroOpAluFunct.or: + return a | b; + case MicroOpAluFunct.xor: + return a ^ b; + case MicroOpAluFunct.masked: + return a & ~b; + case MicroOpAluFunct.sll: + return (a << (b & 63)) & m; + case MicroOpAluFunct.srl: + return a >>> (b & 63); + case MicroOpAluFunct.sra: + return a >> (b & 63); // Dart >> on a 64-bit int is arithmetic + case MicroOpAluFunct.addw: + return signExt32((a + b) & 0xFFFFFFFF); + case MicroOpAluFunct.subw: + return signExt32((a - b) & 0xFFFFFFFF); + case MicroOpAluFunct.sllw: + return signExt32(((a & 0xFFFFFFFF) << (b & 31)) & 0xFFFFFFFF); + case MicroOpAluFunct.srlw: + return signExt32((a & 0xFFFFFFFF) >>> (b & 31)); + case MicroOpAluFunct.sraw: + return signExt32(signExt32(a & 0xFFFFFFFF) >> (b & 31) & 0xFFFFFFFF); + case MicroOpAluFunct.slt: + return signExt32(a) < signExt32(b) ? 1 : 0; // placeholder, overridden + case MicroOpAluFunct.sltu: + return 0; // overridden + case MicroOpAluFunct.czeroEqz: + return b == 0 ? 0 : a; + case MicroOpAluFunct.czeroNez: + return b == 0 ? a : 0; + default: + return 0; + } + } + + // Signed/unsigned compares use full 64-bit semantics, done via BigInt to avoid + // Dart-int sign ambiguity at the 2^63 boundary. + int sltGolden(int a, int b) { + final sa = LogicValue.ofInt(a, 64).toBigInt(); // unsigned BigInt + final sb = LogicValue.ofInt(b, 64).toBigInt(); + BigInt asSigned(BigInt u) => + u >= (BigInt.one << 63) ? u - (BigInt.one << 64) : u; + return asSigned(sa) < asSigned(sb) ? 1 : 0; + } + + int sltuGolden(int a, int b) { + final ua = LogicValue.ofInt(a, 64).toBigInt(); + final ub = LogicValue.ofInt(b, 64).toBigInt(); + return ua < ub ? 1 : 0; + } + + final functs = [ + MicroOpAluFunct.add, + MicroOpAluFunct.sub, + MicroOpAluFunct.and, + MicroOpAluFunct.or, + MicroOpAluFunct.xor, + MicroOpAluFunct.masked, + MicroOpAluFunct.sll, + MicroOpAluFunct.srl, + MicroOpAluFunct.sra, + MicroOpAluFunct.addw, + MicroOpAluFunct.subw, + MicroOpAluFunct.sllw, + MicroOpAluFunct.srlw, + MicroOpAluFunct.sraw, + MicroOpAluFunct.slt, + MicroOpAluFunct.sltu, + MicroOpAluFunct.czeroEqz, + MicroOpAluFunct.czeroNez, + ]; + + final operands = >[ + [0, 0], + [1, 1], + [5, 3], + [3, 5], + [0xDEADBEEF, 0x12345678], + [0x8000000000000000, 1], // INT_MIN, -1-ish edge + [0x7FFFFFFFFFFFFFFF, 1], + [0xFFFFFFFFFFFFFFFF, 0xFFFFFFFFFFFFFFFF], // -1, -1 + [0x00000000FFFFFFFF, 0x40], // 32-bit boundary, shamt 64 + [0xFEDCBA9876543210, 0], + [100, 63], + [0xF0F0F0F0, 4], + ]; + + test( + 'MicrocodeAlu matches the 64-bit golden for every funct/operand', + () async { + final a = Logic(name: 'a', width: 64); + final b = Logic(name: 'b', width: 64); + final funct = Logic(name: 'funct', width: MicroOpAluFunct.width); + final dut = MicrocodeAlu(a, b, funct, mxlen: RiscVMxlen.rv64); + await dut.build(); + + for (final fn in functs) { + for (final ops in operands) { + a.put(ops[0]); + b.put(ops[1]); + funct.put(fn); + final exp = switch (fn) { + MicroOpAluFunct.slt => sltGolden(ops[0], ops[1]), + MicroOpAluFunct.sltu => sltuGolden(ops[0], ops[1]), + _ => golden(fn, ops[0], ops[1]), + }; + expect( + dut.result.value, + LogicValue.ofInt(exp, 64), + reason: + 'funct=$fn a=0x${ops[0].toRadixString(16)} ' + 'b=0x${ops[1].toRadixString(16)} ' + 'got=0x${dut.result.value.toBigInt().toRadixString(16)} ' + 'exp=0x${LogicValue.ofInt(exp, 64).toBigInt().toRadixString(16)}', + ); + } + } + }, + ); +} diff --git a/packages/river_hdl/test/m/microcode_trace.dart b/packages/river_hdl/test/m/microcode_trace.dart new file mode 100644 index 0000000..8330933 --- /dev/null +++ b/packages/river_hdl/test/m/microcode_trace.dart @@ -0,0 +1,114 @@ +import 'dart:async'; + +import 'package:rohd/rohd.dart'; +import 'package:rohd_hcl/rohd_hcl.dart' hide DataPortInterface, DataPortGroup; +import 'package:river/river.dart'; +import 'package:river_hdl/river_hdl.dart'; + +import '../matrix_configs.dart'; +import '../matrix_encoders.dart'; + +/// Diagnostic: dump a VCD of the in-order MICROCODE core running a single base +/// `add` cell, using the SAME memory/bus wiring as the matrix harness (a +/// MemoryModel + a registered Wishbone ack) so the timing is faithful (an +/// earlier ad-hoc combinational memory was misleading). Writes +/// /tmp/microcode_trace.vcd. Not an assertion test. +void main() async { + await Simulator.reset(); + const xlen = 64; + final config = matrixConfig( + RiscVMxlen.rv64, + Uarch.inOrder, + 'base', + microcodeMode: MicrocodeMode.full, + ); + final clk = SimpleClockGenerator(20).clk; + final reset = Logic(name: 'reset'); + final core = RiverCore( + config, + busConfig: WishboneConfig( + addressWidth: xlen, + dataWidth: xlen, + selWidth: xlen ~/ 8, + ), + ); + core.input('clk').srcConnection! <= clk; + core.input('reset').srcConnection! <= reset; + await core.build(); + + final storage = SparseMemoryStorage( + addrWidth: xlen, + dataWidth: xlen, + alignAddress: (addr) => addr, + onInvalidRead: (addr, dataWidth) => + LogicValue.filled(dataWidth, LogicValue.zero), + ); + final memRead = DataPortInterface(xlen, xlen); + final memWrite = DataPortInterface(xlen, xlen); + // ignore: unused_local_variable + final mem = MemoryModel( + clk, + reset, + [wrapWriteForRegisterFile(memWrite)], + [wrapReadForRegisterFile(memRead, clk: clk, readLatency: 0)], + readLatency: 0, + storage: storage, + ); + final wbCyc = core.output('dataBus_CYC'); + final wbStb = core.output('dataBus_STB'); + final wbWe = core.output('dataBus_WE'); + memRead.en <= wbCyc & wbStb & ~wbWe; + memRead.addr <= core.output('dataBus_ADR'); + memWrite.en <= wbCyc & wbStb & wbWe; + memWrite.addr <= core.output('dataBus_ADR'); + memWrite.data <= core.output('dataBus_DAT_MOSI'); + final wbAckReg = Logic(name: 'wbAck'); + Sequential(clk, [ + If( + reset, + then: [wbAckReg < 0], + orElse: [ + If( + wbCyc & wbStb & ~wbAckReg & (wbWe | memRead.valid), + then: [wbAckReg < 1], + orElse: [wbAckReg < 0], + ), + ], + ), + ]); + final seedGate = Logic(name: 'seedGate'); + core.input('dataBus_ACK').srcConnection! <= wbAckReg & ~seedGate; + core.input('dataBus_DAT_MISO').srcConnection! <= memRead.data; + + WaveDumper(core, outputPath: '/tmp/microcode_trace.vcd'); + + // base 'add' cell: addi x1,x0,-5 ; addi x2,x0,3 ; add x3,x1,x2 ; nop. + final prog = [ + iimm(-5, 0, 0x0, 1), + iimm(3, 0, 0x0, 2), + rtype(0x00, 2, 1, 0x0, 3), + nop, + ]; + final memStr = StringBuffer('@0\n'); + for (final w in prog) { + for (var b = 0; b < 4; b++) { + memStr.write(((w >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + memStr.write(' '); + } + } + + reset.inject(1); + seedGate.inject(0); + Simulator.setMaxSimTime(60000); + unawaited(Simulator.run()); + await clk.nextPosedge; + await clk.nextPosedge; + await clk.nextPosedge; + await clk.nextPosedge; + storage.loadMemString(memStr.toString()); + reset.inject(0); + for (var i = 0; i < 500; i++) { + await clk.nextPosedge; + } + await Simulator.endSimulation(); +} diff --git a/packages/river_hdl/test/m/rv32_inorder_test.dart b/packages/river_hdl/test/m/rv32_inorder_test.dart new file mode 100644 index 0000000..446fe96 --- /dev/null +++ b/packages/river_hdl/test/m/rv32_inorder_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'm'; + const mxlen = RiscVMxlen.rv32; + const uarch = Uarch.inOrder; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/m/rv32_ooo_dual_test.dart b/packages/river_hdl/test/m/rv32_ooo_dual_test.dart new file mode 100644 index 0000000..e434f95 --- /dev/null +++ b/packages/river_hdl/test/m/rv32_ooo_dual_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'm'; + const mxlen = RiscVMxlen.rv32; + const uarch = Uarch.oooDual; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/m/rv32_ooo_test.dart b/packages/river_hdl/test/m/rv32_ooo_test.dart new file mode 100644 index 0000000..6b7366b --- /dev/null +++ b/packages/river_hdl/test/m/rv32_ooo_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'm'; + const mxlen = RiscVMxlen.rv32; + const uarch = Uarch.ooo; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/m/rv64_inorder_microcode_test.dart b/packages/river_hdl/test/m/rv64_inorder_microcode_test.dart new file mode 100644 index 0000000..fc9cb9a --- /dev/null +++ b/packages/river_hdl/test/m/rv64_inorder_microcode_test.dart @@ -0,0 +1,22 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +/// In-order MICROCODE path (DynamicExecutionUnit + microcode ROM, +/// MicrocodeMode.full) for the 'm' category, validated against the emulator +/// golden. This is the area-first path rc1-s (creek) uses on small FPGAs. Split +/// per-category so dart test parallelizes across isolates (one big file +/// accumulates heap across builds and times out - see project_parity / +/// feedback_test_parallelism). +void main() { + const category = 'm'; + const mxlen = RiscVMxlen.rv64; + const uarch = Uarch.inOrder; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)} (microcode)', + matrixConfig(mxlen, uarch, category, microcodeMode: MicrocodeMode.full), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/m/rv64_inorder_test.dart b/packages/river_hdl/test/m/rv64_inorder_test.dart new file mode 100644 index 0000000..2b676d6 --- /dev/null +++ b/packages/river_hdl/test/m/rv64_inorder_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'm'; + const mxlen = RiscVMxlen.rv64; + const uarch = Uarch.inOrder; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/m/rv64_microcode_update_test.dart b/packages/river_hdl/test/m/rv64_microcode_update_test.dart new file mode 100644 index 0000000..7ea6fce --- /dev/null +++ b/packages/river_hdl/test/m/rv64_microcode_update_test.dart @@ -0,0 +1,112 @@ +import 'package:harbor/harbor.dart' + show RiscVAlu, RiscVAluFunct, RiscVMicroOpField; +import 'package:river/river.dart'; +import 'package:river_hdl/river_hdl.dart'; +import 'package:rohd/rohd.dart'; +import 'package:test/test.dart'; + +import '../core_harness.dart'; +import '../matrix_encoders.dart'; + +/// Microcode UPDATE: patch a live instruction's microcode through the +/// rmicrocode* CSRs and prove the CPU's behaviour changes. We rewrite addi's +/// Alu micro-op from ADD to SUB in the exec ROM, then run `addi x1, x2, 5`: +/// unpatched that is x2+5=25, patched it must be x2-5=15. A pure-HDL check (the +/// emulator does not model the ROM patch), so coreTest asserts the HDL result +/// directly. See project_hdl_microcode_coverage / project_microcode_update. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + final config = RiverCoreConfig( + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + mxlen: RiscVMxlen.rv64, + extensions: [rv64i, rv32i, rvZicsr, rvZifencei, rvPriv], + interrupts: const [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + microcodeMode: MicrocodeMode.full, + ); + + test('patch addi add->sub via rmicrocode CSRs changes execution', () async { + // Compute the exec-ROM row index of addi's Alu micro-op and the SUB-patched + // encoding for that row, straight from the microcode model. + MicrocodeRom.mopEncodings = kMicroOpTable; + final rom = MicrocodeRom(config.isa, encodings: kMicroOpTable); + final addi = rom.operations.firstWhere((o) => o.mnemonic == 'addi'); + + // Flat layout per op in encodedMops: [count, mop0, mop1, ...]. The Alu mop + // sits at (op base) + 1 (count word) + (its position in the microcode). + var base = 0; + for (final op in rom.operations) { + if (identical(op, addi)) break; + base += 1 + op.microcode.length; + } + final aluPos = addi.microcode.indexWhere((m) => m is RiscVAlu); + final aluRowIndex = base + 1 + aluPos; + + final origAlu = addi.microcode[aluPos] as RiscVAlu; + final aluEnc = kMicroOpTable.firstWhere((e) => e.name == 'Alu'); + final patched = RiscVAlu(RiscVAluFunct.sub, origAlu.a, origAlu.b); + final patchWord = aluEnc.encodeMop(patched, config.mxlen).toInt(); + + // CSR encoders (matrix_encoders: csr=csrrw/rs/rc by f3, csri=immediate). + int csrrw(int addr, int rs1) => csr(addr, rs1, 0x1, 0); + int csrrwi(int addr, int zimm) => csri(addr, zimm, 0x5, 0); + // Load a 32-bit value into rd (lui + addi, with the addi sign carry). + List li(int rd, int v) { + v &= 0xFFFFFFFF; + final lo = v & 0xFFF; + var hi = (v >> 12) & 0xFFFFF; + if (lo & 0x800 != 0) hi = (hi + 1) & 0xFFFFF; + final loSigned = lo & 0x800 != 0 ? lo - 0x1000 : lo; + return [lui(hi, rd), iimm(loSigned, rd, 0x0, rd)]; + } + + const aAddr = 0x7C4; // rmicrocodeaddr + const dAddr = 0x7C5; // rmicrocodedata + const cAddr = 0x7C6; // rmicrocodectl + const push = 0x1, commit = 0x2, clear = 0x4; + + final program = [ + iimm(20, 0, 0x0, 2), // addi x2, x0, 20 (normal add, before the patch) + ...li(5, patchWord), // x5 = SUB-patched Alu row + csrrw(dAddr, 5), // rmicrocodedata = x5 + csrrwi(cAddr, clear), // CLEAR staging + csrrwi(cAddr, push), // PUSH -> staging = patch word + ...li(6, aluRowIndex), // x6 = exec ROM row index (bit63=0 -> exec ROM) + csrrw(aAddr, 6), // rmicrocodeaddr = x6 + csrrwi(cAddr, commit), // COMMIT -> ROM[row] = staging + iimm(5, 2, 0x0, 1), // addi x1, x2, 5 (patched: x2 - 5) + nop, + ]; + final nextPc = (program.length - 1) * 4; + + String memString(List ws) { + final sb = StringBuffer(); + for (final w in ws) { + for (var b = 0; b < 4; b++) { + sb.write(((w >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + return sb.toString().trimRight(); + } + + await coreTest( + memString(program), + {Register.x1: 15}, // x2(20) - 5 = 15 (patched). Unpatched would be 25. + config, + nextPc: nextPc, + ); + }); +} diff --git a/packages/river_hdl/test/m/rv64_ooo_dual_test.dart b/packages/river_hdl/test/m/rv64_ooo_dual_test.dart new file mode 100644 index 0000000..72623db --- /dev/null +++ b/packages/river_hdl/test/m/rv64_ooo_dual_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'm'; + const mxlen = RiscVMxlen.rv64; + const uarch = Uarch.oooDual; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/m/rv64_ooo_test.dart b/packages/river_hdl/test/m/rv64_ooo_test.dart new file mode 100644 index 0000000..82793e0 --- /dev/null +++ b/packages/river_hdl/test/m/rv64_ooo_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'm'; + const mxlen = RiscVMxlen.rv64; + const uarch = Uarch.ooo; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/matrix_configs.dart b/packages/river_hdl/test/matrix_configs.dart new file mode 100644 index 0000000..3382717 --- /dev/null +++ b/packages/river_hdl/test/matrix_configs.dart @@ -0,0 +1,121 @@ +import 'package:river/river.dart'; + +/// The config table for the test matrix: maps (mxlen, microarch, instruction +/// category) to a RiverCoreConfig + label, and gates which microarch x category +/// combinations are actually buildable. List-driven and extensible. + +/// Microarchitecture axis. +enum Uarch { inOrder, ooo, oooDual } + +String uarchLabel(Uarch u) => switch (u) { + Uarch.inOrder => 'inorder', + Uarch.ooo => 'ooo', + Uarch.oooDual => 'ooo_dual', +}; + +String mxlenLabel(RiscVMxlen m) => m == RiscVMxlen.rv64 ? 'rv64' : 'rv32'; + +/// Extensions each instruction category needs beyond the base ISA. The category +/// key is also the directory name (`test//`). Adding an extension is +/// a new entry here + an entry in the instruction table. +final Map> categoryExtensions = { + 'base': [], + 'loadstore': [], + 'branch': [], + 'csr': [], // Zicsr is always enabled in matrixConfig + + 'm': [rvM], + 'a': [rvA], + 'bitmanip': [rvZba, rvZbb, rvZbs], + 'zicond': [rvZicond], + 'zacas': [rvA, rvZacas], + // Single-precision F. The fd cells are all .s and now elaborate + pass on + // BOTH rv32 and rv64 (task #71 coerced the FP read/write ports, the result + // switch, and the roundSatFpToInt W/L mux to the mxlen width). Double stays + // its own rv64-only 'd' category. + 'fd': [rvF, rvFExtra], + // Double-precision (rv64 only - see generator gate). rv64+D elaborates fine. + 'd': [rvF, rvD, rvFExtra, rvDExtra], + 'v': [rvV], // vector (VLEN defaults to 128 in RiverCoreConfig) +}; + +/// Categories that run ONLY on speculative (OoO/dual) configs. Empty now: the +/// in-order taken-branch path is fixed (#69 - exec.dart branch target was +/// missing `currentPc +` and the lt/ge/ltu/geu condition used the unsigned diff +/// sign), so the branch category runs in-order too without a predictor. +const _speculativeOnlyCategories = {}; + +/// Categories that run ONLY on the in-order path for now. Reasons per category: +/// - loadstore/a/zacas: the OoO memory FU is incomplete (stores don't drain/ +/// commit, AMO writeback returns 0, sign-ext loads don't sign-extend - see +/// project_hdl_ooo_state / project_hdl_lsq). +/// (csr now runs on OoO too - #70 fixed: the CsrUnit op-decode + the zimm +/// plumbing were wrong; csrrw/csrrs/csrrc/csrrwi all pass on OoO.) +/// - fd: the OoO core is INTEGER-ONLY (no FP functional unit); F/D execute +/// only on the in-order path (project_hdl_fpu). +/// Flip a category out the moment its OoO path lands - the matrix then +/// validates it immediately. +const _inOrderOnlyCategories = { + 'loadstore', + 'a', + 'zacas', + 'fd', + 'd', + 'v', // vector uses vector loads/stores (OoO mem FU incomplete) + in-order path +}; + +/// Whether (microarch, category) is a buildable + runnable matrix cell-set. +bool microarchSupports(Uarch u, String category) { + if (u == Uarch.inOrder) return !_speculativeOnlyCategories.contains(category); + return !_inOrderOnlyCategories.contains(category); +} + +/// Build the config for (mxlen, microarch, category): base ISA + the category's +/// extensions, on the requested mxlen and pipeline personality. +RiverCoreConfig matrixConfig( + RiscVMxlen mxlen, + Uarch u, + String category, { + int? regfileReadLatency, + MicrocodeMode microcodeMode = MicrocodeMode.none, +}) { + final base = mxlen == RiscVMxlen.rv64 + ? [rv64i, rv32i] + : [rv32i]; + return RiverCoreConfig( + regfileReadLatency: regfileReadLatency, + microcodeMode: microcodeMode, + clock: HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ), + mxlen: mxlen, + extensions: [ + ...base, + rvZicsr, + rvZifencei, + ...categoryExtensions[category]!, + ], + interrupts: const [], + mmu: HarborMmuConfig( + mxlen: mxlen, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + executionMode: u == Uarch.inOrder + ? ExecutionMode.inOrder + : ExecutionMode.outOfOrder, + issueWidth: u == Uarch.oooDual ? IssueWidth.dual : IssueWidth.single, + speculativeFetch: u != Uarch.inOrder, + // A predictor is required for the taken-branch redirect path to resolve + // (with none, a taken branch wedges - see task #69). btfn is the validated + // predictor (core_bpred_test). The config rejects a predictor without + // speculativeFetch, so in-order stays predictor-less (and branch-free in + // the matrix until #69 is resolved). + branchPredictor: u == Uarch.inOrder + ? BranchPredictor.none + : BranchPredictor.btfn, + ); +} diff --git a/packages/river_hdl/test/matrix_encoders.dart b/packages/river_hdl/test/matrix_encoders.dart new file mode 100644 index 0000000..b9ff91d --- /dev/null +++ b/packages/river_hdl/test/matrix_encoders.dart @@ -0,0 +1,136 @@ +// RISC-V instruction encoders shared by the matrix instruction table. + +const nop = 0x00000013; + +/// OP-IMM (addi/slli/...): opcode 0x13. +int iimm(int imm, int rs1, int f3, int rd) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x13; + +/// OP-IMM-32 (addiw/...): opcode 0x1B (rv64). +int iimmW(int imm, int rs1, int f3, int rd) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x1B; + +/// OP (add/sub/and/mul/...): opcode 0x33. +int rtype(int f7, int rs2, int rs1, int f3, int rd) => + (f7 << 25) | (rs2 << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x33; + +/// OP-32 (addw/subw/mulw/...): opcode 0x3B (rv64). +int rtypeW(int f7, int rs2, int rs1, int f3, int rd) => + (f7 << 25) | (rs2 << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x3B; + +/// LOAD (lb/lh/lw/ld/...): opcode 0x03. +int load(int imm, int rs1, int f3, int rd) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x03; + +/// STORE (sb/sh/sw/sd): opcode 0x23. +int store(int imm, int rs2, int rs1, int f3) => + (((imm >> 5) & 0x7F) << 25) | + (rs2 << 20) | + (rs1 << 15) | + (f3 << 12) | + ((imm & 0x1F) << 7) | + 0x23; + +/// LUI: opcode 0x37. +int lui(int imm20, int rd) => ((imm20 & 0xFFFFF) << 12) | (rd << 7) | 0x37; + +/// AUIPC: opcode 0x17. +int auipc(int imm20, int rd) => ((imm20 & 0xFFFFF) << 12) | (rd << 7) | 0x17; + +/// BRANCH (beq/bne/blt/bge/bltu/bgeu): opcode 0x63. [imm] is the signed byte +/// offset (multiple of 2); the B-type immediate is scattered across the word. +int branch(int imm, int rs2, int rs1, int f3) => + (((imm >> 12) & 0x1) << 31) | + (((imm >> 5) & 0x3F) << 25) | + (rs2 << 20) | + (rs1 << 15) | + (f3 << 12) | + (((imm >> 1) & 0xF) << 8) | + (((imm >> 11) & 0x1) << 7) | + 0x63; + +/// JAL: opcode 0x6F. [imm] is the signed byte offset; J-type scattered layout. +int jal(int imm, int rd) => + (((imm >> 20) & 0x1) << 31) | + (((imm >> 1) & 0x3FF) << 21) | + (((imm >> 11) & 0x1) << 20) | + (((imm >> 12) & 0xFF) << 12) | + (rd << 7) | + 0x6F; + +/// JALR: opcode 0x67, funct3 0. +int jalr(int imm, int rs1, int rd) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (0x0 << 12) | (rd << 7) | 0x67; + +/// SYSTEM CSR (csrrw/csrrs/csrrc): opcode 0x73. csr in bits[31:20], rs1 source. +int csr(int csrAddr, int rs1, int f3, int rd) => + ((csrAddr & 0xFFF) << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x73; + +/// SYSTEM CSR immediate (csrrwi/csrrsi/csrrci): the 5-bit zimm sits in the rs1 +/// field; funct3 has bit 2 set (0x5/0x6/0x7). +int csri(int csrAddr, int zimm, int f3, int rd) => + ((csrAddr & 0xFFF) << 20) | + ((zimm & 0x1F) << 15) | + (f3 << 12) | + (rd << 7) | + 0x73; + +/// LOAD-FP flw (funct3 0x2) / fld (funct3 0x3): opcode 0x07. rd is an F-reg. +int flw(int imm, int rs1, int fd) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (0x2 << 12) | (fd << 7) | 0x07; +int fld(int imm, int rs1, int fd) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (0x3 << 12) | (fd << 7) | 0x07; + +/// STORE-FP fsw (funct3 0x2) / fsd (funct3 0x3): opcode 0x27. fs2 is an F-reg. +int fsw(int imm, int fs2, int rs1, int f3) => + (((imm >> 5) & 0x7F) << 25) | + (fs2 << 20) | + (rs1 << 15) | + (f3 << 12) | + ((imm & 0x1F) << 7) | + 0x27; + +/// OP-FP R-type (fadd/fmul/fcvt/feq/fmv...): opcode 0x53. funct3 carries the +/// rounding mode for arithmetic, or a sub-op selector for compares/moves. +int fpOp(int funct7, int rs2, int rs1, int f3, int rd) => + (funct7 << 25) | (rs2 << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x53; + +/// vsetvli rd, rs1, vtypei: opcode 0x57, funct3=7 (OPCFG); vtypei in bits[30:20]. +int vsetvli(int vtypei, int rs1, int rd) => + (vtypei << 20) | (rs1 << 15) | (0x7 << 12) | (rd << 7) | 0x57; + +/// vle32.v vd, (rs1): unit-stride load, opcode 0x07, width(funct3)=6, vm=1. +int vle32(int rs1, int vd) => + (1 << 25) | (rs1 << 15) | (0x6 << 12) | (vd << 7) | 0x07; + +/// vse32.v vs3, (rs1): unit-stride store, opcode 0x27, width=6, vm=1. +int vse32(int rs1, int vs3) => + (1 << 25) | (rs1 << 15) | (0x6 << 12) | (vs3 << 7) | 0x27; + +/// OPIVV vector-vector op vd, vs2, vs1: opcode 0x57, funct3=0, vm=1. +int vopivv(int funct6, int vs2, int vs1, int vd) => + (funct6 << 26) | (1 << 25) | (vs2 << 20) | (vs1 << 15) | (vd << 7) | 0x57; + +/// OPIVX vector-scalar op vd, vs2, rs1: funct3=4 (scalar from a GPR), vm=1. +int vopivx(int funct6, int vs2, int rs1, int vd) => + (funct6 << 26) | + (1 << 25) | + (vs2 << 20) | + (rs1 << 15) | + (0x4 << 12) | + (vd << 7) | + 0x57; + +/// OPIVI vector-immediate op vd, vs2, imm5: funct3=3, vm=1. +int vopivi(int funct6, int vs2, int imm5, int vd) => + (funct6 << 26) | + (1 << 25) | + (vs2 << 20) | + ((imm5 & 0x1F) << 15) | + (0x3 << 12) | + (vd << 7) | + 0x57; + +/// AMO (amoadd/amoswap/amocas/lr/sc): opcode 0x2F. funct5 in bits[31:27]. +int amo(int funct5, int rs2, int rs1, int f3, int rd) => + (funct5 << 27) | (rs2 << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x2F; diff --git a/packages/river_hdl/test/matrix_golden_vectors.dart b/packages/river_hdl/test/matrix_golden_vectors.dart new file mode 100644 index 0000000..5acb2e4 --- /dev/null +++ b/packages/river_hdl/test/matrix_golden_vectors.dart @@ -0,0 +1,133 @@ +import 'package:river/river.dart'; + +import 'matrix_encoders.dart'; +import 'matrix_harness.dart'; + +/// Curated golden vectors: small programs whose architectural results are +/// HAND-VERIFIED here (not emulator-computed). [runGolden] asserts both the +/// emulator and the HDL match these. See [GoldenCell] for why this complements +/// the parity matrix. Expected values are written for the value's signed Dart +/// form; the harness compares the low xlen bits, so rv32 sign-extension matches. + +/// An 8-nop tail (result retires + dual fetcher stays in valid memory). +List get _tail => List.filled(8, nop); + +/// In-order golden vectors: arithmetic, shifts, M, memory round-trip, sub-word +/// sign-extending load, lui. No taken branches (in-order has no predictor). +/// Config should enable M (e.g. matrixConfig(mxlen, inOrder, 'm')). +List inOrderGolden(RiscVMxlen mxlen) => [ + // x1=10, x2=20, x3=x1+x2=30, x4=x2-x1=10. + GoldenCell( + 'add/sub', + [ + iimm(10, 0, 0x0, 1), + iimm(20, 0, 0x0, 2), + rtype(0x00, 2, 1, 0x0, 3), // add x3 = x1 + x2 + rtype(0x20, 1, 2, 0x0, 4), // sub x4 = x2 - x1 + ..._tail, + ], + expectedRegs: {Register.x3: 30, Register.x4: 10}, + nextPc: 0x24, + ), + // x1=1, x2 = x1 << 4 = 16; x3 = x2 >> 2 = 4. + GoldenCell( + 'shift', + [ + iimm(1, 0, 0x0, 1), + iimm(4, 1, 0x1, 2), // slli x2 = x1 << 4 = 16 + iimm(2, 2, 0x5, 3), // srli x3 = x2 >> 2 = 4 + ..._tail, + ], + expectedRegs: {Register.x2: 16, Register.x3: 4}, + nextPc: 0x2C, + ), + // x1=7, x2=6, x3 = x1*x2 = 42 (M extension). + GoldenCell( + 'mul', + [ + iimm(7, 0, 0x0, 1), + iimm(6, 0, 0x0, 2), + rtype(0x01, 2, 1, 0x0, 3), // mul x3 = 42 + ..._tail, + ], + expectedRegs: {Register.x3: 42}, + nextPc: 0x28, + ), + // mem[0x200] low byte = 0x80; lb sign-extends to -128; lbu zero-ext = 128. + GoldenCell( + 'load sign/zero extend', + [ + iimm(0x200, 0, 0x0, 2), // x2 = 0x200 + load(0, 2, 0x0, 1), // lb x1 = sext(mem[0x200]) = -128 + load(0, 2, 0x4, 3), // lbu x3 = zext(mem[0x200]) = 128 + ..._tail, + ], + dataMem: { + 0x200: [0x80], + }, + expectedRegs: {Register.x1: -128, Register.x3: 128}, + nextPc: 0x2C, + ), + // store-then-load round trip: mem[0x200] = 0x55, x3 reads it back. + GoldenCell( + 'store/load round trip', + [ + iimm(0x55, 0, 0x0, 1), // x1 = 0x55 + iimm(0x200, 0, 0x0, 2), // x2 = 0x200 + store(0, 1, 2, 0x2), // sw x1 -> mem[0x200] + load(0, 2, 0x2, 3), // lw x3 = mem[0x200] + ..._tail, + ], + expectedRegs: {Register.x3: 0x55}, + expectedMem: {0x200: 0x55}, + nextPc: 0x30, + ), + // lui x1 = 0x12345 << 12 = 0x12345000. + GoldenCell( + 'lui', + [lui(0x12345, 1), ..._tail], + expectedRegs: {Register.x1: 0x12345000}, + nextPc: 0x24, + ), +]; + +/// A branch golden cell: x1=a, x2=b; branch (funct3 [f3]) at 0x8 either skips +/// x3=99 (taken -> x3 stays 0) or falls through (x3=99). [expectTaken] is the +/// hand-verified direction. +GoldenCell _bgolden( + String name, + int f3, { + required int a, + required int b, + required bool expectTaken, +}) => GoldenCell( + name, + [ + iimm(a, 0, 0x0, 1), + iimm(b, 0, 0x0, 2), + branch(8, 2, 1, f3), + iimm(99, 0, 0x0, 3), + iimm(7, 0, 0x0, 4), + ..._tail, + ], + expectedRegs: {Register.x3: expectTaken ? 0 : 99}, + nextPc: 0x34, +); + +/// Branch golden vectors (need a predictor -> OoO config). The unsigned cases +/// use -1 (largest unsigned) vs 1, where signed and unsigned ordering DISAGREE, +/// so these independently pin both the HDL BLT/BGE and the emulator bltu/bgeu +/// comparisons against hand-verified truth. +List branchGolden(RiscVMxlen mxlen) => [ + _bgolden('beq equal', 0x0, a: 5, b: 5, expectTaken: true), + _bgolden('bne equal', 0x1, a: 5, b: 5, expectTaken: false), + // signed: -1 < 1 is true. + _bgolden('blt signed', 0x4, a: -1, b: 1, expectTaken: true), + _bgolden('bge signed', 0x5, a: -1, b: 1, expectTaken: false), + // unsigned: -1 (=max unsigned) >=u 1, so bltu NOT taken, bgeu taken. + _bgolden('bltu big-vs-1', 0x6, a: -1, b: 1, expectTaken: false), + _bgolden('bgeu big-vs-1', 0x7, a: -1, b: 1, expectTaken: true), + // unsigned: 1 program; + + /// Backdoor-seeded GPRs before the program runs. + final Map seed; + + /// Pre-loaded data memory: address -> words. + final Map> dataMem; + + /// GPRs to compare HDL vs golden. + final List checkRegs; + + /// 64-bit memory words to compare HDL vs golden. + final List checkMem; + + /// PC the program halts at (the trailing nop). + final int nextPc; + + const MatrixCell( + this.name, + this.program, { + this.seed = const {}, + this.dataMem = const {}, + this.checkRegs = const [], + this.checkMem = const [], + required this.nextPc, + }); +} + +/// Register the matrix cells for one [config] as a single test named [label], +/// building the HDL core once and running every cell against it. +/// +/// IMPORTANT: this is ONE test(), not a group of per-cell tests. The HDL +/// Simulator is started with `unawaited(Simulator.run())`, and its microtask- +/// driven clock only advances within the async context that started it. Spread +/// across separate test() cases (via setUpAll), `clk.nextPosedge` in a later +/// test never completes and the cell hangs. Keeping the build + all cell runs in +/// one async body keeps the clock alive. Per-cell localization is preserved in +/// the failure message, which names every broken cell. +void runMatrix( + String label, + RiverCoreConfig config, + List cells, { + Object? skip, +}) { + test(label, skip: skip, () async { + // Emulator goldens FIRST (pure Dart, before the Simulator starts). + final goldens = {}; + for (final cell in cells) { + goldens[cell.name] = await _emulatorGolden(config, cell); + } + // Build the HDL core ONCE (starts the Simulator in this body's context). + final mc = await _MatrixCore.build(config); + // Run every cell against the one built core; collect, don't throw, so all + // cells run and the message lists every failure. + final failures = []; + for (final cell in cells) { + final err = await mc.runHdl(cell, goldens[cell.name]!); + if (err != null) failures.add(' ${cell.name}: $err'); + } + await mc.dispose(); + expect( + failures, + isEmpty, + reason: + '${failures.length}/${cells.length} cells failed:\n' + '${failures.join('\n')}', + ); + }, timeout: Timeout(Duration(minutes: 10))); +} + +/// Golden architectural state for a cell (computed by the emulator). +class _Golden { + final Map regs; + final Map mem; + _Golden(this.regs, this.mem); +} + +/// A golden vector: a program with HAND-VERIFIED expected results (independent +/// truth, NOT emulator-computed). [runGolden] asserts BOTH the emulator AND the +/// HDL match these expected values. This closes the gap the matrix cells leave +/// open: matrix cells check emulator-vs-HDL parity, so a bug PRESENT IN BOTH +/// (or where one is accidentally right) can hide; the golden group pins each +/// engine to external truth (it is exactly what would have independently caught +/// the emulator bltu/bgeu bug) and confirms emulator<->HDL determinism. +class GoldenCell { + final String name; + final List program; + final Map seed; + final Map> dataMem; + final Map expectedRegs; + final Map expectedMem; + final int nextPc; + + const GoldenCell( + this.name, + this.program, { + this.seed = const {}, + this.dataMem = const {}, + this.expectedRegs = const {}, + this.expectedMem = const {}, + required this.nextPc, + }); + + MatrixCell get _asCell => MatrixCell( + name, + program, + seed: seed, + dataMem: dataMem, + checkRegs: expectedRegs.keys.toList(), + checkMem: expectedMem.keys.toList(), + nextPc: nextPc, + ); +} + +/// Architectural equality on the low [xlen] bits (mask = -1/all-ones at 64). +bool _archEq(int a, int b, int xlen) { + final mask = xlen >= 64 ? -1 : (1 << xlen) - 1; + return (a & mask) == (b & mask); +} + +/// Register the golden vectors for one [config] as a single test named [label]. +/// Each cell is checked TWICE against its hand-verified expected values: once on +/// the emulator (pins the golden ISS) and once on the built HDL (pins the RTL). +/// Failures are tagged [emu] or [hdl] so a divergence localizes to the engine. +void runGolden(String label, RiverCoreConfig config, List cells) { + test(label, () async { + final xlen = config.mxlen.size; + final failures = []; + // 1. Pin the EMULATOR against the hand-verified golden (run before the + // Simulator starts, same ordering rule as the matrix). + for (final gc in cells) { + final emu = await _emulatorGolden(config, gc._asCell); + gc.expectedRegs.forEach((r, want) { + final got = emu.regs[r] ?? 0; + if (!_archEq(got, want, xlen)) { + failures.add(' [emu] ${gc.name}: $r emu=$got want=$want'); + } + }); + gc.expectedMem.forEach((a, want) { + final got = emu.mem[a] ?? 0; + if (!_archEq(got, want, xlen)) { + failures.add( + ' [emu] ${gc.name}: mem[0x${a.toRadixString(16)}] emu=$got want=$want', + ); + } + }); + } + // 2. Pin the HDL against the SAME golden (reuses the matrix runner, which + // already masks to xlen bits). + final mc = await _MatrixCore.build(config); + for (final gc in cells) { + final err = await mc.runHdl( + gc._asCell, + _Golden(gc.expectedRegs, gc.expectedMem), + ); + if (err != null) failures.add(' [hdl] ${gc.name}: $err'); + } + await mc.dispose(); + expect( + failures, + isEmpty, + reason: + '${failures.length} golden checks failed:\n' + '${failures.join('\n')}', + ); + }, timeout: Timeout(Duration(minutes: 10))); +} + +/// Run [cell] on the emulator (golden ISS) and capture the observed reg/mem +/// state. Pure Dart, MUST be called before the HDL Simulator starts. +Future<_Golden> _emulatorGolden(RiverCoreConfig config, MatrixCell cell) async { + final sram = emu.Sram( + RiverDevice( + name: 'sram', + compatible: 'river,sram', + range: BusAddressRange(0, 0xFFFFF), + clockFrequency: (config.clock.rate as HarborFixedClockRate).frequency, + ), + ); + void ww(int addr, int value) { + for (var i = 0; i < 4; i++) { + sram.data[addr + i] = (value >> (i * 8)) & 0xFF; + } + } + + int rd64(int addr) { + var v = 0; + for (var i = 0; i < 8; i++) { + v |= sram.data[addr + i] << (i * 8); + } + return v; + } + + final ecore = emu.RiverCore(config, memDevices: Map.fromEntries([sram.mem!])); + for (var i = 0; i < cell.program.length; i++) { + ww(i * 4, cell.program[i]); + } + cell.dataMem.forEach((addr, words) { + for (var j = 0; j < words.length; j++) { + ww(addr + j * 4, words[j]); + } + }); + cell.seed.forEach((r, v) => ecore.xregs[r] = v); + var pc = config.resetVector; + for (var s = 0; s < 5000 && pc != cell.nextPc; s++) { + final instr = await ecore.fetch(pc); + pc = await ecore.cycle(pc, instr); + } + expect( + pc, + cell.nextPc, + reason: 'emulator did not reach nextPc=${cell.nextPc} (got $pc)', + ); + return _Golden( + {for (final r in cell.checkRegs) r: ecore.xregs[r] ?? 0}, + {for (final a in cell.checkMem) a: rd64(a)}, + ); +} + +/// A built-once HDL core, reusable across many programs (build-once-run-many). +class _MatrixCore { + final RiverCoreConfig config; + final int xlen; + final Logic clk; + final Logic reset; + final Logic seedGate; + final RiverCore core; + final SparseMemoryStorage storage; + + _MatrixCore._( + this.config, + this.xlen, + this.clk, + this.reset, + this.seedGate, + this.core, + this.storage, + ); + + static Future<_MatrixCore> build(RiverCoreConfig config) async { + await Simulator.reset(); + final xlen = config.mxlen.size; + final clk = SimpleClockGenerator(20).clk; + final reset = Logic(name: 'reset'); + final wbConfig = WishboneConfig( + addressWidth: xlen, + dataWidth: xlen, + selWidth: xlen ~/ 8, + ); + final core = RiverCore(config, busConfig: wbConfig); + core.input('clk').srcConnection! <= clk; + core.input('reset').srcConnection! <= reset; + await core.build(); + + final storage = SparseMemoryStorage( + addrWidth: xlen, + dataWidth: xlen, + alignAddress: (addr) => addr, + onInvalidRead: (addr, dataWidth) => + LogicValue.filled(dataWidth, LogicValue.zero), + ); + final memRead = DataPortInterface(xlen, xlen); + final memWrite = DataPortInterface(xlen, xlen); + // ignore: unused_local_variable + final mem = MemoryModel( + clk, + reset, + [wrapWriteForRegisterFile(memWrite)], + [wrapReadForRegisterFile(memRead, clk: clk, readLatency: 0)], + readLatency: 0, + storage: storage, + ); + final wbCyc = core.output('dataBus_CYC'); + final wbStb = core.output('dataBus_STB'); + final wbWe = core.output('dataBus_WE'); + memRead.en <= wbCyc & wbStb & ~wbWe; + memRead.addr <= core.output('dataBus_ADR'); + memWrite.en <= wbCyc & wbStb & wbWe; + memWrite.addr <= core.output('dataBus_ADR'); + memWrite.data <= core.output('dataBus_DAT_MOSI'); + final wbAckReg = Logic(name: 'wbAck'); + Sequential(clk, [ + If( + reset, + then: [wbAckReg < 0], + orElse: [ + If( + wbCyc & wbStb & ~wbAckReg & (wbWe | memRead.valid), + then: [wbAckReg < 1], + orElse: [wbAckReg < 0], + ), + ], + ), + ]); + final seedGate = Logic(name: 'seedGate'); + core.input('dataBus_ACK').srcConnection! <= wbAckReg & ~seedGate; + core.input('dataBus_DAT_MISO').srcConnection! <= memRead.data; + + reset.inject(1); + seedGate.inject(0); + Simulator.setMaxSimTime(100000000); + unawaited(Simulator.run()); + await clk.nextPosedge; + return _MatrixCore._(config, xlen, clk, reset, seedGate, core, storage); + } + + String _memString(List program, Map> dataMem) { + String wordsAt(int addr, List words) { + final sb = StringBuffer('@${addr.toRadixString(16)}\n'); + for (final w in words) { + for (var b = 0; b < 4; b++) { + sb.write(((w >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + return '${sb.toString().trimRight()}\n'; + } + + final sb = StringBuffer(wordsAt(0, program)); + dataMem.forEach((addr, words) => sb.write(wordsAt(addr, words))); + return sb.toString(); + } + + /// Run [cell] on the shared built HDL core and compare to the [golden]. + /// Returns null on match, or a human-readable mismatch description on failure + /// (returned, not thrown, so the caller can run every cell). + Future runHdl(MatrixCell cell, _Golden golden) async { + // Reset clears the regfile / pipeline / CSR state from the prior cell. + reset.inject(1); + seedGate.inject(cell.seed.isNotEmpty ? 1 : 0); + for (var i = 0; i < 4; i++) { + await clk.nextPosedge; + } + storage.loadMemString(_memString(cell.program, cell.dataMem)); + reset.inject(0); + await clk.nextPosedge; + for (final e in cell.seed.entries) { + core.regWritePort.en.inject(1); + core.regWritePort.addr.inject(LogicValue.ofInt(e.key.value, 5)); + core.regWritePort.data.inject(LogicValue.ofInt(e.value, xlen)); + await clk.nextPosedge; + } + core.regWritePort.en.inject(0); + seedGate.inject(0); + while (reset.value.toBool()) { + await clk.nextPosedge; + } + var reached = false; + var lastPc = -1; + // Generous cap: the microcode (DynamicExecutionUnit) path is ~10x slower + // per instruction (a multi-cycle linear pattern search per decode), so long + // multi-instruction cells (e.g. the seeded INT_MIN edge cells, ~14 instrs + // plus a 64-cycle divide) need a few thousand cycles. Fast paths break out + // as soon as nextPc is reached, so the higher cap costs them nothing. + for (var i = 0; i < 4000; i++) { + await clk.nextPosedge; + final p = core.pipeline.nextPc.value; + lastPc = p.isValid ? p.toInt() : -1; + if (p.isValid && p.toInt() == cell.nextPc) { + reached = true; + break; + } + } + + if (!reached) { + return 'did not reach nextPc=0x${cell.nextPc.toRadixString(16)} ' + '(stuck at pc=0x${lastPc.toRadixString(16)})'; + } + // Compare the architectural low-xlen bits. The HDL regfile/memory values are + // xlen-bit unsigned; the emulator goldens are signed Dart ints. On rv64 they + // coincide (Dart int is 64-bit two's complement); on rv32 a negative result + // reads as 0xFFFFFFF8 from the HDL vs -8 from the emulator. Masking both to + // xlen bits normalizes the representation (mask = -1 / all-ones for xlen>=64). + final mask = xlen >= 64 ? -1 : (1 << xlen) - 1; + for (final e in golden.regs.entries) { + final v = core.regs.getData(LogicValue.ofInt(e.key.value, 5))!.toInt(); + if ((v & mask) != (e.value & mask)) { + return '${e.key} HDL=$v golden=${e.value}'; + } + } + for (final e in golden.mem.entries) { + final v = storage.getData(LogicValue.ofInt(e.key, xlen))!.toInt(); + if ((v & mask) != (e.value & mask)) { + return 'mem[0x${e.key.toRadixString(16)}] HDL=$v golden=${e.value}'; + } + } + return null; + } + + Future dispose() async { + await Simulator.endSimulation(); + await Simulator.simulationEnded; + } +} diff --git a/packages/river_hdl/test/matrix_instructions.dart b/packages/river_hdl/test/matrix_instructions.dart new file mode 100644 index 0000000..f7c9922 --- /dev/null +++ b/packages/river_hdl/test/matrix_instructions.dart @@ -0,0 +1,862 @@ +import 'package:river/river.dart'; + +import 'matrix_encoders.dart'; +import 'matrix_harness.dart'; + +/// The instruction table: per-category lists of [MatrixCell]s, parameterized by +/// mxlen for width-applicability. The emulator computes the expected result, so +/// a cell only declares the encoding + operands + which reg to observe. +/// +/// Standard 2-operand cell: seed x1=a, x2=b, run [instr] (rs1=1, rs2=2, rd=3), +/// then compare x3 to the emulator golden. +MatrixCell _op(String name, int instr, {int a = -5, int b = 3}) => MatrixCell( + name, + [iimm(a, 0, 0x0, 1), iimm(b, 0, 0x0, 2), instr, nop], + checkRegs: [Register.x3], + nextPc: 0x0C, +); + +/// Single-operand cell (e.g. clz/sext.b): seed x1=a via an addi, run [instr] +/// (rs1=x1, rd=x3), check x3. An 8-nop tail lets the result retire before the +/// halt and keeps the dual fetcher from running off the end. +MatrixCell _unary(String name, int instr, {required int a}) => MatrixCell( + name, + [iimm(a, 0, 0x0, 1), instr, ...List.filled(8, nop)], + checkRegs: [Register.x3], + nextPc: 0x28, +); + +/// Program-built 2-operand cell: [setup] instructions construct x1/x2 (used for +/// values out of a 12-bit immediate's range, e.g. INT_MIN via addi+slli), then +/// [instr] runs (rs1=1, rs2=2, rd=3) and x3 is checked. Operands are built with +/// real instructions rather than the backdoor seed map so there is no seeding +/// race with the running pipeline. The 8-nop tail mirrors [_unary] so the OoO +/// dual fetcher does not run off the end before the result retires. +MatrixCell _opProg(String name, List setup, int instr) { + final program = [...setup, instr, ...List.filled(8, nop)]; + return MatrixCell( + name, + program, + checkRegs: [Register.x3], + nextPc: 4 * program.length, + ); +} + +/// addi rd, x0, imm (load a small signed immediate). +int _li(int imm, int rd) => iimm(imm, 0, 0x0, rd); + +/// slli rd, rs, shamt. +int _slli(int shamt, int rs, int rd) => iimm(shamt, rs, 0x1, rd); + +/// Build `1 << bit` into x1 with addi + chained slli. Each shift amount is +/// kept <= 31 so bit 25 (shamt[5]) is never set: a strict RV32-style decoder +/// reads bits[31:25] as funct7 and rejects slli with a non-zero funct7, so a +/// single `slli 63` would decode illegal. Chained shifts of <= 31 stay legal +/// under both the rv32 and rv64 shift encodings. +List _oneShl(int bit) { + final out = [_li(1, 1)]; + var remaining = bit; + while (remaining > 0) { + final step = remaining > 31 ? 31 : remaining; + out.add(_slli(step, 1, 1)); + remaining -= step; + } + return out; +} + +/// Look up a category's instruction cells for an mxlen. +List instructionsFor(String category, RiscVMxlen mxlen) => + switch (category) { + 'base' => baseAlu(mxlen), + 'm' => mExtension(mxlen), + 'bitmanip' => bitmanip(mxlen), + 'zicond' => zicond(mxlen), + 'a' => atomics(mxlen), + 'zacas' => zacas(mxlen), + 'loadstore' => loadStore(mxlen), + 'branch' => controlFlow(mxlen), + 'csr' => csrOps(mxlen), + 'fd' => fdOps(mxlen), + 'd' => dOps(mxlen), + 'v' => vOps(mxlen), + _ => throw ArgumentError('no instruction table for category "$category"'), + }; + +/// V vector (in-order; uses vector loads/stores - OoO mem FU incomplete). Each +/// cell sets e32/m1 (VLEN=128 -> vl=4 elements), loads two vectors from dataMem +/// via vle32, runs the op, stores the result via vse32, and checks the two +/// 64-bit result words (4x32-bit elements). The emulator computes the golden. +List vOps(RiscVMxlen mxlen) { + const v1 = [10, 20, 30, 40]; + const v2 = [3, 5, 7, 9]; + // vsetvli x1,x0,e32m1 (vl=VLMAX=4); x10/x11 = src bases, x12 = dst base. + List prologue() => [ + vsetvli(0x10, 0, 1), + iimm(0x100, 0, 0x0, 10), + iimm(0x120, 0, 0x0, 11), + iimm(0x200, 0, 0x0, 12), + vle32(10, 1), // v1 = mem[0x100..] + vle32(11, 2), // v2 = mem[0x120..] + ]; + // vector-vector op v3 = v1 OP v2, stored to mem[0x200]. + MatrixCell vv(String name, int funct6) => MatrixCell( + name, + [ + ...prologue(), + vopivv(funct6, 2, 1, 3), + vse32(12, 3), + ...List.filled(8, nop), + ], + dataMem: {0x100: v1, 0x120: v2}, + checkMem: [0x200, 0x208], + nextPc: 0x40, + ); + return [ + vv('vadd.vv', 0x00), + vv('vsub.vv', 0x02), + vv('vand.vv', 0x09), + vv('vor.vv', 0x0A), + vv('vxor.vv', 0x0B), + vv('vminu.vv', 0x04), + vv('vmin.vv', 0x05), + vv('vmaxu.vv', 0x06), + vv('vmax.vv', 0x07), + vv('vsll.vv', 0x25), + vv('vsrl.vv', 0x28), + // vadd.vx: v3 = v1 + x13 (scalar broadcast). + MatrixCell( + 'vadd.vx', + [ + vsetvli(0x10, 0, 1), + iimm(0x100, 0, 0x0, 10), + iimm(0x200, 0, 0x0, 12), + iimm(7, 0, 0x0, 13), // scalar 7 + vle32(10, 1), + vopivx(0x00, 1, 13, 3), // vadd.vx v3, v1, x13 + vse32(12, 3), + ...List.filled(8, nop), + ], + dataMem: {0x100: v1}, + checkMem: [0x200, 0x208], + nextPc: 0x3C, + ), + // vadd.vi: v3 = v1 + imm5 (5). + MatrixCell( + 'vadd.vi', + [ + vsetvli(0x10, 0, 1), + iimm(0x100, 0, 0x0, 10), + iimm(0x200, 0, 0x0, 12), + vle32(10, 1), + vopivi(0x00, 1, 5, 3), // vadd.vi v3, v1, 5 + vse32(12, 3), + ...List.filled(8, nop), + ], + dataMem: {0x100: v1}, + checkMem: [0x200, 0x208], + nextPc: 0x38, + ), + ]; +} + +/// D double-precision (rv64 only - 64-bit doubles + fmv.x.d need 64-bit GPRs; +/// rv32 FP doesn't elaborate, task #71). Same shape as [fdOps]: FS-enable +/// prologue, load 64-bit doubles via fld (little-endian word pairs in dataMem), +/// run the op, move bits to a GPR via fmv.x.d (funct7 0x71) to check. +List dOps(RiscVMxlen mxlen) { + // 2.0d = 0x4000000000000000, 4.0d = 0x4010000000000000 (low word, high word). + const mem = [0x00000000, 0x40000000, 0x00000000, 0x40100000]; + final fsOn = [lui(0x6, 5), csr(0x300, 5, 0x2, 0)]; + MatrixCell arith(String name, int funct7, {int f3sel = 0x0}) => MatrixCell( + name, + [ + ...fsOn, + iimm(0x200, 0, 0x0, 2), + fld(0, 2, 1), // f1 = 2.0d + fld(8, 2, 2), // f2 = 4.0d + fpOp(funct7, 2, 1, f3sel, 3), + fpOp(0x71, 0, 3, 0x0, 3), // fmv.x.d x3, f3 + ...List.filled(8, nop), + ], + dataMem: {0x200: mem}, + checkRegs: [Register.x3], + nextPc: 0x3C, + ); + MatrixCell cmp(String name, int f3) => MatrixCell( + name, + [ + ...fsOn, + iimm(0x200, 0, 0x0, 2), + fld(0, 2, 1), + fld(8, 2, 2), + fpOp(0x51, 2, 1, f3, 3), // feq/flt/fle.d x3, f1, f2 + ...List.filled(8, nop), + ], + dataMem: {0x200: mem}, + checkRegs: [Register.x3], + nextPc: 0x38, + ); + return [ + arith('fadd.d', 0x01), + arith('fsub.d', 0x05), + arith('fmul.d', 0x09), + arith('fdiv.d', 0x0D), + arith('fmin.d', 0x15, f3sel: 0x0), + arith('fmax.d', 0x15, f3sel: 0x1), + cmp('feq.d', 0x2), + cmp('flt.d', 0x1), + cmp('fle.d', 0x0), + // fcvt.w.d x3, f1 : double -> signed int (2.0 -> 2). + MatrixCell( + 'fcvt.w.d', + [ + ...fsOn, + iimm(0x200, 0, 0x0, 2), + fld(0, 2, 1), + fpOp(0x61, 0, 1, 0x0, 3), // fcvt.w.d x3, f1 + ...List.filled(8, nop), + ], + dataMem: {0x200: mem}, + checkRegs: [Register.x3], + nextPc: 0x34, + ), + // fcvt.d.w f3, x1 : int -> double (5 -> 5.0d), then bits to x3. + MatrixCell( + 'fcvt.d.w', + [ + ...fsOn, + iimm(5, 0, 0x0, 1), + fpOp(0x69, 0, 1, 0x0, 3), // fcvt.d.w f3, x1 + fpOp(0x71, 0, 3, 0x0, 3), // fmv.x.d x3, f3 + ...List.filled(8, nop), + ], + checkRegs: [Register.x3], + nextPc: 0x34, + ), + // fcvt.s.d f3, f1 : double -> single (rs2=1 selects .d source), bits to x3. + MatrixCell( + 'fcvt.s.d', + [ + ...fsOn, + iimm(0x200, 0, 0x0, 2), + fld(0, 2, 1), + fpOp(0x20, 1, 1, 0x0, 3), // fcvt.s.d f3, f1 + fpOp(0x70, 0, 3, 0x0, 3), // fmv.x.w x3, f3 + ...List.filled(8, nop), + ], + dataMem: {0x200: mem}, + checkRegs: [Register.x3], + nextPc: 0x38, + ), + ]; +} + +/// F/D single-precision. FP needs mstatus.FS enabled or FP ops trap, so every +/// cell starts with `lui x5,0x6 ; csrrs mstatus,x5` (FS=Dirty). Operands are FP +/// bit patterns loaded from dataMem; results are moved to a GPR via fmv.x.w (the +/// raw bits) and checked there, with the emulator computing the golden. +List fdOps(RiscVMxlen mxlen) { + const a = 0x40000000; // 2.0f + const b = 0x40800000; // 4.0f + // Prologue: enable FP (mstatus.FS = 0b11). x5 = 0x6000, csrrs mstatus, x5. + final fsOn = [lui(0x6, 5), csr(0x300, 5, 0x2, 0)]; + // f1 = mem[0x200], f2 = mem[0x204], f3 = f1 OP f2, x3 = bits(f3). [f3sel] is + // the rounding mode for true arithmetic (RNE=0) or the min/max selector. + MatrixCell arith(String name, int funct7, {int f3sel = 0x0}) => MatrixCell( + name, + [ + ...fsOn, + iimm(0x200, 0, 0x0, 2), + flw(0, 2, 1), + flw(4, 2, 2), + fpOp(funct7, 2, 1, f3sel, 3), // OP.s f3, f1, f2 + fpOp(0x70, 0, 3, 0x0, 3), // fmv.x.w x3, f3 + ...List.filled(8, nop), + ], + dataMem: { + 0x200: [a, b], + }, + checkRegs: [Register.x3], + nextPc: 0x3C, + ); + // Comparisons write a GPR (0/1) directly. + MatrixCell cmp(String name, int f3) => MatrixCell( + name, + [ + ...fsOn, + iimm(0x200, 0, 0x0, 2), + flw(0, 2, 1), + flw(4, 2, 2), + fpOp(0x50, 2, 1, f3, 3), // feq/flt/fle.s x3, f1, f2 + ...List.filled(8, nop), + ], + dataMem: { + 0x200: [a, b], + }, + checkRegs: [Register.x3], + nextPc: 0x38, + ); + return [ + arith('fadd.s', 0x00), + arith('fsub.s', 0x04), + arith('fmul.s', 0x08), + arith('fdiv.s', 0x0C), + arith('fmin.s', 0x14, f3sel: 0x0), // funct7 0x14, funct3 0 = fmin + arith('fmax.s', 0x14, f3sel: 0x1), // funct3 1 = fmax + cmp('feq.s', 0x2), + cmp('flt.s', 0x1), + cmp('fle.s', 0x0), + // fcvt.w.s x3, f1 : float -> signed int (2.0 -> 2). + MatrixCell( + 'fcvt.w.s', + [ + ...fsOn, + iimm(0x200, 0, 0x0, 2), + flw(0, 2, 1), + fpOp(0x60, 0, 1, 0x0, 3), // fcvt.w.s x3, f1 (rs2=0 selects .w) + ...List.filled(8, nop), + ], + dataMem: { + 0x200: [a], + }, + checkRegs: [Register.x3], + nextPc: 0x34, + ), + // fcvt.s.w f3, x1 : int -> float (5 -> 5.0), then bits to x3. + MatrixCell( + 'fcvt.s.w', + [ + ...fsOn, + iimm(5, 0, 0x0, 1), + fpOp(0x68, 0, 1, 0x0, 3), // fcvt.s.w f3, x1 + fpOp(0x70, 0, 3, 0x0, 3), // fmv.x.w x3, f3 + ...List.filled(8, nop), + ], + checkRegs: [Register.x3], + nextPc: 0x34, + ), + ]; +} + +/// Zicsr round-trips through mscratch (a plain read/write CSR, no side effects). +/// CSR ops are multi-cycle + serialized on OoO, so each cell ends with a read +/// into a check reg and carries an 8-nop tail. +List csrOps(RiscVMxlen mxlen) { + const mscratch = 0x340; + const rpipelinectl = 0x7C3; + const rpipelinecap = 0xFC0; + return [ + // csrrw: write x1=0x42 to mscratch (discard old into x0), read back -> x3. + MatrixCell( + 'csrrw', + [ + iimm(0x42, 0, 0x0, 1), + csr(mscratch, 1, 0x1, 0), // csrrw x0, mscratch, x1 + csr(mscratch, 0, 0x2, 3), // csrrs x3, mscratch, x0 (read) + ...List.filled(8, nop), + ], + checkRegs: [Register.x3], + nextPc: 0x2C, + ), + // csrrs: set bit 0; x3 = old (0x42), x4 = new (0x43). + MatrixCell( + 'csrrs', + [ + iimm(0x42, 0, 0x0, 1), + csr(mscratch, 1, 0x1, 0), + iimm(0x1, 0, 0x0, 2), + csr(mscratch, 2, 0x2, 3), // csrrs x3, mscratch, x2 + csr(mscratch, 0, 0x2, 4), // read -> x4 + ...List.filled(8, nop), + ], + checkRegs: [Register.x3, Register.x4], + nextPc: 0x34, + ), + // csrrc: clear low nibble; x3 = old (0xFF), x4 = new (0xF0). + MatrixCell( + 'csrrc', + [ + iimm(0xFF, 0, 0x0, 1), + csr(mscratch, 1, 0x1, 0), + iimm(0x0F, 0, 0x0, 2), + csr(mscratch, 2, 0x3, 3), // csrrc x3, mscratch, x2 + csr(mscratch, 0, 0x2, 4), + ...List.filled(8, nop), + ], + checkRegs: [Register.x3, Register.x4], + nextPc: 0x34, + ), + // csrrwi: write immediate 5, read back -> x3. + MatrixCell( + 'csrrwi', + [ + csri(mscratch, 5, 0x5, 0), + csr(mscratch, 0, 0x2, 3), + ...List.filled(8, nop), + ], + checkRegs: [Register.x3], + nextPc: 0x28, + ), + // rpipelinectl is WARL: write 0xFF, only bits [3:0] stick -> read back 0xF. + // Verifies the vendor pipeline-control CSR masks identically in emu + HDL. + MatrixCell( + 'rpipelinectl-warl', + [ + iimm(0xFF, 0, 0x0, 1), // x1 = 0xFF + csr(rpipelinectl, 1, 0x1, 0), // csrrw x0, rpipelinectl, x1 + csr( + rpipelinectl, + 0, + 0x2, + 3, + ), // csrrs x3, rpipelinectl, x0 (read) -> 0xF + ...List.filled(8, nop), + ], + checkRegs: [Register.x3], + nextPc: 0x2C, + ), + // rpipelinecap is the read-only feature bitmap; emu + HDL both derive it + // from the same config, so the read must match. (csrrs rs1=x0 reads a RO CSR + // without trapping now that the HDL suppresses the no-op write, task #76.) + MatrixCell( + 'rpipelinecap-read', + [ + csr(rpipelinecap, 0, 0x2, 3), // csrrs x3, rpipelinecap, x0 (read) + ...List.filled(8, nop), + ], + checkRegs: [Register.x3], + nextPc: 0x24, + ), + ]; +} + +/// An AMO cell: x10=addr, x11=operand, mem[addr]=memInit; run [instr] (rd=x12 +/// gets the old value), check x12 + mem. [seed] lets amocas pre-set x12. +MatrixCell _amo( + String name, + int instr, { + required int memInit, + Map seed = const {}, + int operand = 5, +}) => MatrixCell( + name, + [iimm(0x100, 0, 0x0, 10), iimm(operand, 0, 0x0, 11), instr, nop], + seed: seed, + dataMem: { + 0x100: [memInit], + }, + checkRegs: [Register.x12], + checkMem: [0x100], + nextPc: 0x10, +); + +/// Base integer ALU: OP + OP-IMM (+ OP-32 / OP-IMM-32 on rv64). +List baseAlu(RiscVMxlen mxlen) => [ + _op('add', rtype(0x00, 2, 1, 0x0, 3)), + _op('sub', rtype(0x20, 2, 1, 0x0, 3)), + _op('sll', rtype(0x00, 2, 1, 0x1, 3)), + _op('slt', rtype(0x00, 2, 1, 0x2, 3)), + _op('sltu', rtype(0x00, 2, 1, 0x3, 3)), + _op('xor', rtype(0x00, 2, 1, 0x4, 3)), + _op('srl', rtype(0x00, 2, 1, 0x5, 3)), + _op('sra', rtype(0x20, 2, 1, 0x5, 3)), + _op('or', rtype(0x00, 2, 1, 0x6, 3)), + _op('and', rtype(0x00, 2, 1, 0x7, 3)), + _op('addi', iimm(7, 1, 0x0, 3)), + _op('andi', iimm(0x0F, 1, 0x7, 3)), + _op('ori', iimm(0x0F, 1, 0x6, 3)), + _op('xori', iimm(0x0F, 1, 0x4, 3)), + _op('slti', iimm(0, 1, 0x2, 3)), + _op('sltiu', iimm(0, 1, 0x3, 3)), + _op('slli', iimm(3, 1, 0x1, 3)), + _op('srli', iimm(3, 1, 0x5, 3)), + _op('srai', iimm(0x403, 1, 0x5, 3)), // shamt=3, funct6=0x10 + // Sign-extended (negative) OP-IMM immediates: the 12-bit imm sign-extends + // to xlen before the op (folded from core_parity_test's OP-IMM subtest). + _op('addi neg imm', iimm(-100, 1, 0x0, 3)), + _op('ori neg imm', iimm(-1, 1, 0x6, 3)), // ori with all-ones imm + _op('andi neg imm', iimm(-16, 1, 0x7, 3)), + // lui/auipc are single-result ops: an 8-nop tail lets the result retire + // and keeps the (dual) fetcher from running off the end into zero memory. + MatrixCell( + 'lui', + [lui(0x12345, 3), ...List.filled(8, nop)], + checkRegs: [Register.x3], + nextPc: 0x24, + ), + MatrixCell( + 'auipc', + [auipc(0x1, 3), ...List.filled(8, nop)], + checkRegs: [Register.x3], + nextPc: 0x24, + ), + if (mxlen == RiscVMxlen.rv64) ...[ + _op('addw', rtypeW(0x00, 2, 1, 0x0, 3)), + _op('subw', rtypeW(0x20, 2, 1, 0x0, 3)), + _op('sllw', rtypeW(0x00, 2, 1, 0x1, 3)), + _op('srlw', rtypeW(0x00, 2, 1, 0x5, 3)), + _op('sraw', rtypeW(0x20, 2, 1, 0x5, 3)), + _op('addiw', iimmW(7, 1, 0x0, 3)), + ], +]; + +/// M extension: mul/div family + signed div/rem edge cases. +List mExtension(RiscVMxlen mxlen) => [ + _op('mul', rtype(0x01, 2, 1, 0x0, 3)), + _op('mulh', rtype(0x01, 2, 1, 0x1, 3)), + _op('mulhsu', rtype(0x01, 2, 1, 0x2, 3)), + _op('mulhu', rtype(0x01, 2, 1, 0x3, 3)), + _op('div', rtype(0x01, 2, 1, 0x4, 3)), + _op('divu', rtype(0x01, 2, 1, 0x5, 3)), + _op('rem', rtype(0x01, 2, 1, 0x6, 3)), + _op('remu', rtype(0x01, 2, 1, 0x7, 3)), + _op('div by zero', rtype(0x01, 0, 1, 0x4, 3)), // x1 / x0 + _op('rem by zero', rtype(0x01, 0, 1, 0x6, 3)), + if (mxlen == RiscVMxlen.rv64) ...[ + _op('mulw', rtypeW(0x01, 2, 1, 0x0, 3)), + _op('divw', rtypeW(0x01, 2, 1, 0x4, 3)), + _op('divuw', rtypeW(0x01, 2, 1, 0x5, 3)), + _op('remw', rtypeW(0x01, 2, 1, 0x6, 3)), + _op('remuw', rtypeW(0x01, 2, 1, 0x7, 3)), + ], + // Signed-overflow corner: INT_MIN / -1. div must return INT_MIN and rem 0 + // (no trap). INT_MIN is built with addi+slli since it is out of a 12-bit + // immediate's range. The emulator computes the golden; the divider only has + // to match it. x1 = INT_MIN, x2 = -1 (or 7 for the wide-unsigned probes). + ...() { + final signBit = mxlen == RiscVMxlen.rv64 ? 63 : 31; + return [ + _opProg('div overflow', [ + ..._oneShl(signBit), + _li(-1, 2), + ], rtype(0x01, 2, 1, 0x4, 3)), + _opProg('rem overflow', [ + ..._oneShl(signBit), + _li(-1, 2), + ], rtype(0x01, 2, 1, 0x6, 3)), + // Full-width unsigned: large dividend / small divisor exercises the top + // quotient bits the small-operand cells never set. + _opProg('divu wide', [ + ..._oneShl(signBit), + _li(7, 2), + ], rtype(0x01, 2, 1, 0x5, 3)), + _opProg('remu wide', [ + ..._oneShl(signBit), + _li(7, 2), + ], rtype(0x01, 2, 1, 0x7, 3)), + if (mxlen == RiscVMxlen.rv64) ...[ + // 32-bit overflow: INT32_MIN / -1 through the W ops. + _opProg('divw overflow', [ + ..._oneShl(31), + _li(-1, 2), + ], rtypeW(0x01, 2, 1, 0x4, 3)), + _opProg('remw overflow', [ + ..._oneShl(31), + _li(-1, 2), + ], rtypeW(0x01, 2, 1, 0x6, 3)), + ], + // Multiply edge cases that stress the FULL 2*XLEN product and the + // signed-high sign corrections (mulh/mulhsu) beyond the default -5*3 cell, + // which only sign-extends. INT_MIN and all-ones operands set the high word + // and flip the correction terms. The emulator computes the golden; the + // iterative multiplier only has to match. (x1=INT_MIN, x2=-1.) + ...() { + final signBit = mxlen == RiscVMxlen.rv64 ? 63 : 31; + final intMin = [..._oneShl(signBit), _li(-1, 2)]; // x1=INT_MIN, x2=-1 + return [ + _opProg('mulh int_min*-1', intMin, rtype(0x01, 2, 1, 0x1, 3)), + _opProg('mulhu int_min*-1', intMin, rtype(0x01, 2, 1, 0x3, 3)), + _opProg('mulhsu int_min*-1', intMin, rtype(0x01, 2, 1, 0x2, 3)), + _opProg('mul int_min*-1', intMin, rtype(0x01, 2, 1, 0x0, 3)), + ]; + }(), + ]; + }(), +]; + +/// Zba/Zbb/Zbs R-type bit-manipulation ops. +List bitmanip(RiscVMxlen mxlen) => [ + _op('andn', rtype(0x20, 2, 1, 0x7, 3)), + _op('orn', rtype(0x20, 2, 1, 0x6, 3)), + _op('xnor', rtype(0x20, 2, 1, 0x4, 3)), + _op('min', rtype(0x05, 2, 1, 0x4, 3)), + _op('max', rtype(0x05, 2, 1, 0x6, 3)), + _op('minu', rtype(0x05, 2, 1, 0x5, 3)), + _op('maxu', rtype(0x05, 2, 1, 0x7, 3)), + _op('sh1add', rtype(0x10, 2, 1, 0x2, 3)), + _op('sh2add', rtype(0x10, 2, 1, 0x4, 3)), + _op('sh3add', rtype(0x10, 2, 1, 0x6, 3)), + _op('bset', rtype(0x14, 2, 1, 0x1, 3), a: 1, b: 5), + _op('bclr', rtype(0x24, 2, 1, 0x1, 3), a: 0xFF, b: 3), + _op('binv', rtype(0x34, 2, 1, 0x1, 3), a: 0xFF, b: 3), + _op('bext', rtype(0x24, 2, 1, 0x5, 3), a: 0xFF, b: 3), + _op('rol', rtype(0x30, 2, 1, 0x1, 3)), + _op('ror', rtype(0x30, 2, 1, 0x5, 3)), + // Unary Zbb (rs2 field is a function selector, not a register; rs1=x1). + _unary('clz', rtype(0x30, 0x0, 1, 0x1, 3), a: 1), // count leading zeros + _unary('ctz', rtype(0x30, 0x1, 1, 0x1, 3), a: 8), // count trailing zeros + _unary('cpop', rtype(0x30, 0x2, 1, 0x1, 3), a: 0xFF), // popcount + _unary('sext.b', rtype(0x30, 0x4, 1, 0x1, 3), a: 0x80), + _unary('sext.h', rtype(0x30, 0x5, 1, 0x1, 3), a: 0x8000), + if (mxlen == RiscVMxlen.rv64) ...[ + _unary('clzw', rtypeW(0x30, 0x0, 1, 0x1, 3), a: 1), + _unary('ctzw', rtypeW(0x30, 0x1, 1, 0x1, 3), a: 8), + _unary('cpopw', rtypeW(0x30, 0x2, 1, 0x1, 3), a: 0xFF), + ], +]; + +/// Zicond: conditional-zero (czero.eqz / czero.nez), funct7 0x07, opcode OP. +/// Both the take and skip directions of the condition are covered. +List zicond(RiscVMxlen mxlen) => [ + // czero.eqz: rd = (rs2 == 0) ? 0 : rs1 + _op('czero.eqz rs2!=0', rtype(0x07, 2, 1, 0x5, 3), a: 0x1234, b: 7), + _op('czero.eqz rs2==0', rtype(0x07, 0, 1, 0x5, 3), a: 0x1234), + // czero.nez: rd = (rs2 != 0) ? 0 : rs1 + _op('czero.nez rs2!=0', rtype(0x07, 2, 1, 0x7, 3), a: 0x1234, b: 7), + _op('czero.nez rs2==0', rtype(0x07, 0, 1, 0x7, 3), a: 0x1234), +]; + +/// LR/SC cell: lr.X reserves (x12 = mem), sc.X stores 42 (x13 = 0 success); +/// check the loaded value, the success flag, and the written memory. +MatrixCell _lrsc(String name, int f3) => MatrixCell( + name, + [ + iimm(0x100, 0, 0x0, 10), // x10 = addr + iimm(42, 0, 0x0, 11), // x11 = store value + amo(0x02, 0, 10, f3, 12), // lr.X x12 = mem[x10], reserve + amo(0x03, 11, 10, f3, 13), // sc.X mem[x10] = x11, x13 = 0 on success + nop, + ], + dataMem: { + 0x100: [77], + }, + checkRegs: [Register.x12, Register.x13], + checkMem: [0x100], + nextPc: 0x14, +); + +/// A extension: AMO read-modify-write (.w on all widths, .d on rv64) + LR/SC. +List atomics(RiscVMxlen mxlen) => [ + _amo('amoadd.w', amo(0x00, 11, 10, 0x2, 12), memInit: 100), + _amo('amoswap.w', amo(0x01, 11, 10, 0x2, 12), memInit: 100), + _amo('amoxor.w', amo(0x04, 11, 10, 0x2, 12), memInit: 0xF0), + _amo('amoand.w', amo(0x0C, 11, 10, 0x2, 12), memInit: 0xFF), + _amo('amoor.w', amo(0x08, 11, 10, 0x2, 12), memInit: 0xF0), + _amo( + 'amomin.w', + amo(0x10, 11, 10, 0x2, 12), + memInit: -100, + operand: 5, + ), // signed/unsigned-differing operands + _amo( + 'amomax.w', + amo(0x14, 11, 10, 0x2, 12), + memInit: -100, + operand: 5, + ), // signed/unsigned-differing operands + _amo( + 'amominu.w', + amo(0x18, 11, 10, 0x2, 12), + memInit: -100, + operand: 5, + ), // signed/unsigned-differing operands + _amo( + 'amomaxu.w', + amo(0x1C, 11, 10, 0x2, 12), + memInit: -100, + operand: 5, + ), // signed/unsigned-differing operands + _lrsc('lr/sc.w', 0x2), + // sc-fail edge: a 2nd sc.w must FAIL (x14=1) since the 1st cleared the + // reservation (folded from core_parity_test's LR/SC subtest). + MatrixCell( + 'lr/sc.w fail', + [ + iimm(0x100, 0, 0x0, 10), + iimm(42, 0, 0x0, 11), + amo(0x02, 0, 10, 0x2, 12), // lr.w x12 = mem, reserve + amo(0x03, 11, 10, 0x2, 13), // sc.w x13 = 0 (ok), mem = 42 + amo(0x03, 11, 10, 0x2, 14), // sc.w x14 = 1 (fail) + nop, + ], + dataMem: { + 0x100: [7], + }, + checkRegs: [Register.x12, Register.x13, Register.x14], + checkMem: [0x100], + nextPc: 0x18, + ), + if (mxlen == RiscVMxlen.rv64) ...[ + _amo('amoadd.d', amo(0x00, 11, 10, 0x3, 12), memInit: 100), + _amo('amoswap.d', amo(0x01, 11, 10, 0x3, 12), memInit: 100), + _amo('amoxor.d', amo(0x04, 11, 10, 0x3, 12), memInit: 0xF0), + _amo('amoand.d', amo(0x0C, 11, 10, 0x3, 12), memInit: 0xFF), + _amo('amoor.d', amo(0x08, 11, 10, 0x3, 12), memInit: 0xF0), + _amo( + 'amomin.d', + amo(0x10, 11, 10, 0x3, 12), + memInit: -100, + operand: 5, + ), // signed/unsigned-differing operands + _amo( + 'amomax.d', + amo(0x14, 11, 10, 0x3, 12), + memInit: -100, + operand: 5, + ), // signed/unsigned-differing operands + _amo( + 'amominu.d', + amo(0x18, 11, 10, 0x3, 12), + memInit: -100, + operand: 5, + ), // signed/unsigned-differing operands + _amo( + 'amomaxu.d', + amo(0x1C, 11, 10, 0x3, 12), + memInit: -100, + operand: 5, + ), // signed/unsigned-differing operands + _lrsc('lr/sc.d', 0x3), + ], +]; + +/// amocas cell: x12 holds the compare value (and gets the old value back), +/// x11 is the swap value. Swap happens only when mem == compare. +MatrixCell _amocas( + String name, + int f3, { + required int memInit, + required int compare, + int swap = 0x55, +}) => MatrixCell( + name, + [ + iimm(0x100, 0, 0x0, 10), + iimm(swap, 0, 0x0, 11), + amo(0x05, 11, 10, f3, 12), + nop, + ], + seed: {Register.x12: compare}, + dataMem: { + 0x100: [memInit], + }, + checkRegs: [Register.x12], + checkMem: [0x100], + nextPc: 0x10, +); + +/// Zacas: amocas.w/.d compare-and-swap, both the match (swap) and no-match +/// (leave) outcomes. +List zacas(RiscVMxlen mxlen) => [ + _amocas('amocas.w match', 0x2, memInit: 77, compare: 77), + _amocas('amocas.w nomatch', 0x2, memInit: 77, compare: 12), + if (mxlen == RiscVMxlen.rv64) ...[ + _amocas('amocas.d match', 0x3, memInit: 77, compare: 77), + _amocas('amocas.d nomatch', 0x3, memInit: 77, compare: 12), + ], +]; + +/// Load cell: x2 = base 0x200, mem[0x200] = [lo, hi]; load x3 = mem[base+0], +/// check x3 (the emulator handles the sign/zero extension per width). +MatrixCell _load(String name, int f3, {required int lo, int hi = 0}) => + MatrixCell( + name, + [iimm(0x200, 0, 0x0, 2), load(0, 2, f3, 3), nop], + dataMem: { + 0x200: [lo, hi], + }, + checkRegs: [Register.x3], + nextPc: 0x0C, + ); + +/// Store cell: x1 = value (seeded), x2 = base 0x200; store x1 -> mem[base+0], +/// then check the written memory. +MatrixCell _store(String name, int f3, {required int value}) => MatrixCell( + name, + [iimm(0x200, 0, 0x0, 2), store(0, 1, 2, f3), nop], + seed: {Register.x1: value}, + checkMem: [0x200], + nextPc: 0x0C, +); + +/// Loads + stores. Sign/zero extension is exercised with high-bit values; +/// width-only ops (ld/lwu/sd) are gated to rv64. +List loadStore(RiscVMxlen mxlen) => [ + _load('lb sign', 0x0, lo: 0x80), + _load('lb pos', 0x0, lo: 0x7F), + _load('lh sign', 0x1, lo: 0x8000), + _load('lw', 0x2, lo: 0x12345678), + _load('lbu', 0x4, lo: 0x80), + _load('lhu', 0x5, lo: 0x8000), + _store('sb', 0x0, value: 0x9A), + _store('sh', 0x1, value: 0xBEEF), + _store('sw', 0x2, value: 0x12345678), + if (mxlen == RiscVMxlen.rv64) ...[ + _load('lw sign', 0x2, lo: 0x80000000), + _load('lwu', 0x6, lo: 0x80000000), + _load('ld', 0x3, lo: 0x89ABCDEF, hi: 0x01234567), + _store('sd', 0x3, value: 0x0123456789ABCDEF), + ], +]; + +/// Eight-nop tail so a taken redirect / misprediction-recovery fully drains +/// before the harness samples nextPc (mirrors core_bpred_test: never make the +/// branch target itself the halt PC, that races the redirect). +List get _tail => List.filled(8, nop); + +/// A conditional-branch cell, modeled on the proven bpred layout. x1=a, x2=b are +/// set by program instrs (NOT backdoor seed: the single write-port seed only +/// reliably lands one reg). The branch at 0x8 skips x3=99 (0xC) when taken and +/// lands on the x4=7 target (0x10); both paths converge through the nop tail to +/// nextPc=0x34. x3 (=0 taken / 99 fall-through) distinguishes the two paths. +MatrixCell _branch(String name, int f3, {required int a, required int b}) => + MatrixCell( + name, + [ + iimm(a, 0, 0x0, 1), // 0x0: x1 = a + iimm(b, 0, 0x0, 2), // 0x4: x2 = b + branch(8, 2, 1, f3), // 0x8: if cond, pc -> 0x10 (skip 0xC) + iimm(99, 0, 0x0, 3), // 0xC: x3 = 99 (fall-through only) + iimm(7, 0, 0x0, 4), // 0x10: x4 = 7 (branch target / converge) + ..._tail, // 0x14..0x30 + ], + checkRegs: [Register.x3], + nextPc: 0x34, + ); + +/// Branches (both directions) plus jal / jalr. +List controlFlow(RiscVMxlen mxlen) => [ + _branch('beq taken', 0x0, a: 5, b: 5), + _branch('beq fall', 0x0, a: 5, b: 6), + _branch('bne taken', 0x1, a: 5, b: 6), + _branch('bne fall', 0x1, a: 5, b: 5), + _branch('blt taken', 0x4, a: -1, b: 1), + _branch('blt fall', 0x4, a: 1, b: -1), + _branch('bge taken', 0x5, a: 1, b: -1), + _branch('bge fall', 0x5, a: -1, b: 1), + _branch('bltu taken', 0x6, a: 1, b: 2), + _branch('bltu fall', 0x6, a: 2, b: 1), + _branch('bgeu taken', 0x7, a: 2, b: 1), + _branch('bgeu fall', 0x7, a: 1, b: 2), + // Sign-differing operands: -1 is the largest UNSIGNED value, so unsigned + // and signed ordering disagree. Distinguishes bltu/bgeu from blt/bge and + // catches the "unsigned compare folded to signed" class of bug. + _branch('bltu big', 0x6, a: -1, b: 1), // -1 >=u 1 -> not taken + _branch('bltu small', 0x6, a: 1, b: -1), // 1 taken + _branch('bgeu big', 0x7, a: -1, b: 1), // -1 >=u 1 -> taken + _branch('bgeu small', 0x7, a: 1, b: -1), // 1 not taken + // jal x3, +8: link x3 = 0x4, jump to 0x8 skipping the x4=99 filler. + MatrixCell( + 'jal', + [jal(8, 3), iimm(99, 0, 0x0, 4), iimm(7, 0, 0x0, 2), ..._tail], + checkRegs: [Register.x3, Register.x4], + nextPc: 0x2C, + ), + // jalr x3, 8(x0): jump to 0x8, link x3 = 0x4, skipping x4=99. + MatrixCell( + 'jalr', + [jalr(8, 0, 3), iimm(99, 0, 0x0, 4), iimm(7, 0, 0x0, 2), ..._tail], + checkRegs: [Register.x3, Register.x4], + nextPc: 0x2C, + ), +]; diff --git a/packages/river_hdl/test/memory/port_test.dart b/packages/river_hdl/test/memory/port_test.dart index 7c19830..404cc97 100644 --- a/packages/river_hdl/test/memory/port_test.dart +++ b/packages/river_hdl/test/memory/port_test.dart @@ -2,7 +2,6 @@ import 'dart:async'; import 'package:test/test.dart'; import 'package:rohd/rohd.dart'; -import 'package:rohd_hcl/rohd_hcl.dart'; import 'package:river_hdl/river_hdl.dart'; Future testMultiDataPortWriter( diff --git a/packages/river_hdl/test/mmu/core_mmu_ooo_fault_test.dart b/packages/river_hdl/test/mmu/core_mmu_ooo_fault_test.dart new file mode 100644 index 0000000..ac36235 --- /dev/null +++ b/packages/river_hdl/test/mmu/core_mmu_ooo_fault_test.dart @@ -0,0 +1,119 @@ +import 'package:rohd/rohd.dart'; +import 'package:river/river.dart'; +import 'package:test/test.dart'; +import '../core_harness.dart'; + +/// OoO load page-fault path (task #73). A faulting load on the out-of-order core +/// used to HANG: the MemoryUnit's request FSM waits for a bus ack that never +/// arrives, because the MMU drives dport_valid=0 (no ack) on a page fault and +/// the FSM had no fault input (wbErr was tied to 0). The fix feeds the dport +/// `done & ~valid` page fault into the MemoryUnit so the access traps at commit. +/// +/// Same program + page tables as core_mmu_perm_test (S-mode load of a U=1 page +/// with SUM=0 -> load page fault, mcause 13), but on an outOfOrder config. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + final config = RiverCoreConfig( + mxlen: RiscVMxlen.rv64, + extensions: kRva22S64Extensions, + type: RiverCoreType.general, + executionMode: ExecutionMode.outOfOrder, + speculativeFetch: true, + branchPredictor: BranchPredictor.btfn, + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + hasSupervisorUserMemory: true, + hasMakeExecutableReadable: true, + ), + interrupts: [], + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + ); + + int csrw(int csr, int rs1) => (csr << 20) | (rs1 << 15) | (0x1 << 12) | 0x73; + int csrr(int csr, int rd) => (csr << 20) | (0x2 << 12) | (rd << 7) | 0x73; + int addi(int rd, int rs1, int imm) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (rd << 7) | 0x13; + int slli(int rd, int rs1, int sh) => + (sh << 20) | (rs1 << 15) | (0x1 << 12) | (rd << 7) | 0x13; + int lui(int rd, int imm20) => (imm20 << 12) | (rd << 7) | 0x37; + int ld(int rd, int rs1, int imm) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (0x3 << 12) | (rd << 7) | 0x03; + int ori(int rd, int rs1, int imm) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (0x6 << 12) | (rd << 7) | 0x13; + const jalLoop = 0x0000006F; + const nop = 0x00000013; + + String words(List ws) { + final sb = StringBuffer(); + for (final w in ws) { + for (var b = 0; b < 4; b++) { + sb.write(((w >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + return sb.toString().trimRight(); + } + + String pte(int v) { + final sb = StringBuffer(); + for (var b = 0; b < 8; b++) { + sb.write(((v >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + return sb.toString().trimRight(); + } + + // Full OoO supervisor + page-fault path (#77). The satp value is COMPUTED in + // the program rather than seeded: the initRegisters backdoor writes the + // architectural regfile, which the OoO core does not read (it reads renamed + // physical regs), so a seeded satp never reached the MMU and translation never + // activated. Computing it (and the #76 fix so csrrw is never suppressed as a + // no-op write) makes satp.MODE=Sv39 reach the MMU, the S-mode load translates, + // hits the U=1 page with SUM=0, and takes a load page fault that vectors to + // mtvec where mcause==13. + test( + 'OoO: S-mode load of a user page faults (traps, does not hang)', + timeout: Timeout(Duration(seconds: 180)), + () { + final prog = words([ + addi(10, 0, 1), // 0 @0x00 x10 = 1 + slli(10, 10, 63), // 1 @0x04 x10 = 1<<63 + ori(10, 10, 0x10), // 2 @0x08 x10 = 0x8000000000000010 (Sv39|root 0x10) + csrw(0x180, 10), // 3 @0x0c csrw satp, x10 + addi(11, 0, 0x30), // 4 @0x10 mepc target = 0x30 (S-mode entry) + csrw(0x341, 11), // 5 @0x14 csrw mepc, x11 + addi(12, 0, 1), // 6 @0x18 + slli(12, 12, 11), // 7 @0x1c x12 = 0x800 (MPP=S, MPV=0 -> virt=0) + csrw(0x300, 12), // 8 @0x20 csrw mstatus, x12 + addi(14, 0, 0x50), // 9 @0x24 x14 = 0x50 (mtvec) + csrw(0x305, 14), // 10 @0x28 csrw mtvec, x14 + 0x30200073, // 11 @0x2c mret -> S-mode, pc=0x30 + lui(13, 0x20), // 12 @0x30 a3 = 0x20000 + ld(5, 13, 0), // 13 @0x34 S-mode load of a U=1 page -> page fault + nop, nop, nop, nop, nop, nop, // 14-19 @0x38..0x4c + csrr(0x342, 5), // 20 @0x50 handler: x5 = mcause (== 13 loadPageFault) + jalLoop, // 21 @0x54 loop + ]); + return coreTest( + '@0\n$prog\n' + '@10000\n${pte(0x4401)}\n' + '@11000\n${pte(0x4801)}\n' + '@12000\n${pte(0x00B)}\n' + '@12100\n${pte(0xC01F)}\n' // l0[32] leaf: V|R|W|X|U=1 -> user page + '@30000\n${pte(0xCAFEF00D)}\n', + {Register.x5: 13}, // loadPageFault: S-mode denied the user page + config, + nextPc: 0x54, + ); + }, + ); +} diff --git a/packages/river_hdl/test/mmu/core_mmu_perm_test.dart b/packages/river_hdl/test/mmu/core_mmu_perm_test.dart new file mode 100644 index 0000000..61b7725 --- /dev/null +++ b/packages/river_hdl/test/mmu/core_mmu_perm_test.dart @@ -0,0 +1,101 @@ +import 'package:rohd/rohd.dart'; +import 'package:river/river.dart'; +import 'package:test/test.dart'; +import '../core_harness.dart'; + +/// MMU stage-2: leaf U-bit / SUM permission checks. A supervisor-mode load from +/// a user page (PTE.U=1) with mstatus.SUM=0 must take a load page fault. (M-mode +/// accesses bypass the U-check, which is why the other MMU tests are unaffected.) +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + final config = RiverCoreConfig( + mxlen: RiscVMxlen.rv64, + extensions: kRva22S64Extensions, + type: RiverCoreType.general, + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + hasSupervisorUserMemory: true, + hasMakeExecutableReadable: true, + ), + interrupts: [], + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + ); + + int csrw(int csr, int rs1) => (csr << 20) | (rs1 << 15) | (0x1 << 12) | 0x73; + int csrr(int csr, int rd) => (csr << 20) | (0x2 << 12) | (rd << 7) | 0x73; + int addi(int rd, int rs1, int imm) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (rd << 7) | 0x13; + int slli(int rd, int rs1, int sh) => + (sh << 20) | (rs1 << 15) | (0x1 << 12) | (rd << 7) | 0x13; + int lui(int rd, int imm20) => (imm20 << 12) | (rd << 7) | 0x37; + int ld(int rd, int rs1, int imm) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (0x3 << 12) | (rd << 7) | 0x03; + const jalLoop = 0x0000006F; + const nop = 0x00000013; + + String words(List ws) { + final sb = StringBuffer(); + for (final w in ws) { + for (var b = 0; b < 4; b++) { + sb.write(((w >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + return sb.toString().trimRight(); + } + + String pte(int v) { + final sb = StringBuffer(); + for (var b = 0; b < 8; b++) { + sb.write(((v >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + return sb.toString().trimRight(); + } + + test( + 'S-mode load of a user page (U=1, no SUM) faults', + timeout: Timeout(Duration(seconds: 120)), + () { + final prog = words([ + csrw(0x180, 10), // 0 csrw satp, a0 (Sv39 | root 0x10) + addi(11, 0, 0x24), //1 x11 = 0x24 (mepc = the load region) + csrw(0x341, 11), // 2 csrw mepc, x11 + addi(12, 0, 1), // 3 + slli(12, 12, 11), // 4 x12 = 0x800 (MPP=S, MPV=0 -> virt=0) + csrw(0x300, 12), // 5 csrw mstatus, x12 + addi(14, 0, 0x40), //6 x14 = 0x40 (mtvec) + csrw(0x305, 14), // 7 csrw mtvec, x14 + 0x30200073, // 8 @0x20 mret -> S-mode, pc=0x24 + lui(13, 0x20), // 9 @0x24 a3 = 0x20000 + ld(5, 13, 0), // 10 @0x28 S-mode load of a U=1 page -> page fault + nop, nop, nop, nop, nop, // 11-15 @0x2c..0x3c + csrr(0x342, 5), // 16 @0x40 handler: x5 = mcause (== 13 loadPageFault) + jalLoop, // 17 @0x44 loop + ]); + return coreTest( + '@0\n$prog\n' + '@10000\n${pte(0x4401)}\n' + '@11000\n${pte(0x4801)}\n' + // l0[0]: identity-map virtual page 0 -> PA 0 as a supervisor RX page so the + // S-mode code (after mret) can be fetched through translation (V|R|X, U=0). + '@12000\n${pte(0x00B)}\n' + '@12100\n${pte(0xC01F)}\n' // l0[32] leaf: V|R|W|X|U=1 -> user page + '@30000\n${pte(0xCAFEF00D)}\n', + {Register.x5: 13}, // loadPageFault: S-mode denied the user page + config, + initRegisters: {Register.x10: 0x8000000000000010}, + nextPc: 0x44, + ); + }, + ); +} diff --git a/packages/river_hdl/test/mmu/core_mmu_test.dart b/packages/river_hdl/test/mmu/core_mmu_test.dart new file mode 100644 index 0000000..29869f2 --- /dev/null +++ b/packages/river_hdl/test/mmu/core_mmu_test.dart @@ -0,0 +1,185 @@ +import 'package:rohd/rohd.dart'; +import 'package:river/river.dart'; +import 'package:test/test.dart'; +import '../core_harness.dart'; + +/// Sv39 page-table-walk verification for the HDL MMU. Mirrors the emulator's +/// `rva22_smode_test.dart` page-table setup: a 3-level walk that maps a virtual +/// page to a *different* physical page, proving the MMU actually translates +/// (rather than passing the address through). See project_hdl_mmu in memory. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + final config = RiverCoreConfig( + mxlen: RiscVMxlen.rv64, + extensions: kRva22S64Extensions, + type: RiverCoreType.general, + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + hasSupervisorUserMemory: true, + hasMakeExecutableReadable: true, + ), + interrupts: [], + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + ); + + // Page tables (identity within physical memory): + // l2 @ 0x10000 (satp root, PPN 0x10) + // l1 @ 0x11000 + // l0 @ 0x12000 + // Maps vaddr 0x20000 -> paddr 0x30000 (a *different* page). + // vpn2=0, vpn1=0, vpn0=0x20 -> l0 PTE at 0x12000 + 0x20*8 = 0x12100 + // PTEs: non-leaf = (nextPPN<<10)|V; leaf = (physPPN<<10)|V|R|W|X. + // l2[0] @ 0x10000 = (0x11<<10)|1 = 0x4401 + // l1[0] @ 0x11000 = (0x12<<10)|1 = 0x4801 + // l0[0x20]@ 0x12100 = (0x30<<10)|0xF = 0xC00F + // Diagnostic: bare (paging off) 64-bit load through the modified MMU, no walk. + test( + 'bare ld (no paging) loads 0x30000', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + // lui a2, 0x30 (0x00030637) -> a2 = 0x30000 + // ld a1, 0(a2) (0x00063583) + // nop + '''@0 +37 06 03 00 83 35 06 00 13 00 00 00 +@30000 +0D F0 FE CA 00 00 00 00 +''', + {Register.x11: 0xCAFEF00D}, + config, + nextPc: 0x0C, + ), + ); + + test( + 'Sv39 dport load translates 0x20000 -> 0x30000', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + // satp (MODE=8 Sv39, root PPN 0x10) is preloaded into a0; enable paging, + // then load from virtual 0x20000 (mapped to physical 0x30000). + // csrw satp, a0 (0x18051073) + // lui a2, 0x20 (0x00020637) -> a2 = 0x20000 (virtual) + // ld a1, 0(a2) (0x00063583) + // nop (0x00000013) + '''@0 +73 10 05 18 37 06 02 00 83 35 06 00 13 00 00 00 +@10000 +01 44 00 00 00 00 00 00 +@11000 +01 48 00 00 00 00 00 00 +@12100 +0F C0 00 00 00 00 00 00 +@30000 +0D F0 FE CA 00 00 00 00 +''', + {Register.x11: 0xCAFEF00D}, + config, + initRegisters: { + // satp: MODE=8 (Sv39) bits 63:60, root PPN = 0x10000>>12 = 0x10. + Register.x10: 0x8000000000000010, + }, + nextPc: 0x10, + ), + ); + + test( + 'Sv39 dport store translates 0x20000 -> 0x30000', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + // Enable Sv39, build a3 in-program, then store it to virtual 0x20000 + // (-> physical 0x30000). a3 is set in-program because the harness's + // initRegisters can only reliably preload a single register. + // csrw satp, a0 (0x18051073) + // lui a2, 0x20 (0x00020637) -> a2 = 0x20000 (virtual) + // addi a3, x0, 0x234 (0x23400693) + // sd a3, 0(a2) (0x00d63023) + // nop (0x00000013) + '''@0 +73 10 05 18 37 06 02 00 93 06 40 23 23 30 d6 00 +13 00 00 00 +@10000 +01 44 00 00 00 00 00 00 +@11000 +01 48 00 00 00 00 00 00 +@12100 +0F C0 00 00 00 00 00 00 +@30000 +00 00 00 00 00 00 00 00 +''', + const {}, + config, + initRegisters: {Register.x10: 0x8000000000000010}, + // The translated physical address 0x30000 holds the stored value. + memStates: {0x30000: 0x234}, + nextPc: 0x14, + ), + ); + + final sv48Config = RiverCoreConfig( + mxlen: RiscVMxlen.rv64, + extensions: kRva22S64Extensions, + type: RiverCoreType.general, + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [ + RiscVPagingMode.bare, + RiscVPagingMode.sv39, + RiscVPagingMode.sv48, + ], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + hasSupervisorUserMemory: true, + hasMakeExecutableReadable: true, + ), + interrupts: [], + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + ); + + // Sv48: 4-level walk. Page tables identity within memory: + // l3 @ 0x10000 (root, PPN 0x10), l2 @ 0x11000, l1 @ 0x12000, l0 @ 0x13000. + // Maps vaddr 0x20000 -> paddr 0x30000. + // vpn3=0, vpn2=0, vpn1=0, vpn0=0x20 -> l0 PTE at 0x13000 + 0x20*8 = 0x13100 + // l3[0] @ 0x10000 = (0x11<<10)|1 = 0x4401 + // l2[0] @ 0x11000 = (0x12<<10)|1 = 0x4801 + // l1[0] @ 0x12000 = (0x13<<10)|1 = 0x4C01 + // l0[0x20] @ 0x13100 = (0x30<<10)|0xF = 0xC00F + test( + 'Sv48 dport load translates 0x20000 -> 0x30000 (4-level)', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + // satp MODE=9 (Sv48), root PPN 0x10. + '''@0 +73 10 05 18 37 06 02 00 83 35 06 00 13 00 00 00 +@10000 +01 44 00 00 00 00 00 00 +@11000 +01 48 00 00 00 00 00 00 +@12000 +01 4C 00 00 00 00 00 00 +@13100 +0F C0 00 00 00 00 00 00 +@30000 +0D F0 FE CA 00 00 00 00 +''', + {Register.x11: 0xCAFEF00D}, + sv48Config, + initRegisters: { + // satp: MODE=9 (Sv48) bits 63:60, root PPN 0x10. + Register.x10: 0x9000000000000010, + }, + nextPc: 0x10, + ), + ); +} diff --git a/packages/river_hdl/test/mmu/core_twostage_test.dart b/packages/river_hdl/test/mmu/core_twostage_test.dart new file mode 100644 index 0000000..3f7ea48 --- /dev/null +++ b/packages/river_hdl/test/mmu/core_twostage_test.dart @@ -0,0 +1,112 @@ +import 'package:rohd/rohd.dart'; +import 'package:river/river.dart'; +import 'package:test/test.dart'; +import '../core_harness.dart'; + +/// H3: full two-stage translation. A guest load is translated VS-stage +/// (vsatp: gva 0x20000 -> gpa 0x30000) and then every VS page-table access AND +/// the final gpa are G-translated (hgatp). The G-stage identity-maps the VS +/// table pages but REMAPS gpa 0x30000 -> host 0x40000, where the data lives, +/// so the load only returns the right value if BOTH stages walk correctly. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + final config = RiverCoreConfig( + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + mxlen: RiscVMxlen.rv64, + extensions: [rv64i, rv32i, rvZicsr, rvZifencei, rvPriv, rvH], + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + ); + + int csrw(int csr, int rs1) => (csr << 20) | (rs1 << 15) | (0x1 << 12) | 0x73; + int addi(int rd, int rs1, int imm) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (rd << 7) | 0x13; + int slli(int rd, int rs1, int sh) => + (sh << 20) | (rs1 << 15) | (0x1 << 12) | (rd << 7) | 0x13; + int orr(int rd, int rs1, int rs2) => + (rs2 << 20) | (rs1 << 15) | (0x6 << 12) | (rd << 7) | 0x33; + int lui(int rd, int imm20) => (imm20 << 12) | (rd << 7) | 0x37; + int ld(int rd, int rs1, int imm) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (0x3 << 12) | (rd << 7) | 0x03; + const mret = 0x30200073; + + String words(List ws) { + final sb = StringBuffer(); + for (final w in ws) { + for (var b = 0; b < 4; b++) { + sb.write(((w >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + return sb.toString().trimRight(); + } + + // 8-byte little-endian PTE string. + String pte(int v) { + final sb = StringBuffer(); + for (var b = 0; b < 8; b++) { + sb.write(((v >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + return sb.toString().trimRight(); + } + + test( + 'two-stage VS+G translates guest load to remapped host page', + timeout: Timeout(Duration(seconds: 180)), + () { + final prog = words([ + csrw(0x280, 10), // 0 csrw vsatp, a0 (Sv39 | root gpa-PPN 0x10) + addi(15, 0, 1), // 1 x15 = 1 + slli(15, 15, 63), // 2 x15 = 1<<63 + addi(14, 0, 0x50), //3 x14 = 0x50 + orr(14, 14, 15), // 4 x14 = hgatp (Sv39 | root host-PPN 0x50) + csrw(0x680, 14), // 5 csrw hgatp, x14 + addi(12, 0, 1), // 6 x12 = 1 + slli(12, 12, 11), // 7 x12 = 0x800 (MPP=S) + addi(13, 0, 1), // 8 x13 = 1 + slli(13, 13, 39), // 9 x13 = MPV bit + orr(12, 12, 13), //10 x12 = 0x8000000800 + csrw(0x300, 12), //11 csrw mstatus, x12 + addi(11, 0, 0x3c), //12 x11 = 0x3c (mepc target = idx15) + csrw(0x341, 11), //13 csrw mepc, x11 + mret, // 14 -> VS-mode (S, virt=1), pc=0x3c + lui(13, 0x20), // 15 x13 = 0x20000 (guest virtual) + ld(3, 13, 0), // 16 x3 = *(two-stage translate(0x20000)) + 0x00000013, // 17 nop + ]); + return coreTest( + '@0\n$prog\n' + // VS-stage tables (live at host = identity of their gpa via G-stage): + '@10000\n${pte(0x4401)}\n' // vs_l2[0] -> gpa 0x11000 + '@11000\n${pte(0x4801)}\n' // vs_l1[0] -> gpa 0x12000 + '@12100\n${pte(0xC00F)}\n' // vs_l0[0x20] leaf -> gpa 0x30000 + // Data lives at HOST 0x40000 (gpa 0x30000 remapped by the G-stage): + '@40000\n${pte(0xCAFEF00D)}\n' + // G-stage tables (host-physical; hgatp root host-PPN 0x50): + '@50000\n${pte(0x14401)}\n' // g_l2[0] -> host 0x51000 + '@51000\n${pte(0x14801)}\n' // g_l1[0] -> host 0x52000 + '@52080\n${pte(0x401F)}\n' // g_l0[0x10] gpa0x10->host0x10 (V|R|W|X|U) + '@52088\n${pte(0x441F)}\n' // g_l0[0x11] gpa0x11->host0x11 + '@52090\n${pte(0x481F)}\n' // g_l0[0x12] gpa0x12->host0x12 + '@52180\n${pte(0x1001F)}\n', // g_l0[0x30] gpa0x30->host0x40 (remap!) + {Register.x3: 0xCAFEF00D}, + config, + initRegisters: {Register.x10: 0x8000000000000010}, + nextPc: 0x48, + ); + }, + ); +} diff --git a/packages/river_hdl/test/mmu/mmu_fault_test.dart b/packages/river_hdl/test/mmu/mmu_fault_test.dart new file mode 100644 index 0000000..2ad0583 --- /dev/null +++ b/packages/river_hdl/test/mmu/mmu_fault_test.dart @@ -0,0 +1,174 @@ +import 'dart:async'; + +import 'package:rohd/rohd.dart'; +import 'package:rohd_hcl/rohd_hcl.dart' hide DataPortInterface, DataPortGroup; +import 'package:river/river.dart'; +import 'package:river_hdl/river_hdl.dart'; +import 'package:test/test.dart'; + +/// End-to-end MMU page-fault: a store to a read-only mapped page must raise a +/// store page fault (cause 15), matching the emulator. Observes the pipeline's +/// trap/trapCause directly (independent of the trap vector). +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + test( + 'Sv39 store to a read-only page raises storePageFault (cause 15)', + () async { + final config = RiverCoreConfig( + mxlen: RiscVMxlen.rv64, + extensions: kRva22S64Extensions, + type: RiverCoreType.general, + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + hasSupervisorUserMemory: true, + hasMakeExecutableReadable: true, + ), + interrupts: [], + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + ); + + // l0 leaf @ 0x12100 = 0xC00B: V=1,R=1,W=0,X=1 -> read-only (store faults). + const memString = '''@0 +73 10 05 18 37 06 02 00 93 06 50 00 23 30 d6 00 +13 00 00 00 +@10000 +01 44 00 00 00 00 00 00 +@11000 +01 48 00 00 00 00 00 00 +@12100 +0B C0 00 00 00 00 00 00 +'''; + + final clk = SimpleClockGenerator(20).clk; + final reset = Logic(); + final addrWidth = config.mxlen.size; + final wbConfig = WishboneConfig( + addressWidth: addrWidth, + dataWidth: config.mxlen.size, + selWidth: config.mxlen.size ~/ 8, + ); + + final core = RiverCore(config, busConfig: wbConfig); + core.input('clk').srcConnection! <= clk; + core.input('reset').srcConnection! <= reset; + await core.build(); + + final storage = SparseMemoryStorage( + addrWidth: addrWidth, + dataWidth: config.mxlen.size, + alignAddress: (addr) => addr, + onInvalidRead: (addr, dataWidth) => + LogicValue.filled(dataWidth, LogicValue.zero), + ); + + final memRead = DataPortInterface(config.mxlen.size, addrWidth); + final memWrite = DataPortInterface(config.mxlen.size, addrWidth); + // ignore: unused_local_variable + final mem = MemoryModel( + clk, + reset, + [wrapWriteForRegisterFile(memWrite)], + [wrapReadForRegisterFile(memRead, clk: clk, readLatency: 0)], + readLatency: 0, + storage: storage, + ); + + final wbCyc = core.output('dataBus_CYC'); + final wbStb = core.output('dataBus_STB'); + final wbWe = core.output('dataBus_WE'); + final wbAdr = core.output('dataBus_ADR'); + final wbDatMosi = core.output('dataBus_DAT_MOSI'); + + memRead.en <= wbCyc & wbStb & ~wbWe; + memRead.addr <= wbAdr; + memWrite.en <= wbCyc & wbStb & wbWe; + memWrite.addr <= wbAdr; + memWrite.data <= wbDatMosi; + + final wbAckReg = Logic(name: 'wbAck'); + final readyForAck = wbWe | memRead.valid; + Sequential(clk, [ + If( + reset, + then: [wbAckReg < 0], + orElse: [ + If( + wbCyc & wbStb & ~wbAckReg & readyForAck, + then: [wbAckReg < 1], + orElse: [wbAckReg < 0], + ), + ], + ), + ]); + core.input('dataBus_ACK').srcConnection! <= wbAckReg; + core.input('dataBus_DAT_MISO').srcConnection! <= memRead.data; + + reset.inject(1); + Simulator.registerAction(20, () { + reset.put(0); + core.regWritePort.en.inject(1); + core.regWritePort.addr.inject(LogicValue.ofInt(10, 5)); + // satp: Sv39 (MODE 8) | root PPN 0x10. + core.regWritePort.data.inject(LogicValue.ofInt(0x8000000000000010, 64)); + storage.loadMemString(memString); + }); + Simulator.setMaxSimTime(100000); + unawaited(Simulator.run()); + + await clk.nextPosedge; + core.regWritePort.en.inject(0); + while (reset.value.toBool()) { + await clk.nextPosedge; + } + + var sawStoreFault = false; + var sawWriteTo30000 = false; + for (var i = 0; i < 200; i++) { + await clk.nextPosedge; + // The translated write would target 0x30000, it must never happen. + final adr = wbAdr.value; + if (wbCyc.value.toInt() == 1 && + wbWe.value.toInt() == 1 && + adr.isValid && + adr.toInt() == 0x30000) { + sawWriteTo30000 = true; + } + final trap = core.pipeline.trap.value; + if (trap.isValid && trap.toInt() == 1) { + final cause = core.pipeline.trapCause.value; + expect(cause.isValid, isTrue, reason: 'trapCause invalid'); + expect( + cause.toInt(), + Trap.storePageFault.causeCode, + reason: 'expected storePageFault (15), got ${cause.toInt()}', + ); + sawStoreFault = true; + break; + } + } + + await Simulator.endSimulation(); + await Simulator.simulationEnded; + + expect( + sawStoreFault, + isTrue, + reason: 'no trap raised for read-only store', + ); + expect( + sawWriteTo30000, + isFalse, + reason: 'faulting store must not write memory', + ); + }, + ); +} diff --git a/packages/river_hdl/test/mmu/mmu_unit_test.dart b/packages/river_hdl/test/mmu/mmu_unit_test.dart new file mode 100644 index 0000000..125dd4f --- /dev/null +++ b/packages/river_hdl/test/mmu/mmu_unit_test.dart @@ -0,0 +1,973 @@ +import 'dart:async'; + +import 'package:rohd/rohd.dart'; +import 'package:river/river.dart'; +import 'package:river_hdl/river_hdl.dart'; +import 'package:test/test.dart'; + +/// Standalone exercise of the RiverMmu page-table walk against a mock combinational +/// Wishbone slave. Prints the bus transaction sequence so the walk FSM can be +/// inspected cycle-by-cycle. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + test('Sv39 walk drives the expected PTE fetch sequence', () async { + final clk = SimpleClockGenerator(20).clk; + final reset = Logic(name: 'reset'); + final dportEn = Logic(name: 'dportEn'); + final dportAddr = Logic(name: 'dportAddr', width: 64); + final satpMode = Logic(name: 'satpMode', width: 4); + final satpRoot = Logic(name: 'satpRoot', width: 64); + + final wbConfig = WishboneConfig( + addressWidth: 64, + dataWidth: 64, + selWidth: 8, + ); + final mmuConfig = HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + hasSupervisorUserMemory: true, + hasMakeExecutableReadable: true, + ); + + // Source signals the MMU consumes (driven below from the mock slave). + final ackSrc = Logic(name: 'ackSrc'); + final misoSrc = Logic(name: 'misoSrc', width: 64); + + final mmu = RiverMmu( + clk, + reset, + Const(0), // ifetchEn + Const(0, width: 64), // ifetchAddr + dportEn, + dportAddr, + Const(0), // dportWe + Const(0, width: 64), // dportWdata + Const(3, width: 3), // dportSize = 8 bytes + ackSrc, + misoSrc, + mmuConfig: mmuConfig, + busConfig: wbConfig, + satpMode: satpMode, + satpRoot: satpRoot, + ); + + await mmu.build(); + + // Mock combinational memory: returns the PTE/value at the requested address. + Logic memData(Logic a) => mux( + a.eq(0x10000), + Const(0x4401, width: 64), + mux( + a.eq(0x11000), + Const(0x4801, width: 64), + mux( + a.eq(0x12100), + Const(0xC00F, width: 64), + mux(a.eq(0x30000), Const(0xCAFEF00D, width: 64), Const(0, width: 64)), + ), + ), + ); + misoSrc <= memData(mmu.wbAdr); + + // Single-cycle ACK pulse, like the core_harness slave. + final ackReg = Logic(name: 'ackReg'); + Sequential(clk, [ + If( + reset, + then: [ackReg < 0], + orElse: [ + If( + mmu.wbCyc & mmu.wbStb & ~ackReg, + then: [ackReg < 1], + orElse: [ackReg < 0], + ), + ], + ), + ]); + ackSrc <= ackReg; + + reset.inject(1); + dportEn.inject(0); + dportAddr.inject(0); + satpMode.inject(8); // Sv39 + satpRoot.inject(0x10); // root PPN -> 0x10000 + + Simulator.setMaxSimTime(10000); + unawaited(Simulator.run()); + + await clk.nextPosedge; + reset.inject(0); + await clk.nextPosedge; + + // Issue the dport access to virtual 0x20000. + dportEn.inject(1); + dportAddr.inject(0x20000); + + var done = false; + var rdata = 0; + for (var i = 0; i < 40; i++) { + await clk.nextPosedge; + final cyc = mmu.wbCyc.value.toInt(); + final stb = mmu.wbStb.value.toInt(); + final we = mmu.wbWe.value.toInt(); + final adr = mmu.wbAdr.value; + final ack = ackSrc.value.toInt(); + final dpDone = mmu.dportDone.value.toInt(); + final dpData = mmu.dportRdata.value; + print( + 'cyc$i: CYC=$cyc STB=$stb WE=$we ' + 'ADR=0x${adr.isValid ? adr.toInt().toRadixString(16) : "x"} ' + 'ACK=$ack dportDone=$dpDone ' + 'dportRdata=0x${dpData.isValid ? dpData.toInt().toRadixString(16) : "x"}', + ); + if (dpDone == 1) { + done = true; + rdata = dpData.toInt(); + break; + } + } + + await Simulator.endSimulation(); + await Simulator.simulationEnded; + + expect(done, isTrue, reason: 'dportDone never asserted'); + expect(rdata, 0xCAFEF00D); + }); + + test( + 'bare-mode sub-word load returns the addressed byte lane (offset 5)', + () async { + // A byte load from a non-zero offset issues an aligned bus read; the + // addressed byte comes back in its lane and must be shifted down to lane 0 + // so the core's low-byte slice is correct. Regression for the THRE-poll + // wedge: lbu of the ns16550a LSR at offset 5 read lane 0 (0x00) instead of + // the real status byte, so the boot banner never streamed. + final clk = SimpleClockGenerator(20).clk; + final reset = Logic(name: 'reset'); + final dportEn = Logic(name: 'dportEn'); + final dportAddr = Logic(name: 'dportAddr', width: 64); + + final wbConfig = WishboneConfig( + addressWidth: 64, + dataWidth: 64, + selWidth: 8, + ); + final mmuConfig = HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + hasSupervisorUserMemory: true, + hasMakeExecutableReadable: true, + ); + + final ackSrc = Logic(name: 'ackSrc'); + final misoSrc = Logic(name: 'misoSrc', width: 64); + + final mmu = RiverMmu( + clk, + reset, + Const(0), // ifetchEn + Const(0, width: 64), // ifetchAddr + dportEn, + dportAddr, + Const(0), // dportWe (read) + Const(0, width: 64), // dportWdata + Const(0, width: 3), // dportSize = 1 byte + ackSrc, + misoSrc, + mmuConfig: mmuConfig, + busConfig: wbConfig, + satpMode: Logic(name: 'satpMode', width: 4)..gets(Const(0, width: 4)), + satpRoot: Const(0, width: 64), + ); + + await mmu.build(); + + // Aligned word at 0x10000000 holds distinct bytes per lane; byte 5 = 0x66. + misoSrc <= + mux( + mmu.wbAdr.eq(0x10000000), + Const(0x8877665544332211, width: 64), + Const(0, width: 64), + ); + + final ackReg = Logic(name: 'ackReg'); + Sequential(clk, [ + If( + reset, + then: [ackReg < 0], + orElse: [ + If( + mmu.wbCyc & mmu.wbStb & ~ackReg, + then: [ackReg < 1], + orElse: [ackReg < 0], + ), + ], + ), + ]); + ackSrc <= ackReg; + + reset.inject(1); + dportEn.inject(0); + dportAddr.inject(0); + Simulator.setMaxSimTime(10000); + unawaited(Simulator.run()); + + await clk.nextPosedge; + reset.inject(0); + await clk.nextPosedge; + + dportEn.inject(1); + dportAddr.inject(0x10000005); // byte offset 5 within the word + + var done = false; + var rdata = 0; + for (var i = 0; i < 40; i++) { + await clk.nextPosedge; + if (mmu.dportDone.value.toInt() == 1) { + done = true; + rdata = mmu.dportRdata.value.toInt(); + break; + } + } + + await Simulator.endSimulation(); + await Simulator.simulationEnded; + + expect(done, isTrue, reason: 'dportDone never asserted'); + // The core slices the low byte for lbu, so byte 5 (0x66) must be in lane 0. + expect( + rdata & 0xff, + 0x66, + reason: 'lane shift wrong: 0x${rdata.toRadixString(16)}', + ); + }, + ); + + test('Sv39 walk issues a translated store after the walk', () async { + final clk = SimpleClockGenerator(20).clk; + final reset = Logic(name: 'reset'); + final dportEn = Logic(name: 'dportEn'); + final dportAddr = Logic(name: 'dportAddr', width: 64); + final dportWe = Logic(name: 'dportWe'); + final dportWdata = Logic(name: 'dportWdata', width: 64); + final satpMode = Logic(name: 'satpMode', width: 4); + final satpRoot = Logic(name: 'satpRoot', width: 64); + + final wbConfig = WishboneConfig( + addressWidth: 64, + dataWidth: 64, + selWidth: 8, + ); + final mmuConfig = HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + hasSupervisorUserMemory: true, + hasMakeExecutableReadable: true, + ); + + final ackSrc = Logic(name: 'ackSrc'); + final misoSrc = Logic(name: 'misoSrc', width: 64); + + final mmu = RiverMmu( + clk, + reset, + Const(0), + Const(0, width: 64), + dportEn, + dportAddr, + dportWe, + dportWdata, + Const(3, width: 3), + ackSrc, + misoSrc, + mmuConfig: mmuConfig, + busConfig: wbConfig, + satpMode: satpMode, + satpRoot: satpRoot, + ); + + await mmu.build(); + + Logic memData(Logic a) => mux( + a.eq(0x10000), + Const(0x4401, width: 64), + mux( + a.eq(0x11000), + Const(0x4801, width: 64), + mux(a.eq(0x12100), Const(0xC00F, width: 64), Const(0, width: 64)), + ), + ); + misoSrc <= memData(mmu.wbAdr); + + final ackReg = Logic(name: 'ackReg'); + Sequential(clk, [ + If( + reset, + then: [ackReg < 0], + orElse: [ + If( + mmu.wbCyc & mmu.wbStb & ~ackReg, + then: [ackReg < 1], + orElse: [ackReg < 0], + ), + ], + ), + ]); + ackSrc <= ackReg; + + reset.inject(1); + dportEn.inject(0); + dportAddr.inject(0); + dportWe.inject(0); + dportWdata.inject(0); + satpMode.inject(8); + satpRoot.inject(0x10); + + Simulator.setMaxSimTime(10000); + unawaited(Simulator.run()); + + await clk.nextPosedge; + reset.inject(0); + await clk.nextPosedge; + + // Issue a store to virtual 0x20000. + dportEn.inject(1); + dportWe.inject(1); + dportAddr.inject(0x20000); + dportWdata.inject(0xABCD1234); + + var sawWrite = false; + var writeAddr = 0; + var writeData = 0; + var done = false; + for (var i = 0; i < 40; i++) { + await clk.nextPosedge; + final cyc = mmu.wbCyc.value.toInt(); + final stb = mmu.wbStb.value.toInt(); + final we = mmu.wbWe.value.toInt(); + final adr = mmu.wbAdr.value; + final mosi = mmu.wbDatMosi.value; + if (cyc == 1 && stb == 1 && we == 1) { + sawWrite = true; + writeAddr = adr.toInt(); + writeData = mosi.toInt(); + } + if (mmu.dportDone.value.toInt() == 1) { + done = true; + break; + } + } + + await Simulator.endSimulation(); + await Simulator.simulationEnded; + + expect(done, isTrue, reason: 'dportDone never asserted for store'); + expect(sawWrite, isTrue, reason: 'no write transaction issued'); + expect(writeAddr, 0x30000, reason: 'store went to wrong physical address'); + expect(writeData, 0xABCD1234); + }); + + // Walk fault: an invalid leaf PTE (V=0) must raise dportFault with + // dportDone & ~dportValid, and must NOT issue the translated access. + test('Sv39 walk faults on an invalid (V=0) leaf PTE', () async { + final clk = SimpleClockGenerator(20).clk; + final reset = Logic(name: 'reset'); + final dportEn = Logic(name: 'dportEn'); + final dportAddr = Logic(name: 'dportAddr', width: 64); + final satpMode = Logic(name: 'satpMode', width: 4); + final satpRoot = Logic(name: 'satpRoot', width: 64); + + final wbConfig = WishboneConfig( + addressWidth: 64, + dataWidth: 64, + selWidth: 8, + ); + final mmuConfig = HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + hasSupervisorUserMemory: true, + hasMakeExecutableReadable: true, + ); + + final ackSrc = Logic(name: 'ackSrc'); + final misoSrc = Logic(name: 'misoSrc', width: 64); + + final mmu = RiverMmu( + clk, + reset, + Const(0), + Const(0, width: 64), + dportEn, + dportAddr, + Const(0), + Const(0, width: 64), + Const(3, width: 3), + ackSrc, + misoSrc, + mmuConfig: mmuConfig, + busConfig: wbConfig, + satpMode: satpMode, + satpRoot: satpRoot, + ); + + await mmu.build(); + + // l0 leaf @ 0x12100 has V=0 (0xC00E) -> invalid -> fault. + Logic memData(Logic a) => mux( + a.eq(0x10000), + Const(0x4401, width: 64), + mux( + a.eq(0x11000), + Const(0x4801, width: 64), + mux( + a.eq(0x12100), + Const(0xC00E, width: 64), // V=0 + Const(0, width: 64), + ), + ), + ); + misoSrc <= memData(mmu.wbAdr); + + final ackReg = Logic(name: 'ackReg'); + Sequential(clk, [ + If( + reset, + then: [ackReg < 0], + orElse: [ + If( + mmu.wbCyc & mmu.wbStb & ~ackReg, + then: [ackReg < 1], + orElse: [ackReg < 0], + ), + ], + ), + ]); + ackSrc <= ackReg; + + reset.inject(1); + dportEn.inject(0); + dportAddr.inject(0); + satpMode.inject(8); + satpRoot.inject(0x10); + + Simulator.setMaxSimTime(10000); + unawaited(Simulator.run()); + + await clk.nextPosedge; + reset.inject(0); + await clk.nextPosedge; + + dportEn.inject(1); + dportAddr.inject(0x20000); + + var faulted = false; + var sawTranslatedAccess = false; + for (var i = 0; i < 40; i++) { + await clk.nextPosedge; + final adr = mmu.wbAdr.value; + // The translated leaf access would be to 0x30000, it must never happen. + if (mmu.wbCyc.value.toInt() == 1 && + adr.isValid && + adr.toInt() == 0x30000) { + sawTranslatedAccess = true; + } + if (mmu.dportDone.value.toInt() == 1) { + expect(mmu.dportFault.value.toInt(), 1, reason: 'expected page fault'); + expect(mmu.dportValid.value.toInt(), 0, reason: 'fault => ~valid'); + faulted = true; + break; + } + } + + await Simulator.endSimulation(); + await Simulator.simulationEnded; + + expect(faulted, isTrue, reason: 'walk never completed/faulted'); + expect( + sawTranslatedAccess, + isFalse, + reason: 'must not access memory on a faulting walk', + ); + }); + + // Instruction-fetch translation (translateFetch: true). Walks the same Sv39 + // table as the dport tests but as an instruction access: the leaf needs X, the + // result/fault route to the ifetch ports. priv = supervisor so fetch is + // translated (M-mode would bypass). + Future<(bool done, int rdata, bool fault)> runFetch(int leafPte) async { + final clk = SimpleClockGenerator(20).clk; + final reset = Logic(name: 'reset'); + final ifetchEn = Logic(name: 'ifetchEn'); + final ifetchAddr = Logic(name: 'ifetchAddr', width: 64); + final satpMode = Logic(name: 'satpMode', width: 4); + final satpRoot = Logic(name: 'satpRoot', width: 64); + final priv = Logic(name: 'priv', width: 3); + final wbConfig = WishboneConfig( + addressWidth: 64, + dataWidth: 64, + selWidth: 8, + ); + final mmuConfig = HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ); + final ackSrc = Logic(name: 'ackSrc'); + final misoSrc = Logic(name: 'misoSrc', width: 64); + final mmu = RiverMmu( + clk, + reset, + ifetchEn, + ifetchAddr, + Const(0), + Const(0, width: 64), + Const(0), + Const(0, width: 64), + Const(3, width: 3), + ackSrc, + misoSrc, + mmuConfig: mmuConfig, + busConfig: wbConfig, + satpMode: satpMode, + satpRoot: satpRoot, + privMode: priv, + translateFetch: true, + ); + await mmu.build(); + // root@0x10000 -> 0x11000, l1@0x11000 -> 0x12000, l0[32]@0x12100 = leafPte, + // instruction word @0x30000 (PPN 0x30 from the leaf). + Logic memData(Logic a) => mux( + a.eq(0x10000), + Const(0x4401, width: 64), + mux( + a.eq(0x11000), + Const(0x4801, width: 64), + mux( + a.eq(0x12100), + Const(leafPte, width: 64), + mux(a.eq(0x30000), Const(0xCAFEF00D, width: 64), Const(0, width: 64)), + ), + ), + ); + misoSrc <= memData(mmu.wbAdr); + final ackReg = Logic(name: 'ackReg'); + Sequential(clk, [ + If( + reset, + then: [ackReg < 0], + orElse: [ + If( + mmu.wbCyc & mmu.wbStb & ~ackReg, + then: [ackReg < 1], + orElse: [ackReg < 0], + ), + ], + ), + ]); + ackSrc <= ackReg; + reset.inject(1); + ifetchEn.inject(0); + ifetchAddr.inject(0); + satpMode.inject(8); + satpRoot.inject(0x10); + priv.inject(1); // supervisor + Simulator.setMaxSimTime(10000); + unawaited(Simulator.run()); + await clk.nextPosedge; + reset.inject(0); + await clk.nextPosedge; + ifetchEn.inject(1); + ifetchAddr.inject(0x20000); + var done = false, fault = false, rdata = 0; + for (var i = 0; i < 40; i++) { + await clk.nextPosedge; + if (mmu.ifetchDone.value.toInt() == 1) { + done = true; + fault = mmu.ifetchFault.value.toInt() == 1; + final d = mmu.ifetchRdata.value; + rdata = d.isValid ? d.toInt() : -1; + break; + } + } + await Simulator.endSimulation(); + await Simulator.simulationEnded; + return (done, rdata, fault); + } + + test( + 'Sv39 fetch translation returns the instruction at the mapped PA', + () async { + // leaf 0xC00F = V|R|W|X -> executable. + final (done, rdata, fault) = await runFetch(0xC00F); + expect(done, isTrue, reason: 'ifetchDone never asserted'); + expect(fault, isFalse, reason: 'a mapped executable page must not fault'); + expect(rdata, 0xCAFEF00D); + }, + ); + + test('Sv39 fetch of a non-executable page raises ifetch_fault', () async { + // leaf 0xC007 = V|R|W (no X) -> fetch is a page fault. + final (done, _, fault) = await runFetch(0xC007); + expect(done, isTrue, reason: 'a faulting fetch must still complete'); + expect(fault, isTrue, reason: 'a non-X page must raise ifetch_fault'); + }); + + // Fetch-TLB: a repeated fetch of the same page hits the cache (one walk, then + // direct reads). A tlbFlush (sfence.vma) makes the next fetch walk again. + // Returns the number of page-table WALKS observed (root-PTE reads at 0x10000). + Future countWalks({int? flushAtCycle}) async { + final clk = SimpleClockGenerator(20).clk; + final reset = Logic(name: 'reset'); + final ifetchEn = Logic(name: 'ifetchEn'); + final satpMode = Logic(name: 'satpMode', width: 4); + final satpRoot = Logic(name: 'satpRoot', width: 64); + final priv = Logic(name: 'priv', width: 3); + final tlbFlush = Logic(name: 'tlbFlush'); + final wbConfig = WishboneConfig( + addressWidth: 64, + dataWidth: 64, + selWidth: 8, + ); + final mmuConfig = HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ); + final ackSrc = Logic(name: 'ackSrc'); + final misoSrc = Logic(name: 'misoSrc', width: 64); + final mmu = RiverMmu( + clk, + reset, + ifetchEn, + Const(0x20000, width: 64), + Const(0), + Const(0, width: 64), + Const(0), + Const(0, width: 64), + Const(3, width: 3), + ackSrc, + misoSrc, + mmuConfig: mmuConfig, + busConfig: wbConfig, + satpMode: satpMode, + satpRoot: satpRoot, + privMode: priv, + translateFetch: true, + tlbFlush: tlbFlush, + ); + await mmu.build(); + Logic memData(Logic a) => mux( + a.eq(0x10000), + Const(0x4401, width: 64), + mux( + a.eq(0x11000), + Const(0x4801, width: 64), + mux( + a.eq(0x12100), + Const(0xC00F, width: 64), + mux(a.eq(0x30000), Const(0xCAFEF00D, width: 64), Const(0, width: 64)), + ), + ), + ); + misoSrc <= memData(mmu.wbAdr); + final ackReg = Logic(name: 'ackReg'); + Sequential(clk, [ + If( + reset, + then: [ackReg < 0], + orElse: [ + If( + mmu.wbCyc & mmu.wbStb & ~ackReg, + then: [ackReg < 1], + orElse: [ackReg < 0], + ), + ], + ), + ]); + ackSrc <= ackReg; + reset.inject(1); + ifetchEn.inject(0); + satpMode.inject(8); + satpRoot.inject(0x10); + priv.inject(1); + tlbFlush.inject(0); + Simulator.setMaxSimTime(20000); + unawaited(Simulator.run()); + await clk.nextPosedge; + reset.inject(0); + await clk.nextPosedge; + ifetchEn.inject(1); + var walks = 0; + var prevRoot = false; + for (var i = 0; i < 160; i++) { + await clk.nextPosedge; + tlbFlush.inject(i == flushAtCycle ? 1 : 0); + final adr = mmu.wbAdr.value; + final atRoot = + mmu.wbStb.value.toInt() == 1 && adr.isValid && adr.toInt() == 0x10000; + if (atRoot && !prevRoot) walks++; + prevRoot = atRoot; + } + await Simulator.endSimulation(); + await Simulator.simulationEnded; + return walks; + } + + test('fetch-TLB: repeated same-page fetch walks once, then hits', () async { + final walks = await countWalks(); + expect( + walks, + 1, + reason: 'only the first fetch should walk; rest hit the TLB', + ); + }); + + test('fetch-TLB: tlbFlush (sfence.vma) forces a re-walk', () async { + final walks = await countWalks(flushAtCycle: 60); + expect(walks, 2, reason: 'a flush mid-run must cause a second walk'); + }); + + // Data-TLB: a repeated load of the same page hits the cache (one walk, then a + // direct translated read). A tlbFlush (sfence.vma) forces the next load to + // walk again. Mirrors countWalks but drives the data port. + Future countDataWalks({int? flushAtCycle}) async { + final clk = SimpleClockGenerator(20).clk; + final reset = Logic(name: 'reset'); + final dportEn = Logic(name: 'dportEn'); + final satpMode = Logic(name: 'satpMode', width: 4); + final satpRoot = Logic(name: 'satpRoot', width: 64); + final priv = Logic(name: 'priv', width: 3); + final tlbFlush = Logic(name: 'tlbFlush'); + final wbConfig = WishboneConfig( + addressWidth: 64, + dataWidth: 64, + selWidth: 8, + ); + final mmuConfig = HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ); + final ackSrc = Logic(name: 'ackSrc'); + final misoSrc = Logic(name: 'misoSrc', width: 64); + final mmu = RiverMmu( + clk, + reset, + Const(0), // ifetchEn + Const(0, width: 64), // ifetchAddr + dportEn, + Const(0x20000, width: 64), + Const(0), // dportWe (load) + Const(0, width: 64), // dportWdata + Const(3, width: 3), // dportSize = 8 bytes + ackSrc, + misoSrc, + mmuConfig: mmuConfig, + busConfig: wbConfig, + satpMode: satpMode, + satpRoot: satpRoot, + privMode: priv, + tlbFlush: tlbFlush, + ); + await mmu.build(); + Logic memData(Logic a) => mux( + a.eq(0x10000), + Const(0x4401, width: 64), + mux( + a.eq(0x11000), + Const(0x4801, width: 64), + mux( + a.eq(0x12100), + Const(0xC00F, width: 64), + mux(a.eq(0x30000), Const(0xCAFEF00D, width: 64), Const(0, width: 64)), + ), + ), + ); + misoSrc <= memData(mmu.wbAdr); + final ackReg = Logic(name: 'ackReg'); + Sequential(clk, [ + If( + reset, + then: [ackReg < 0], + orElse: [ + If( + mmu.wbCyc & mmu.wbStb & ~ackReg, + then: [ackReg < 1], + orElse: [ackReg < 0], + ), + ], + ), + ]); + ackSrc <= ackReg; + reset.inject(1); + dportEn.inject(0); + satpMode.inject(8); + satpRoot.inject(0x10); + priv.inject(1); + tlbFlush.inject(0); + Simulator.setMaxSimTime(20000); + unawaited(Simulator.run()); + await clk.nextPosedge; + reset.inject(0); + await clk.nextPosedge; + dportEn.inject(1); + var walks = 0; + var prevRoot = false; + for (var i = 0; i < 160; i++) { + await clk.nextPosedge; + tlbFlush.inject(i == flushAtCycle ? 1 : 0); + final adr = mmu.wbAdr.value; + final atRoot = + mmu.wbStb.value.toInt() == 1 && adr.isValid && adr.toInt() == 0x10000; + if (atRoot && !prevRoot) walks++; + prevRoot = atRoot; + } + await Simulator.endSimulation(); + await Simulator.simulationEnded; + return walks; + } + + test('data-TLB: repeated same-page load walks once, then hits', () async { + final walks = await countDataWalks(); + expect( + walks, + 1, + reason: 'only the first load should walk; rest hit the TLB', + ); + }); + + test('data-TLB: tlbFlush (sfence.vma) forces a re-walk', () async { + final walks = await countDataWalks(flushAtCycle: 60); + expect(walks, 2, reason: 'a flush mid-run must cause a second walk'); + }); + + // Svadu hardware A/D update: a translated access whose leaf PTE has A=0 (or + // D=0 on a store) writes the updated PTE back to memory before the access. + // The leaf PTE is 0xC00F at 0x12100 (V|R|W|X, A=0, D=0). Returns the value + // written to the leaf PTE, or null if no writeback occurred. + Future adWriteback({required bool write}) async { + final clk = SimpleClockGenerator(20).clk; + final reset = Logic(name: 'reset'); + final dportEn = Logic(name: 'dportEn'); + final satpMode = Logic(name: 'satpMode', width: 4); + final satpRoot = Logic(name: 'satpRoot', width: 64); + final priv = Logic(name: 'priv', width: 3); + final wbConfig = WishboneConfig( + addressWidth: 64, + dataWidth: 64, + selWidth: 8, + ); + final mmuConfig = HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ); + final ackSrc = Logic(name: 'ackSrc'); + final misoSrc = Logic(name: 'misoSrc', width: 64); + final mmu = RiverMmu( + clk, + reset, + Const(0), // ifetchEn + Const(0, width: 64), // ifetchAddr + dportEn, + Const(0x20000, width: 64), + Const(write ? 1 : 0), // dportWe + Const(0xDEAD, width: 64), // dportWdata + Const(3, width: 3), // dportSize + ackSrc, + misoSrc, + mmuConfig: mmuConfig, + busConfig: wbConfig, + satpMode: satpMode, + satpRoot: satpRoot, + privMode: priv, + ); + await mmu.build(); + Logic memData(Logic a) => mux( + a.eq(0x10000), + Const(0x4401, width: 64), + mux( + a.eq(0x11000), + Const(0x4801, width: 64), + mux(a.eq(0x12100), Const(0xC00F, width: 64), Const(0, width: 64)), + ), + ); + misoSrc <= memData(mmu.wbAdr); + final ackReg = Logic(name: 'ackReg'); + Sequential(clk, [ + If( + reset, + then: [ackReg < 0], + orElse: [ + If( + mmu.wbCyc & mmu.wbStb & ~ackReg, + then: [ackReg < 1], + orElse: [ackReg < 0], + ), + ], + ), + ]); + ackSrc <= ackReg; + reset.inject(1); + dportEn.inject(0); + satpMode.inject(8); + satpRoot.inject(0x10); + priv.inject(1); + Simulator.setMaxSimTime(20000); + unawaited(Simulator.run()); + await clk.nextPosedge; + reset.inject(0); + await clk.nextPosedge; + dportEn.inject(1); + int? pteWrite; + for (var i = 0; i < 120; i++) { + await clk.nextPosedge; + final cyc = mmu.wbCyc.value; + final stb = mmu.wbStb.value; + final we = mmu.wbWe.value; + final adr = mmu.wbAdr.value; + if (cyc.isValid && + cyc.toInt() == 1 && + stb.toInt() == 1 && + we.isValid && + we.toInt() == 1 && + adr.isValid && + adr.toInt() == 0x12100) { + pteWrite ??= mmu.wbDatMosi.value.toInt(); + } + } + await Simulator.endSimulation(); + await Simulator.simulationEnded; + return pteWrite; + } + + test('Svadu: a load writes the leaf PTE back with A set', () async { + final pte = await adWriteback(write: false); + expect(pte, isNotNull, reason: 'a load with A=0 must write the PTE back'); + expect((pte! >> 6) & 1, 1, reason: 'A (bit 6) set on access'); + expect((pte >> 7) & 1, 0, reason: 'D (bit 7) not set by a load'); + }); + + test('Svadu: a store writes the leaf PTE back with A and D set', () async { + final pte = await adWriteback(write: true); + expect(pte, isNotNull, reason: 'a store with D=0 must write the PTE back'); + expect((pte! >> 6) & 1, 1, reason: 'A (bit 6) set on access'); + expect((pte >> 7) & 1, 1, reason: 'D (bit 7) set by a store'); + }); +} diff --git a/packages/river_hdl/test/openocd-river-sim.cfg b/packages/river_hdl/test/openocd-river-sim.cfg new file mode 100644 index 0000000..61fa390 --- /dev/null +++ b/packages/river_hdl/test/openocd-river-sim.cfg @@ -0,0 +1,28 @@ +# OpenOCD config to drive river_sim --remote-bitbang (the River HDL RTL). +adapter driver remote_bitbang +adapter speed 1000 +# Force IPv4: "localhost" can resolve to ::1 first and OpenOCD then dies with +# "Bad file descriptor" on the IPv4 fallback. The sim binds IPv4 loopback only. +remote_bitbang host 127.0.0.1 +remote_bitbang port 44900 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10000001 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME + +gdb_port disabled +telnet_port disabled +tcl_port disabled + +init +echo "=== halting the River RTL ===" +halt +echo "=== dpc / x6 ===" +reg pc +reg x6 +echo "=== resuming ===" +resume +echo "=== OK ===" +shutdown diff --git a/packages/river_hdl/test/parity/core_parity_test.dart b/packages/river_hdl/test/parity/core_parity_test.dart new file mode 100644 index 0000000..2956c1c --- /dev/null +++ b/packages/river_hdl/test/parity/core_parity_test.dart @@ -0,0 +1,525 @@ +import 'package:river/river.dart'; +import 'package:river_emulator/river_emulator.dart'; +import 'package:rohd/rohd.dart'; +import 'package:test/test.dart'; + +import '../core_harness.dart'; + +/// Differential parity sweep: each program runs on the EMULATOR (golden ISS) and +/// the HDL core, and their architectural state must match. The emulator computes +/// the expected register/memory values; the HDL is checked against them. This +/// proves the HDL and emulator agree on SCENARIO paths (traps, CSR WARL, fence, +/// F/D incl. FMA/fsgnj, hypervisor CSRs, MMU walks) + a few representation edges. +/// Per-instruction parity (integer/M/OP-IMM/AMO/LR-SC/Zacas/vector/W-variants) is +/// now covered systematically by the matrix categories (#66 dedupe), so the plain +/// per-op cases were removed here and their edges folded into matrix cells. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + // Lean integer/M config - no F/D/V, so the core builds and simulates fast + // enough for a long instruction battery. + RiverCoreConfig intConfig() => RiverCoreConfig( + clock: HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ), + mxlen: RiscVMxlen.rv64, + extensions: [rv64i, rv32i, rvM, rvZicsr, rvZifencei], + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + vlen: 128, + ); + + // rv32 base config (the nano profile's width). No rv64i. Probes whether 32-bit + // results are consistently masked (add-overflow wrap, 5-bit shift amounts). + RiverCoreConfig rv32Config() => RiverCoreConfig( + clock: HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ), + mxlen: RiscVMxlen.rv32, + extensions: [rv32i, rvM, rvZicsr, rvZifencei], + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv32, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + vlen: 128, + ); + + // F/D config without vector - much faster to build/simulate than fdvConfig for + // a long FP battery (the vector lane units dominate elaboration). + RiverCoreConfig fdConfig() => RiverCoreConfig( + clock: HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ), + mxlen: RiscVMxlen.rv64, + // rvFExtra/rvDExtra add fmin/fmax/fsgnj*/fclass/fmv (not in Harbor's base F/D). + extensions: [ + rv64i, + rv32i, + rvM, + rvF, + rvD, + rvFExtra, + rvDExtra, + rvZicsr, + rvZifencei, + ], + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + vlen: 128, + ); + + // Lean config with rvPriv (ecall/mret) + Zicsr for the trap/CSR sweep. + RiverCoreConfig trapConfig() => RiverCoreConfig( + clock: HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ), + mxlen: RiscVMxlen.rv64, + extensions: [rv64i, rv32i, rvM, rvZicsr, rvZifencei, rvPriv], + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + vlen: 128, + ); + + RiverCoreConfig hvConfig() => RiverCoreConfig( + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + mxlen: RiscVMxlen.rv64, + extensions: [rv64i, rv32i, rvZicsr, rvZifencei, rvPriv, rvH], + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + ); + + void ww(Sram sram, int addr, int value) { + for (var i = 0; i < 4; i++) { + sram.data[addr + i] = (value >> (i * 8)) & 0xFF; + } + } + + int rd64(Sram sram, int addr) { + var v = 0; + for (var i = 0; i < 8; i++) { + v |= sram.data[addr + i] << (i * 8); + } + return v; + } + + void appendWord(StringBuffer sb, int w) { + for (var b = 0; b < 4; b++) { + sb.write(((w >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + + /// Run [program] (words at 0,4,8,...) on the emulator, collect the golden + /// register/memory state, then check the HDL against it. + Future parityCheck( + List program, + RiverCoreConfig config, { + Map seed = const {}, + Map> dataMem = const {}, + required int nextPc, + required List checkRegs, + List checkMem = const [], + }) async { + // --- Emulator golden run --- + final sram = Sram( + RiverDevice( + name: 'sram', + compatible: 'river,sram', + range: BusAddressRange(0, 0xFFFFF), + clockFrequency: (config.clock.rate as HarborFixedClockRate).frequency, + ), + ); + final ecore = RiverCore(config, memDevices: Map.fromEntries([sram.mem!])); + for (var i = 0; i < program.length; i++) { + ww(sram, i * 4, program[i]); + } + dataMem.forEach((addr, words) { + for (var j = 0; j < words.length; j++) { + ww(sram, addr + j * 4, words[j]); + } + }); + seed.forEach((r, v) => ecore.xregs[r] = v); + // fetch + cycle (NOT runPipeline): cycle() routes V opcodes to executeVector; + // runPipeline would hit the stub rv_v microcode and skip vector execution. + var pc = config.resetVector; + for (var s = 0; s < 5000 && pc != nextPc; s++) { + final instr = await ecore.fetch(pc); + pc = await ecore.cycle(pc, instr); + } + expect( + pc, + nextPc, + reason: 'emulator did not reach nextPc=$nextPc (got $pc)', + ); + final goldRegs = {for (final r in checkRegs) r: ecore.xregs[r] ?? 0}; + final goldMem = {for (final a in checkMem) a: rd64(sram, a)}; + + // --- HDL check vs golden --- + final sb = StringBuffer('@0\n'); + for (final w in program) { + appendWord(sb, w); + } + dataMem.forEach((addr, words) { + sb.write('\n@${addr.toRadixString(16)}\n'); + for (final w in words) { + appendWord(sb, w); + } + }); + await coreTest( + '$sb\n', + goldRegs, + config, + memStates: goldMem, + initRegisters: seed, + nextPc: nextPc, + ); + } + + // ---- instruction encoders ---- + int iimm(int imm, int rs1, int f3, int rd) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x13; + int rtype(int f7, int rs2, int rs1, int f3, int rd) => + (f7 << 25) | (rs2 << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x33; + int store(int imm, int rs2, int rs1, int f3, int op) => + (((imm >> 5) & 0x7F) << 25) | + (rs2 << 20) | + (rs1 << 15) | + (f3 << 12) | + ((imm & 0x1F) << 7) | + op; + int fop(int f7, int rs2, int rs1, int rm, int rd) => + (f7 << 25) | (rs2 << 20) | (rs1 << 15) | (rm << 12) | (rd << 7) | 0x53; + int fop4(int op, int rs3, int rs2, int rs1, int rd, {int fmt = 0}) => + (rs3 << 27) | (fmt << 25) | (rs2 << 20) | (rs1 << 15) | (rd << 7) | op; + int csrw(int csr, int rs1) => (csr << 20) | (rs1 << 15) | (0x1 << 12) | 0x73; + int csrr(int csr, int rd) => (csr << 20) | (0x2 << 12) | (rd << 7) | 0x73; + int lui(int imm20, int rd) => (imm20 << 12) | (rd << 7) | 0x37; + int ld(int imm, int rs1, int rd) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (0x3 << 12) | (rd << 7) | 0x03; + const nop = 0x00000013; + + // NOTE: per-instruction integer OP/OP-IMM/M/W-variants parity (same -5/3 + // operands + div-by-zero edge cases) is now covered systematically by the + // matrix base/ + m/ categories across ALL configs (#66 dedupe) - removed here. + + // Trap + CSR behavior: ecall traps to mtvec; the handler reads mcause (11 = + // ecall-from-M) and mepc (the ecall PC), advances mepc past the ecall, and + // mret resumes. Verifies trap save (mcause/mepc) + mret restore are identical. + test('parity: trap (ecall -> mtvec -> mret) + mcause/mepc', () async { + const ecall = 0x00000073; + const mret = 0x30200073; + final prog = [ + // main @ 0x00 + iimm(0x40, 0, 0x0, 5), // x5 = 0x40 (handler addr) + csrw(0x305, 5), // mtvec = 0x40 + iimm(0x55, 0, 0x0, 6), // x6 = 0x55 (pre-ecall marker) + ecall, // @0x0C: trap -> mepc=0x0C, mcause=11 + iimm(0x99, 0, 0x0, 7), // @0x10: post-mret marker + nop, // @0x14: halt target + ]; + // pad 0x18..0x3C so the handler lands at 0x40 (index 16). + while (prog.length < 16) { + prog.add(nop); + } + prog.addAll([ + csrr(0x342, 10), // @0x40: x10 = mcause (11) + csrr(0x341, 11), // @0x44: x11 = mepc (0x0C) + iimm(4, 11, 0x0, 12), // @0x48: x12 = mepc + 4 = 0x10 + csrw(0x341, 12), // @0x4C: mepc = 0x10 + mret, // @0x50: return to mepc = 0x10 + ]); + await parityCheck( + prog, + trapConfig(), + nextPc: 0x14, + checkRegs: [Register.x6, Register.x7, Register.x10, Register.x11], + ); + }); + + // M-mode CSR WARL: write mstatus/mie/mscratch and read back. The writable-bit + // masking (mstatus MIE/MPIE/MPP..., mie's SIE/TIE/EIE) must match the HDL. + test('parity: M-CSR WARL (mstatus / mie / mscratch)', () async { + await parityCheck( + [ + iimm(0x88, 0, 0x0, 10), // MIE(3) + MPIE(7) + csrw(0x300, 10), csrr(0x300, 11), // mstatus + iimm(0x888, 0, 0x0, 12), // MSIE/MTIE/MEIE + csrw(0x304, 12), csrr(0x304, 13), // mie + iimm(0x123, 0, 0x0, 16), + csrw(0x340, 16), csrr(0x340, 17), // mscratch (fully writable) + nop, + ], + trapConfig(), + nextPc: 0x28, + checkRegs: [Register.x11, Register.x13, Register.x17], + ); + }); + + // NOTE: AMO (incl signed amomax / unsigned amominu), LR/SC (incl sc-fail), and + // Zacas amocas parity moved to the matrix a/ + zacas/ categories - the + // signed/unsigned + sc-fail edges were folded into those cells (#66 dedupe). + + // rv32 representation: 32-bit add must wrap, shift amounts mask to 5 bits, and + // slt/sltu use 32-bit signedness. The emulator returns raw Dart ints, so this + // catches any rv32 result that isn't masked to 32 bits like the HDL regfile. + test('parity: rv32 representation (add wrap / 5-bit shamt / slt)', () async { + await parityCheck( + [ + iimm(-1, 0, 0x0, 1), // x1 = 0xFFFFFFFF (-1 in rv32) + iimm(1, 0, 0x0, 2), // x2 = 1 + rtype(0x00, 2, 1, 0x0, 3), // add x3 = x1+x2 -> wraps to 0 in rv32 + iimm(33, 0, 0x0, 4), // x4 = 33 + iimm(1, 0, 0x0, 5), // x5 = 1 + rtype(0x00, 4, 5, 0x1, 6), // sll x6 = x5 << (33 & 31) = 1<<1 = 2 + rtype(0x00, 2, 1, 0x3, 7), // sltu x7 = (0xFFFFFFFF compare vs + // 0xFFFF..FFFF); srli/srai must be logical/arith on a negative operand. + test('parity: OP-IMM (slti/sltiu/shift-imm + sign-extended imm)', () async { + await parityCheck( + [ + iimm(5, 0, 0x0, 1), // x1 = 5 + iimm(-5, 0, 0x0, 13), // x13 = -5 + iimm(10, 1, 0x0, 2), // addi x2 = 15 + iimm(3, 1, 0x2, 3), // slti x3 = (5<3) = 0 + iimm(-1, 1, 0x2, 4), // slti x4 = (5<-1) = 0 + iimm(-1, 1, 0x3, 5), // sltiu x5 = (5 >a 1 = -3 (funct6=0x10) + iimm(1, 13, 0x5, 15), // srli x15 = -5 >>l 1 (huge positive) + iimm(3, 13, 0x3, 16), // sltiu x16 = (-5 + rtype(f7, rs2, rs1, f3, rd) | 0x08; // opcode 0x33 -> 0x3B (OP-32) + test('parity: W-variants (addw..remuw, sign-extension)', () async { + await parityCheck( + [ + iimm(-1, 0, 0x0, 1), // x1 = -1 (low32 = 0xFFFFFFFF) + iimm(3, 0, 0x0, 2), // x2 = 3 + iimm(1, 0, 0x0, 3), // x3 = 1 + rtypew(0x00, 2, 1, 0x0, 4), // addw + rtypew(0x20, 2, 1, 0x0, 5), // subw + rtypew(0x00, 2, 1, 0x1, 6), // sllw + rtypew(0x00, 2, 1, 0x5, 7), // srlw (logical) + rtypew(0x20, 2, 1, 0x5, 8), // sraw (arithmetic) + rtypew(0x01, 2, 1, 0x0, 9), // mulw + rtypew(0x01, 2, 1, 0x4, 10), // divw + rtypew(0x01, 2, 1, 0x5, 11), // divuw + rtypew( + 0x01, + 0, + 1, + 0x5, + 12, + ), // divuw / x0 -> div by zero (all-ones -> -1) + rtypew(0x01, 3, 1, 0x5, 16), // divuw x1/1 = 0xFFFFFFFF -> sign-ext -1 + rtypew(0x01, 2, 1, 0x6, 13), // remw + rtypew(0x01, 2, 1, 0x7, 14), // remuw + rtypew(0x01, 3, 1, 0x7, 15), // remuw x1%1 = 0 + nop, + ], + intConfig(), + nextPc: 0x40, + checkRegs: [for (var i = 4; i <= 16; i++) Register.values[i]], + ); + }); + + // F/D broad: arith (add/sub/mul/div/sqrt), min/max/sgnj, FMA (madd/msub/nmsub), + // compares (feq/flt/fle), and fcvt. Arith results land in the separate HDL FP + // regfile, so each is fsw'd to memory and compared there; compares + fcvt write + // integer regs and are compared directly. f1=2, f2=3, f3=4 (built via fcvt.s.w). + int fsw(int off, int fp, int base) => store(off, fp, base, 0x2, 0x27); + test('parity: F/D broad (arith/min-max/sgnj/FMA/cmp/fcvt)', () async { + await parityCheck( + [ + iimm(2, 0, 0x0, 5), iimm(3, 0, 0x0, 6), iimm(4, 0, 0x0, 7), + fop(0x68, 0, 5, 0, 1), // f1 = 2.0 + fop(0x68, 0, 6, 0, 2), // f2 = 3.0 + fop(0x68, 0, 7, 0, 3), // f3 = 4.0 + iimm(0x100, 0, 0x0, 10), // x10 = result base + fop(0x00, 2, 1, 0, 4), fsw(0, 4, 10), // fadd f4 = 5.0 -> 0x100 + fop(0x04, 2, 1, 0, 5), fsw(8, 5, 10), // fsub f5 = -1.0 -> 0x108 + fop(0x08, 2, 1, 0, 8), fsw(16, 8, 10), // fmul f8 = 6.0 -> 0x110 + fop(0x0C, 1, 3, 0, 9), fsw(24, 9, 10), // fdiv f9 = 4/2=2 -> 0x118 + fop(0x2C, 0, 3, 0, 11), fsw(32, 11, 10), // fsqrt(4)=2.0 -> 0x120 + fop(0x14, 2, 1, 0, 12), fsw(40, 12, 10), // fmin = 2.0 -> 0x128 + fop(0x14, 2, 1, 1, 13), fsw(48, 13, 10), // fmax = 3.0 -> 0x130 + fop(0x10, 2, 1, 0, 14), fsw(56, 14, 10), // fsgnj = 2.0 -> 0x138 + fop4(0x43, 3, 2, 1, 15), fsw(64, 15, 10), // fmadd = 10.0 -> 0x140 + fop4(0x47, 3, 2, 1, 16), fsw(72, 16, 10), // fmsub = 2.0 -> 0x148 + fop4(0x4B, 3, 2, 1, 17), fsw(80, 17, 10), // fnmsub = -2 -> 0x150 + fop(0x50, 2, 1, 2, 18), // feq.s x18 = (f1==f2) = 0 + fop(0x50, 2, 1, 1, 19), // flt.s x19 = (f1 l1 @ 0x11000 -> l0 @ 0x12000 + // l0[0] identity VA 0x0 -> PA 0x0 (code) + // l0[0x20] maps VA 0x20000 -> PA 0x30000 (data) + test('parity: MMU Sv39 translated load (0x20000 -> 0x30000)', () async { + await parityCheck( + [ + csrw(0x180, 10), // csrw satp, a0 (MODE=8 Sv39, root PPN 0x10) + lui(0x20, 12), // a2 = 0x20000 (virtual) + ld(0, 12, 11), // a1 = *(a2) -> phys 0x30000 + nop, + ], + hvConfig(), + seed: {Register.x10: 0x8000000000000010}, + dataMem: { + 0x10000: [0x4401, 0], // l2[0] -> l1 (PPN 0x11), V + 0x11000: [0x4801, 0], // l1[0] -> l0 (PPN 0x12), V + 0x12000: [0xCF, 0], // l0[0] PA 0x0, V|R|W|X|A|D + 0x12100: [0xC0CF, 0], // l0[0x20] PA 0x30000, V|R|W|X|A|D + 0x30000: [0xDEADBEEF, 0x12345678], // data @ phys 0x30000 + }, + nextPc: 0x0C, + checkRegs: [Register.x11], + ); + }); +} diff --git a/packages/river_hdl/test/perf/core_cadence_bench_test.dart b/packages/river_hdl/test/perf/core_cadence_bench_test.dart new file mode 100644 index 0000000..400a92b --- /dev/null +++ b/packages/river_hdl/test/perf/core_cadence_bench_test.dart @@ -0,0 +1,264 @@ +import 'dart:async'; + +import 'package:rohd/rohd.dart'; +import 'package:rohd_hcl/rohd_hcl.dart' hide DataPortInterface, DataPortGroup; +import 'package:river/river.dart'; +import 'package:river_hdl/river_hdl.dart'; +import 'package:test/test.dart'; + +/// Fast, hang-safe front-end cadence harness. Multi-outstanding fetch from a +/// FULLY-DEFINED ROM (no X), BOUNDED cycle loop (cannot hang), and COMMIT-based +/// measurement (via retire_valid). Isolates the alloc cadence and lets us check +/// correctness at period 1. See project_hdl_frontend_perf. +void main() { + RiverCoreConfig mk() => RiverCoreConfig( + clock: HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ), + mxlen: RiscVMxlen.rv64, + extensions: [rv64i, rv32i, rvM, rvZicsr, rvZifencei], + interrupts: const [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + executionMode: ExecutionMode.outOfOrder, + speculativeFetch: true, + prefetchFetch: true, + prefetchDepth: 8, + fetchOutstanding: 4, + // The fast alloc cadence requires the LSQ (memory disambiguation). + loadStoreQueue: LoadStoreQueue.forwarding, + ); + + int iimm(int imm, int rs1, int f3, int rd) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x13; + int btype(int imm, int rs2, int rs1, int f3) => + (((imm >> 12) & 1) << 31) | + (((imm >> 5) & 0x3F) << 25) | + (rs2 << 20) | + (rs1 << 15) | + (f3 << 12) | + (((imm >> 1) & 0xF) << 8) | + (((imm >> 11) & 1) << 7) | + 0x63; + int stype(int imm, int rs2, int rs1, int f3) => + (((imm >> 5) & 0x7F) << 25) | + (rs2 << 20) | + (rs1 << 15) | + (f3 << 12) | + ((imm & 0x1F) << 7) | + 0x23; + + /// Build a multi-outstanding core, run [cycles] bounded cycles, return the + /// commit-cycle list and the data-memory storage (for result checks). + Future<(List, SparseMemoryStorage)> runCore( + List program, { + int cycles = 150, + }) async { + await Simulator.reset(); + final clk = SimpleClockGenerator(20).clk; + final reset = Logic(); + const aw = 64; + final wbConfig = WishboneConfig( + addressWidth: aw, + dataWidth: aw, + selWidth: aw ~/ 8, + ); + final core = RiverCore(mk(), busConfig: wbConfig); + core.input('clk').srcConnection! <= clk; + core.input('reset').srcConnection! <= reset; + + // Pad with `addi x31, x0, imm` (writes x31, reads x0): truly independent. + // (A real `nop` = addi x0,x0,0 WRITES x0; if x0 isn't special-cased that + // creates a false read-x0 dependency chain that serialises the stream.) + final padded = [ + ...program, + for (var i = program.length; i < 64; i++) + iimm((i & 0x1F) + 1, 0, 0x0, 31), + ]; + final link = FetchReadInterface(32, aw); + link.reqValid <= core.output('fetchReq_valid'); + link.reqAddr <= core.output('fetchReq_addr'); + core.input('fetchReq_ready').srcConnection! <= link.reqReady; + core.input('fetchRsp_valid').srcConnection! <= link.rspValid; + core.input('fetchRsp_data').srcConnection! <= link.rspData; + PipelinedFetchMemory( + clk, + reset, + link, + initWords: padded, + words: 64, + readLatency: 1, + ); + + await core.build(); + + final storage = SparseMemoryStorage( + addrWidth: aw, + dataWidth: aw, + alignAddress: (addr) => addr, + onInvalidRead: (addr, dataWidth) => + LogicValue.filled(dataWidth, LogicValue.zero), + ); + final memRead = DataPortInterface(aw, aw); + final memWrite = DataPortInterface(aw, aw); + // ignore: unused_local_variable + final mem = MemoryModel( + clk, + reset, + [wrapWriteForRegisterFile(memWrite)], + [wrapReadForRegisterFile(memRead, clk: clk, readLatency: 0)], + readLatency: 0, + storage: storage, + ); + final wbCyc = core.output('dataBus_CYC'); + final wbStb = core.output('dataBus_STB'); + final wbWe = core.output('dataBus_WE'); + memRead.en <= wbCyc & wbStb & ~wbWe; + memRead.addr <= core.output('dataBus_ADR'); + memWrite.en <= wbCyc & wbStb & wbWe; + memWrite.addr <= core.output('dataBus_ADR'); + memWrite.data <= core.output('dataBus_DAT_MOSI'); + final wbAckReg = Logic(name: 'wbAck'); + Sequential(clk, [ + If( + reset, + then: [wbAckReg < 0], + orElse: [ + If( + wbCyc & wbStb & ~wbAckReg & (wbWe | memRead.valid), + then: [wbAckReg < 1], + orElse: [wbAckReg < 0], + ), + ], + ), + ]); + core.input('dataBus_ACK').srcConnection! <= wbAckReg; + core.input('dataBus_DAT_MISO').srcConnection! <= memRead.data; + + reset.inject(1); + Simulator.registerAction(20, () => reset.put(0)); + Simulator.setMaxSimTime(300000); + unawaited(Simulator.run()); + await clk.nextPosedge; + while (reset.value.toBool()) { + await clk.nextPosedge; + } + + final retire = core.pipeline.output('retire_valid'); + bool hi(Logic l) => l.value.isValid && l.value.toBool(); + final commitCycles = []; + var cyc = 0; + for (var i = 0; i < cycles; i++) { + await clk.nextPosedge; + cyc++; + if (hi(retire)) commitCycles.add(cyc); + } + await Simulator.endSimulation(); + await Simulator.simulationEnded; + return (commitCycles, storage); + } + + int rd64(SparseMemoryStorage s, int addr) => + s.getData(LogicValue.ofInt(addr, 64))?.toInt() ?? 0; + + tearDown(() async { + await Simulator.reset(); + }); + + test( + 'cadence: commit throughput on straight-line (bounded, no-X)', + () async { + final program = [ + for (var i = 0; i < 24; i++) iimm((i & 0x3F) + 1, 0, 0x0, (i % 30) + 1), + ]; + final (commits, _) = await runCore(program, cycles: 150); + final gaps = []; + for (var i = 1; i < commits.length; i++) { + gaps.add(commits[i] - commits[i - 1]); + } + final steady = gaps.length > 6 ? gaps.sublist(3) : gaps; + final avg = steady.isEmpty + ? 0.0 + : steady.reduce((a, b) => a + b) / steady.length; + // ignore: avoid_print + print( + '\n=== CADENCE: commits=${commits.length}/150 cyc, ' + 'steady commit period=${avg.toStringAsFixed(2)} ' + '(slow advance ~3.0, fast advance ~1.0) ===\n', + ); + expect( + commits.length, + greaterThan(20), + reason: 'must retire a steady stream (not wedge)', + ); + // The LSQ-gated fast advance + independent stream should sustain ~1.0 + // commit/cyc (the full front-end lift). Guard against cadence regressions. + expect( + avg, + lessThan(1.4), + reason: 'fast cadence should sustain ~1 commit/cyc (got $avg)', + ); + }, + timeout: Timeout(Duration(seconds: 120)), + ); + + // x0 special-casing: a stream of canonical nops (addi x0,x0,0) must NOT + // false-chain through x0. Without the x0-always-ready fix this serialises to + // ~1.5 cyc/instr; with it, ~1.0. (Safe: the OoO path is integer-only.) + test( + 'cadence: canonical nops do not false-chain through x0', + () async { + final program = [for (var i = 0; i < 40; i++) 0x00000013]; // addi x0,x0,0 + final (commits, _) = await runCore(program, cycles: 120); + final gaps = []; + for (var i = 1; i < commits.length; i++) { + gaps.add(commits[i] - commits[i - 1]); + } + final steady = gaps.length > 6 ? gaps.sublist(3) : gaps; + final avg = steady.isEmpty + ? 0.0 + : steady.reduce((a, b) => a + b) / steady.length; + // ignore: avoid_print + print( + '\n=== NOP cadence: period=${avg.toStringAsFixed(2)} ' + '(no x0 fix ~1.5, with x0 fix ~1.0) ===\n', + ); + expect( + avg, + lessThan(1.4), + reason: 'nops must not false-chain through x0 (got $avg)', + ); + }, + timeout: Timeout(Duration(seconds: 120)), + ); + + // THE LANDING TEST: a counted loop (backward-branch redirect) must execute + // CORRECTLY at period 1. Loop 5 times to compute x1=5, store it to mem[0]. + test( + 'correctness: counted loop at period 1 -> mem[0]==5', + () async { + final program = [ + iimm(0, 0, 0x0, 1), // addi x1,x0,0 @0 + iimm(5, 0, 0x0, 2), // addi x2,x0,5 @4 + iimm(1, 1, 0x0, 1), // addi x1,x1,1 (loop) @8 + iimm(-1, 2, 0x0, 2), // addi x2,x2,-1 @12 + btype(-8, 0, 2, 0x1), // bne x2,x0,@8 @16 + stype(0, 1, 0, 0x2), // sw x1,0(x0) @20 + ]; + final (commits, storage) = await runCore(program, cycles: 120); + final result = rd64(storage, 0); + // ignore: avoid_print + print( + '\n=== LOOP: commits=${commits.length}, mem[0]=$result (expect 5) ===\n', + ); + expect(result, 5, reason: 'counted loop must compute x1=5 and store it'); + }, + timeout: Timeout(Duration(seconds: 120)), + ); +} diff --git a/packages/river_hdl/test/perf/ipc_benchmark.dart b/packages/river_hdl/test/perf/ipc_benchmark.dart new file mode 100644 index 0000000..c376c27 --- /dev/null +++ b/packages/river_hdl/test/perf/ipc_benchmark.dart @@ -0,0 +1,570 @@ +import 'dart:async'; + +import 'package:rohd/rohd.dart'; +import 'package:rohd_hcl/rohd_hcl.dart' hide DataPortInterface, DataPortGroup; +import 'package:river/river.dart'; +import 'package:river_hdl/river_hdl.dart'; +import 'package:test/test.dart'; + +/// Microarchitecture IPC benchmark. Measures cycles-to-complete for a workload +/// under several pipeline personalities, isolating the contribution of the +/// instruction cache (fast re-fetch) and dual-dispatch (2-wide issue). +/// +/// Memory has a non-trivial read latency so that a bus fetch is meaningfully +/// slower than a cache hit, which is where the icache earns its keep. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + HarborMmuConfig mmu() => HarborMmuConfig( + mxlen: RiscVMxlen.rv32, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ); + + RiverCoreConfig mk({ + required ExecutionMode mode, + bool speculative = false, + IssueWidth issue = IssueWidth.single, + bool icache = false, + bool prefetch = false, + int prefetchDepth = 2, + BranchPredictor bp = BranchPredictor.none, + LoadStoreQueue lsq = LoadStoreQueue.none, + }) => RiverCoreConfig( + clock: HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ), + mxlen: RiscVMxlen.rv32, + extensions: [rv32i, rvZicsr, rvZifencei, rvM], + interrupts: [], + mmu: mmu(), + type: RiverCoreType.general, + executionMode: mode, + speculativeFetch: speculative, + prefetchFetch: prefetch, + prefetchDepth: prefetchDepth, + issueWidth: issue, + l1cache: icache + ? HarborL1CacheConfig.split(iSize: 32, dSize: 64, ways: 1, lineSize: 4) + : null, + branchPredictor: bp, + loadStoreQueue: lsq, + ); + + int iimm(int imm, int rs1, int f3, int rd) => + (imm << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x13; + int b(int imm, int rs2, int rs1, int f3) => + (((imm >> 12) & 0x1) << 31) | + (((imm >> 5) & 0x3F) << 25) | + (rs2 << 20) | + (rs1 << 15) | + (f3 << 12) | + (((imm >> 1) & 0xF) << 8) | + (((imm >> 11) & 0x1) << 7) | + 0x63; + String prog(List words) { + final sb = StringBuffer('@0\n'); + for (final w in words) { + for (var i = 0; i < 4; i++) { + sb.write(((w >> (i * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + return '$sb\n'; + } + + /// Run [config] on [memString] until nextPc==[nextPc]; return the cycle count. + Future measureCycles( + RiverCoreConfig config, + String memString, + int nextPc, { + int memLatency = 0, + }) async { + // Each measurement is an independent simulation; reset the global Simulator + // so its clock starts at zero again (multiple runs in one test). + await Simulator.reset(); + final clk = SimpleClockGenerator(20).clk; + final reset = Logic(); + final addrWidth = config.mxlen.size; + final wbConfig = WishboneConfig( + addressWidth: addrWidth, + dataWidth: config.mxlen.size, + selWidth: config.mxlen.size ~/ 8, + ); + final core = RiverCore(config, busConfig: wbConfig); + core.input('clk').srcConnection! <= clk; + core.input('reset').srcConnection! <= reset; + await core.build(); + + final storage = SparseMemoryStorage( + addrWidth: addrWidth, + dataWidth: config.mxlen.size, + alignAddress: (addr) => addr, + onInvalidRead: (addr, dataWidth) => + LogicValue.filled(dataWidth, LogicValue.zero), + ); + final memRead = DataPortInterface(config.mxlen.size, addrWidth); + final memWrite = DataPortInterface(config.mxlen.size, addrWidth); + // ignore: unused_local_variable + final mem = MemoryModel( + clk, + reset, + [wrapWriteForRegisterFile(memWrite)], + [wrapReadForRegisterFile(memRead, clk: clk, readLatency: memLatency)], + readLatency: memLatency, + storage: storage, + ); + final wbCyc = core.output('dataBus_CYC'); + final wbStb = core.output('dataBus_STB'); + final wbWe = core.output('dataBus_WE'); + final wbAdr = core.output('dataBus_ADR'); + final wbDatMosi = core.output('dataBus_DAT_MOSI'); + memRead.en <= wbCyc & wbStb & ~wbWe; + memRead.addr <= wbAdr; + memWrite.en <= wbCyc & wbStb & wbWe; + memWrite.addr <= wbAdr; + memWrite.data <= wbDatMosi; + final wbAckReg = Logic(name: 'wbAck'); + final readyForAck = wbWe | memRead.valid; + Sequential(clk, [ + If( + reset, + then: [wbAckReg < 0], + orElse: [ + If( + wbCyc & wbStb & ~wbAckReg & readyForAck, + then: [wbAckReg < 1], + orElse: [wbAckReg < 0], + ), + ], + ), + ]); + core.input('dataBus_ACK').srcConnection! <= wbAckReg; + core.input('dataBus_DAT_MISO').srcConnection! <= memRead.data; + + reset.inject(1); + Simulator.registerAction(20, () { + reset.put(0); + storage.loadMemString(memString); + }); + Simulator.setMaxSimTime(2000000); + unawaited(Simulator.run()); + await clk.nextPosedge; + while (reset.value.toBool()) { + await clk.nextPosedge; + } + var cycles = 0; + for (var i = 0; i < 20000; i++) { + await clk.nextPosedge; + cycles++; + final pc = core.pipeline.nextPc.value; + if (pc.isValid && pc.toInt() == nextPc) break; + } + await Simulator.endSimulation(); + await Simulator.simulationEnded; + return cycles; + } + + // Loop workload: a counted loop whose body is re-fetched every iteration, + // and the icache turns those re-fetches into hits. Kept short (ROHD sim of the + // full OoO core is slow). The per-iteration re-fetch is what the icache + // accelerates, so even a few iterations show the effect. + // 0x00 addi x1,x0,6 + // 0x04 addi x2,x2,1 (loop body start) + // 0x08 addi x3,x3,2 + // 0x0C addi x1,x1,-1 + // 0x10 bne x1,x0,-12 -> back to 0x04 + // 0x14.. nop tail + String loopProg() => prog([ + iimm(6, 0, 0x0, 1), + iimm(1, 2, 0x0, 2), + iimm(2, 3, 0x0, 3), + iimm(-1, 1, 0x0, 1), + b(-12, 0, 1, 0x1), + ...List.filled(10, 0x00000013), + ]); + const loopNextPc = 0x3C; + + // Cached-loop workload: a loop whose body is a run of independent adds. After + // the first iteration the body is cached, so the 2-port icache feeds both + // lanes 2 instructions/cycle and dual-dispatch can co-issue the independent + // body, which is where 2-wide issue earns its keep (cold straight-line code is + // fill-bound at one word/cycle and dual can't beat single there). The wider + // the independent body, the more the 2-wide lanes amortize the serial + // loop-carried recurrence (dec then branch), so a longer body gives more + // speedup: measured ~1.20x at 12 adds, ~1.34x at 16 adds (the latter run + // standalone at memLatency=4, since the 16-body at memLatency=12 is too slow + // for this 5-config bench, and core_dual_test's M6 guards 16-body behaviour). + // 0x00 addi x14,x0,5 (iteration count) + // 0x04..0x30 addi x1..x12,x0,k loop body (12 independent adds) + // 0x34 addi x14,x14,-1 + // 0x38 bne x14,x0,-52 -> back to 0x04 + // 0x3C.. nop tail + // 12 independent adds + dec + back-edge. + String cachedLoopProg() => prog([ + iimm(5, 0, 0x0, 14), + for (var r = 1; r <= 12; r++) iimm(r, 0, 0x0, r), + iimm(-1, 14, 0x0, 14), + b(-52, 0, 14, 0x1), + ...List.filled(10, 0x00000013), + ]); + const cachedLoopNextPc = 0x64; // 25 words + + test( + 'IPC: instruction-cache and dual-dispatch', + timeout: Timeout(Duration(seconds: 900)), + () async { + // memLatency makes a bus fetch cost several cycles; cache hits cost one. + // Higher latency = larger gap between a bus fetch and a cache hit, so the + // icache's benefit grows with it (real memory hierarchies have deep misses). + const lat = 12; + + // Loop: instruction-cache effect (no prediction in either). + final loopNoIc = await measureCycles( + mk(mode: ExecutionMode.outOfOrder, speculative: true), + loopProg(), + loopNextPc, + memLatency: lat, + ); + final loopIc = await measureCycles( + mk(mode: ExecutionMode.outOfOrder, speculative: true, icache: true), + loopProg(), + loopNextPc, + memLatency: lat, + ); + // Loop: branch-prediction effect (both have the icache). + final loopBp = await measureCycles( + mk( + mode: ExecutionMode.outOfOrder, + speculative: true, + icache: true, + bp: BranchPredictor.btfn, + ), + loopProg(), + loopNextPc, + memLatency: lat, + ); + + // Cached independent-body loop with prediction: single vs dual. With the + // back-edge predicted, the per-iteration flush is gone, so the 2-wide lanes + // can finally co-issue the independent body. + final clSingleBp = await measureCycles( + mk( + mode: ExecutionMode.outOfOrder, + speculative: true, + icache: true, + bp: BranchPredictor.btfn, + ), + cachedLoopProg(), + cachedLoopNextPc, + memLatency: lat, + ); + final clDualBp = await measureCycles( + mk( + mode: ExecutionMode.outOfOrder, + speculative: true, + issue: IssueWidth.dual, + icache: true, + bp: BranchPredictor.btfn, + ), + cachedLoopProg(), + cachedLoopNextPc, + memLatency: lat, + ); + + // ignore: avoid_print + print('=== IPC benchmark (memLatency=$lat) ==='); + // ignore: avoid_print + print( + 'Loop, re-fetched body: no-icache = $loopNoIc, +icache = $loopIc' + ' -> icache ${(loopNoIc / loopIc).toStringAsFixed(2)}x', + ); + // ignore: avoid_print + print( + 'Loop, branch predict: icache = $loopIc, icache+btfn = $loopBp' + ' -> bpred ${(loopIc / loopBp).toStringAsFixed(2)}x', + ); + // ignore: avoid_print + print( + 'Cached loop +btfn: single = $clSingleBp, dual = $clDualBp' + ' -> dual ${(clSingleBp / clDualBp).toStringAsFixed(2)}x', + ); + + expect( + loopIc, + lessThan(loopNoIc), + reason: 'icache should speed up the re-fetched loop', + ); + expect( + loopBp, + lessThan(loopIc), + reason: 'branch prediction should speed up the loop further', + ); + expect( + clDualBp, + lessThanOrEqualTo(clSingleBp), + reason: 'dual should be no slower than single', + ); + }, + ); + + // Prefetch fetcher: a long straight-line, dependency-free run (the case the + // classic fetcher serialises worst, fetch->decode->rename->alloc per instr). + // The prefetch fetcher reads one ahead into a FIFO so the next fetch overlaps + // the current instruction's decode/rename/alloc. With a bus fetch latency the + // win should be visible. See project_hdl_prefetch. + String chainProg() => prog([ + for (var i = 0; i < 24; i++) iimm((i & 0x3F) + 1, 0, 0x0, (i % 30) + 1), + ...List.filled(8, 0x00000013), + ]); + + test( + 'IPC: prefetch fetcher (straight-line)', + timeout: Timeout(Duration(seconds: 600)), + () async { + const end = 24 * 4; // PC after the 24th addi commits + print('=== prefetch fetcher (straight-line 24 instr) ==='); + // (icache, memLatency) points: the no-icache headline win, plus the icache + // cases where line-fill should let prefetch hide the per-hit fetch latency. + final points = [(false, 0), (true, 0), (true, 2), (true, 4)]; + for (final (ic, lat) in points) { + final base = await measureCycles( + mk(mode: ExecutionMode.outOfOrder, speculative: true, icache: ic), + chainProg(), + end, + memLatency: lat, + ); + final pf = await measureCycles( + mk( + mode: ExecutionMode.outOfOrder, + speculative: true, + icache: ic, + prefetch: true, + ), + chainProg(), + end, + memLatency: lat, + ); + print( + 'icache=$ic memLatency=$lat: ' + 'classic=$base, prefetch=$pf -> ${(base / pf).toStringAsFixed(2)}x', + ); + expect( + pf, + lessThanOrEqualTo(base), + reason: 'prefetch should be no slower (icache=$ic lat=$lat)', + ); + } + // FIFO-depth sweep at icache + latency. NOTE: deeper does NOT help here, + // reads are single-outstanding, so the FIFO fills at the read rate (~= the + // consume rate during icache hits) and never gets far enough ahead to cover + // a line-fill miss. Getting ahead needs MULTIPLE outstanding reads (pipelined + // fetch), which needs a request/response-decoupled interconnect. Kept as a + // regression guard that depth is correct + no-slower. See project_hdl_prefetch. + final dBase = await measureCycles( + mk(mode: ExecutionMode.outOfOrder, speculative: true, icache: true), + chainProg(), + end, + memLatency: 4, + ); + for (final d in [2, 4]) { + final pf = await measureCycles( + mk( + mode: ExecutionMode.outOfOrder, + speculative: true, + icache: true, + prefetch: true, + prefetchDepth: d, + ), + chainProg(), + end, + memLatency: 4, + ); + print( + 'icache+memLatency=4 prefetchDepth=$d: ' + 'classic=$dBase, prefetch=$pf -> ${(dBase / pf).toStringAsFixed(2)}x', + ); + } + }, + ); + + // Load-store-queue benchmark. A dependent store→load loop: each iteration + // stores a value and loads it straight back from the same address, then uses + // it. With memLatency the store's write to memory costs several cycles, so: + // - storeQueue: the load waits for the store to drain every iteration; + // - forwarding: the load takes the value from the queue, no drain wait; + // - speculative: same forward, and loads may also run ahead of the store. + int s(int imm, int rs2, int rs1, int f3) => + (((imm >> 5) & 0x7F) << 25) | + (rs2 << 20) | + (rs1 << 15) | + (f3 << 12) | + ((imm & 0x1F) << 7) | + 0x23; + int lw(int imm, int rs1, int rd) => + (imm << 20) | (rs1 << 15) | (0x2 << 12) | (rd << 7) | 0x03; + // jal x0, 0: an unconditional jump to self, used to terminate a benchmark + // program so the speculative front-end stays put instead of running off the + // end of the nop tail into uninitialised memory during long stalls. + const selfLoop = 0x0000006F; + + // 0x00 addi x10,x0,0x400 (data address) + // 0x04 addi x14,x0,8 (iteration count) + // 0x08 addi x5,x0,1 (initial value) + // 0x0C sw x5,0(x10) loop body: store + // 0x10 lw x6,0(x10) load it back (store then load, same addr) + // 0x14 addi x5,x6,1 use the loaded value (dep chain via mem) + // 0x18 addi x14,x14,-1 + // 0x1C bne x14,x0,-16 -> back to 0x0C + // 0x20 jal x0,0 (terminating self-loop) + String memLoopProg() => prog([ + iimm(0x400, 0, 0x0, 10), + iimm(8, 0, 0x0, 14), + iimm(1, 0, 0x0, 5), + s(0, 5, 10, 0x2), + lw(0, 10, 6), + iimm(1, 6, 0x0, 5), + iimm(-1, 14, 0x0, 14), + b(-16, 0, 14, 0x1), + selfLoop, + ]); + const memLoopNextPc = 0x20; + + test( + 'IPC: load-store queue (store→load dependent loop)', + timeout: Timeout(Duration(seconds: 900)), + () async { + const lat = 4; + RiverCoreConfig lsqCfg( + LoadStoreQueue q, { + IssueWidth issue = IssueWidth.single, + }) => mk( + mode: ExecutionMode.outOfOrder, + speculative: true, + icache: true, + bp: BranchPredictor.btfn, + issue: issue, + lsq: q, + ); + + final sq = await measureCycles( + lsqCfg(LoadStoreQueue.storeQueue), + memLoopProg(), + memLoopNextPc, + memLatency: lat, + ); + final fwd = await measureCycles( + lsqCfg(LoadStoreQueue.forwarding), + memLoopProg(), + memLoopNextPc, + memLatency: lat, + ); + final fwdDual = await measureCycles( + lsqCfg(LoadStoreQueue.forwarding, issue: IssueWidth.dual), + memLoopProg(), + memLoopNextPc, + memLatency: lat, + ); + + // ignore: avoid_print + print('=== LSQ benchmark (memLatency=$lat, store→load dep loop) ==='); + // ignore: avoid_print + print( + 'storeQueue = $sq, forwarding = $fwd, forwarding+dual = $fwdDual' + ' -> dual ${(fwd / fwdDual).toStringAsFixed(2)}x over single', + ); + + expect( + fwd, + lessThanOrEqualTo(sq), + reason: 'forwarding should not be slower than waiting for the drain', + ); + expect( + fwdDual, + lessThanOrEqualTo(fwd), + reason: 'dual mem co-dispatch should be no slower than single', + ); + }, + ); + + int rr(int f7, int rs2, int rs1, int f3, int rd) => + (f7 << 25) | (rs2 << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x33; + + // Independent load behind a SLOW store. Each iteration computes the store's + // address with a multi-cycle mul, stores there, then loads from a different + // (fast) address and accumulates. In-order memory (storeQueue/forwarding) must + // hold the load behind the not-ready store, so every iteration waits the full + // mul latency. Speculative loads bypass the not-ready store and overlap the + // mul, hiding it. + // 0x00 addi x10,x0,0x500 load address (fast) + // 0x04 addi x21,x0,0x400 store-base operand + // 0x08 addi x22,x0,1 mul operand + // 0x0C addi x14,x0,6 count + // 0x10 addi x5,x0,0xAA store value + // 0x14 mul x20,x21,x22 slow -> store address (0x400) + // 0x18 sw x5,0(x20) store (address not ready until the mul finishes) + // 0x1C lw x6,0(x10) load from 0x500 (independent, ready early) + // 0x20 add x7,x7,x6 accumulate + // 0x24 addi x14,x14,-1 + // 0x28 bne x14,x0,-20 -> 0x14 + // 0x2C jal x0,0 + String slowStoreLoopProg() => + '${prog([ + iimm(0x500, 0, 0x0, 10), + iimm(0x400, 0, 0x0, 21), + iimm(1, 0, 0x0, 22), + iimm(6, 0, 0x0, 14), + iimm(0xAA, 0, 0x0, 5), + rr(0x01, 22, 21, 0x0, 20), // mul x20, x21, x22 + s(0, 5, 20, 0x2), + lw(0, 10, 6), + rr(0x00, 6, 7, 0x0, 7), // add x7, x7, x6 + iimm(-1, 14, 0x0, 14), + b(-20, 0, 14, 0x1), + selfLoop, + ])}@500\n05 00 00 00\n'; + const slowStoreNextPc = 0x2C; + + test( + 'IPC: speculative loads bypass a slow store', + timeout: Timeout(Duration(seconds: 900)), + () async { + RiverCoreConfig cfg(LoadStoreQueue q) => mk( + mode: ExecutionMode.outOfOrder, + speculative: true, + icache: true, + bp: BranchPredictor.btfn, + lsq: q, + ); + + final fwd = await measureCycles( + cfg(LoadStoreQueue.forwarding), + slowStoreLoopProg(), + slowStoreNextPc, + ); + final spec = await measureCycles( + cfg(LoadStoreQueue.speculative), + slowStoreLoopProg(), + slowStoreNextPc, + ); + + // ignore: avoid_print + print('=== speculative-load benchmark (load behind slow store) ==='); + // ignore: avoid_print + print( + 'forwarding = $fwd, speculative = $spec' + ' -> speculative ${(fwd / spec).toStringAsFixed(2)}x', + ); + + expect( + spec, + lessThanOrEqualTo(fwd), + reason: 'speculative loads should bypass the slow store', + ); + }, + ); +} diff --git a/packages/river_hdl/test/regfile/inorder_read_latency_test.dart b/packages/river_hdl/test/regfile/inorder_read_latency_test.dart new file mode 100644 index 0000000..2ebcfd1 --- /dev/null +++ b/packages/river_hdl/test/regfile/inorder_read_latency_test.dart @@ -0,0 +1,27 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +/// Validates the registered (full-cycle) register-file read path in simulation. +/// +/// The ECP5 EBR register file reads on the posedge (readLatency == 1) so the +/// read stays off the combinational ALU path and timing closes at 48 MHz. The +/// DP16KD is a blackbox with no sim model, so here we force the *flop* register +/// file to the same latency via [matrixConfig]'s regfileReadLatency. If the +/// in-order operand-read handshake (hold address, wait for done&valid, then +/// latch) correctly absorbs the extra cycle, every instruction still produces +/// the golden result. Runs the operand-read-heavy base + M categories. +void main() { + const mxlen = RiscVMxlen.rv64; + const uarch = Uarch.inOrder; + for (final category in ['base', 'm']) { + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)} ' + '(regfile readLatency=1)', + matrixConfig(mxlen, uarch, category, regfileReadLatency: 1), + instructionsFor(category, mxlen), + ); + } +} diff --git a/packages/river_hdl/test/regfile/regfile_multiport_test.dart b/packages/river_hdl/test/regfile/regfile_multiport_test.dart new file mode 100644 index 0000000..40e2e98 --- /dev/null +++ b/packages/river_hdl/test/regfile/regfile_multiport_test.dart @@ -0,0 +1,265 @@ +import 'dart:async'; + +import 'package:harbor/harbor.dart'; +import 'package:rohd/rohd.dart'; +import 'package:test/test.dart'; + +/// External net feeding module input [name]. +Logic _pin(HarborRegisterFile r, String name) => r.input(name).srcConnection!; + +void _inj(HarborRegisterFile r, String name, int v) => _pin(r, name).inject(v); + +String _en(int w, int n) => n == 1 ? 'wr_en' : 'wr${w}_en'; +String _addr(int w, int n) => n == 1 ? 'wr_addr' : 'wr${w}_addr'; +String _data(int w, int n) => n == 1 ? 'wr_data' : 'wr${w}_data'; +String _ready(int w, int n) => n == 1 ? 'wr_ready' : 'wr${w}_ready'; + +int _get(HarborRegisterFile regs, int reg) => + regs.getData(LogicValue.ofInt(reg, 5))!.toInt(); + +/// Build a register file (flop/sim backend, target=null), drive its clock and +/// reset, settle out of reset, and return it ready for poking. +Future _mk({ + int numReadPorts = 2, + int numWritePorts = 1, + int numBanks = 1, + int writeBufferDepth = 0, +}) async { + final clk = SimpleClockGenerator(10).clk; + final regs = HarborRegisterFile( + numEntries: 32, + dataWidth: 32, + numReadPorts: numReadPorts, + numWritePorts: numWritePorts, + numBanks: numBanks, + writeBufferDepth: writeBufferDepth, + ); + _pin(regs, 'clk') <= clk; + // Default every input so nothing floats to X. + _inj(regs, 'reset', 1); + for (var w = 0; w < numWritePorts; w++) { + _inj(regs, _en(w, numWritePorts), 0); + _inj(regs, _addr(w, numWritePorts), 0); + _inj(regs, _data(w, numWritePorts), 0); + } + for (var r = 0; r < numReadPorts; r++) { + _inj(regs, 'rd${r}_addr', 0); + } + await regs.build(); + Simulator.setMaxSimTime(100000); + unawaited(Simulator.run()); + await clk.nextPosedge; + await clk.nextPosedge; + _inj(regs, 'reset', 0); + await clk.nextPosedge; + return regs; +} + +void main() { + tearDown(() async { + await Simulator.endSimulation(); + Simulator.reset(); + }); + + test('default 2R/1W: write then read back (back-compat)', () async { + final regs = await _mk(); + final clk = _pin(regs, 'clk'); + _inj(regs, 'wr_en', 1); + _inj(regs, 'wr_addr', 5); + _inj(regs, 'wr_data', 0xABCD); + await clk.nextNegedge; + expect(regs.output('wr_ready').value.toInt(), 1, reason: 'always ready'); + await clk.nextPosedge; + await clk.nextNegedge; + expect(_get(regs, 5), 0xABCD); + _inj(regs, 'wr_en', 0); + _inj(regs, 'rd0_addr', 5); + await clk.nextNegedge; + expect(regs.rd0Data.value.toInt(), 0xABCD); + }); + + test('2W/2banks: writes to different banks both commit same cycle', () async { + final regs = await _mk(numWritePorts: 2, numBanks: 2); + final clk = _pin(regs, 'clk'); + // reg 2 -> bank 0, reg 3 -> bank 1 (bank = low bit). + _inj(regs, _en(0, 2), 1); + _inj(regs, _addr(0, 2), 2); + _inj(regs, _data(0, 2), 0x11); + _inj(regs, _en(1, 2), 1); + _inj(regs, _addr(1, 2), 3); + _inj(regs, _data(1, 2), 0x22); + await clk.nextNegedge; + expect(regs.output(_ready(0, 2)).value.toInt(), 1); + expect(regs.output(_ready(1, 2)).value.toInt(), 1); + await clk.nextPosedge; + await clk.nextNegedge; + expect(_get(regs, 2), 0x11); + expect(_get(regs, 3), 0x22); + }); + + test( + '2W/1bank conflict (distinct addrs): older wins, younger stalls', + () async { + final regs = await _mk(numWritePorts: 2, numBanks: 1); + final clk = _pin(regs, 'clk'); + _inj(regs, _en(0, 2), 1); + _inj(regs, _addr(0, 2), 2); + _inj(regs, _data(0, 2), 0x11); + _inj(regs, _en(1, 2), 1); + _inj(regs, _addr(1, 2), 4); + _inj(regs, _data(1, 2), 0x22); + await clk.nextNegedge; + expect( + regs.output(_ready(0, 2)).value.toInt(), + 1, + reason: 'older accepted', + ); + expect( + regs.output(_ready(1, 2)).value.toInt(), + 0, + reason: 'younger stalled', + ); + await clk.nextPosedge; + await clk.nextNegedge; + expect(_get(regs, 2), 0x11); + expect(_get(regs, 4), 0, reason: 'younger not yet written'); + // Retry younger alone next cycle. + _inj(regs, _en(0, 2), 0); + await clk.nextNegedge; + expect(regs.output(_ready(1, 2)).value.toInt(), 1); + await clk.nextPosedge; + await clk.nextNegedge; + expect(_get(regs, 4), 0x22); + }, + ); + + test('2W same address WAW: younger value wins, both ready', () async { + final regs = await _mk(numWritePorts: 2, numBanks: 1); + final clk = _pin(regs, 'clk'); + _inj(regs, _en(0, 2), 1); + _inj(regs, _addr(0, 2), 6); + _inj(regs, _data(0, 2), 0x11); + _inj(regs, _en(1, 2), 1); + _inj(regs, _addr(1, 2), 6); + _inj(regs, _data(1, 2), 0x22); + await clk.nextNegedge; + expect(regs.output(_ready(0, 2)).value.toInt(), 1); + expect(regs.output(_ready(1, 2)).value.toInt(), 1); + await clk.nextPosedge; + await clk.nextNegedge; + expect(_get(regs, 6), 0x22, reason: 'younger (slot 1) wins'); + }); + + test( + 'depth=1 buffer: same-bank conflict buffers younger (no stall)', + () async { + final regs = await _mk( + numWritePorts: 2, + numBanks: 1, + writeBufferDepth: 1, + ); + final clk = _pin(regs, 'clk'); + _inj(regs, _en(0, 2), 1); + _inj(regs, _addr(0, 2), 2); + _inj(regs, _data(0, 2), 0x11); + _inj(regs, _en(1, 2), 1); + _inj(regs, _addr(1, 2), 4); + _inj(regs, _data(1, 2), 0x22); + await clk.nextNegedge; + expect(regs.output(_ready(0, 2)).value.toInt(), 1); + expect( + regs.output(_ready(1, 2)).value.toInt(), + 1, + reason: 'younger buffered, not stalled', + ); + await clk.nextPosedge; // x2 written direct; x4 enqueued + await clk.nextNegedge; + expect(_get(regs, 2), 0x11); + expect(_get(regs, 4), 0, reason: 'x4 still buffered, not drained yet'); + // Read bypass: x4 must be visible from the buffer before it drains. + _inj(regs, _en(0, 2), 0); + _inj(regs, _en(1, 2), 0); + _inj(regs, 'rd0_addr', 4); + await clk.nextNegedge; + expect( + regs.rd0Data.value.toInt(), + 0x22, + reason: 'bypass from write buffer', + ); + await clk.nextPosedge; // buffer drains x4 -> storage + await clk.nextNegedge; + expect(_get(regs, 4), 0x22, reason: 'drained to storage'); + }, + ); + + test( + 'depth=1 buffer overflow: second conflict stalls when buffer full', + () async { + final regs = await _mk( + numWritePorts: 2, + numBanks: 1, + writeBufferDepth: 1, + ); + final clk = _pin(regs, 'clk'); + // Cycle T: x2 direct, x4 buffered. + _inj(regs, _en(0, 2), 1); + _inj(regs, _addr(0, 2), 2); + _inj(regs, _data(0, 2), 0x11); + _inj(regs, _en(1, 2), 1); + _inj(regs, _addr(1, 2), 4); + _inj(regs, _data(1, 2), 0x22); + await clk.nextPosedge; + // Cycle T+1: buffer holds x4 (drains this cycle), and two NEW writes + // arrive. x6 buffers (slot freed by drain); x8 overflows depth-1 buffer. + _inj(regs, _addr(0, 2), 6); + _inj(regs, _data(0, 2), 0x33); + _inj(regs, _addr(1, 2), 8); + _inj(regs, _data(1, 2), 0x44); + await clk.nextNegedge; + expect(regs.output(_ready(0, 2)).value.toInt(), 1, reason: 'x6 buffered'); + expect( + regs.output(_ready(1, 2)).value.toInt(), + 0, + reason: 'x8 stalls: buffer full', + ); + }, + ); + + test('depth=2 buffer: two conflicts buffer and both drain', () async { + final regs = await _mk(numWritePorts: 2, numBanks: 1, writeBufferDepth: 2); + final clk = _pin(regs, 'clk'); + // T: x2 direct, x4 -> buffer[0]. + _inj(regs, _en(0, 2), 1); + _inj(regs, _addr(0, 2), 2); + _inj(regs, _data(0, 2), 0x11); + _inj(regs, _en(1, 2), 1); + _inj(regs, _addr(1, 2), 4); + _inj(regs, _data(1, 2), 0x22); + await clk.nextPosedge; + // T+1: buffer drains x4; x6 and x8 both buffer (depth 2 holds both). + _inj(regs, _addr(0, 2), 6); + _inj(regs, _data(0, 2), 0x33); + _inj(regs, _addr(1, 2), 8); + _inj(regs, _data(1, 2), 0x44); + await clk.nextNegedge; + expect(regs.output(_ready(0, 2)).value.toInt(), 1); + expect( + regs.output(_ready(1, 2)).value.toInt(), + 1, + reason: 'depth-2 holds both', + ); + await clk + .nextPosedge; // latch: drain x4, enqueue x6 & x8 (inputs still driven) + _inj(regs, _en(0, 2), 0); + _inj(regs, _en(1, 2), 0); + // Drain the buffer over the next few cycles. + for (var i = 0; i < 3; i++) { + await clk.nextPosedge; + } + await clk.nextNegedge; + expect(_get(regs, 2), 0x11); + expect(_get(regs, 4), 0x22); + expect(_get(regs, 6), 0x33); + expect(_get(regs, 8), 0x44); + }); +} diff --git a/packages/river_hdl/test/rvc_load_decode_test.dart b/packages/river_hdl/test/rvc_load_decode_test.dart new file mode 100644 index 0000000..e6bd7f3 --- /dev/null +++ b/packages/river_hdl/test/rvc_load_decode_test.dart @@ -0,0 +1,166 @@ +import 'dart:async'; + +import 'package:river/river.dart'; +import 'package:rohd/rohd.dart'; +import 'package:rohd_hcl/rohd_hcl.dart' hide DataPortInterface, DataPortGroup; +import 'package:river_hdl/river_hdl.dart'; +import 'package:test/test.dart'; + +RiverCoreConfig _rv64() => RiverCoreConfigV1.small( + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + hasSupervisorUserMemory: true, + hasMakeExecutableReadable: true, + ), + interrupts: [], + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(12000000), + ), + resetVector: 0, +); + +void main() { + test( + 'c.ld prime-register register-relative load (creek microcode)', + () async { + await Simulator.reset(); + final config = _rv64(); + const xlen = 64; + final clk = SimpleClockGenerator(20).clk; + final reset = Logic(name: 'reset'); + final wbConfig = WishboneConfig( + addressWidth: xlen, + dataWidth: xlen, + selWidth: xlen ~/ 8, + ); + final core = RiverCore(config, busConfig: wbConfig); + core.input('clk').srcConnection! <= clk; + core.input('reset').srcConnection! <= reset; + await core.build(); + + final storage = SparseMemoryStorage( + addrWidth: xlen, + dataWidth: xlen, + alignAddress: (addr) => addr, + onInvalidRead: (addr, dataWidth) => + LogicValue.filled(dataWidth, LogicValue.zero), + ); + final memRead = DataPortInterface(xlen, xlen); + final memWrite = DataPortInterface(xlen, xlen); + // ignore: unused_local_variable + final mem = MemoryModel( + clk, + reset, + [wrapWriteForRegisterFile(memWrite)], + [wrapReadForRegisterFile(memRead, clk: clk, readLatency: 0)], + readLatency: 0, + storage: storage, + ); + final wbCyc = core.output('dataBus_CYC'); + final wbStb = core.output('dataBus_STB'); + final wbWe = core.output('dataBus_WE'); + memRead.en <= wbCyc & wbStb & ~wbWe; + memRead.addr <= core.output('dataBus_ADR'); + memWrite.en <= wbCyc & wbStb & wbWe; + memWrite.addr <= core.output('dataBus_ADR'); + memWrite.data <= core.output('dataBus_DAT_MOSI'); + final wbAckReg = Logic(name: 'wbAck'); + Sequential(clk, [ + If( + reset, + then: [wbAckReg < 0], + orElse: [ + If( + wbCyc & wbStb & ~wbAckReg & (wbWe | memRead.valid), + then: [wbAckReg < 1], + orElse: [wbAckReg < 0], + ), + ], + ), + ]); + final seedGate = Logic(name: 'seedGate'); + core.input('dataBus_ACK').srcConnection! <= wbAckReg & ~seedGate; + core.input('dataBus_DAT_MISO').srcConnection! <= memRead.data; + + reset.inject(1); + seedGate.inject(0); + Simulator.setMaxSimTime(100000000); + unawaited(Simulator.run()); + await clk.nextPosedge; + + // Program (RV64), reset vector 0: + // 0: auipc ra, 0x0 ra = 0 0x00000097 + // 4: jalr ra, 16(ra) tgt=0x10, ra=0x8 0x010080e7 + // 8: addi x5, x0, 0xAA SENTINEL (return) 0x0aa00293 + // c: nop (halt here) 0x00000013 + // 10: addi x6, x0, 0xBB subroutine body 0x0bb00313 + // 14: c.ret (c.jr ra) -> ra = 0x8 0x8082 (+ c.nop pad) + // Program (RV64), reset vector 0. Exercises c.ld (register-relative, + // PRIME registers x8-x15, cldsd imm) which c.ldsp does not cover. + // 0: addi s0, x0, 0x300 s0(x8)=0x300 0x30000413 + // 4: addi s2, x0, 0x55 s2(x18)=0x55 0x05500913 + // 8: sd s2, 16(s0) mem[0x310]=0x55 0x01243823 + // c: c.ld s1, 16(s0) s1(x9)=mem[0x310] 0x6804 (+ c.nop pad) + // 10: j . (halt) 0x0000006f + final program = [ + 0x30000413, + 0x05500913, + 0x01243823, + 0x00016804, + 0x0000006f, + ]; + ; + + reset.inject(1); + seedGate.inject(0); + for (var i = 0; i < 4; i++) { + await clk.nextPosedge; + } + final sb = StringBuffer('@0\n'); + for (final w in program) { + for (var b = 0; b < 4; b++) { + sb.write(((w >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + storage.loadMemString('${sb.toString().trimRight()}\n'); + reset.inject(0); + await clk.nextPosedge; + while (reset.value.toBool()) { + await clk.nextPosedge; + } + + const haltPc = 0x10; + var reached = false; + var lastPc = -1; + for (var i = 0; i < 1200; i++) { + await clk.nextPosedge; + final p = core.pipeline.nextPc.value; + lastPc = p.isValid ? p.toInt() : -1; + if (p.isValid && p.toInt() == haltPc) { + reached = true; + break; + } + } + + final s1 = core.regs.getData(LogicValue.ofInt(Register.x9.value, 5)); + final stored = storage.getData(LogicValue.ofInt(0x310, xlen)); + + await Simulator.endSimulation(); + await Simulator.simulationEnded; + + expect(reached, isTrue, reason: 'never reached halt'); + expect(stored?.toInt(), 0x55, reason: 'sd to s0+16 did not land'); + expect( + s1!.toInt(), + 0x55, + reason: 'c.ld s1,16(s0) loaded wrong value (prime reg or imm)', + ); + }, + timeout: Timeout(Duration(minutes: 5)), + ); +} diff --git a/packages/river_hdl/test/rvc_stack_decode_test.dart b/packages/river_hdl/test/rvc_stack_decode_test.dart new file mode 100644 index 0000000..abfd003 --- /dev/null +++ b/packages/river_hdl/test/rvc_stack_decode_test.dart @@ -0,0 +1,172 @@ +import 'dart:async'; + +import 'package:river/river.dart'; +import 'package:rohd/rohd.dart'; +import 'package:rohd_hcl/rohd_hcl.dart' hide DataPortInterface, DataPortGroup; +import 'package:river_hdl/river_hdl.dart'; +import 'package:test/test.dart'; + +/// Regression for the creek (rc1-s) microcode decoder dropping the implicit +/// stack-pointer base and the RVC immediate descramble on compressed stack +/// ops. Before the fix, [DynamicInstructionDecoder] decoded fields purely by +/// instruction format type, so `c.sdsp`/`c.ldsp` (fixedRs1 = sp, immKind = +/// css/ci) came out rs1 = 0, imm = 0 and stored/loaded to address 0. This is +/// the instruction the Weir FSBL prologue hangs on. The OoO path was fine +/// because its StaticInstructionDecoder already applied compReg/immFor. +/// +/// The program sets sp with real auipc+addi, stores ra through `c.sdsp`, then +/// reads it back through `c.ldsp`. Pass requires the store to land at sp+off +/// AND the load to recover it (both the fixed sp base and the scaled imm). +RiverCoreConfig _rv64() => RiverCoreConfigV1.small( + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + hasSupervisorUserMemory: true, + hasMakeExecutableReadable: true, + ), + interrupts: [], + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(12000000), + ), + resetVector: 0, +); + +void main() { + test( + 'c.sdsp/c.ldsp decode fixed sp base + scaled imm (creek microcode)', + () async { + await Simulator.reset(); + final config = _rv64(); + const xlen = 64; + final clk = SimpleClockGenerator(20).clk; + final reset = Logic(name: 'reset'); + final wbConfig = WishboneConfig( + addressWidth: xlen, + dataWidth: xlen, + selWidth: xlen ~/ 8, + ); + final core = RiverCore(config, busConfig: wbConfig); + core.input('clk').srcConnection! <= clk; + core.input('reset').srcConnection! <= reset; + await core.build(); + + final storage = SparseMemoryStorage( + addrWidth: xlen, + dataWidth: xlen, + alignAddress: (addr) => addr, + onInvalidRead: (addr, dataWidth) => + LogicValue.filled(dataWidth, LogicValue.zero), + ); + final memRead = DataPortInterface(xlen, xlen); + final memWrite = DataPortInterface(xlen, xlen); + // ignore: unused_local_variable + final mem = MemoryModel( + clk, + reset, + [wrapWriteForRegisterFile(memWrite)], + [wrapReadForRegisterFile(memRead, clk: clk, readLatency: 0)], + readLatency: 0, + storage: storage, + ); + final wbCyc = core.output('dataBus_CYC'); + final wbStb = core.output('dataBus_STB'); + final wbWe = core.output('dataBus_WE'); + memRead.en <= wbCyc & wbStb & ~wbWe; + memRead.addr <= core.output('dataBus_ADR'); + memWrite.en <= wbCyc & wbStb & wbWe; + memWrite.addr <= core.output('dataBus_ADR'); + memWrite.data <= core.output('dataBus_DAT_MOSI'); + final wbAckReg = Logic(name: 'wbAck'); + Sequential(clk, [ + If( + reset, + then: [wbAckReg < 0], + orElse: [ + If( + wbCyc & wbStb & ~wbAckReg & (wbWe | memRead.valid), + then: [wbAckReg < 1], + orElse: [wbAckReg < 0], + ), + ], + ), + ]); + final seedGate = Logic(name: 'seedGate'); + core.input('dataBus_ACK').srcConnection! <= wbAckReg & ~seedGate; + core.input('dataBus_DAT_MISO').srcConnection! <= memRead.data; + + reset.inject(1); + seedGate.inject(0); + Simulator.setMaxSimTime(100000000); + unawaited(Simulator.run()); + await clk.nextPosedge; + + // Program (RV64), reset vector 0: + // 0: auipc sp, 0x0 sp = 0 0x00000117 + // 4: addi sp, sp, 0x200 sp = 0x200 0x20010113 + // 8: addi ra, x0, 0x42 ra = 0x42 0x04200093 + // c: c.sdsp ra, 8(sp) store @0x208 0xe406 (low half) + // e: c.ldsp x5, 8(sp) x5 = mem[0x208] 0x62a2 (high half) + // 10: nop (halt here) 0x00000013 + final program = [ + 0x00000117, + 0x20010113, + 0x04200093, + 0x62a2e406, // low = c.sdsp ra,8(sp); high = c.ldsp x5,8(sp) + 0x00000013, + ]; + + reset.inject(1); + seedGate.inject(0); + for (var i = 0; i < 4; i++) { + await clk.nextPosedge; + } + final sb = StringBuffer('@0\n'); + for (final w in program) { + for (var b = 0; b < 4; b++) { + sb.write(((w >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + storage.loadMemString('${sb.toString().trimRight()}\n'); + reset.inject(0); + await clk.nextPosedge; + while (reset.value.toBool()) { + await clk.nextPosedge; + } + + const nextPc = 0x10; + var reached = false; + for (var i = 0; i < 2000; i++) { + await clk.nextPosedge; + final p = core.pipeline.nextPc.value; + if (p.isValid && p.toInt() == nextPc) { + reached = true; + break; + } + } + + final stored = storage.getData(LogicValue.ofInt(0x208, xlen)); + final x5 = core.regs.getData(LogicValue.ofInt(Register.x5.value, 5)); + + await Simulator.endSimulation(); + await Simulator.simulationEnded; + + expect(reached, isTrue, reason: 'never reached nextPc=0x10'); + expect(stored, isNotNull, reason: 'c.sdsp store never landed at sp+8'); + expect( + stored!.toInt(), + 0x42, + reason: 'c.sdsp wrote wrong value/address (fixed sp base or imm lost)', + ); + expect( + x5!.toInt(), + 0x42, + reason: 'c.ldsp read back wrong value (fixed sp base or imm lost)', + ); + }, + timeout: Timeout(Duration(minutes: 5)), + ); +} diff --git a/packages/river_hdl/test/sba_wishbone_test.dart b/packages/river_hdl/test/sba_wishbone_test.dart new file mode 100644 index 0000000..c9c035c --- /dev/null +++ b/packages/river_hdl/test/sba_wishbone_test.dart @@ -0,0 +1,114 @@ +import 'dart:async'; + +import 'package:rohd/rohd.dart'; +import 'package:river_hdl/src/core/sba_wishbone.dart'; +import 'package:test/test.dart'; + +/// Drives the adapter's SBA side and models a 64-bit Wishbone memory cell on its +/// master side (sel-masked write, combinational read+ack), checking that +/// sub-word and full-word SBA accesses lane-shift correctly both ways. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + test('SBA word and sub-word accesses lane-shift through Wishbone', () async { + const dw = 64, aw = 64, xlen = 64; + final dut = SbaWishboneAdapter(dataWidth: dw, addressWidth: aw, xlen: xlen); + + final clk = SimpleClockGenerator(10).clk; + final reset = Logic(name: 'reset'); + final sbaReq = Logic(name: 'sba_req'); + final sbaWe = Logic(name: 'sba_we'); + final sbaAddr = Logic(name: 'sba_addr', width: xlen); + final sbaWdata = Logic(name: 'sba_wdata', width: xlen); + final sbaSize = Logic(name: 'sba_size', width: 3); + + dut.input('sba_req').srcConnection! <= sbaReq; + dut.input('sba_we').srcConnection! <= sbaWe; + dut.input('sba_addr').srcConnection! <= sbaAddr; + dut.input('sba_wdata').srcConnection! <= sbaWdata; + dut.input('sba_size').srcConnection! <= sbaSize; + + // 64-bit memory cell. Combinational ACK + read; sel-masked write on edge. + final cell = Logic(name: 'cell', width: dw); + final wbCyc = dut.output('wb_cyc'); + final wbStb = dut.output('wb_stb'); + final wbWe = dut.output('wb_we'); + final wbDatMosi = dut.output('wb_dat_mosi'); + final wbSel = dut.output('wb_sel'); + dut.input('wb_ack').srcConnection! <= (wbCyc & wbStb); + dut.input('wb_dat_miso').srcConnection! <= cell; + + // Per-byte write mask expanded from sel. + final byteMask = []; + for (var i = 0; i < dw ~/ 8; i++) { + byteMask.add(mux(wbSel[i], Const(0xff, width: 8), Const(0, width: 8))); + } + final mask = byteMask.rswizzle(); + Sequential(clk, reset: reset, [ + If( + wbCyc & wbStb & wbWe, + then: [cell < ((cell & ~mask) | (wbDatMosi & mask))], + ), + ]); + + reset.inject(1); + sbaReq.inject(0); + sbaWe.inject(0); + sbaAddr.inject(0); + sbaWdata.inject(0); + sbaSize.inject(0); + + Simulator.setMaxSimTime(100000); + unawaited(Simulator.run()); + await clk.nextPosedge; + reset.inject(0); + await clk.nextPosedge; + + Future wr(int addr, int data, int size) async { + sbaWe.inject(1); + sbaAddr.inject(addr); + sbaWdata.inject(data); + sbaSize.inject(size); + sbaReq.inject(1); + await clk.nextPosedge; + sbaReq.inject(0); + await clk.nextPosedge; + } + + Future rd(int addr, int size) async { + sbaWe.inject(0); + sbaAddr.inject(addr); + sbaSize.inject(size); + sbaReq.inject(1); + // Combinational read; sample after settle. + await clk.nextPosedge; + final v = dut.output('sba_rdata').value.toInt(); + sbaReq.inject(0); + await clk.nextPosedge; + return v; + } + + // 32-bit (size=2) into the low and high lanes of one 64-bit beat. The DM + // takes the access-sized low bytes (sbdata0), so compare masked. + await wr(0x00, 0x11223344, 2); + await wr(0x04, 0xaabbccdd, 2); + expect( + (await rd(0x00, 2)) & 0xffffffff, + equals(0x11223344), + reason: 'low-lane 32-bit readback', + ); + expect( + (await rd(0x04, 2)) & 0xffffffff, + equals(0xaabbccdd), + reason: 'high-lane 32-bit readback (lane shift both ways)', + ); + + // Byte (size=0) into byte 5. + await wr(0x05, 0x9a, 0); + expect((await rd(0x05, 0)) & 0xff, equals(0x9a), reason: 'byte lane 5'); + + await Simulator.endSimulation(); + }); +} diff --git a/packages/river_hdl/test/scalar/core_bitmanip_test.dart b/packages/river_hdl/test/scalar/core_bitmanip_test.dart new file mode 100644 index 0000000..48ace32 --- /dev/null +++ b/packages/river_hdl/test/scalar/core_bitmanip_test.dart @@ -0,0 +1,372 @@ +import 'package:rohd/rohd.dart'; +import 'package:river/river.dart'; +import 'package:test/test.dart'; +import '../core_harness.dart'; + +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + // Bit-manipulation (Zba/Zbb/Zbs) plus M/A and the Zcb compressed bit-manip on + // the in-order RV64 ALU. The config is composed in-test from exactly the + // extensions these cases exercise (the old shared smallB tier was dropped from + // the RC1 lineup). + group('in-order RV64 IMAC + Zba/Zbb/Zbs + Zcb', () { + final config = RiverCoreConfig( + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + mxlen: RiscVMxlen.rv64, + extensions: [ + rv64i, + rv32i, + rvZicsr, + rvZifencei, + rvM, + rvA, + rvC, + rvZba, + rvZbb, + rvZbs, + rvZcb, + ], + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + executionMode: ExecutionMode.inOrder, + ); + + int r(int f7, int rs2, int rs1, int f3, int rd) => + (f7 << 25) | (rs2 << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x33; + int iimm(int imm, int rs1, int f3, int rd) => + (imm << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x13; + int s(int imm, int rs2, int rs1, int f3) => + (((imm >> 5) & 0x7F) << 25) | + (rs2 << 20) | + (rs1 << 15) | + (f3 << 12) | + ((imm & 0x1F) << 7) | + 0x23; + int amo(int funct7, int rs2, int rs1, int f3, int rd) => + (funct7 << 25) | + (rs2 << 20) | + (rs1 << 15) | + (f3 << 12) | + (rd << 7) | + 0x2F; + String prog(List words) { + final sb = StringBuffer('@0\n'); + for (final w in words) { + for (var b = 0; b < 4; b++) { + sb.write(((w >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + return '$sb\n'; + } + + test( + 'max/minu/andn/sh1add/rol/clz/cpop/rev8/orcb/bset', + timeout: Timeout(Duration(seconds: 300)), + () => coreTest( + prog([ + iimm(16, 0, 0x0, 1), // addi x1, x0, 16 + iimm(3, 0, 0x0, 2), // addi x2, x0, 3 + r(0x05, 2, 1, 0x6, 5), // max x5, x1, x2 -> 16 + r(0x05, 2, 1, 0x5, 6), // minu x6, x1, x2 -> 3 + r(0x20, 2, 1, 0x7, 7), // andn x7, x1, x2 -> 16 + r(0x10, 1, 2, 0x2, 8), // sh1add x8, x2, x1 -> (3<<1)+16 = 22 + r(0x30, 2, 1, 0x1, 9), // rol x9, x1, x2 -> 128 + iimm(0x600, 2, 0x1, 10), // clz x10, x2 -> 62 + iimm(0x602, 1, 0x1, 11), // cpop x11, x1 -> 1 + iimm(0x6B8, 1, 0x5, 12), // rev8 x12, x1 -> 0x1000000000000000 + iimm(0x287, 1, 0x5, 13), // orc.b x13, x1 -> 0xFF + r(0x14, 2, 0, 0x1, 14), // bset x14, x0, x2 -> 8 + 0x00000013, // nop (halt target) + ]), + { + Register.x5: 16, + Register.x6: 3, + Register.x7: 16, + Register.x8: 22, + Register.x9: 128, + Register.x10: 62, + Register.x11: 1, + Register.x12: 0x1000000000000000, + Register.x13: 0xFF, + Register.x14: 8, + }, + config, + nextPc: 0x30, + ), + ); + + test( + 'AMO: amoadd.w / amoor.w (read-modify-write)', + timeout: Timeout(Duration(seconds: 300)), + () => coreTest( + prog([ + iimm(0x200, 0, 0x0, 7), // addi x7, x0, 0x200 (addr A) + iimm(5, 0, 0x0, 6), // addi x6, x0, 5 + iimm(10, 0, 0x0, 8), // addi x8, x0, 10 + s(0, 8, 7, 0x2), // sw x8, 0(x7) -> mem[0x200] = 10 + amo(0x00, 6, 7, 0x2, 5), // amoadd.w x5, x6, (x7) -> x5=10, mem=15 + iimm(0x210, 0, 0x0, 11), // addi x11, x0, 0x210 (addr B) + iimm(0xF0, 0, 0x0, 10), // addi x10, x0, 0xF0 + iimm(0x0F, 0, 0x0, 12), // addi x12, x0, 0x0F + s(0, 12, 11, 0x2), // sw x12, 0(x11) -> mem[0x210] = 0x0F + amo( + 0x20, + 10, + 11, + 0x2, + 9, + ), // amoor.w x9, x10, (x11) -> x9=0x0F, mem=0xFF + 0x00000013, // nop (halt target) + ]), + {Register.x5: 10, Register.x9: 0x0F}, + config, + nextPc: 0x28, + memStates: {0x200: 15, 0x210: 0xFF}, + ), + ); + + test( + 'LR/SC: lr.w sets reservation, first sc.w succeeds, second fails', + timeout: Timeout(Duration(seconds: 300)), + () => coreTest( + prog([ + iimm(0x300, 0, 0x0, 7), // addi x7, x0, 0x300 (addr) + iimm(42, 0, 0x0, 10), // addi x10, x0, 42 + s(0, 10, 7, 0x2), // sw x10, 0(x7) -> mem[0x300] = 42 + iimm(99, 0, 0x0, 6), // addi x6, x0, 99 + amo(0x08, 0, 7, 0x2, 5), // lr.w x5, (x7) -> x5=42, reserve 0x300 + amo(0x0C, 6, 7, 0x2, 8), // sc.w x8, x6, (x7) -> store 99, x8=0 (ok) + amo(0x0C, 6, 7, 0x2, 9), // sc.w x9, x6, (x7) -> x9=1 (no reservation) + 0x00000013, // nop (halt target) + ]), + {Register.x5: 42, Register.x8: 0, Register.x9: 1}, + config, + nextPc: 0x1C, + memStates: {0x300: 99}, + ), + ); + + test( + 'signed slt + mulh* high-half (x1=-5, x2=3)', + timeout: Timeout(Duration(seconds: 300)), + () => coreTest( + prog([ + iimm(0xFFB, 0, 0x0, 1), // addi x1, x0, -5 + iimm(3, 0, 0x0, 2), // addi x2, x0, 3 + r(0x00, 2, 1, 0x2, 5), // slt x5, x1, x2 -> 1 (signed -5 < 3) + r(0x00, 2, 1, 0x3, 6), // sltu x6, x1, x2 -> 0 (unsigned) + r(0x01, 2, 1, 0x0, 7), // mul x7, x1, x2 -> -15 + r(0x01, 2, 1, 0x1, 8), // mulh x8, x1, x2 -> -1 + r(0x01, 2, 1, 0x3, 9), // mulhu x9, x1, x2 -> 2 + r(0x01, 2, 1, 0x2, 10), // mulhsu x10, x1, x2 -> -1 + 0x00000013, // nop (halt target) + ]), + { + Register.x5: 1, + Register.x6: 0, + Register.x7: -15, + Register.x8: -1, + Register.x9: 2, + Register.x10: -1, + }, + config, + nextPc: 0x20, + ), + ); + + test( + 'signed div/rem + divide-by-zero (x1=-7, x2=2)', + timeout: Timeout(Duration(seconds: 300)), + () => coreTest( + prog([ + iimm(0xFF9, 0, 0x0, 1), // addi x1, x0, -7 + iimm(2, 0, 0x0, 2), // addi x2, x0, 2 + r(0x01, 2, 1, 0x4, 5), // div x5, x1, x2 -> -3 (trunc toward zero) + r(0x01, 2, 1, 0x6, 6), // rem x6, x1, x2 -> -1 (sign of dividend) + r(0x01, 0, 1, 0x4, 7), // div x7, x1, x0 -> -1 (div by zero) + r( + 0x01, + 0, + 1, + 0x6, + 8, + ), // rem x8, x1, x0 -> -7 (rem by zero = dividend) + r(0x01, 1, 2, 0x5, 9), // divu x9, x2, x1 -> 0 (2 < huge unsigned) + 0x00000013, // nop (halt target) + ]), + { + Register.x5: -3, + Register.x6: -1, + Register.x7: -1, + Register.x8: -7, + Register.x9: 0, + }, + config, + nextPc: 0x1C, + ), + ); + + // Zcb compressed bit-manip: c.zext.b x8 (16-bit, 0x9C61) zero-extends the + // low byte of x8 (prime reg). x8 = 0x1F0 -> 0xF0. Program mixes the 2-byte + // compressed op with 32-bit setup/store. + // 0x0: c.zext.b x8 (61 9C) + // 0x2: addi x10,x0,0x200 (13 05 00 20) + // 0x6: sw x8, 0(x10) (23 20 85 00) + // 0xA: nop (13 00 00 00) + test( + 'c.zext.b (Zcb compressed)', + timeout: Timeout(Duration(seconds: 300)), + () => coreTest( + '@0\n61 9c 13 05 00 20 23 20 85 00 13 00 00 00\n', + {Register.x8: 0xF0}, + config, + initRegisters: {Register.x8: 0x1F0}, + nextPc: 0xA, + memStates: {0x200: 0xF0}, + ), + ); + + // c.mul (overlaps the unary CA ops, no matchMask) + c.not, prime regs. + // addi x8,x0,7 (13 04 70 00) + // addi x9,x0,6 (93 04 60 00) + // c.mul x8,x9 (45 9C) -> x8 = 42 + // c.not x9 (f5 9C) -> x9 = ~6 = -7 + // nop (13 00 00 00) + test( + 'c.mul / c.not (Zcb compressed)', + timeout: Timeout(Duration(seconds: 300)), + () => coreTest( + '@0\n13 04 70 00 93 04 60 00 45 9c f5 9c 13 00 00 00\n', + {Register.x8: 42, Register.x9: -7}, + config, + nextPc: 0xC, + ), + ); + + // Isolation: 32-bit sext.b x8,x8 (0x60441413) to tell ALU-vs-decode apart + // from the compressed c.sext.b. x8=0x80 -> -128. + test( + '32-bit sext.b (ALU isolation)', + timeout: Timeout(Duration(seconds: 300)), + () => coreTest( + '@0\n13 14 44 60 13 00 00 00\n', + {Register.x8: -128}, + config, + initRegisters: {Register.x8: 0x80}, + nextPc: 0x4, + ), + ); + + // Zcb unary extends (CU format, funct6=100111): c.sext.b/zext.h/sext.h/ + // zext.w on prime regs x8-x11. Regs seeded so each extend is observable. + // c.sext.b x8 (65 9c): 0x80 -> -128 (sign byte) + // c.zext.h x9 (e9 9c): 0x12345 -> 0x2345 + // c.sext.h x10 (6d 9d): 0x8765 -> -30875 (sign halfword) + // c.zext.w x11 (f1 9d): 0x1_8000_0000 -> 0x8000_0000 + test( + 'c.sext.b / c.zext.h / c.sext.h / c.zext.w (Zcb extends)', + timeout: Timeout(Duration(seconds: 300)), + () => coreTest( + '@0\n65 9c e9 9c 6d 9d f1 9d 13 00 00 00\n', + { + Register.x8: -128, + Register.x9: 0x2345, + Register.x10: -30875, + Register.x11: 0x80000000, + }, + config, + initRegisters: { + Register.x8: 0x80, + Register.x9: 0x12345, + Register.x10: 0x8765, + Register.x11: 0x180000000, + }, + nextPc: 0x8, + ), + ); + + // Sub-word load lane selection: lbu reads the addressed byte regardless of + // the low address bits (the load shifts the bus word by the byte offset). + // mem[0x200..0x203] = [0x11,0x22,0xab,0x44]; lbu @2 -> 0xab, @0 -> 0x11. + // (This also underpins the Zcb compressed c.lbu/c.lhu/c.lh.) + test( + 'lbu sub-word lane select (offset 2 and 0)', + timeout: Timeout(Duration(seconds: 300)), + () => coreTest( + // addi x9,x0,0x200 ; lbu x10,2(x9) (0024C503) ; lbu x11,0(x9) (0004C583) + '@0\n93 04 00 20 03 c5 24 00 83 c5 04 00 13 00 00 00\n' + '@200\n11 22 ab 44\n', + {Register.x10: 0xAB, Register.x11: 0x11}, + config, + nextPc: 0x10, + ), + ); + + // Zcb compressed byte store + load round-trip (c.sb then c.lbu), prime regs. + // addi x8,x0,0x200 (base) ; addi x9,x0,0xCD (value) ; + // c.sb x9,0(x8) (04 88) ; c.lbu x10,0(x8) (08 80) ; c.nop (01 00) + // mem[0x200] byte <- 0xCD ; x10 <- 0xCD. + test( + 'c.sb / c.lbu byte store-load round-trip (Zcb)', + timeout: Timeout(Duration(seconds: 300)), + () => coreTest( + '@0\n13 04 00 20 93 04 d0 0c 04 88 08 80 01 00\n', + {Register.x10: 0xCD}, + config, + nextPc: 0xC, + memStates: {0x200: 0xCD}, + ), + ); + + // Zcb compressed half store + SIGNED load (c.sh then c.lh). x9=0x8ABC has + // bit15 set so the signed/unsigned distinction is observable, but its upper + // bits are 0 so it dodges two PRE-EXISTING, non-Zcb in-order core bugs that + // values like -16 would trip (documented, fixes deferred): + // * sub-word stores write the full register width to memory (upper bytes + // leak) - so we check only the loaded register, not memStates here. + // * an unsigned load after a store + a signed load reads `unsigned` stale + // and sign-extends (project_inorder_load_unsigned_stale) - so the signed + // and unsigned cases are split into separate 2-op programs. + // c.sh x9,0(x8) (04 8c) ; c.lh x10,0(x8) (48 84) ; c.nop + // c.lh sign-extends 0x8ABC (bit15 set) to 0xFFFF_FFFF_FFFF_8ABC. + test( + 'c.sh / c.lh half store + signed load (Zcb)', + timeout: Timeout(Duration(seconds: 300)), + () => coreTest( + '@0\n04 8c 48 84 01 00\n', + {Register.x10: -30020}, // 0xFFFFFFFFFFFF8ABC (0x8ABC sign-extended) + config, + initRegisters: {Register.x8: 0x300, Register.x9: 0x8ABC}, + nextPc: 0x4, + ), + ); + + // Zcb compressed half store + UNSIGNED load (c.sh then c.lhu). + // c.sh x9,0(x8) (04 8c) ; c.lhu x10,0(x8) (08 84) ; c.nop + // c.lhu zero-extends 0x8ABC to 0x8ABC. + test( + 'c.sh / c.lhu half store + unsigned load (Zcb)', + timeout: Timeout(Duration(seconds: 300)), + () => coreTest( + '@0\n04 8c 08 84 01 00\n', + {Register.x10: 0x8ABC}, + config, + initRegisters: {Register.x8: 0x300, Register.x9: 0x8ABC}, + nextPc: 0x4, + ), + ); + }); +} diff --git a/packages/river_hdl/test/scalar/core_shift_test.dart b/packages/river_hdl/test/scalar/core_shift_test.dart new file mode 100644 index 0000000..197cff4 --- /dev/null +++ b/packages/river_hdl/test/scalar/core_shift_test.dart @@ -0,0 +1,41 @@ +import 'package:rohd/rohd.dart'; +import 'package:river/river.dart'; +import 'package:test/test.dart'; +import '../core_harness.dart'; + +/// RV64 shift-immediates with shamt >= 32 (6-bit shamt). These previously hung +/// the in-order decoder because slli/srli/srai matched the full 7-bit funct7 +/// (bit 25 = shamt[5]); the decoder now matches funct6 for OP-IMM shifts. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + final config = RiverCoreConfigV1.small( + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + interrupts: [], + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + ); + + // addi x2,x0,1 ; slli x1,x2,39 (->1<<39) ; srai x3,x1,33 (->(1<<39)>>33=0x40) ; nop + test( + 'slli/srai with shamt>=32', + timeout: Timeout(Duration(seconds: 120)), + () { + return coreTest( + '@0\n13 01 10 00 93 10 71 02 93 d1 10 42 13 00 00 00\n', + {Register.x1: 0x8000000000, Register.x3: 0x40}, + config, + nextPc: 0x10, + ); + }, + ); +} diff --git a/packages/river_hdl/test/scalar/core_test.dart b/packages/river_hdl/test/scalar/core_test.dart new file mode 100644 index 0000000..12bcff0 --- /dev/null +++ b/packages/river_hdl/test/scalar/core_test.dart @@ -0,0 +1,108 @@ +import 'package:rohd/rohd.dart'; +import 'package:river/river.dart'; +import 'package:test/test.dart'; +import '../core_harness.dart'; +import '../constants.dart'; + +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + cpuTests('RV32I', condition: (c) => c.mxlen == RiscVMxlen.rv32, (config) { + test( + 'Small program', + timeout: Timeout(Duration(seconds: 30)), + () => coreTest( + '''@${config.resetVector.toRadixString(16)} +93 00 80 3E 13 81 00 7D 93 01 81 C1 13 82 01 83 +93 02 82 3E 13 00 00 00 +''', + { + Register.x1: 0x3E8, + Register.x2: 0xBB8, + Register.x3: 0x7D0, + Register.x4: 0, + Register.x5: 0x3E8, + }, + config, + nextPc: 0x18, + ), + ); + test( + 'lw loads from memory', + timeout: Timeout(Duration(seconds: 30)), + () => coreTest( + // addi x10, x0, 0x100 (base addr) + // lw x5, 0(x10) (load word from 0x100) + // nop + '''@${config.resetVector.toRadixString(16)} +13 05 00 10 83 22 05 00 13 00 00 00 +@100 +ef be ad de +''', + {Register.x5: 0xDEADBEEF, Register.x10: 0x100}, + config, + nextPc: 0x0C, + ), + ); + + test( + 'sw stores to memory', + timeout: Timeout(Duration(seconds: 30)), + () => coreTest( + // addi x10, x0, 0x200 (base addr) + // addi x5, x0, 42 (value) + // sw x5, 0(x10) (store word) + // nop + '''@${config.resetVector.toRadixString(16)} +13 05 00 20 93 02 a0 02 23 20 55 00 13 00 00 00 +''', + {Register.x10: 0x200, Register.x5: 42}, + config, + nextPc: 0x10, + memStates: {0x200: 42}, + ), + ); + + // Variable-latency robustness: the in-order pipeline's load handshake must + // wait for memRead.done however many cycles the memory takes. The + // emulator/fetcher tests cover fetch latency; these exercise the dport. + // Multi-cycle memory (single-cycle SRAM through DRAM-ish latencies). Higher + // latencies are correct too but make the full-core sim too slow to be worth + // running here; fetcher_test covers the high-latency extreme on the fetch + // port directly. + const memLatencies = [1, 4, 12]; + for (final lat in memLatencies) { + test( + 'lw with memLatency=$lat', + timeout: Timeout(Duration(seconds: lat ~/ 10 + 30)), + () => coreTest( + '''@${config.resetVector.toRadixString(16)} +13 05 00 10 83 22 05 00 13 00 00 00 +@100 +ef be ad de +''', + {Register.x5: 0xDEADBEEF, Register.x10: 0x100}, + config, + nextPc: 0x0C, + memLatency: lat, + ), + ); + test( + 'sw with memLatency=$lat', + timeout: Timeout(Duration(seconds: lat ~/ 10 + 30)), + () => coreTest( + '''@${config.resetVector.toRadixString(16)} +13 05 00 20 93 02 a0 02 23 20 55 00 13 00 00 00 +''', + {Register.x10: 0x200, Register.x5: 42}, + config, + nextPc: 0x10, + memStates: {0x200: 42}, + memLatency: lat, + ), + ); + } + }); +} diff --git a/packages/river_hdl/test/superscalar/core_dual_compressed_test.dart b/packages/river_hdl/test/superscalar/core_dual_compressed_test.dart new file mode 100644 index 0000000..0b8bb90 --- /dev/null +++ b/packages/river_hdl/test/superscalar/core_dual_compressed_test.dart @@ -0,0 +1,130 @@ +import 'package:river/river.dart'; +import 'package:rohd/rohd.dart'; +import 'package:test/test.dart'; + +import '../core_harness.dart'; + +/// RV64GC dual-issue: variable-length (compressed) instructions co-dispatch two +/// per cycle through the CompressedFetchBuffer + aligner, decode as RVC, and +/// execute out-of-order. This is the macro (RC1.ma) superscalar path. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + // The actual shipped RC1.ma macro config (RV64GC + bit-manip, OoO dual). Using + // the factory here doubles as a build+run smoke for the macro tier. + RiverCoreConfig dualCConfig() => RiverCoreConfigV1.macro( + clock: HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ), + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + ); + + // RVC encodings (quadrant 1/2 forms used here). + int cli(int rd, int imm) => + 0x4000 | (((imm >> 5) & 1) << 12) | (rd << 7) | ((imm & 0x1f) << 2) | 1; + int cmv(int rd, int rs2) => 0x8000 | (rd << 7) | (rs2 << 2) | 2; + int cadd(int rd, int rs2) => 0x9000 | (rd << 7) | (rs2 << 2) | 2; + int caddi(int rd, int imm) => + (((imm >> 5) & 1) << 12) | (rd << 7) | ((imm & 0x1f) << 2) | 1; + int cslli(int rd, int sh) => (rd << 7) | ((sh & 0x1f) << 2) | 2; + + /// Lay a (value,byteLen) instruction stream into a mem string, padding with a + /// 32-bit-nop tail. Returns (memString, firstNopPc). + (String, int) lay(List<(int, int)> instrs, {int nopTail = 16}) { + final bytes = []; + for (final (v, len) in instrs) { + for (var b = 0; b < len; b++) { + bytes.add((v >> (8 * b)) & 0xFF); + } + } + final firstNopPc = bytes.length; + for (var i = 0; i < nopTail; i++) { + for (final b in [0x13, 0x00, 0x00, 0x00]) { + bytes.add(b); + } + } + final sb = StringBuffer('@0\n'); + for (final b in bytes) { + sb.write(b.toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + return ('$sb\n', firstNopPc); + } + + test('dual: independent compressed c.li pairs retire', () { + final (mem, nopPc) = lay([ + for (var k = 8; k <= 15; k++) (cli(k, k - 7), 2), + ]); + return coreTest( + mem, + {for (var k = 8; k <= 15; k++) Register.values[k]: k - 7}, + dualCConfig(), + // A few nops into the tail (a PC the dual-commit core lands on, before it + // could run off the end). nopPc is the first nop; +8 = 2 nops in. + nextPc: nopPc + 8, + ); + }); + + test('dual: compressed arithmetic with intra-bundle hazards', () { + // x8=5; x9=3; x10=0; x10=x8(5); x10+=x9(8); x8+=4(9); x9<<=1(6); fills. + final (mem, nopPc) = lay([ + (cli(8, 5), 2), + (cli(9, 3), 2), + (cli(10, 0), 2), + (cmv(10, 8), 2), + (cadd(10, 9), 2), + (caddi(8, 4), 2), + (cslli(9, 1), 2), + (cli(11, 4), 2), + (cli(12, 5), 2), + (cli(13, 6), 2), + (cli(14, 7), 2), + (cli(15, 8), 2), + ]); + return coreTest( + mem, + { + Register.x8: 9, + Register.x9: 6, + Register.x10: 8, + Register.x11: 4, + Register.x12: 5, + Register.x13: 6, + Register.x14: 7, + Register.x15: 8, + }, + dualCConfig(), + nextPc: nopPc + 8, + ); + }); + + test('dual: mixed compressed + 32-bit stream', () { + int addi(int rd, int rs1, int imm) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (rd << 7) | 0x13; + final (mem, nopPc) = lay([ + (cli(8, 1), 2), + (addi(9, 0, 2), 4), + (cli(10, 3), 2), + (cli(11, 4), 2), + (addi(12, 0, 5), 4), + (cli(13, 6), 2), + (addi(14, 0, 7), 4), + (cli(15, 8), 2), + ]); + return coreTest( + mem, + {for (var k = 8; k <= 15; k++) Register.values[k]: k - 7}, + dualCConfig(), + nextPc: nopPc + 8, + ); + }); +} diff --git a/packages/river_hdl/test/superscalar/core_dual_test.dart b/packages/river_hdl/test/superscalar/core_dual_test.dart new file mode 100644 index 0000000..96636ed --- /dev/null +++ b/packages/river_hdl/test/superscalar/core_dual_test.dart @@ -0,0 +1,221 @@ +import 'package:river/river.dart'; +import 'package:rohd/rohd.dart'; +import 'package:test/test.dart'; + +import '../core_harness.dart'; + +/// Dual-dispatch bring-up: two instructions rename/allocate per cycle. Uses the +/// speculative front-end + PRF operand datapath; gated by issueWidth==dual. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + RiverCoreConfig dualConfig() => RiverCoreConfig( + clock: HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ), + mxlen: RiscVMxlen.rv32, + extensions: [rv32i, rvZicsr, rvZifencei, rvM], + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv32, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + executionMode: ExecutionMode.outOfOrder, + speculativeFetch: true, + issueWidth: IssueWidth.dual, + ); + + // Like dualConfig but with the icache + back-edge prediction, so a loop runs + // speculatively (no per-iteration flush) and many bundles are in flight at + // once, the condition under which ALU1 and the branch/CSR unit complete the + // same cycle. With a shared wakeup port that collision dropped a wakeup and + // deadlocked; the dedicated 3rd wakeup port fixes it. + RiverCoreConfig dualSpecConfig() => RiverCoreConfig( + clock: HarborClockConfig( + name: 'sysclk', + rate: HarborFixedClockRate(48000000), + ), + mxlen: RiscVMxlen.rv32, + extensions: [rv32i, rvZicsr, rvZifencei, rvM], + interrupts: [], + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv32, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + type: RiverCoreType.general, + executionMode: ExecutionMode.outOfOrder, + speculativeFetch: true, + issueWidth: IssueWidth.dual, + l1cache: HarborL1CacheConfig.split( + iSize: 32, + dSize: 64, + ways: 1, + lineSize: 4, + ), + branchPredictor: BranchPredictor.btfn, + ); + + int iimm(int imm, int rs1, int f3, int rd) => + (imm << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x13; + int r(int f7, int rs2, int rs1, int f3, int rd) => + (f7 << 25) | (rs2 << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x33; + int b(int imm, int rs2, int rs1, int f3) => + (((imm >> 12) & 0x1) << 31) | + (((imm >> 5) & 0x3F) << 25) | + (rs2 << 20) | + (rs1 << 15) | + (f3 << 12) | + (((imm >> 1) & 0xF) << 8) | + (((imm >> 11) & 0x1) << 7) | + 0x63; + String prog(List words) { + final sb = StringBuffer('@0\n'); + for (final w in words) { + for (var b = 0; b < 4; b++) { + sb.write(((w >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + return '$sb\n'; + } + + // M2: four mutually independent adds. Each consecutive pair should + // co-dispatch (slot 0 + slot 1) and retire. Verifies the 2-wide + // fetch→decode→rename→ROB/IQ→dual-commit path end to end. + test( + 'dual-dispatch retires independent ALU pairs', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + iimm(0x111, 0, 0x0, 1), // addi x1, x0, 0x111 + iimm(0x222, 0, 0x0, 2), // addi x2, x0, 0x222 + iimm(0x333, 0, 0x0, 3), // addi x3, x0, 0x333 + iimm(0x444, 0, 0x0, 4), // addi x4, x0, 0x444 + ...List.filled(8, 0x00000013), // nop tail + ]), + { + Register.x1: 0x111, + Register.x2: 0x222, + Register.x3: 0x333, + Register.x4: 0x444, + }, + dualConfig(), + nextPc: 0x2C, + ), + ); + + // M3: intra-bundle RAW, slot 1 depends on slot 0. Rename redirects slot1's + // source to slot0's pdst and the PRF/wakeup forwards the value. + test( + 'dual-dispatch handles intra-bundle RAW (slot1 ← slot0)', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + iimm(0x10, 0, 0x0, 1), // addi x1, x0, 0x10 + iimm(0x20, 1, 0x0, 2), // addi x2, x1, 0x20 -> 0x30 + ...List.filled(8, 0x00000013), // nop tail + ]), + {Register.x1: 0x10, Register.x2: 0x30}, + dualConfig(), + nextPc: 0x28, + ), + ); + + // M4: dual-dispatch mixed with a taken branch. The branch must dispatch in + // slot 0 alone (eligibility forbids co-dispatching past a control transfer), + // redirect correctly, and the surrounding independent adds still pair up. + test( + 'dual-dispatch with a taken branch (eligibility + redirect)', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + iimm(5, 0, 0x0, 1), // 0x00 addi x1, x0, 5 + iimm(5, 0, 0x0, 2), // 0x04 addi x2, x0, 5 + b(8, 2, 1, 0x0), // 0x08 beq x1, x2, +8 -> taken, skip 0x0C + iimm(99, 0, 0x0, 5), // 0x0C addi x5, x0, 99 (SKIPPED) + iimm(7, 0, 0x0, 3), // 0x10 addi x3, x0, 7 (target) + iimm(8, 0, 0x0, 4), // 0x14 addi x4, x0, 8 + ...List.filled(8, 0x00000013), // nop tail + ]), + { + Register.x1: 5, + Register.x2: 5, + Register.x3: 7, + Register.x4: 8, + Register.x5: 0, // skipped by the branch + }, + dualConfig(), + nextPc: 0x38, + ), + ); + + // M5: dual-dispatch + dual-commit together. A multi-cycle mul stalls at the + // ROB head while independent adds behind it dual-dispatch and queue; when the + // mul retires they retire alongside it. Exercises both 2-wide lanes + the + // multi-cycle ALU + slot-1 commit. + test( + 'dual-dispatch retires a backlog behind a multi-cycle mul', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + iimm(6, 0, 0x0, 1), // addi x1, x0, 6 + iimm(7, 0, 0x0, 2), // addi x2, x0, 7 + r(0x01, 2, 1, 0x0, 3), // mul x3, x1, x2 -> 42 + iimm(1, 1, 0x0, 4), // addi x4, x1, 1 -> 7 + iimm(2, 1, 0x0, 5), // addi x5, x1, 2 -> 8 + iimm(3, 1, 0x0, 6), // addi x6, x1, 3 -> 9 + iimm(4, 1, 0x0, 7), // addi x7, x1, 4 -> 10 + ...List.filled(8, 0x00000013), // nop tail + ]), + { + Register.x1: 6, + Register.x2: 7, + Register.x3: 42, + Register.x4: 7, + Register.x5: 8, + Register.x6: 9, + Register.x7: 10, + }, + dualConfig(), + nextPc: 0x3C, + ), + ); + + // M6: long independent loop body (16 adds) run speculatively with the icache + + // back-edge prediction. Regression guard for the wakeup-port collision that + // deadlocked dual-dispatch on long bodies, without the dedicated 3rd wakeup + // port this never reaches nextPc (hangs at the 5000-cycle cap). x20 counts the + // iterations down to 0; each iteration rewrites x1..x16 to their constants. + test( + 'dual-dispatch long body (16 adds) does not deadlock', + timeout: Timeout(Duration(seconds: 120)), + () => coreTest( + prog([ + iimm(3, 0, 0x0, 20), // 0x00 addi x20, x0, 3 (iteration count) + for (var k = 1; k <= 16; k++) + iimm(k, 0, 0x0, k), // 0x04..0x40 addi xk, x0, k + iimm(-1, 20, 0x0, 20), // 0x44 addi x20, x20, -1 + b(-68, 0, 20, 0x1), // 0x48 bne x20, x0, -68 -> back to 0x04 + ...List.filled(10, 0x00000013), // nop tail + ]), + {for (var k = 1; k <= 16; k++) Register.values[k]: k, Register.x20: 0}, + dualSpecConfig(), + // A few nops past the loop exit (0x4C). The completion sentinel must be a + // PC the dual-commit core actually lands on: when two instructions retire + // together, nextPc skips the second's PC. After the loop-exit flush the + // buffer resumes single-issue for one instruction, so the nop pairing is + // 0x4c, then (0x50,0x54), (0x58,0x5c)... nextPc hits 0x50 and 0x58 but + // not 0x54. 0x58 is a stable landing point in the nop tail. (Register + // checks below are the real correctness assertion.) + nextPc: 0x58, + ), + ); +} diff --git a/packages/river_hdl/test/superscalar/core_ooo_common.dart b/packages/river_hdl/test/superscalar/core_ooo_common.dart new file mode 100644 index 0000000..6c94a55 --- /dev/null +++ b/packages/river_hdl/test/superscalar/core_ooo_common.dart @@ -0,0 +1,121 @@ +import 'package:river/river.dart'; + +/// Shared instruction encoders and OoO config builders for the core_ooo_* +/// test files. Split out of core_ooo_test.dart so each test file stays well +/// under the per-file timeout (each test builds a fresh HDL core, ~30-40s). + +// ── instruction encoders ── +int r(int f7, int rs2, int rs1, int f3, int rd) => + (f7 << 25) | (rs2 << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x33; +int iimm(int imm, int rs1, int f3, int rd) => + (imm << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x13; +int s(int imm, int rs2, int rs1, int f3, int op) => + (((imm >> 5) & 0x7F) << 25) | + (rs2 << 20) | + (rs1 << 15) | + (f3 << 12) | + ((imm & 0x1F) << 7) | + op; +int lw(int imm, int rs1, int rd) => + (imm << 20) | (rs1 << 15) | (0x2 << 12) | (rd << 7) | 0x03; +// B-type (branch). imm is the byte offset from the branch PC. +int b(int imm, int rs2, int rs1, int f3) => + (((imm >> 12) & 0x1) << 31) | + (((imm >> 5) & 0x3F) << 25) | + (rs2 << 20) | + (rs1 << 15) | + (f3 << 12) | + (((imm >> 1) & 0xF) << 8) | + (((imm >> 11) & 0x1) << 7) | + 0x63; +// CSR instruction (SYSTEM opcode 0x73). csr=addr, rs1/uimm, funct3=op. +int csr(int addr, int rs1, int f3, int rd) => + (addr << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x73; +// J-type (JAL). imm is the byte offset from the jump PC. +int jal(int imm, int rd) => + (((imm >> 20) & 0x1) << 31) | + (((imm >> 1) & 0x3FF) << 21) | + (((imm >> 11) & 0x1) << 20) | + (((imm >> 12) & 0xFF) << 12) | + (rd << 7) | + 0x6F; +// I-type JALR (funct3=0, opcode 0x67): target = rs1 + imm, link = pc + 4. +int jalr(int imm, int rs1, int rd) => + (imm << 20) | (rs1 << 15) | (0x0 << 12) | (rd << 7) | 0x67; + +String prog(List words) { + final sb = StringBuffer('@0\n'); + for (final w in words) { + for (var b = 0; b < 4; b++) { + sb.write(((w >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + return '$sb\n'; +} + +HarborMmuConfig _bareMmu() => HarborMmuConfig( + mxlen: RiscVMxlen.rv32, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, +); + +HarborClockConfig _clk() => + HarborClockConfig(name: 'sysclk', rate: HarborFixedClockRate(48000000)); + +// ── config builders ── +RiverCoreConfig oooConfig() => RiverCoreConfig( + clock: _clk(), + mxlen: RiscVMxlen.rv32, + extensions: [rv32i, rvZicsr, rvZifencei], + interrupts: [], + mmu: _bareMmu(), + type: RiverCoreType.general, + executionMode: ExecutionMode.outOfOrder, +); + +RiverCoreConfig oooBConfig() => RiverCoreConfig( + clock: _clk(), + mxlen: RiscVMxlen.rv32, + extensions: [rv32i, rvZicsr, rvZifencei, rvM, rvZba, rvZbb, rvZbs, rvZicond], + interrupts: [], + mmu: _bareMmu(), + type: RiverCoreType.general, + executionMode: ExecutionMode.outOfOrder, +); + +RiverCoreConfig oooDualConfig() => RiverCoreConfig( + clock: _clk(), + mxlen: RiscVMxlen.rv32, + extensions: [rv32i, rvZicsr, rvZifencei, rvM], + interrupts: [], + mmu: _bareMmu(), + type: RiverCoreType.general, + executionMode: ExecutionMode.outOfOrder, + commitWidth: IssueWidth.dual, +); + +RiverCoreConfig oooDualBufConfig() => RiverCoreConfig( + clock: _clk(), + mxlen: RiscVMxlen.rv32, + extensions: [rv32i, rvZicsr, rvZifencei, rvM], + interrupts: [], + mmu: _bareMmu(), + type: RiverCoreType.general, + executionMode: ExecutionMode.outOfOrder, + commitWidth: IssueWidth.dual, + writeBufferDepth: 2, +); + +RiverCoreConfig oooSpecConfig() => RiverCoreConfig( + clock: _clk(), + mxlen: RiscVMxlen.rv32, + extensions: [rv32i, rvZicsr, rvZifencei, rvM], + interrupts: [], + mmu: _bareMmu(), + type: RiverCoreType.general, + executionMode: ExecutionMode.outOfOrder, + commitWidth: IssueWidth.dual, + speculativeFetch: true, +); diff --git a/packages/river_hdl/test/superscalar/core_ooo_spec_test.dart b/packages/river_hdl/test/superscalar/core_ooo_spec_test.dart new file mode 100644 index 0000000..6e893e5 --- /dev/null +++ b/packages/river_hdl/test/superscalar/core_ooo_spec_test.dart @@ -0,0 +1,200 @@ +import 'package:river/river.dart'; +import 'package:rohd/rohd.dart'; +import 'package:test/test.dart'; + +import '../core_harness.dart'; +import 'core_ooo_common.dart'; + +/// Out-of-order SPECULATIVE front-end (speculativeFetch=true): fetch advances at +/// allocation, instructions overlap in the ROB, and branch/jump redirects flush +/// the back-end and steer the fetcher. Split from core_ooo_test.dart so each +/// file stays under the per-file timeout (each test builds a fresh HDL core). +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + // Speculative fetch: the PC advances every cycle instead of waiting for + // commit, so the addis/nops overlap the multi-cycle mul in the ROB. + test( + 'speculative fetch overlaps a multi-cycle mul with a straight-line backlog', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + iimm(6, 0, 0x0, 1), // addi x1, x0, 6 + iimm(7, 0, 0x0, 2), // addi x2, x0, 7 + r(0x01, 2, 1, 0x0, 3), // mul x3, x1, x2 -> 42 (multi-cycle) + iimm(1, 1, 0x0, 4), // addi x4, x1, 1 -> 7 + iimm(2, 1, 0x0, 5), // addi x5, x1, 2 -> 8 + iimm(3, 1, 0x0, 6), // addi x6, x1, 3 -> 9 + iimm(4, 1, 0x0, 7), // addi x7, x1, 4 -> 10 + ...List.filled(8, 0x00000013), // nop tail (halt target inside it) + ]), + { + Register.x1: 6, + Register.x2: 7, + Register.x3: 42, + Register.x4: 7, + Register.x5: 8, + Register.x6: 9, + Register.x7: 10, + }, + oooSpecConfig(), + nextPc: 0x3C, + ), + ); + + // Speculative + taken branch: commits its redirect through the ROB -> flush + // back-end + steer the fetcher to the target. The skipped instruction must NOT + // retire. + test( + 'speculative taken branch redirects past the skipped instruction', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + iimm(5, 0, 0x0, 1), // addi x1, x0, 5 + iimm(5, 0, 0x0, 2), // addi x2, x0, 5 + b(8, 2, 1, 0x0), // beq x1, x2, +8 -> taken, target = 0x08+8 = 0x10 + iimm(99, 0, 0x0, 3), // addi x3, x0, 99 (SKIPPED, x3 stays 0) + iimm(7, 0, 0x0, 4), // addi x4, x0, 7 (branch target @0x10) + ...List.filled(8, 0x00000013), // nop tail + ]), + {Register.x1: 5, Register.x2: 5, Register.x3: 0, Register.x4: 7}, + oooSpecConfig(), + nextPc: 0x34, + ), + ); + + // Speculative + NOT-taken branch: must fall through (no redirect) and the + // following instruction MUST execute. + test( + 'speculative not-taken branch falls through', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + iimm(5, 0, 0x0, 1), // addi x1, x0, 5 + iimm(6, 0, 0x0, 2), // addi x2, x0, 6 + b(8, 2, 1, 0x0), // beq x1, x2, +8 -> NOT taken (5 != 6) + iimm(99, 0, 0x0, 3), // addi x3, x0, 99 (executes; x3 = 99) + iimm(7, 0, 0x0, 4), // addi x4, x0, 7 + ...List.filled(8, 0x00000013), // nop tail + ]), + {Register.x1: 5, Register.x2: 6, Register.x3: 99, Register.x4: 7}, + oooSpecConfig(), + nextPc: 0x34, + ), + ); + + // Speculative + LOOP (backward taken branches): repeated taken redirects to an + // earlier PC plus a cross-iteration RAW chain. + test( + 'speculative counted loop (backward branch redirects)', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + iimm(3, 0, 0x0, 1), // 0x00 addi x1, x0, 3 (loop count) + iimm(0, 0, 0x0, 2), // 0x04 addi x2, x0, 0 (accumulator) + iimm(1, 2, 0x0, 2), // 0x08 addi x2, x2, 1 loop body <- target + iimm(-1, 1, 0x0, 1), // 0x0C addi x1, x1, -1 + b(-8, 0, 1, 0x1), // 0x10 bne x1, x0, -8 -> back to 0x08 while x1!=0 + ...List.filled(11, 0x00000013), // 0x14.. nop tail + ]), + {Register.x1: 0, Register.x2: 3}, + oooSpecConfig(), + nextPc: 0x3C, + ), + ); + + // Straight-line RAW chain in SPECULATIVE mode: every instruction depends on + // the immediately preceding one with no branch to serialise them, so the + // producer is still in flight when the consumer renames - exercises the + // physical-register-file + wakeup forwarding end to end. + test( + 'speculative straight-line RAW chain forwards in-flight operands', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + iimm(1, 0, 0x0, 1), // addi x1, x0, 1 -> 1 + iimm(1, 1, 0x0, 2), // addi x2, x1, 1 -> 2 + iimm(1, 2, 0x0, 3), // addi x3, x2, 1 -> 3 + iimm(1, 3, 0x0, 4), // addi x4, x3, 1 -> 4 + iimm(1, 4, 0x0, 5), // addi x5, x4, 1 -> 5 + ...List.filled(8, 0x00000013), // nop tail + ]), + { + Register.x1: 1, + Register.x2: 2, + Register.x3: 3, + Register.x4: 4, + Register.x5: 5, + }, + oooSpecConfig(), + nextPc: 0x34, + ), + ); + + // CSR execution in OoO: write a CSR then read it back through mscratch. + // Exercises the CsrUnit completion -> ROB port 2 + the serialisation barrier. + test( + 'OoO executes csrrw/csrrs round-trip through mscratch', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + iimm(0x42, 0, 0x0, 1), // addi x1, x0, 0x42 + csr(0x340, 1, 0x1, 0), // csrrw x0, mscratch, x1 -> mscratch = 0x42 + csr(0x340, 0, 0x2, 3), // csrrs x3, mscratch, x0 -> x3 = mscratch + ...List.filled(8, 0x00000013), // nop tail + ]), + {Register.x1: 0x42, Register.x3: 0x42}, + oooSpecConfig(), + nextPc: 0x2C, + ), + ); + + // Speculative + JAL: an unconditional jump must redirect past the skipped + // instruction AND write the link register (rd = pc + 4). + test( + 'speculative JAL redirects and writes the link register', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + iimm(5, 0, 0x0, 1), // 0x00 addi x1, x0, 5 + jal(8, 3), // 0x04 jal x3, +8 -> link x3=0x08, jump 0x0C + iimm(99, 0, 0x0, 4), // 0x08 addi x4, x0, 99 (SKIPPED) + iimm(7, 0, 0x0, 2), // 0x0C addi x2, x0, 7 (JAL target) + ...List.filled(8, 0x00000013), // nop tail + ]), + { + Register.x1: 5, + Register.x2: 7, + Register.x3: 0x08, // link = pc(0x04) + 4 + Register.x4: 0, // skipped by the jump + }, + oooSpecConfig(), + nextPc: 0x30, + ), + ); + + // Speculative + JALR: indirect jump to a register-computed target, with link. + test( + 'speculative JALR jumps to a computed target and writes link', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + iimm(0x0C, 0, 0x0, 1), // 0x00 addi x1, x0, 0x0C (target addr) + jalr(0, 1, 3), // 0x04 jalr x3, x1, 0 -> link x3=0x08, jump x1=0x0C + iimm(99, 0, 0x0, 4), // 0x08 addi x4, x0, 99 (SKIPPED) + iimm(7, 0, 0x0, 2), // 0x0C addi x2, x0, 7 (JALR target) + ...List.filled(8, 0x00000013), // nop tail + ]), + { + Register.x1: 0x0C, + Register.x2: 7, + Register.x3: 0x08, // link = pc(0x04) + 4 + Register.x4: 0, // skipped by the jump + }, + oooSpecConfig(), + nextPc: 0x30, + ), + ); +} diff --git a/packages/river_hdl/test/superscalar/core_ooo_test.dart b/packages/river_hdl/test/superscalar/core_ooo_test.dart new file mode 100644 index 0000000..5d6f722 --- /dev/null +++ b/packages/river_hdl/test/superscalar/core_ooo_test.dart @@ -0,0 +1,192 @@ +import 'package:river/river.dart'; +import 'package:rohd/rohd.dart'; +import 'package:test/test.dart'; + +import '../core_harness.dart'; +import 'core_ooo_common.dart'; + +/// Out-of-order pipeline bring-up: basic single-issue, dual-commit, and the +/// memory functional unit. The speculative front-end tests live in +/// core_ooo_spec_test.dart (split so each file stays under the per-file timeout; +/// each test builds a fresh HDL core). See project_hdl_ooo_state in memory. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + // Single-issue OoO retires register-only programs correctly. + test( + 'OoO runs RV32I small program', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + // addi x1,x0,0x3E8 ; addi x2,x2,0x7D0 ; addi x3,x2,-0x3E8 ; + // addi x4,x3,0x18 ; addi x5,x5,0x3E8 ; nop + '''@0 +93 00 80 3E 13 81 00 7D 93 01 81 C1 13 82 01 83 +93 02 82 3E 13 00 00 00 +''', + { + Register.x1: 0x3E8, + Register.x2: 0xBB8, + Register.x3: 0x7D0, + Register.x5: 0x3E8, + }, + oooConfig(), + nextPc: 0x18, + ), + ); + + // Dual-commit (commitWidth=dual): a second register write port lets two ROB + // entries retire in one cycle. A multi-cycle `mul` stalls at the ROB head + // while the independent `addi`s behind it complete and queue; when the mul + // finally retires, the queued ops retire alongside it through slot 1. + test( + 'dual-commit retires a backlog behind a multi-cycle mul', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + iimm(6, 0, 0x0, 1), // addi x1, x0, 6 + iimm(7, 0, 0x0, 2), // addi x2, x0, 7 + r(0x01, 2, 1, 0x0, 3), // mul x3, x1, x2 -> 42 (multi-cycle) + iimm(1, 1, 0x0, 4), // addi x4, x1, 1 -> 7 + iimm(2, 1, 0x0, 5), // addi x5, x1, 2 -> 8 + iimm(3, 1, 0x0, 6), // addi x6, x1, 3 -> 9 + iimm(4, 1, 0x0, 7), // addi x7, x1, 4 -> 10 + ...List.filled(8, 0x00000013), // nop tail (halt target inside it) + ]), + { + Register.x1: 6, + Register.x2: 7, + Register.x3: 42, + Register.x4: 7, + Register.x5: 8, + Register.x6: 9, + Register.x7: 10, + }, + oooDualConfig(), + nextPc: 0x3C, + ), + ); + + // Same backlog program with a depth-2 register-file write buffer + // (writeBufferDepth=2): same-bank commit collisions are buffered instead of + // stalling. The architectural result must be identical. + test( + 'dual-commit with write buffer retires backlog behind a multi-cycle mul', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + iimm(6, 0, 0x0, 1), // addi x1, x0, 6 + iimm(7, 0, 0x0, 2), // addi x2, x0, 7 + r(0x01, 2, 1, 0x0, 3), // mul x3, x1, x2 -> 42 (multi-cycle) + iimm(1, 1, 0x0, 4), // addi x4, x1, 1 -> 7 + iimm(2, 1, 0x0, 5), // addi x5, x1, 2 -> 8 + iimm(3, 1, 0x0, 6), // addi x6, x1, 3 -> 9 + iimm(4, 1, 0x0, 7), // addi x7, x1, 4 -> 10 + ...List.filled(8, 0x00000013), // nop tail (halt target inside it) + ]), + { + Register.x1: 6, + Register.x2: 7, + Register.x3: 42, + Register.x4: 7, + Register.x5: 8, + Register.x6: 9, + Register.x7: 10, + }, + oooDualBufConfig(), + nextPc: 0x3C, + ), + ); + + // OoO branch bring-up (lockstep): kept skipped to document that lockstep OoO + // has no branch-redirect path (it advances the arch PC only at commit). Branch + // support in OoO requires speculativeFetch=true (see core_ooo_spec_test.dart). + test( + 'OoO taken branch redirects past the skipped instruction', + timeout: Timeout(Duration(seconds: 60)), + skip: 'lockstep OoO has no branch-redirect path; use speculativeFetch', + () => coreTest( + prog([ + iimm(5, 0, 0x0, 1), // addi x1, x0, 5 + iimm(5, 0, 0x0, 2), // addi x2, x0, 5 + b(8, 2, 1, 0x0), // beq x1, x2, +8 -> taken, target = 0x08+8 = 0x10 + iimm(99, 0, 0x0, 3), // addi x3, x0, 99 (SKIPPED, x3 stays 0) + iimm(7, 0, 0x0, 4), // addi x4, x0, 7 (branch target @0x10) + ...List.filled(8, 0x00000013), // nop tail + ]), + {Register.x1: 5, Register.x2: 5, Register.x3: 0, Register.x4: 7}, + oooConfig(), + nextPc: 0x34, + ), + ); + + // Zbb/Zba/Zbs ALU ops through the OoO datapath. A nop tail lets the ROB drain. + test( + 'OoO runs bitmanip (max/minu/andn/rol/clz/cpop/sh1add)', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + iimm(16, 0, 0x0, 1), // addi x1, x0, 16 + iimm(3, 0, 0x0, 2), // addi x2, x0, 3 + r(0x05, 2, 1, 0x6, 5), // max x5, x1, x2 -> 16 + r(0x05, 2, 1, 0x5, 6), // minu x6, x1, x2 -> 3 + r(0x20, 2, 1, 0x7, 7), // andn x7, x1, x2 -> 16 + r(0x30, 2, 1, 0x1, 9), // rol x9, x1, x2 -> 128 + iimm(0x600, 2, 0x1, 10), // clz x10, x2 -> 30 (rv32) + iimm(0x602, 1, 0x1, 11), // cpop x11, x1 -> 1 + r(0x10, 1, 2, 0x2, 8), // sh1add x8, x2, x1 -> 22 + ...List.filled(8, 0x00000013), // nop tail (halt target inside it) + ]), + { + Register.x5: 16, + Register.x6: 3, + Register.x7: 16, + Register.x9: 128, + Register.x10: 30, + Register.x11: 1, + Register.x8: 22, + }, + oooBConfig(), + nextPc: 0x3C, + ), + ); + + // Memory functional unit on the OoO datapath: store a value then load it back. + // The separation nops between sw and lw are load-bearing (store visibility + // takes several cycles through the MMU->Wishbone->memory path). + test( + 'OoO runs sw + lw round-trip through memory (with store-visibility gap)', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + iimm(0x100, 0, 0x0, 10), // addi x10, x0, 0x100 (base addr) + iimm(0x123, 0, 0x0, 5), // addi x5, x0, 0x123 (value) + s(0, 5, 10, 0x2, 0x23), // sw x5, 0(x10) mem[0x100]=0x123 + ...List.filled(4, 0x00000013), // separation nops (diagnose visibility) + lw(0, 10, 6), // lw x6, 0(x10) x6 = 0x123 + ...List.filled(8, 0x00000013), // nop tail + ]), + {Register.x10: 0x100, Register.x5: 0x123, Register.x6: 0x123}, + oooConfig(), + nextPc: 0x3C, + memStates: {0x100: 0x123}, + ), + ); + + // Isolate the load path: read from pre-initialized memory (no store dep). + test( + 'OoO runs lw from preloaded memory', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + '${prog([ + iimm(0x100, 0, 0x0, 10), // addi x10, x0, 0x100 + lw(0, 10, 6), // lw x6, 0(x10) -> 0xDEADBEEF + ...List.filled(8, 0x00000013), // nop tail + ])}@100\nef be ad de\n', + {Register.x10: 0x100, Register.x6: 0xDEADBEEF}, + oooConfig(), + nextPc: 0x24, + ), + ); +} diff --git a/packages/river_hdl/test/superscalar/ooo_seed_probe_test.dart b/packages/river_hdl/test/superscalar/ooo_seed_probe_test.dart new file mode 100644 index 0000000..253a6f5 --- /dev/null +++ b/packages/river_hdl/test/superscalar/ooo_seed_probe_test.dart @@ -0,0 +1,35 @@ +import 'package:river/river.dart'; +import 'package:rohd/rohd.dart'; +import 'package:test/test.dart'; + +import '../core_harness.dart'; +import 'core_ooo_common.dart'; + +/// Regression for the OoO initRegisters-seed limitation (task #78). coreTest's +/// initRegisters seeds the ARCHITECTURAL regfile (core.regWritePort -> regs), +/// but the OoO core reads operand values from a SEPARATE PHYSICAL register file +/// (`prf` in pipeline.dart - srcValue() reads `muxArr(prf, psrc)`), which is +/// written only at execute-writeback (by physical dest), never from the seed. So +/// a seeded register reads as 0 on OoO. SKIPPED until a prf seed port lands; +/// until then OoO tests must COMPUTE register inputs in the program, not seed. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + test( + 'OoO: a small seeded register reaches the read path', + timeout: Timeout(Duration(seconds: 60)), + () => coreTest( + prog([ + csr(0x340, 10, 0x1, 0), // csrrw x0, mscratch, x10 -> mscratch = x10 + csr(0x340, 0, 0x2, 3), // csrrs x3, mscratch, x0 -> x3 = mscratch + ...List.filled(8, 0x00000013), + ]), + {Register.x3: 0x42}, + oooSpecConfig(), + initRegisters: {Register.x10: 0x42}, + nextPc: 0x28, + ), + ); +} diff --git a/packages/river_hdl/test/tool_generate_matrix.sh b/packages/river_hdl/test/tool_generate_matrix.sh new file mode 100644 index 0000000..14f3096 --- /dev/null +++ b/packages/river_hdl/test/tool_generate_matrix.sh @@ -0,0 +1,57 @@ +#!/usr/bin/env bash +# Regenerates the matrix cell files: test//__test.dart +# for every supported (category, mxlen, uarch). Each is a 5-line thin file that +# calls runMatrix with the table-driven config + instruction list. Run from the +# river_hdl/test directory. Gating mirrors microarchSupports in matrix_configs.dart: +# - in-order runs all categories (branch included now that #69 is fixed). +# - ooo / ooo_dual run all EXCEPT the in-order-only ones (loadstore/a/zacas, +# whose OoO mem-FU path is incomplete - project_hdl_ooo_state). +# Adding a category: add it here AND to matrix_instructions.dart + matrix_configs.dart. +set -euo pipefail +cd "$(dirname "$0")" + +cats=(base loadstore branch m a bitmanip zicond zacas csr fd d v) +declare -A uenum=( [inorder]=inOrder [ooo]=ooo [ooo_dual]=oooDual ) + +gen() { + local cat=$1 mx=$2 ul=$3 uev=$4 + mkdir -p "$cat" + cat > "$cat/${mx}_${ul}_test.dart" < (csr << 20) | (rs1 << 15) | (0x1 << 12) | 0x73; + int addi(int rd, int rs1, int imm) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (rd << 7) | 0x13; + int slli(int rd, int rs1, int sh) => + (sh << 20) | (rs1 << 15) | (0x1 << 12) | (rd << 7) | 0x13; + const mret = 0x30200073; + const jalLoop = 0x0000006F; + const nop = 0x00000013; + + String words(List ws) { + final sb = StringBuffer(); + for (final w in ws) { + for (var b = 0; b < 4; b++) { + sb.write(((w >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + return sb.toString().trimRight(); + } + + test( + 'OoO: mret redirects to mepc and flushes the wrong-path successor', + timeout: Timeout(Duration(seconds: 180)), + () { + // mepc = 0x40 (target). MPP=3 (machine) so mret stays in M-mode. + final prog = words([ + addi(14, 0, 0x40), // 0 x14 = 0x40 + csrw(0x341, 14), // 1 csrw mepc, x14 + addi(12, 0, 3), // 2 x12 = 3 + slli(12, 12, 11), // 3 x12 = 0x1800 (mstatus.MPP = 3 = machine) + csrw(0x300, 12), // 4 csrw mstatus, x12 + mret, // 5 @0x14 mret -> pc = mepc = 0x40, mode = M + addi(5, 0, 0xFF), // 6 @0x18 WRONG PATH: clobbers x5 if not flushed + nop, nop, nop, nop, nop, nop, nop, nop, nop, // 7-15 + addi(5, 0, 0xAB), // 16 @0x40 correct target: x5 = 0xAB + jalLoop, // 17 @0x44 loop + ]); + return coreTest( + '@0\n$prog\n', + {Register.x5: 0xAB}, // proves mret landed at 0x40 and 0x18 was squashed + config, + nextPc: 0x44, + ); + }, + ); +} diff --git a/packages/river_hdl/test/trap/core_ooo_mret_trap_test.dart b/packages/river_hdl/test/trap/core_ooo_mret_trap_test.dart new file mode 100644 index 0000000..2c1679f --- /dev/null +++ b/packages/river_hdl/test/trap/core_ooo_mret_trap_test.dart @@ -0,0 +1,82 @@ +import 'package:rohd/rohd.dart'; +import 'package:river/river.dart'; +import 'package:test/test.dart'; +import '../core_harness.dart'; + +/// OoO trap + return composed (task #75) without paging/translated fetch: mret +/// to M-mode (Step B) lands at mepc, where an illegal-CSR access raises an +/// exception that vectors to mtvec (Step A). Confirms the two deliveries compose +/// in M-mode; the remaining S-mode+paging fault path is a separate OoO gap. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + final config = RiverCoreConfig( + mxlen: RiscVMxlen.rv64, + extensions: kRva22S64Extensions, + type: RiverCoreType.general, + executionMode: ExecutionMode.outOfOrder, + speculativeFetch: true, + branchPredictor: BranchPredictor.btfn, + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + interrupts: [], + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + ); + + int csrw(int csr, int rs1) => (csr << 20) | (rs1 << 15) | (0x1 << 12) | 0x73; + int csrrw(int csr, int rs1, int rd) => + (csr << 20) | (rs1 << 15) | (0x1 << 12) | (rd << 7) | 0x73; + int csrr(int csr, int rd) => (csr << 20) | (0x2 << 12) | (rd << 7) | 0x73; + int addi(int rd, int rs1, int imm) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (rd << 7) | 0x13; + int slli(int rd, int rs1, int sh) => + (sh << 20) | (rs1 << 15) | (0x1 << 12) | (rd << 7) | 0x13; + const mret = 0x30200073; + const jalLoop = 0x0000006F; + const nop = 0x00000013; + + String words(List ws) { + final sb = StringBuffer(); + for (final w in ws) { + for (var b = 0; b < 4; b++) { + sb.write(((w >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + return sb.toString().trimRight(); + } + + test( + 'OoO: mret lands, then an illegal-CSR trap vectors to mtvec (compose)', + timeout: Timeout(Duration(seconds: 180)), + () { + // mret target = 0x20; mtvec = 0x40. After mret runs to 0x20, the illegal + // CSR there traps to 0x40 where mcause (==2) is read into x5. + final prog = words([ + addi(14, 0, 0x20), // 0 x14 = 0x20 (mepc) + csrw(0x341, 14), // 1 csrw mepc, x14 + addi(12, 0, 3), // 2 + slli(12, 12, 11), // 3 x12 = 0x1800 (MPP=3=M) + csrw(0x300, 12), // 4 csrw mstatus, x12 + addi(13, 0, 0x40), // 5 x13 = 0x40 (mtvec) + csrw(0x305, 13), // 6 csrw mtvec, x13 + mret, // 7 @0x1C mret -> pc = 0x20, M-mode + csrrw(0xBFF, 0, 1), //8 @0x20 illegal CSR -> trap (cause 2) to mtvec + nop, nop, nop, nop, nop, nop, // 9-14 + nop, // 15 + csrr(0x342, 5), // 16 @0x40 handler: x5 = mcause (== 2) + jalLoop, // 17 @0x44 loop + ]); + return coreTest('@0\n$prog\n', {Register.x5: 2}, config, nextPc: 0x44); + }, + ); +} diff --git a/packages/river_hdl/test/trap/core_ooo_trap_test.dart b/packages/river_hdl/test/trap/core_ooo_trap_test.dart new file mode 100644 index 0000000..fb6110d --- /dev/null +++ b/packages/river_hdl/test/trap/core_ooo_trap_test.dart @@ -0,0 +1,81 @@ +import 'package:rohd/rohd.dart'; +import 'package:river/river.dart'; +import 'package:test/test.dart'; +import '../core_harness.dart'; + +/// OoO exception delivery (task #75, Step A). A committing synchronous exception +/// on the out-of-order core must redirect the fetch PC to the trap vector +/// (mtvec) and write mcause, the same way the in-order path does. Before #75 the +/// OoO commit path hardcoded nextMode=currentMode and never redirected to mtvec, +/// so a trap was silently dropped. +/// +/// M-mode test (the OoO core runs M-mode in tests): set mtvec, then touch an +/// unimplemented CSR -> the CsrUnit raises an illegal-instruction exception +/// (cause 2) -> the commit path vectors to mtvec, the handler reads mcause==2. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + final config = RiverCoreConfig( + mxlen: RiscVMxlen.rv64, + extensions: kRva22S64Extensions, + type: RiverCoreType.general, + executionMode: ExecutionMode.outOfOrder, + speculativeFetch: true, + branchPredictor: BranchPredictor.btfn, + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + interrupts: [], + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + ); + + int csrw(int csr, int rs1) => (csr << 20) | (rs1 << 15) | (0x1 << 12) | 0x73; + int csrrw(int csr, int rs1, int rd) => + (csr << 20) | (rs1 << 15) | (0x1 << 12) | (rd << 7) | 0x73; + int csrr(int csr, int rd) => (csr << 20) | (0x2 << 12) | (rd << 7) | 0x73; + int addi(int rd, int rs1, int imm) => + ((imm & 0xFFF) << 20) | (rs1 << 15) | (rd << 7) | 0x13; + const jalLoop = 0x0000006F; + const nop = 0x00000013; + + String words(List ws) { + final sb = StringBuffer(); + for (final w in ws) { + for (var b = 0; b < 4; b++) { + sb.write(((w >> (b * 8)) & 0xFF).toRadixString(16).padLeft(2, '0')); + sb.write(' '); + } + } + return sb.toString().trimRight(); + } + + test( + 'OoO: an illegal-CSR exception vectors to mtvec and sets mcause', + timeout: Timeout(Duration(seconds: 180)), + () { + // mtvec = 0x40 (direct mode, low bits 0). Handler reads mcause. + final prog = words([ + addi(14, 0, 0x40), // 0 x14 = 0x40 + csrw(0x305, 14), // 1 csrw mtvec, x14 + csrrw(0xBFF, 0, 1), //2 csrrw x1, 0xBFF, x0 -> illegal CSR (cause 2) + nop, nop, nop, nop, nop, nop, nop, nop, nop, nop, nop, nop, nop, // 3-15 + csrr(0x342, 5), // 16 @0x40 handler: x5 = mcause (== 2) + jalLoop, // 17 @0x44 loop + ]); + return coreTest( + '@0\n$prog\n', + {Register.x5: 2}, // illegal instruction cause + config, + nextPc: 0x44, + ); + }, + ); +} diff --git a/packages/river_hdl/test/trap/core_trap_return_test.dart b/packages/river_hdl/test/trap/core_trap_return_test.dart new file mode 100644 index 0000000..6a77275 --- /dev/null +++ b/packages/river_hdl/test/trap/core_trap_return_test.dart @@ -0,0 +1,75 @@ +import 'package:rohd/rohd.dart'; +import 'package:river/river.dart'; +import 'package:test/test.dart'; +import '../core_harness.dart'; + +/// MRET / trap-return support in the in-order HDL core. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + final config = RiverCoreConfigV1.small( + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + interrupts: [], + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + ); + + // Isolated MRET return: preload mepc=0x10 (computed) and mstatus.MPP=M + // (0x1800, from x11), then mret. PC must jump to 0x10 and execute addi. + // 0x00 addi x10,x0,0x10 ; 13 05 00 01 + // 0x04 csrw mepc,x10 ; 73 10 15 34 + // 0x08 csrw mstatus,x11 ; 73 90 05 30 + // 0x0c mret ; 73 00 20 30 + // 0x10 addi x12,x0,0x55 ; 13 06 50 05 <- return target + test( + 'mret returns to mepc and restores mode', + timeout: Timeout(Duration(seconds: 200)), + () { + return coreTest( + '@0\n' + '13 05 00 01 73 10 15 34 73 90 05 30 73 00 20 30 13 06 50 05\n', + {Register.x12: 0x55}, + config, + initRegisters: {Register.x11: 0x1800}, + nextPc: 0x14, + ); + }, + ); + + // Full trap round-trip: ecall (M) saves mepc, jumps to mtvec handler; handler + // reads mepc, bumps it past the ecall, mret returns to the next instruction. + // 0x00 csrw mtvec,x10 ; 73 10 55 30 (x10=0x1c) + // 0x04 ecall ; 73 00 00 00 + // 0x08 addi x11,x0,0x55 ; 93 05 50 05 <- resumes here + // 0x0c (nextPc target) ; 13 00 00 00 + // 0x10..0x18 nops + // 0x1c csrr x12,mepc ; 73 26 10 34 + // 0x20 addi x12,x12,4 ; 13 06 46 00 + // 0x24 csrw mepc,x12 ; 73 10 16 34 + // 0x28 mret ; 73 00 20 30 + test( + 'ecall traps to mtvec, mret resumes after ecall', + timeout: Timeout(Duration(seconds: 200)), + () { + return coreTest( + '@0\n' + '73 10 55 30 73 00 00 00 93 05 50 05 13 00 00 00 ' + '13 00 00 00 13 00 00 00 13 00 00 00 73 26 10 34 ' + '13 06 46 00 73 10 16 34 73 00 20 30\n', + {Register.x11: 0x55, Register.x12: 0x8}, + config, + initRegisters: {Register.x10: 0x1c}, + nextPc: 0xc, + ); + }, + ); +} diff --git a/packages/river_hdl/test/trap/core_wfi_test.dart b/packages/river_hdl/test/trap/core_wfi_test.dart new file mode 100644 index 0000000..4396e95 --- /dev/null +++ b/packages/river_hdl/test/trap/core_wfi_test.dart @@ -0,0 +1,43 @@ +import 'package:rohd/rohd.dart'; +import 'package:river/river.dart'; +import 'package:test/test.dart'; +import '../core_harness.dart'; + +/// wfi must retire as a NOP-hint and advance past itself so the core does not +/// wedge (Linux idles with wfi). The dynamic microcode interpreter (creek path) +/// had no handler for the WaitForInterrupt micro-op, so wfi stalled forever. +void main() { + tearDown(() async { + await Simulator.reset(); + }); + + final config = RiverCoreConfigV1.small( + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + interrupts: [], + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + ); + + // 0x00 wfi ; 73 00 50 10 (0x10500073) + // 0x04 addi x1,x0,0x42 ; 93 00 20 04 (0x04200093) <- must run + test( + 'wfi retires and the core continues to the next instruction', + timeout: Timeout(Duration(seconds: 120)), + () { + return coreTest( + '@0\n' + '73 00 50 10 93 00 20 04\n', + {Register.x1: 0x42}, + config, + nextPc: 0x08, + ); + }, + ); +} diff --git a/packages/river_hdl/test/v/rv64_inorder_test.dart b/packages/river_hdl/test/v/rv64_inorder_test.dart new file mode 100644 index 0000000..c790368 --- /dev/null +++ b/packages/river_hdl/test/v/rv64_inorder_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'v'; + const mxlen = RiscVMxlen.rv64; + const uarch = Uarch.inOrder; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/zacas/rv32_inorder_test.dart b/packages/river_hdl/test/zacas/rv32_inorder_test.dart new file mode 100644 index 0000000..4e327b4 --- /dev/null +++ b/packages/river_hdl/test/zacas/rv32_inorder_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'zacas'; + const mxlen = RiscVMxlen.rv32; + const uarch = Uarch.inOrder; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/zacas/rv64_inorder_test.dart b/packages/river_hdl/test/zacas/rv64_inorder_test.dart new file mode 100644 index 0000000..7194c8a --- /dev/null +++ b/packages/river_hdl/test/zacas/rv64_inorder_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'zacas'; + const mxlen = RiscVMxlen.rv64; + const uarch = Uarch.inOrder; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/zicond/rv32_inorder_test.dart b/packages/river_hdl/test/zicond/rv32_inorder_test.dart new file mode 100644 index 0000000..1118d81 --- /dev/null +++ b/packages/river_hdl/test/zicond/rv32_inorder_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'zicond'; + const mxlen = RiscVMxlen.rv32; + const uarch = Uarch.inOrder; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/zicond/rv32_ooo_dual_test.dart b/packages/river_hdl/test/zicond/rv32_ooo_dual_test.dart new file mode 100644 index 0000000..4e4b1eb --- /dev/null +++ b/packages/river_hdl/test/zicond/rv32_ooo_dual_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'zicond'; + const mxlen = RiscVMxlen.rv32; + const uarch = Uarch.oooDual; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/zicond/rv32_ooo_test.dart b/packages/river_hdl/test/zicond/rv32_ooo_test.dart new file mode 100644 index 0000000..c448594 --- /dev/null +++ b/packages/river_hdl/test/zicond/rv32_ooo_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'zicond'; + const mxlen = RiscVMxlen.rv32; + const uarch = Uarch.ooo; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/zicond/rv64_inorder_microcode_test.dart b/packages/river_hdl/test/zicond/rv64_inorder_microcode_test.dart new file mode 100644 index 0000000..4236b15 --- /dev/null +++ b/packages/river_hdl/test/zicond/rv64_inorder_microcode_test.dart @@ -0,0 +1,22 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +/// In-order MICROCODE path (DynamicExecutionUnit + microcode ROM, +/// MicrocodeMode.full) for the 'zicond' category, validated against the emulator +/// golden. This is the area-first path rc1-s (creek) uses on small FPGAs. Split +/// per-category so dart test parallelizes across isolates (one big file +/// accumulates heap across builds and times out - see project_parity / +/// feedback_test_parallelism). +void main() { + const category = 'zicond'; + const mxlen = RiscVMxlen.rv64; + const uarch = Uarch.inOrder; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)} (microcode)', + matrixConfig(mxlen, uarch, category, microcodeMode: MicrocodeMode.full), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/zicond/rv64_inorder_test.dart b/packages/river_hdl/test/zicond/rv64_inorder_test.dart new file mode 100644 index 0000000..ce81539 --- /dev/null +++ b/packages/river_hdl/test/zicond/rv64_inorder_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'zicond'; + const mxlen = RiscVMxlen.rv64; + const uarch = Uarch.inOrder; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/zicond/rv64_ooo_dual_test.dart b/packages/river_hdl/test/zicond/rv64_ooo_dual_test.dart new file mode 100644 index 0000000..5fc658d --- /dev/null +++ b/packages/river_hdl/test/zicond/rv64_ooo_dual_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'zicond'; + const mxlen = RiscVMxlen.rv64; + const uarch = Uarch.oooDual; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_hdl/test/zicond/rv64_ooo_test.dart b/packages/river_hdl/test/zicond/rv64_ooo_test.dart new file mode 100644 index 0000000..65c408b --- /dev/null +++ b/packages/river_hdl/test/zicond/rv64_ooo_test.dart @@ -0,0 +1,16 @@ +import 'package:river/river.dart'; + +import '../matrix_configs.dart'; +import '../matrix_instructions.dart'; +import '../matrix_harness.dart'; + +void main() { + const category = 'zicond'; + const mxlen = RiscVMxlen.rv64; + const uarch = Uarch.ooo; + runMatrix( + 'matrix: $category ${mxlenLabel(mxlen)} ${uarchLabel(uarch)}', + matrixConfig(mxlen, uarch, category), + instructionsFor(category, mxlen), + ); +} diff --git a/packages/river_maskrom/analysis_options.yaml b/packages/river_maskrom/analysis_options.yaml new file mode 100644 index 0000000..f5d48c9 --- /dev/null +++ b/packages/river_maskrom/analysis_options.yaml @@ -0,0 +1,2 @@ +# Inherits the workspace production analysis baseline. +include: ../../analysis_options.yaml diff --git a/packages/river_maskrom/bin/emit_ddr_probe.dart b/packages/river_maskrom/bin/emit_ddr_probe.dart new file mode 100644 index 0000000..08094e3 --- /dev/null +++ b/packages/river_maskrom/bin/emit_ddr_probe.dart @@ -0,0 +1,40 @@ +import 'dart:io'; + +import 'package:river/river.dart'; +import 'package:river_maskrom/river_maskrom.dart'; + +/// Emit a serial-monitor load frame for the [RiverDdrProbe] payload. +/// Usage: `dart run river_maskrom:emit_ddr_probe [out.hex] [dram] [uart] [clockHz]` +Future main(List args) async { + final out = args.isNotEmpty ? args[0] : '/tmp/ddr_probe.hex'; + final dram = args.length > 1 ? int.parse(args[1]) : 0x90000000; + final uart = args.length > 2 ? int.parse(args[2]) : 0x10000000; + final clockHz = args.length > 3 ? int.parse(args[3]) : 48000000; + + final isa = RiscVIsaConfig(mxlen: RiscVMxlen.rv32, extensions: [rv32i]); + final payloadProg = RiverDdrProbe( + isa: isa, + uartBase: uart, + dramBase: dram, + clockHz: clockHz, + ); + await payloadProg.build(); + final payload = payloadProg.generateBytes(); + + final sum = payload.fold(0, (a, b) => (a + b) & 0xff); + final frame = [ + payload.length & 0xff, + (payload.length >> 8) & 0xff, + ...payload, + sum, + ]; + await File(out).writeAsString( + frame.map((b) => b.toRadixString(16).padLeft(2, '0')).join('\n'), + ); + final binOut = out.replaceAll(RegExp(r'\.hex$'), '.bin'); + await File(binOut == out ? '$out.bin' : binOut).writeAsBytes(payload); + stdout.writeln( + 'wrote $out (+ payload .bin): ${payload.length}-byte payload, checksum ' + '0x${sum.toRadixString(16)}, frame ${frame.length} bytes', + ); +} diff --git a/packages/river_maskrom/bin/emit_ddr_sweep.dart b/packages/river_maskrom/bin/emit_ddr_sweep.dart new file mode 100644 index 0000000..323df57 --- /dev/null +++ b/packages/river_maskrom/bin/emit_ddr_sweep.dart @@ -0,0 +1,40 @@ +import 'dart:io'; + +import 'package:river/river.dart'; +import 'package:river_maskrom/river_maskrom.dart'; + +/// Emit a serial-monitor load frame for the [RiverDdrSweepProbe] payload. +/// Usage: `dart run river_maskrom:emit_ddr_sweep [out.hex] [dram] [uart] [clockHz]` +Future main(List args) async { + final out = args.isNotEmpty ? args[0] : '/tmp/ddr_sweep.hex'; + final dram = args.length > 1 ? int.parse(args[1]) : 0x90000000; + final uart = args.length > 2 ? int.parse(args[2]) : 0x10000000; + final clockHz = args.length > 3 ? int.parse(args[3]) : 48000000; + + final isa = RiscVIsaConfig(mxlen: RiscVMxlen.rv32, extensions: [rv32i]); + final payloadProg = RiverDdrSweepProbe( + isa: isa, + uartBase: uart, + dramBase: dram, + clockHz: clockHz, + ); + await payloadProg.build(); + final payload = payloadProg.generateBytes(); + + final sum = payload.fold(0, (a, b) => (a + b) & 0xff); + final frame = [ + payload.length & 0xff, + (payload.length >> 8) & 0xff, + ...payload, + sum, + ]; + await File(out).writeAsString( + frame.map((b) => b.toRadixString(16).padLeft(2, '0')).join('\n'), + ); + final binOut = out.replaceAll(RegExp(r'\.hex$'), '.bin'); + await File(binOut == out ? '$out.bin' : binOut).writeAsBytes(payload); + stdout.writeln( + 'wrote $out (+ payload .bin): ${payload.length}-byte payload, checksum ' + '0x${sum.toRadixString(16)}, frame ${frame.length} bytes', + ); +} diff --git a/packages/river_maskrom/bin/emit_ddr_test.dart b/packages/river_maskrom/bin/emit_ddr_test.dart new file mode 100644 index 0000000..3d50c62 --- /dev/null +++ b/packages/river_maskrom/bin/emit_ddr_test.dart @@ -0,0 +1,44 @@ +import 'dart:io'; + +import 'package:river/river.dart'; +import 'package:river_maskrom/river_maskrom.dart'; + +/// Emit a serial-monitor load frame for the [RiverDdrTest] payload, as hex +/// bytes for `$readmemh` plus the raw payload `.bin` for river_load. +/// Usage: `dart run river_maskrom:emit_ddr_test [out.hex] [dram] [uart] [clockHz]` +Future main(List args) async { + final out = args.isNotEmpty ? args[0] : '/tmp/ddr_frame.hex'; + final dram = args.length > 1 ? int.parse(args[1]) : 0x90000000; + final uart = args.length > 2 ? int.parse(args[2]) : 0x10000000; + final clockHz = args.length > 3 ? int.parse(args[3]) : 48000000; + + final isa = RiscVIsaConfig(mxlen: RiscVMxlen.rv32, extensions: [rv32i]); + final payloadProg = RiverDdrTest( + isa: isa, + uartBase: uart, + dramBase: dram, + // Train-control MMIO window sits just above the DRAM array (dramBase + + // dramSize). 128M is the standard creek/x8 layout. + trainCtrlBase: dram + 0x08000000, + clockHz: clockHz, + ); + await payloadProg.build(); + final payload = payloadProg.generateBytes(); + + final sum = payload.fold(0, (a, b) => (a + b) & 0xff); + final frame = [ + payload.length & 0xff, + (payload.length >> 8) & 0xff, + ...payload, + sum, + ]; + await File(out).writeAsString( + frame.map((b) => b.toRadixString(16).padLeft(2, '0')).join('\n'), + ); + final binOut = out.replaceAll(RegExp(r'\.hex$'), '.bin'); + await File(binOut == out ? '$out.bin' : binOut).writeAsBytes(payload); + stdout.writeln( + 'wrote $out (+ payload .bin): ${payload.length}-byte payload, checksum ' + '0x${sum.toRadixString(16)}, frame ${frame.length} bytes', + ); +} diff --git a/packages/river_maskrom/bin/emit_frame.dart b/packages/river_maskrom/bin/emit_frame.dart new file mode 100644 index 0000000..e144445 --- /dev/null +++ b/packages/river_maskrom/bin/emit_frame.dart @@ -0,0 +1,50 @@ +import 'dart:io'; + +import 'package:river/river.dart'; +import 'package:river_maskrom/river_maskrom.dart'; + +/// Emit a serial-monitor load frame (len_lo len_hi payload checksum) for a +/// sample [RiverHelloWorld] payload, as one hex byte per line (for +/// `$readmemh` in a testbench), plus the raw payload as a sibling `.bin` +/// for sending to real hardware with river_load. +/// Usage: `dart run river_maskrom:emit_frame [out.hex] [ram] [uart] [clockHz]` +/// The payload prints from RAM, so its data buffer sits 32KB above its code +/// (inside even the smallest 64KB board RAM). +/// clockHz must match the TARGET BOARD (the payload re-derives the UART +/// divisor from it): 12000000 for the iCESugar, 48000000 for the OrangeCrab. +Future main(List args) async { + final out = args.isNotEmpty ? args[0] : '/tmp/frame.hex'; + final ram = args.length > 1 ? int.parse(args[1]) : 0x80000000; + final uart = args.length > 2 ? int.parse(args[2]) : 0x10000000; + final clockHz = args.length > 3 ? int.parse(args[3]) : 12000000; + + final isa = RiscVIsaConfig(mxlen: RiscVMxlen.rv32, extensions: [rv32i]); + final payloadProg = RiverHelloWorld( + isa: isa, + uartBase: uart, + ramBase: + ram + 0x8000, // data buffer 32KB up, clear of code, within 64KB RAMs + clockHz: clockHz, + message: 'Hi from RAM!\r\n', + ); + await payloadProg.build(); + final payload = payloadProg.generateBytes(); + + final sum = payload.fold(0, (a, b) => (a + b) & 0xff); + final frame = [ + payload.length & 0xff, + (payload.length >> 8) & 0xff, + ...payload, + sum, + ]; + await File(out).writeAsString( + frame.map((b) => b.toRadixString(16).padLeft(2, '0')).join('\n'), + ); + // The raw payload alongside, for sending to real hardware via river_load. + final binOut = out.replaceAll(RegExp(r'\.hex$'), '.bin'); + await File(binOut == out ? '$out.bin' : binOut).writeAsBytes(payload); + stdout.writeln( + 'wrote $out (+ payload .bin): ${payload.length}-byte payload, checksum ' + '0x${sum.toRadixString(16)}, frame ${frame.length} bytes', + ); +} diff --git a/packages/river_maskrom/bin/emit_hello.dart b/packages/river_maskrom/bin/emit_hello.dart new file mode 100644 index 0000000..4de46e9 --- /dev/null +++ b/packages/river_maskrom/bin/emit_hello.dart @@ -0,0 +1,23 @@ +import 'dart:io'; + +import 'package:river/river.dart'; +import 'package:river_maskrom/river_maskrom.dart'; + +/// Emit the hello-world demo as an ELF for emulator/HDL testing. +/// Usage: `dart run river_maskrom:emit_hello [out.elf] [entry] [ram] [uart]` +/// (all addresses are integers, e.g. 0x80000000). +Future main(List args) async { + final out = args.isNotEmpty ? args[0] : '/tmp/hello.elf'; + final entry = args.length > 1 ? int.parse(args[1]) : 0x80000000; + final ram = args.length > 2 ? int.parse(args[2]) : 0x80008000; + final uart = args.length > 3 ? int.parse(args[3]) : 0x10000000; + + final isa = RiscVIsaConfig(mxlen: RiscVMxlen.rv32, extensions: [rv32i]); + final prog = RiverHelloWorld(isa: isa, uartBase: uart, ramBase: ram); + await prog.build(); + await File(out).writeAsBytes(prog.emitElfBytes(entryPoint: entry)); + stdout.writeln( + 'wrote $out (entry=0x${entry.toRadixString(16)}, ' + 'ram=0x${ram.toRadixString(16)}, uart=0x${uart.toRadixString(16)})', + ); +} diff --git a/packages/river_maskrom/bin/emit_timer_poll.dart b/packages/river_maskrom/bin/emit_timer_poll.dart new file mode 100644 index 0000000..7b7697e --- /dev/null +++ b/packages/river_maskrom/bin/emit_timer_poll.dart @@ -0,0 +1,42 @@ +import 'dart:io'; + +import 'package:river/river.dart'; +import 'package:river_maskrom/river_maskrom.dart'; + +/// Emit the CLINT polling demo as a monitor payload: a raw `.bin` for +/// `river_load`, plus a `.hex` frame for testbenches. +/// Usage: `dart run river_maskrom:emit_timer_poll [out_base] [tickHz] [ticks]` +/// (out_base defaults to /tmp/timer_poll; tickHz to 12000000 = one-second +/// ticks at 12MHz, use a small value like 50000 for simulation). +Future main(List args) async { + final base = args.isNotEmpty ? args[0] : '/tmp/timer_poll'; + final tickHz = args.length > 1 ? int.parse(args[1]) : 12000000; + final ticks = args.length > 2 ? int.parse(args[2]) : 5; + + final isa = RiscVIsaConfig(mxlen: RiscVMxlen.rv32, extensions: [rv32i]); + final prog = RiverTimerPollDemo( + isa: isa, + uartBase: 0x10000000, + clintBase: 0x02000000, + tickHz: tickHz, + ticks: ticks, + ); + await prog.build(); + final payload = prog.generateBytes(); + + final sum = payload.fold(0, (a, b) => (a + b) & 0xff); + final frame = [ + payload.length & 0xff, + (payload.length >> 8) & 0xff, + ...payload, + sum, + ]; + await File('$base.bin').writeAsBytes(payload); + await File('$base.hex').writeAsString( + frame.map((b) => b.toRadixString(16).padLeft(2, '0')).join('\n'), + ); + stdout.writeln( + 'wrote $base.bin / $base.hex: ${payload.length}-byte payload, ' + '${frame.length}-byte frame, tickHz=$tickHz, ticks=$ticks', + ); +} diff --git a/packages/river_maskrom/bin/river_load.dart b/packages/river_maskrom/bin/river_load.dart new file mode 100644 index 0000000..bf023a5 --- /dev/null +++ b/packages/river_maskrom/bin/river_load.dart @@ -0,0 +1,39 @@ +import 'dart:io'; + +/// Send a raw binary to the River serial boot monitor. +/// +/// Usage: `dart run river_maskrom:river_load [device]` +/// (device defaults to /dev/ttyACM0). +/// +/// Keep a terminal (e.g. `picocom -b 115200`) attached in another window to +/// see the monitor's K/E verdict and the program's output. picocom holds the +/// port settings, this tool only writes the frame. With no terminal attached, +/// configure the port first: `stty -F /dev/ttyACM0 115200 raw`. +Future main(List args) async { + if (args.isEmpty) { + stderr.writeln('usage: river_load [device]'); + exit(64); + } + final bin = await File(args[0]).readAsBytes(); + final dev = args.length > 1 ? args[1] : '/dev/ttyACM0'; + if (bin.length > 0xffff) { + stderr.writeln('payload too large: ${bin.length} bytes (max 65535)'); + exit(65); + } + + final sum = bin.fold(0, (a, b) => (a + b) & 0xff); + final frame = [bin.length & 0xff, (bin.length >> 8) & 0xff, ...bin, sum]; + + // Plain write-only: append mode seeks to end-of-file on open, which a tty + // (a character device) rejects with an illegal-seek error. + final port = File(dev).openSync(mode: FileMode.writeOnly); + // writeFromSync is a direct write syscall, and a tty rejects fsync with + // EINVAL, so there is deliberately no flush here. + port.writeFromSync(frame); + port.closeSync(); + + stdout.writeln( + 'sent ${bin.length}-byte payload (+3 framing) to $dev, ' + 'checksum 0x${sum.toRadixString(16).padLeft(2, '0')}', + ); +} diff --git a/packages/river_maskrom/lib/river_maskrom.dart b/packages/river_maskrom/lib/river_maskrom.dart new file mode 100644 index 0000000..229dd29 --- /dev/null +++ b/packages/river_maskrom/lib/river_maskrom.dart @@ -0,0 +1,20 @@ +library; + +export 'src/ddr_diag.dart'; +export 'src/ddr_eye_sweep.dart'; +export 'src/ddr_level.dart'; +export 'src/ddr_level_xilinx.dart'; +export 'src/ddr_probe.dart'; +export 'src/ddr_sweep_probe.dart'; +export 'src/ddr_test.dart'; +export 'src/ddr_verify.dart'; +export 'src/dram_exec.dart'; +export 'src/dram_ping.dart'; +export 'src/dram_stress.dart'; +export 'src/bundle_selftest.dart'; +export 'src/flash_hexdump.dart'; +export 'src/hello_world.dart'; +export 'src/serial_monitor.dart'; +export 'src/timer_poll_demo.dart'; +export 'src/trap_wfi_test.dart'; +export 'src/maskrom.dart'; diff --git a/packages/river_maskrom/lib/src/bundle_selftest.dart b/packages/river_maskrom/lib/src/bundle_selftest.dart new file mode 100644 index 0000000..a1276d3 --- /dev/null +++ b/packages/river_maskrom/lib/src/bundle_selftest.dart @@ -0,0 +1,178 @@ +import 'dart:typed_data'; + +import 'package:river/river.dart'; +import 'package:river_adl/river_adl.dart'; + +/// Boot-ROM diagnostic mirroring the bundled-flash boot (copy flash -> SRAM, +/// jump) but instrumented at every boundary so one boot localizes which layer +/// breaks when the real bundle is silent. +/// +/// UART sequence: +/// "A\r\n" boot + UART alive +/// "F:\r\n" + 64-byte dump lbu XIP read from [flashSource] +/// "B\r\n" flash dump done (read path did not hang) +/// (copy [copyWords] words flash -> SRAM, exactly as the maskrom does) +/// "S:\r\n" + 64-byte dump read SRAM back: proves the copy landed +/// "C\r\n" copy done +/// "J\r\n" about to jalr into SRAM +/// firmware takes over the UART here +/// +/// Last thing seen localizes the break: no output = structural (PLL/reset/UART); +/// stall after "A" = flash read hangs; zero/garbage flash dump = flash-read lane +/// wrong on silicon; stall after "J" = the jalr into SRAM is broken. +/// +/// All control flow is PC-relative; only [uartBase]/[flashSource]/[copyDest] are +/// absolute. +class RiverBundleSelfTest extends Module { + @override + final RiscVIsaConfig isa; + + /// Absolute flash XIP address the firmware lives at (flash base + offset). + final int flashSource; + + /// Absolute SRAM address the maskrom copies into and jumps to. + final int copyDest; + + /// Number of 32-bit words to copy (the maskrom's copySize / 4). + final int copyWords; + + /// Bytes dumped from each window (flash and SRAM). Multiple of 16. + final int probeBytes; + + int _labelSeq = 0; + + RiverBundleSelfTest({ + required this.isa, + required int uartBase, + required this.flashSource, + required this.copyDest, + required this.copyWords, + this.probeBytes = 64, + int clockHz = 12000000, + int baud = 115200, + }) { + // Configure the ns16550a for 8N1 at the requested baud (mandatory on real + // hardware: the UART gates TX on a non-zero divisor that resets to 0). + final divisor = (clockHz ~/ baud).clamp(1, 0xffff); + register(Register.x13).bind(li(uartBase)); + register(Register.x11).bind(li(0x83)); // LCR: DLAB=1, 8N1 + sb(register(Register.x13), register(Register.x11), offset: 3); + register(Register.x11).bind(li(divisor & 0xff)); + sb(register(Register.x13), register(Register.x11), offset: 0); + register(Register.x11).bind(li((divisor >> 8) & 0xff)); + sb(register(Register.x13), register(Register.x11), offset: 1); + register(Register.x11).bind(li(0x03)); // LCR: DLAB=0, 8N1 + sb(register(Register.x13), register(Register.x11), offset: 3); + + _sendStr('A\r\n'); // boot + UART alive + + _sendStr('F:\r\n'); + _dumpWindow(flashSource, probeBytes); // flash read on silicon + _sendStr('B\r\n'); + + _copyWords(flashSource, copyDest, copyWords); // mirror the maskrom copy + + _sendStr('S:\r\n'); + _dumpWindow(copyDest, probeBytes); // copy landed real bytes? + _sendStr('C\r\n'); + + _sendStr('J\r\n'); + fence(); + register(Register.x5).bind(li(copyDest)); + jalr(register(Register.x5)); // run the firmware, exactly like the maskrom + + // Safety trap if the jump ever returns. + final trap = label('trap'); + jal(trap); + } + + /// Copy [nwords] words from flash [src] to SRAM [dst] via lw/sw, the exact + /// word-aligned loop the maskrom runs (same flash-read lane path as the boot). + void _copyWords(int src, int dst, int nwords) { + // Single loop-carried pointer (x10); dst recomputed each iteration as + // x10 + (dst - src). A separate `dst += 4` read only across the back-edge is + // dropped by the non-loop-aware dead-code pass. Scratch avoids x13 (UART base + // held by _send*); use x16 (delta) / x17 (dst) / x15 (word). + register(Register.x10).bind(li(src)); + register(Register.x16).bind(li(dst - src)); + register(Register.x12).bind(li(src + nwords * 4)); + final loop = label('copy${_labelSeq++}'); + register(Register.x15).bind(lw(register(Register.x10))); + register( + Register.x17, + ).bind(add(register(Register.x10), register(Register.x16))); + sw(register(Register.x17), register(Register.x15)); + register(Register.x10).bind(addi(register(Register.x10), 4)); + bne(register(Register.x10), register(Register.x12), loop); + } + + /// Hex-dump [length] bytes from absolute [base] via lbu: "OOOOOOOO: HH ..\r\n". + void _dumpWindow(int base, int length) { + register(Register.x10).bind(li(base)); // read cursor + register(Register.x12).bind(li(base + length)); // end + register(Register.x15).bind(li(0)); // running offset for the label + final lineLoop = label('line${_labelSeq++}'); + _sendHexWord(Register.x15); + _sendImm(0x3a); // ':' + _sendImm(0x20); // ' ' + register(Register.x17).bind(li(0)); // column counter + final byteLoop = label('byte${_labelSeq++}'); + register(Register.x16).bind(lbu(register(Register.x10))); + _sendHexByte(Register.x16); + _sendImm(0x20); + register(Register.x10).bind(addi(register(Register.x10), 1)); + register(Register.x17).bind(addi(register(Register.x17), 1)); + register(Register.x18).bind(li(16)); + bne(register(Register.x17), register(Register.x18), byteLoop); + _sendImm(0x0d); + _sendImm(0x0a); + register(Register.x15).bind(addi(register(Register.x15), 16)); + bne(register(Register.x10), register(Register.x12), lineLoop); + } + + void _sendStr(String s) { + for (final ch in s.codeUnits) { + _sendImm(ch); + } + } + + /// Polls LSR (offset 5) bit 5 (THRE), then writes x11 to THR (offset 0). + void _sendX11() { + final wait = label('txw${_labelSeq++}'); + final lsr = lbu(register(Register.x13), offset: 5); + register(Register.x14).bind(andi(lsr, 0x20)); + beq(register(Register.x14), register(Register.x0), wait); + sb(register(Register.x13), register(Register.x11)); + } + + void _sendImm(int ch) { + register(Register.x11).bind(li(ch & 0xff)); + _sendX11(); + } + + /// Branchless nibble-to-ASCII (avoids the ADL dead-store-across-branch bug). + void _sendHexNibble(DataField value) { + final n = andi(value, 0xf); + register(Register.x18).bind(n); + final ltTen = slti(register(Register.x18), 10); + final geTenMask = addi(ltTen, -1); + final adj = andi(geTenMask, 0x27); + final base = addi(register(Register.x18), 0x30); + register(Register.x11).bind(add(base, adj)); + _sendX11(); + } + + void _sendHexByte(Register reg) { + _sendHexNibble(srli(register(reg), 4)); + _sendHexNibble(register(reg)); + } + + void _sendHexWord(Register reg) { + for (var shift = 28; shift >= 0; shift -= 4) { + _sendHexNibble(srli(register(reg), shift)); + } + } + + /// Raw machine code for baking into a boot ROM's init data. + Uint8List generateBytes() => Uint8List.fromList(generateBinary()); +} diff --git a/packages/river_maskrom/lib/src/ddr_diag.dart b/packages/river_maskrom/lib/src/ddr_diag.dart new file mode 100644 index 0000000..c36a32f --- /dev/null +++ b/packages/river_maskrom/lib/src/ddr_diag.dart @@ -0,0 +1,315 @@ +import 'dart:typed_data'; + +import 'package:river/river.dart'; +import 'package:river_adl/river_adl.dart'; + +/// DDR3 combined write-delay x read-setting leveling sweep firmware (creek +/// OrangeCrab). Tests whether any (write-DQS-delay, read-setting) combo makes a +/// write round-trip. If every pass shows SCANDONE0, no combo works and the +/// problem is analog. +/// +/// Train-control registers (8-byte strided, decoded on bus[5:3], at +/// [trainCtrlBase] = dramBase + dramSize = 0x88000000 on creek): +/// reg0 +0x00 RDTAP target (7-bit DELAYF read tap, 0..127) +/// reg1 +0x08 CTL bit0 SET (load RDTAP target into the delay walk) +/// reg2 +0x10 RDSLACK read-window slack cycles +/// reg4 +0x20 READCLKSEL 3-bit DQSBUFM read-gate select +/// reg7 +0x38 WRDLY write-DQS delay, 4 bits PER LANE. Writing it latches +/// the tap AND flips the apply toggle, so firmware then +/// OWNS the write delay (overrides write-leveling). +/// Both lanes set the same: value = (tap<<4)|tap. +/// DRAM array base = [dramBase] (0x80000000). +/// +/// FOUR nested RUNTIME loops (body emitted once, no Dart unroll), 8*4*4*2 = 256: +/// WRDLY tap in 0..7 (OUTER, 8) - write reg7=(tap<<4)|tap +/// RDTAP in {0,32,64,96} (4) - write reg0 + pulse reg1 SET +/// READCLKSEL in {0,2,4,6} (4) - write reg4 +/// RDSLACK in {2,4} (INNER, 2) - write reg2 +/// Each register program is followed by a fixed-delay countdown, not a STATUS +/// busy-poll, so the sweep cannot hang on a flag that never fires. +/// +/// Per combo: fresh write of three distinct words to the DRAM base +/// 0x11112222 -> dramBase+0 0x33334444 -> dramBase+4 0x55556666 -> +8 +/// a warm-up `lw`, then read back and compare all three (bne per word). First +/// match prints `HIT W R C S V`. Each pass ends +/// `SCANDONE` then loops forever (UART-glitch tolerance). +/// +/// The printer is INLINE (no subroutine): a subroutine-based printer streamed a +/// stuck constant on silicon. 12345678 prints first as a liveness check. +/// +/// Register allocation (printer reads x13/x14, clobbers x15..x18): +/// x13 = uartBase x14 = print value x15..x18 = printer scratch +/// x10/x11/x12 = address/data scratch (printer never touches them) +/// x27 = WRDLY tap x26 = RDTAP x25 = READCLKSEL x24 = RDSLACK (counters) +/// x4/x5/x6 = read-back words x20 = match count x21 = found flag +/// x22 = fixed-delay countdown scratch (separate from the counters) +class RiverDdrDiag extends Module { + @override + final RiscVIsaConfig isa; + + RiverDdrDiag({ + required this.isa, + required int uartBase, + required int dramBase, + required int trainCtrlBase, + int clockHz = 48000000, + int baud = 115200, + }) { + // Train-control register addresses (8-byte strided, decoded on bus[5:3]). + final regRdtap = trainCtrlBase + 0x00; // reg0 (7-bit DELAYF read tap) + final regCtl = trainCtrlBase + 0x08; // reg1 (bit0 SET) + final regRdslack = trainCtrlBase + 0x10; // reg2 (read-window slack) + final regReadClkSel = + trainCtrlBase + 0x20; // reg4 (3-bit DQS read-gate sel) + final regWrDly = trainCtrlBase + 0x38; // reg7 (write-DQS delay, per lane) + + // The three distinct words written + checked at the DRAM base each combo. + const w0 = 0x11112222; + const w1 = 0x33334444; + const w2 = 0x55556666; + + // Sweep extents (runtime, body emitted once). Counters STEP by the listed + // increment and stop at the listed (exclusive) top: + // WRDLY tap 0..7 step 1 top 8 -> 8 values + // RDTAP 0..96 step 32 top 128 -> {0,32,64,96}, 4 values + // READCLKSEL 0..6 step 2 top 8 -> {0,2,4,6}, 4 values + // RDSLACK 2,4 step 2 top 6 -> {2,4}, 2 values + const wrdlyTop = 8; + const rdtapStep = 32; + const rdtapTop = 128; + const rcsStep = 2; + const rcsTop = 8; + const slkStart = 2; + const slkStep = 2; + const slkTop = 6; + + // Fixed-delay countdown after each control-register program. No STATUS + // busy-poll, so the sweep can never hang on a flag. + const fixedDelay = 2000; + + // ns16550a setup (the divisor gates the transmitter). x13 holds uartBase for + // the whole program (the inline hex/crlf printers read it). + final divisor = (clockHz ~/ baud).clamp(1, 0xffff); + register(Register.x13).bind(li(uartBase)); + register(Register.x11).bind(li(0x83)); // LCR: DLAB=1, 8N1 + sb(register(Register.x13), register(Register.x11), offset: 3); + register(Register.x11).bind(li(divisor & 0xff)); // DLL + sb(register(Register.x13), register(Register.x11), offset: 0); + register(Register.x11).bind(li((divisor >> 8) & 0xff)); // DLM + sb(register(Register.x13), register(Register.x11), offset: 1); + register(Register.x11).bind(li(0x03)); // LCR: DLAB=0, 8N1 + sb(register(Register.x13), register(Register.x11), offset: 3); + + // 1. Liveness: this line must read 12345678 so we know the core is alive. + // Printed FIRST, via the INLINE printer, BEFORE any control access. + register(Register.x14).bind(li(0x12345678)); + _printHexX14(); + _crlf(); + + // Combined WRDLY x read-grid sweep. x27=WRDLY tap, x26=RDTAP, x25=READCLKSEL, + // x24=RDSLACK, x4/x5/x6=read-back words, x20=match count, x21=found flag. + final sweepTop = label('swtop'); + + // Reset the per-pass trackers at the top of every pass. + register(Register.x20).bind(li(0)); // match count + register(Register.x21).bind(li(0)); // found flag + + // ---- WRDLY (OUTER) ---- + register(Register.x27).bind(li(0)); // WRDLY tap + final wrdlyTopLbl = label('swwrdly'); + + // Program reg7 WRDLY = (tap<<4)|tap (both lanes), then fixed delay. + register(Register.x10).bind(li(regWrDly)); + register( + Register.x11, + ).bind(or(slli(register(Register.x27), 4), register(Register.x27))); + sw(register(Register.x10), register(Register.x11)); + _fixedDelay(fixedDelay); + + // ---- RDTAP ---- + register(Register.x26).bind(li(0)); // RDTAP + final rdtapTopLbl = label('swrdtap'); + + // Program reg0 RDTAP target = x26, then pulse reg1 CTL bit0 SET to load the + // delay walk. Then a FIXED delay (no STATUS busy-poll). + register(Register.x10).bind(li(regRdtap)); + sw(register(Register.x10), register(Register.x26)); + register(Register.x10).bind(li(regCtl)); + register(Register.x11).bind(li(0x1)); // SET + sw(register(Register.x10), register(Register.x11)); + _fixedDelay(fixedDelay); + + // ---- READCLKSEL ---- + register(Register.x25).bind(li(0)); // READCLKSEL + final rcsTopLbl = label('swrcs'); + + // Program reg4 READCLKSEL = x25. Then a FIXED delay. + register(Register.x10).bind(li(regReadClkSel)); + sw(register(Register.x10), register(Register.x25)); + _fixedDelay(fixedDelay); + + // ---- RDSLACK (INNER) ---- + register(Register.x24).bind(li(slkStart)); // RDSLACK starts at 2 + final slkTopLbl = label('swslk'); + + // Program reg2 RDSLACK = x24. Then a FIXED delay. + register(Register.x10).bind(li(regRdslack)); + sw(register(Register.x10), register(Register.x24)); + _fixedDelay(fixedDelay); + + // FRESH WRITE of the three distinct words to the DRAM base (plain `sw`, the + // same path ddrtest uses). + register(Register.x10).bind(li(dramBase + 0x0)); + register(Register.x11).bind(li(w0)); + sw(register(Register.x10), register(Register.x11)); + register(Register.x10).bind(li(dramBase + 0x4)); + register(Register.x11).bind(li(w1)); + sw(register(Register.x10), register(Register.x11)); + register(Register.x10).bind(li(dramBase + 0x8)); + register(Register.x11).bind(li(w2)); + sw(register(Register.x10), register(Register.x11)); + + // Warm-up read (absorb write->read turnaround), then read the three words + // into x4..x6. Plain `lw` acks even on a bad eye (rdTimeout floor), no hang. + register(Register.x10).bind(li(dramBase + 0x0)); + register(Register.x12).bind(lw(register(Register.x10))); // warm-up + register(Register.x10).bind(li(dramBase + 0x0)); + register(Register.x4).bind(lw(register(Register.x10))); // rb0 + register(Register.x10).bind(li(dramBase + 0x4)); + register(Register.x5).bind(lw(register(Register.x10))); // rb1 + register(Register.x10).bind(li(dramBase + 0x8)); + register(Register.x6).bind(lw(register(Register.x10))); // rb2 + + // MATCH = all three readback words equal. Any mismatch bne's to mFail, + // skipping the hit handling. + final mFail = label('swmfail'); + register(Register.x11).bind(li(w0)); + bne(register(Register.x4), register(Register.x11), mFail); + register(Register.x11).bind(li(w1)); + bne(register(Register.x5), register(Register.x11), mFail); + register(Register.x11).bind(li(w2)); + bne(register(Register.x6), register(Register.x11), mFail); + + // All three matched: count it, and on the first match print HIT with the + // actual readback (x4 must read 11112222), then latch the found flag. + register( + Register.x20, + ).bind(addi(register(Register.x20), 1)); // match count++ + final notFirst = label('swnotfirst'); + bne( + register(Register.x21), + register(Register.x0), + notFirst, + ); // already found + register(Register.x21).bind(li(1)); // latch found + _printStr('HIT W'); + register(Register.x14).bind(mv(register(Register.x27))); // WRDLY tap + _printHexX14(); + _printStr(' R'); + register(Register.x14).bind(mv(register(Register.x26))); // RDTAP + _printHexX14(); + _printStr(' C'); + register(Register.x14).bind(mv(register(Register.x25))); // READCLKSEL + _printHexX14(); + _printStr(' S'); + register(Register.x14).bind(mv(register(Register.x24))); // RDSLACK + _printHexX14(); + _printStr(' V'); + register( + Register.x14, + ).bind(mv(register(Register.x4))); // ACTUAL readback rb0 + _printHexX14(); + _crlf(); + placeLabel(notFirst); + placeLabel(mFail); + + // ---- INNER step: RDSLACK += 2; repeat while < slkTop ({2,4}) ---- + register(Register.x24).bind(addi(register(Register.x24), slkStep)); + register(Register.x11).bind(li(slkTop)); + blt(register(Register.x24), register(Register.x11), slkTopLbl); + + // ---- READCLKSEL step: += 2; repeat while < rcsTop ({0,2,4,6}) ---- + register(Register.x25).bind(addi(register(Register.x25), rcsStep)); + register(Register.x11).bind(li(rcsTop)); + blt(register(Register.x25), register(Register.x11), rcsTopLbl); + + // ---- RDTAP step: += 32; repeat while < rdtapTop ({0,32,64,96}) ---- + register(Register.x26).bind(addi(register(Register.x26), rdtapStep)); + register(Register.x11).bind(li(rdtapTop)); + blt(register(Register.x26), register(Register.x11), rdtapTopLbl); + + // ---- WRDLY (OUTER) step: += 1; repeat while < wrdlyTop (0..7) ---- + register(Register.x27).bind(addi(register(Register.x27), 1)); + register(Register.x11).bind(li(wrdlyTop)); + blt(register(Register.x27), register(Register.x11), wrdlyTopLbl); + + // 3. End of pass: print SCANDONE. + _printStr('SCANDONE'); + register(Register.x14).bind(mv(register(Register.x20))); + _printHexX14(); + _crlf(); + + // 4. Loop forever (a fresh sweep streams each pass; FPGA reconfig eats the + // first UART bytes, so streaming clean copies is the readable path). + jal(sweepTop); + } + + /// Fixed-delay countdown loop (no STATUS poll). Counts [count] down in x22, + /// a dedicated register clear of the loop counters and printer registers. + void _fixedDelay(int count) { + register(Register.x22).bind(li(count)); + final delay = label('dly'); + register(Register.x22).bind(addi(register(Register.x22), -1)); + bne(register(Register.x22), register(Register.x0), delay); + } + + /// Prints x14 as eight uppercase hex digits, MSB first. Inline at every + /// callsite. Reads x13 (uartBase) and x14; clobbers x15..x18. + void _printHexX14() { + register(Register.x17).bind(li(0x3A)); + register(Register.x18).bind(li(28)); + final nibble = label('nib'); + register( + Register.x15, + ).bind(srl(register(Register.x14), register(Register.x18))); + register(Register.x15).bind(andi(register(Register.x15), 0xF)); + register(Register.x15).bind(addi(register(Register.x15), 0x30)); + final noAdjust = Label('noadj'); + blt(register(Register.x15), register(Register.x17), noAdjust); + register(Register.x15).bind(addi(register(Register.x15), 7)); + placeLabel(noAdjust); + final poll = label('p'); + final lsr = lbu(register(Register.x13), offset: 5); + register(Register.x16).bind(andi(lsr, 0x20)); + beq(register(Register.x16), register(Register.x0), poll); + sb(register(Register.x13), register(Register.x15)); + register(Register.x18).bind(addi(register(Register.x18), -4)); + bge(register(Register.x18), register(Register.x0), nibble); + } + + /// Transmits a single byte, polling the LSR THRE bit first. + void _printChar(int ch) { + final poll = label('p'); + final lsr = lbu(register(Register.x13), offset: 5); + register(Register.x16).bind(andi(lsr, 0x20)); + beq(register(Register.x16), register(Register.x0), poll); + register(Register.x15).bind(li(ch)); + sb(register(Register.x13), register(Register.x15)); + } + + /// Transmits an ASCII string byte by byte (immediates only, no data table). + void _printStr(String s) { + for (final ch in s.codeUnits) { + _printChar(ch); + } + } + + void _crlf() { + for (final ch in const [0x0D, 0x0A]) { + _printChar(ch); + } + } + + /// Raw machine code for a monitor load frame. + Uint8List generateBytes() => Uint8List.fromList(generateBinary()); +} diff --git a/packages/river_maskrom/lib/src/ddr_eye_sweep.dart b/packages/river_maskrom/lib/src/ddr_eye_sweep.dart new file mode 100644 index 0000000..e8db2c7 --- /dev/null +++ b/packages/river_maskrom/lib/src/ddr_eye_sweep.dart @@ -0,0 +1,530 @@ +import 'dart:typed_data'; + +import 'package:river/river.dart'; +import 'package:river_adl/river_adl.dart'; + +/// DDR3 read-leveling eye-sweep firmware (creek OrangeCrab), built on the +/// ddrdiag run-structure. +/// +/// Control + DRAM both work (STATUS=0x400 = DLL_LOCK[10]=1 but DATAVALID[8]=0 / +/// BURSTDET[9]=0, so the DQS read eye is not centred). This sweeps the +/// read-leveling knobs to find where DATAVALID / BURSTDET fire and a written +/// pattern reads back. +/// +/// Train-control registers (8-byte strided, decoded on bus[5:3], at +/// [trainCtrlBase] = dramBase + dramSize = 0x88000000 on creek): +/// reg0 +0x00 RDTAP target (7-bit DELAYF read tap, 0..127) +/// reg1 +0x08 CTL bit0 SET (load RDTAP target into the delay walk) +/// reg2 +0x10 RDSLACK read-window slack cycles +/// reg3 +0x18 STATUS (read-only) busy[0], curTap[7:1], DATAVALID[8], +/// BURSTDET[9], DLL_LOCK[10], BDET_SEEN[11], DVALID_SEEN[12] +/// reg4 +0x20 READCLKSEL 3-bit DQSBUFM read-gate select (0..7) +/// DRAM array base = [dramBase] (0x80000000). +/// +/// Sequence: +/// 1. UART init + `12345678` liveness, and a one-shot `DLL=` STATUS +/// snapshot (proves control READ works). +/// 2. THREE nested RUNTIME loops (body emitted once, no Dart unroll): RDTAP in +/// {0,8,..,120} (16) x READCLKSEL 0..7 (8) x RDSLACK 0..4 (5) = 640 combos. +/// Each combo: program reg0=RDTAP + pulse reg1 SET, reg4=RCS, reg2=SLK; +/// write the 4-word C0DE pattern; warm-up read; read 4 words + STATUS. +/// MATCH judged by DATA (4 readback words == pattern), not flags. Prints +/// only when INTERESTING (MATCH, or STATUS DVALID_SEEN[12]/BDET_SEEN[11]): +/// `EYE TAP= RCS= SLK= ST= W0= [MATCH]` +/// 3. Summary, looped for UART-glitch tolerance: +/// `EYEBEST TAP= RCS= SLK=` first full-C0DE MATCH (or NONE) +/// `EYEDV TAP= RCS= SLK=` first DV/BD seen (or NONE) +/// +/// DRAM read-back uses plain `lw`, which acks even on a bad eye (rdTimeout +/// floor), so no access can stall the sweep. Pure-ROM, position independent +/// except for the absolute UART / train-control / DRAM addresses. +class RiverDdrEyeSweep extends Module { + @override + final RiscVIsaConfig isa; + + RiverDdrEyeSweep({ + required this.isa, + required int uartBase, + required int dramBase, + required int trainCtrlBase, + int clockHz = 48000000, + int baud = 115200, + }) { + // Train-control register addresses (8-byte strided, decoded on bus[5:3]). + final regRdtap = trainCtrlBase + 0x00; // reg0 (7-bit DELAYF read tap) + final regCtl = trainCtrlBase + 0x08; // reg1 (bit0 SET) + final regRdslack = trainCtrlBase + 0x10; // reg2 (read-window slack) + final regStatus = trainCtrlBase + 0x18; // reg3 (read-only) + final regReadClkSel = + trainCtrlBase + 0x20; // reg4 (3-bit DQS read-gate sel) + + // The 4-word C0DE pattern written + checked at the DRAM base each combo. + const pat0 = 0xC0DE0000; + const pat1 = 0xC0DE1111; + const pat2 = 0xC0DE2222; + const pat3 = 0xC0DE3333; + + // Sweep extents (runtime, body emitted once). + const tapStep = 8; // RDTAP {0,8,...,120} + const tapTop = 121; // while tap < 121 (0..120) -> 16 steps + const rcsTop = 8; // READCLKSEL 0..7 + const slkTop = 5; // RDSLACK 0..4 + + // ns16550a setup (the divisor gates the transmitter). x13 holds uartBase for + // the whole program (the hex/crlf printers read it). EXACTLY ddrdiag's setup. + final divisor = (clockHz ~/ baud).clamp(1, 0xffff); + register(Register.x13).bind(li(uartBase)); + register(Register.x11).bind(li(0x83)); // LCR: DLAB=1, 8N1 + sb(register(Register.x13), register(Register.x11), offset: 3); + register(Register.x11).bind(li(divisor & 0xff)); // DLL + sb(register(Register.x13), register(Register.x11), offset: 0); + register(Register.x11).bind(li((divisor >> 8) & 0xff)); // DLM + sb(register(Register.x13), register(Register.x11), offset: 1); + register(Register.x11).bind(li(0x03)); // LCR: DLAB=0, 8N1 + sb(register(Register.x13), register(Register.x11), offset: 3); + + // 1. Liveness: this line must read 12345678 so we know the core is alive. + register(Register.x14).bind(li(0x12345678)); + _printHexX14(); + _crlf(); + + // reg7 WRDLY is the per-lane 4-bit write pointer ([3:0]=lane0, [7:4]=lane1, + // auto-applies on write). Set it once to the env-baked WRPTR before the pass. + const wrPtr = 0; + final regWrDly = trainCtrlBase + 0x38; + register(Register.x10).bind(li(regWrDly)); + register(Register.x11).bind(li(wrPtr)); + sw(register(Register.x10), register(Register.x11)); + + // Beat/lane scramble decoder. A written value rereads stable, but each fresh + // write lands in a rotating set of wrong values, so the defect is a write + // beat/lane placement, not the read eye. Write a counting pattern (4 words = + // 16 bytes 00..0F: 0x03020100 07060504 0B0A0908 0F0E0D0C) so the readback + // reveals which byte lands where. Print "P w0 w1 w2 w3" per pass: identical + // every pass = fixed permutation; rotating = per-burst gearbox phase. + // x4..x7 = readback, x11 = write scratch, x10 = addr. + final passTop = label('passtop'); + + // Rewrite the 4-word counting pattern each pass (fresh write burst). + register(Register.x10).bind(li(dramBase + 0x0)); + register(Register.x11).bind(li(0x03020100)); + sw(register(Register.x10), register(Register.x11)); + register(Register.x10).bind(li(dramBase + 0x4)); + register(Register.x11).bind(li(0x07060504)); + sw(register(Register.x10), register(Register.x11)); + register(Register.x10).bind(li(dramBase + 0x8)); + register(Register.x11).bind(li(0x0B0A0908)); + sw(register(Register.x10), register(Register.x11)); + register(Register.x10).bind(li(dramBase + 0xC)); + register(Register.x11).bind(li(0x0F0E0D0C)); + sw(register(Register.x10), register(Register.x11)); + + // Read the 4 words back into x4..x7 (warm-up read first). + register(Register.x10).bind(li(dramBase + 0x0)); + register(Register.x14).bind(lw(register(Register.x10))); // warm-up + register(Register.x10).bind(li(dramBase + 0x0)); + register(Register.x4).bind(lw(register(Register.x10))); + register(Register.x10).bind(li(dramBase + 0x4)); + register(Register.x5).bind(lw(register(Register.x10))); + register(Register.x10).bind(li(dramBase + 0x8)); + register(Register.x6).bind(lw(register(Register.x10))); + register(Register.x10).bind(li(dramBase + 0xC)); + register(Register.x7).bind(lw(register(Register.x10))); + + _printStr('P '); + register(Register.x14).bind(addi(register(Register.x4), 0)); + _printHexX14(); + _printChar(0x20); + register(Register.x14).bind(addi(register(Register.x5), 0)); + _printHexX14(); + _printChar(0x20); + register(Register.x14).bind(addi(register(Register.x6), 0)); + _printHexX14(); + _printChar(0x20); + register(Register.x14).bind(addi(register(Register.x7), 0)); + _printHexX14(); + _crlf(); + + jal(passTop); + return; + + // ignore: dead_code + // Nested read-leveling sweep: outer RDTAP x27 {0,8,..,120}, inner READCLKSEL + // x26 {0..7}. For each combo: program rdtap(reg0)+pulse SET(reg1), program + // READCLKSEL(reg4), write pattern to dramBase, read back, beq-match. + register(Register.x11).bind(li(0x40DE0001)); // pattern (bit31 clear) + register(Register.x12).bind(li(0x1)); // CTL.SET pulse value + register(Register.x27).bind(li(0)); // rdtap + final calTapTop = label('caltaptop'); + register(Register.x10).bind(li(regRdtap)); + sw(register(Register.x10), register(Register.x27)); // rdtap target + register(Register.x10).bind(li(regCtl)); + sw(register(Register.x10), register(Register.x12)); // pulse SET (load walk) + register(Register.x26).bind(li(0)); // rcs + final calRcsTop = label('calrcstop'); + register(Register.x10).bind(li(regReadClkSel)); + sw(register(Register.x10), register(Register.x26)); // READCLKSEL + register(Register.x10).bind(li(dramBase)); + sw(register(Register.x10), register(Register.x11)); // write pattern + register(Register.x24).bind(lw(register(Register.x10))); // read back + final calOk = label('calok'); + beq(register(Register.x24), register(Register.x11), calOk); + register(Register.x26).bind(addi(register(Register.x26), 1)); + register(Register.x18).bind(li(8)); + final calRcsDone = label('calrcsdone'); + beq(register(Register.x26), register(Register.x18), calRcsDone); + jal(calRcsTop); + placeLabel(calRcsDone); + register(Register.x27).bind(addi(register(Register.x27), 8)); + register(Register.x18).bind(li(128)); + final calNone = label('calnone'); + beq(register(Register.x27), register(Register.x18), calNone); + jal(calTapTop); + // NONE - loop printing the last DRAM read value (how wrong) + status. + placeLabel(calNone); + final calNoneLoop = label('calnoneloop'); + register(Register.x10).bind(li(dramBase)); + register(Register.x24).bind(lw(register(Register.x10))); + _printStr('NONE DR='); + register(Register.x14).bind(addi(register(Register.x24), 0)); + _printHexX14(); + _crlf(); + jal(calNoneLoop); + // OK - loop printing the winning tap + rcs forever. + placeLabel(calOk); + final calOkLoop = label('calokloop'); + _printStr('OK t'); + register(Register.x14).bind(addi(register(Register.x27), 0)); + _printHexX14(); + _printStr(' r'); + register(Register.x14).bind(addi(register(Register.x26), 0)); + _printHexX14(); + _crlf(); + jal(calOkLoop); + return; + + // ignore: dead_code + // One-shot STATUS (reg3) snapshot of DLL lock (like ddrdiag's RDOK proof + // that a control READ acks). `DLL=`. + register(Register.x10).bind(li(regStatus)); + register(Register.x24).bind(lw(register(Register.x10))); + _printStr('DLL='); + register(Register.x14).bind(andi(srli(register(Register.x24), 10), 0x1)); + _printHexX14(); + _crlf(); + + // EYE sweep. x27=RDTAP (OUTER), x26=READCLKSEL (MID), x25=RDSLACK (INNER), + // x4..x7=read-back words, x8=STATUS snapshot, x9=MATCH flag. Trackers: + // x20=best-found, x21/x22/x23=best TAP/RCS/SLK, x28=dv-found, + // x29/x30/x31=first-dv TAP/RCS/SLK. + register(Register.x20).bind(li(0)); // best-found flag + register(Register.x28).bind(li(0)); // dv-found flag + + register(Register.x27).bind(li(0)); // RDTAP + final tapTopLbl = label('eyetap'); + + // Program RDTAP target (reg0) = x27, then pulse reg1 SET to load the walk. + register(Register.x10).bind(li(regRdtap)); + sw(register(Register.x10), register(Register.x27)); + register(Register.x10).bind(li(regCtl)); + register(Register.x11).bind(li(0x1)); // SET + sw(register(Register.x10), register(Register.x11)); + + register(Register.x26).bind(li(0)); // READCLKSEL + final rcsTopLbl = label('eyercs'); + + // Program READCLKSEL (reg4) = x26. + register(Register.x10).bind(li(regReadClkSel)); + sw(register(Register.x10), register(Register.x26)); + + register(Register.x25).bind(li(0)); // RDSLACK + final slkTopLbl = label('eyeslk'); + + // Program RDSLACK (reg2) = x25. + register(Register.x10).bind(li(regRdslack)); + sw(register(Register.x10), register(Register.x25)); + + // Write the 4-word C0DE pattern to DRAM base (plain sw, same as ddrtest). + register(Register.x10).bind(li(dramBase + 0x0)); + register(Register.x11).bind(li(pat0)); + sw(register(Register.x10), register(Register.x11)); + register(Register.x10).bind(li(dramBase + 0x4)); + register(Register.x11).bind(li(pat1)); + sw(register(Register.x10), register(Register.x11)); + register(Register.x10).bind(li(dramBase + 0x8)); + register(Register.x11).bind(li(pat2)); + sw(register(Register.x10), register(Register.x11)); + register(Register.x10).bind(li(dramBase + 0xC)); + register(Register.x11).bind(li(pat3)); + sw(register(Register.x10), register(Register.x11)); + + // Warm-up read (absorb write->read turnaround), then read 4 words into + // x4..x7. Plain `lw` acks even on a bad eye (rdTimeout floor), no hang. + register(Register.x10).bind(li(dramBase + 0x0)); + register(Register.x14).bind(lw(register(Register.x10))); // warm-up + register(Register.x10).bind(li(dramBase + 0x0)); + register(Register.x4).bind(lw(register(Register.x10))); // w0 + register(Register.x10).bind(li(dramBase + 0x4)); + register(Register.x5).bind(lw(register(Register.x10))); // w1 + register(Register.x10).bind(li(dramBase + 0x8)); + register(Register.x6).bind(lw(register(Register.x10))); // w2 + register(Register.x10).bind(li(dramBase + 0xC)); + register(Register.x7).bind(lw(register(Register.x10))); // w3 + + // Snapshot STATUS (reg3) for this combo (DV/BD seen bits + the raw value). + register(Register.x10).bind(li(regStatus)); + register(Register.x8).bind(lw(register(Register.x10))); + + // MATCH = (w0==pat0) & (w1==pat1) & (w2==pat2) & (w3==pat3). Build x9: start + // 1, clear to 0 on any mismatch. + register(Register.x9).bind(li(1)); + final mFail = label('eyemfail'); + register(Register.x11).bind(li(pat0)); + final mc1 = label('eyemc1'); + beq(register(Register.x4), register(Register.x11), mc1); + jal(mFail); + placeLabel(mc1); + register(Register.x11).bind(li(pat1)); + final mc2 = label('eyemc2'); + beq(register(Register.x5), register(Register.x11), mc2); + jal(mFail); + placeLabel(mc2); + register(Register.x11).bind(li(pat2)); + final mc3 = label('eyemc3'); + beq(register(Register.x6), register(Register.x11), mc3); + jal(mFail); + placeLabel(mc3); + register(Register.x11).bind(li(pat3)); + final mc4 = label('eyemc4'); + beq(register(Register.x7), register(Register.x11), mc4); + jal(mFail); + placeLabel(mc4); + final mNext = label('eyemnext'); + jal(mNext); + placeLabel(mFail); + register(Register.x9).bind(li(0)); // mismatch + placeLabel(mNext); + + // x12 = DV-or-BD seen for this combo = STATUS[12] | STATUS[11] (nonzero if + // the strobe fired anywhere on this combo). STATUS bits [12:11] -> srli 11, + // mask 0x3. + register(Register.x12).bind(andi(srli(register(Register.x8), 11), 0x3)); + + // INTERESTING = MATCH (x9!=0) OR DV-or-BD seen (x12!=0). x11 = x9|x12; if + // x11==0 skip the whole print block (keeps UART readable). + register( + Register.x11, + ).bind(or(register(Register.x9), register(Register.x12))); + final eyeSkip = label('eyeskip'); + beq(register(Register.x11), register(Register.x0), eyeSkip); + + // Print: EYE TAP= RCS= SLK= ST= W0= [MATCH] + _printStr('EYE TAP='); + register(Register.x14).bind(mv(register(Register.x27))); + _printHexX14(); + _printStr(' RCS='); + register(Register.x14).bind(mv(register(Register.x26))); + _printHexX14(); + _printStr(' SLK='); + register(Register.x14).bind(mv(register(Register.x25))); + _printHexX14(); + _printStr(' ST='); + register(Register.x14).bind(mv(register(Register.x8))); + _printHexX14(); + _printStr(' W0='); + register(Register.x14).bind(mv(register(Register.x4))); + _printHexX14(); + // " MATCH" only when all four words matched (x9 != 0). + final noMatchTag = label('eyenomatch'); + beq(register(Register.x9), register(Register.x0), noMatchTag); + _printStr(' MATCH'); + placeLabel(noMatchTag); + _crlf(); + placeLabel(eyeSkip); + + // Latch EYEBEST: FIRST fully-matching combo. Record only if x9 (match) and + // not already latched (x20==0). + final bestDone = label('eyebestdone'); + beq(register(Register.x9), register(Register.x0), bestDone); // no match + register(Register.x11).bind(li(1)); + beq( + register(Register.x20), + register(Register.x11), + bestDone, + ); // already set + register(Register.x20).bind(li(1)); // latch best-found + register(Register.x21).bind(mv(register(Register.x27))); // best TAP + register(Register.x22).bind(mv(register(Register.x26))); // best RCS + register(Register.x23).bind(mv(register(Register.x25))); // best SLK + placeLabel(bestDone); + + // Latch EYEDV: FIRST combo where DATAVALID-seen OR BURSTDET-seen was set. + // Record only if x12 (dv-or-bd) nonzero and not already latched (x28==0). + final dvDone = label('eyedvdone'); + beq(register(Register.x12), register(Register.x0), dvDone); // no strobe + register(Register.x11).bind(li(1)); + beq(register(Register.x28), register(Register.x11), dvDone); // already set + register(Register.x28).bind(li(1)); // latch dv-found + register(Register.x29).bind(mv(register(Register.x27))); // first-dv TAP + register(Register.x30).bind(mv(register(Register.x26))); // first-dv RCS + register(Register.x31).bind(mv(register(Register.x25))); // first-dv SLK + placeLabel(dvDone); + + // INNER step: RDSLACK += 1; repeat while < slkTop (0..4). + register(Register.x25).bind(addi(register(Register.x25), 1)); + register(Register.x11).bind(li(slkTop)); + blt(register(Register.x25), register(Register.x11), slkTopLbl); + + // MID step: READCLKSEL += 1; repeat while < rcsTop (0..7). + register(Register.x26).bind(addi(register(Register.x26), 1)); + register(Register.x11).bind(li(rcsTop)); + blt(register(Register.x26), register(Register.x11), rcsTopLbl); + + // OUTER step: RDTAP += tapStep; repeat while < tapTop ({0,8,..,120}). + register(Register.x27).bind(addi(register(Register.x27), tapStep)); + register(Register.x11).bind(li(tapTop)); + blt(register(Register.x27), register(Register.x11), tapTopLbl); + + // Summary, looped 3x for UART-glitch tolerance (x19 = counter): + // EYEBEST TAP= RCS= SLK= (first full match) or NONE + // EYEDV TAP= RCS= SLK= (first strobe) or NONE + register(Register.x19).bind(li(0)); + final sumTop = label('eyesumtop'); + + // EYEBEST line. + _printStr('EYEBEST '); + final bestNone = label('eyebestnone'); + beq(register(Register.x20), register(Register.x0), bestNone); + _printStr('TAP='); + register(Register.x14).bind(mv(register(Register.x21))); + _printHexX14(); + _printStr(' RCS='); + register(Register.x14).bind(mv(register(Register.x22))); + _printHexX14(); + _printStr(' SLK='); + register(Register.x14).bind(mv(register(Register.x23))); + _printHexX14(); + final bestSumDone = label('eyebestsumdone'); + jal(bestSumDone); + placeLabel(bestNone); + _printStr('NONE'); + placeLabel(bestSumDone); + _crlf(); + + // EYEDV line. + _printStr('EYEDV '); + final dvNone = label('eyedvnone'); + beq(register(Register.x28), register(Register.x0), dvNone); + _printStr('TAP='); + register(Register.x14).bind(mv(register(Register.x29))); + _printHexX14(); + _printStr(' RCS='); + register(Register.x14).bind(mv(register(Register.x30))); + _printHexX14(); + _printStr(' SLK='); + register(Register.x14).bind(mv(register(Register.x31))); + _printHexX14(); + final dvSumDone = label('eyedvsumdone'); + jal(dvSumDone); + placeLabel(dvNone); + _printStr('NONE'); + placeLabel(dvSumDone); + _crlf(); + + // Repeat the summary block 3 times total. + register(Register.x19).bind(addi(register(Register.x19), 1)); + register(Register.x11).bind(li(3)); + blt(register(Register.x19), register(Register.x11), sumTop); + + // Loop the summary forever: streaming clean EYEBEST/EYEDV copies is the + // readable path through the FPGA-reconfig UART glitch. + final tailTop = label('eyetailtop'); + _printStr('EYEBEST '); + final bestNone2 = label('eyebestnone2'); + beq(register(Register.x20), register(Register.x0), bestNone2); + _printStr('TAP='); + register(Register.x14).bind(mv(register(Register.x21))); + _printHexX14(); + _printStr(' RCS='); + register(Register.x14).bind(mv(register(Register.x22))); + _printHexX14(); + _printStr(' SLK='); + register(Register.x14).bind(mv(register(Register.x23))); + _printHexX14(); + final bestSumDone2 = label('eyebestsumdone2'); + jal(bestSumDone2); + placeLabel(bestNone2); + _printStr('NONE'); + placeLabel(bestSumDone2); + _crlf(); + + _printStr('EYEDV '); + final dvNone2 = label('eyedvnone2'); + beq(register(Register.x28), register(Register.x0), dvNone2); + _printStr('TAP='); + register(Register.x14).bind(mv(register(Register.x29))); + _printHexX14(); + _printStr(' RCS='); + register(Register.x14).bind(mv(register(Register.x30))); + _printHexX14(); + _printStr(' SLK='); + register(Register.x14).bind(mv(register(Register.x31))); + _printHexX14(); + final dvSumDone2 = label('eyedvsumdone2'); + jal(dvSumDone2); + placeLabel(dvNone2); + _printStr('NONE'); + placeLabel(dvSumDone2); + _crlf(); + jal(tailTop); + } + + /// Prints x14 as eight uppercase hex digits, MSB first. + void _printHexX14() { + register(Register.x17).bind(li(0x3A)); + register(Register.x18).bind(li(28)); + final nibble = label('nib'); + register( + Register.x15, + ).bind(srl(register(Register.x14), register(Register.x18))); + register(Register.x15).bind(andi(register(Register.x15), 0xF)); + register(Register.x15).bind(addi(register(Register.x15), 0x30)); + final noAdjust = Label('noadj'); + blt(register(Register.x15), register(Register.x17), noAdjust); + register(Register.x15).bind(addi(register(Register.x15), 7)); + placeLabel(noAdjust); + final poll = label('p'); + final lsr = lbu(register(Register.x13), offset: 5); + register(Register.x16).bind(andi(lsr, 0x20)); + beq(register(Register.x16), register(Register.x0), poll); + sb(register(Register.x13), register(Register.x15)); + register(Register.x18).bind(addi(register(Register.x18), -4)); + bge(register(Register.x18), register(Register.x0), nibble); + } + + /// Transmits a single byte, polling the LSR THRE bit first. + void _printChar(int ch) { + final poll = label('p'); + final lsr = lbu(register(Register.x13), offset: 5); + register(Register.x16).bind(andi(lsr, 0x20)); + beq(register(Register.x16), register(Register.x0), poll); + register(Register.x15).bind(li(ch)); + sb(register(Register.x13), register(Register.x15)); + } + + /// Transmits an ASCII string byte by byte (immediates only, no data table). + void _printStr(String s) { + for (final ch in s.codeUnits) { + _printChar(ch); + } + } + + void _crlf() { + for (final ch in const [0x0D, 0x0A]) { + _printChar(ch); + } + } + + /// Raw machine code for a monitor load frame. + Uint8List generateBytes() => Uint8List.fromList(generateBinary()); +} diff --git a/packages/river_maskrom/lib/src/ddr_level.dart b/packages/river_maskrom/lib/src/ddr_level.dart new file mode 100644 index 0000000..7406ade --- /dev/null +++ b/packages/river_maskrom/lib/src/ddr_level.dart @@ -0,0 +1,874 @@ +import 'dart:typed_data'; + +import 'package:river/river.dart'; +import 'package:river_adl/river_adl.dart'; + +/// DDR3 read-leveling eye-sweep firmware (OrangeCrab). The read eye is centered +/// by the DELAYF read tap (reg0 RDTAP + reg1 SET), the knob that makes DATAVALID +/// / BURSTDET fire. This sweeps it (plus READCLKSEL and RDSLACK) while +/// writing+reading a known pattern to find where the array reads back correctly. +/// +/// THREE nested RUNTIME loops, body emitted once (no Dart unroll): +/// OUTER RDTAP in {0,8,..,120} (16; reg0=tap, reg1 SET pulse) +/// MID READCLKSEL in 0..7 (reg4) -> 8 +/// INNER RDSLACK in 0..7 (reg2) -> 8 +/// = 1024 combos. READCLKSEL[1:0] also selects the PHY per-DQ BitSlip read-beat +/// rotation (RCS 0/4->slp0, 1/5->slp1, 2/6->slp2, 3/7->slp3). RDSLACK also moves +/// the PHY fabric read-capture anchor cycle (rdPipe[clSys + rdSlackRt]). +/// +/// Per combo: write the 4-word C0DE pattern +/// [0xC0DE0000, 0xC0DE1111, 0xC0DE2222, 0xC0DE3333] +/// to DRAM base, warm-up read, then read back and compare. MATCH judged by DATA +/// (4 words == pattern), not the DV/BD flags. Prints only INTERESTING combos +/// (MATCH, or STATUS DATAVALID-seen[12]/BURSTDET-seen[11] set): +/// `LVL TAP= RCS= SLK= -> DV= BD=` +/// Summary (looped for UART-glitch tolerance): +/// `LVLBEST TAP= RCS= SLK=` first full match, or NONE +/// `LVLDV TAP= RCS=` first DV/BD-seen combo, or NONE +/// +/// Train-control registers (8-byte strided, address bits [5:3], at +/// [trainCtrlBase] = dramBase + dramSize on creek): +/// reg0 +0x00 RDTAP target (7-bit DELAYF read tap, 0..127) +/// reg1 +0x08 CTL bit0 SET (load RDTAP target into the delay walk) +/// reg2 +0x10 RDSLACK read-window slack cycles +/// reg3 +0x18 STATUS (read-only) DATAVALID[8], BURSTDET[9], DLL_LOCK[10], +/// BDET_SEEN[11], DVALID_SEEN[12] +/// reg4 +0x20 READCLKSEL 3-bit DQSBUFM read-gate select (0..7) +/// +/// Pure ROM, runtime loops. Only the four DRAM words at the base are touched. +class RiverDdrLevel extends Module { + @override + final RiscVIsaConfig isa; + + RiverDdrLevel({ + required this.isa, + required int uartBase, + required int dramBase, + required int trainCtrlBase, + int clockHz = 48000000, + int baud = 115200, + }) { + // Train-control register addresses (8-byte strided, decoded on bus[5:3]). + final regRdtap = trainCtrlBase + 0x00; // reg0 (7-bit DELAYF read tap) + final regCtl = trainCtrlBase + 0x08; // reg1 (bit0 SET) + final regRdslack = trainCtrlBase + 0x10; // reg2 (read-window slack) + final regStatus = trainCtrlBase + 0x18; // reg3 (read-only) + final regReadClkSel = + trainCtrlBase + 0x20; // reg4 (3-bit DQS read-gate sel) + final regWlres = trainCtrlBase + 0x30; // reg6 (read-only WL-RESULT) + final regWrdly = trainCtrlBase + 0x38; // reg7 WRDLY (per-lane tap + dir) + final regWtrim = + trainCtrlBase + 0x40; // reg8 WRITE-TRIM (lane0 DYNDELAY[7:0]) + + // The 4-word C0DE pattern written + checked at the DRAM base each combo. + const pat0 = 0xC0DE0000; + const pat1 = 0xC0DE1111; + const pat2 = 0xC0DE2222; + const pat3 = 0xC0DE3333; + + // Sweep extents (runtime, body emitted once). + const tapStep = 8; // RDTAP {0,8,...,120} + const tapTop = 121; // exclusive-ish: while tap < 121 (0..120) + const rcsTop = 8; // READCLKSEL 0..7 + const slkTop = 8; // RDSLACK 0..7 (now also moves the fabric capture anchor) + + // ns16550a setup (the divisor gates the transmitter). x13 holds uartBase for + // the whole program (the hex/crlf printers read it). + final divisor = (clockHz ~/ baud).clamp(1, 0xffff); + register(Register.x13).bind(li(uartBase)); + register(Register.x11).bind(li(0x83)); // LCR: DLAB=1, 8N1 + sb(register(Register.x13), register(Register.x11), offset: 3); + register(Register.x11).bind(li(divisor & 0xff)); // DLL + sb(register(Register.x13), register(Register.x11), offset: 0); + register(Register.x11).bind(li((divisor >> 8) & 0xff)); // DLM + sb(register(Register.x13), register(Register.x11), offset: 1); + register(Register.x11).bind(li(0x03)); // LCR: DLAB=0, 8N1 + sb(register(Register.x13), register(Register.x11), offset: 3); + + // Printer self-test: this line must read 12345678 so we know the core is + // alive before the sweep. + register(Register.x14).bind(li(0x12345678)); + _printHexX14(); + _crlf(); + + // DIAG: one-shot STATUS (reg3) snapshot of the sticky read-path flags before + // the sweep: DLL lock, BURSTDET-seen[11], DATAVALID-seen[12]. + register(Register.x10).bind(li(regStatus)); + register(Register.x24).bind(lw(register(Register.x10))); + _printStr('DIAG DLL='); + register(Register.x14).bind(andi(srli(register(Register.x24), 10), 0x1)); + _printHexX14(); + _printStr(' BDET='); + register(Register.x14).bind(andi(srli(register(Register.x24), 11), 0x1)); + _printHexX14(); + _printStr(' DVAL='); + register(Register.x14).bind(andi(srli(register(Register.x24), 12), 0x1)); + _printHexX14(); + _crlf(); + + // EYE sweep. x27=RDTAP (OUTER), x26=READCLKSEL (MID), x25=RDSLACK (INNER), + // x4..x7=read-back words, x8=STATUS snapshot, x9=MATCH flag. Trackers: + // x20=best-found, x21/x22/x23=best TAP/RCS/SLK, x28=dv-found, + // x29/x30=first-dv TAP/RCS. + register(Register.x20).bind(li(0)); // best-found flag + register(Register.x28).bind(li(0)); // dv-found flag + + register(Register.x27).bind(li(0)); // RDTAP + final tapTopLbl = label('lvltap'); + + // Program RDTAP target (reg0) = x27, then pulse reg1 SET to load the walk. + register(Register.x10).bind(li(regRdtap)); + sw(register(Register.x10), register(Register.x27)); + register(Register.x10).bind(li(regCtl)); + register(Register.x11).bind(li(0x1)); // SET + sw(register(Register.x10), register(Register.x11)); + + register(Register.x26).bind(li(0)); // READCLKSEL + final rcsTopLbl = label('lvlrcs'); + + // Program READCLKSEL (reg4) = x26. + register(Register.x10).bind(li(regReadClkSel)); + sw(register(Register.x10), register(Register.x26)); + + register(Register.x25).bind(li(0)); // RDSLACK + final slkTopLbl = label('lvlslk'); + + // Program RDSLACK (reg2) = x25. + register(Register.x10).bind(li(regRdslack)); + sw(register(Register.x10), register(Register.x25)); + + // Write the 4-word C0DE pattern to DRAM base. + register(Register.x10).bind(li(dramBase + 0x0)); + register(Register.x11).bind(li(pat0)); + sw(register(Register.x10), register(Register.x11)); + register(Register.x10).bind(li(dramBase + 0x4)); + register(Register.x11).bind(li(pat1)); + sw(register(Register.x10), register(Register.x11)); + register(Register.x10).bind(li(dramBase + 0x8)); + register(Register.x11).bind(li(pat2)); + sw(register(Register.x10), register(Register.x11)); + register(Register.x10).bind(li(dramBase + 0xC)); + register(Register.x11).bind(li(pat3)); + sw(register(Register.x10), register(Register.x11)); + + // Warm-up read (absorb the write->read turnaround beat), then capture the + // four words into x4..x7. + register(Register.x10).bind(li(dramBase + 0x0)); + register(Register.x14).bind(lw(register(Register.x10))); // warm-up + register(Register.x10).bind(li(dramBase + 0x0)); + register(Register.x4).bind(lw(register(Register.x10))); // w0 + register(Register.x10).bind(li(dramBase + 0x4)); + register(Register.x5).bind(lw(register(Register.x10))); // w1 + register(Register.x10).bind(li(dramBase + 0x8)); + register(Register.x6).bind(lw(register(Register.x10))); // w2 + register(Register.x10).bind(li(dramBase + 0xC)); + register(Register.x7).bind(lw(register(Register.x10))); // w3 + + // Snapshot STATUS (reg3) for the DV/BD-seen bits of this combo. + register(Register.x10).bind(li(regStatus)); + register(Register.x8).bind(lw(register(Register.x10))); + + // MATCH = (w0==pat0) & (w1==pat1) & (w2==pat2) & (w3==pat3). Build x9: start + // 1, clear to 0 on any mismatch. + register(Register.x9).bind(li(1)); + final mNext = label('lvlmnext'); + final mFail = label('lvlmfail'); + register(Register.x11).bind(li(pat0)); + final mc1 = label('lvlmc1'); + beq(register(Register.x4), register(Register.x11), mc1); + jal(mFail); + placeLabel(mc1); + register(Register.x11).bind(li(pat1)); + final mc2 = label('lvlmc2'); + beq(register(Register.x5), register(Register.x11), mc2); + jal(mFail); + placeLabel(mc2); + register(Register.x11).bind(li(pat2)); + final mc3 = label('lvlmc3'); + beq(register(Register.x6), register(Register.x11), mc3); + jal(mFail); + placeLabel(mc3); + register(Register.x11).bind(li(pat3)); + final mc4 = label('lvlmc4'); + beq(register(Register.x7), register(Register.x11), mc4); + jal(mFail); + placeLabel(mc4); + jal(mNext); + placeLabel(mFail); + register(Register.x9).bind(li(0)); // mismatch + placeLabel(mNext); + + // x12 = DV-or-BD seen for this combo = STATUS[12] | STATUS[11] (nonzero if + // the strobe fired anywhere on this combo). + register(Register.x12).bind(andi(srli(register(Register.x8), 11), 0x3)); + + // INTERESTING = MATCH (x9!=0) OR DV-or-BD seen (x12!=0). Compute x11 = + // x9|x12; if x11==0 skip the whole print block. + register( + Register.x11, + ).bind(or(register(Register.x9), register(Register.x12))); + final lvlSkip = label('lvlskip'); + beq(register(Register.x11), register(Register.x0), lvlSkip); + + // Print: LVL TAP= RCS= SLK= -> DV= BD= + _printStr('LVL TAP='); + register(Register.x14).bind(mv(register(Register.x27))); + _printHexX14(); + _printStr(' RCS='); + register(Register.x14).bind(mv(register(Register.x26))); + _printHexX14(); + _printStr(' SLK='); + register(Register.x14).bind(mv(register(Register.x25))); + _printHexX14(); + _printStr(' -> '); + register(Register.x14).bind(mv(register(Register.x4))); + _printHexX14(); + _printChar(0x20); + register(Register.x14).bind(mv(register(Register.x5))); + _printHexX14(); + _printStr(' DV='); + register(Register.x14).bind(andi(srli(register(Register.x8), 12), 0x1)); + _printHexX14(); + _printStr(' BD='); + register(Register.x14).bind(andi(srli(register(Register.x8), 11), 0x1)); + _printHexX14(); + _crlf(); + placeLabel(lvlSkip); + + // Latch LVLBEST: FIRST fully-matching combo. Record only if x9 (match) and + // not already latched (x20==0). + final bestDone = label('lvlbestdone'); + beq(register(Register.x9), register(Register.x0), bestDone); // no match + register(Register.x11).bind(li(1)); + beq( + register(Register.x20), + register(Register.x11), + bestDone, + ); // already set + register(Register.x20).bind(li(1)); // latch best-found + register(Register.x21).bind(mv(register(Register.x27))); // best TAP + register(Register.x22).bind(mv(register(Register.x26))); // best RCS + register(Register.x23).bind(mv(register(Register.x25))); // best SLK + placeLabel(bestDone); + + // Latch LVLDV: FIRST combo where DATAVALID-seen OR BURSTDET-seen was set. + // Record only if x12 (dv-or-bd) nonzero and not already latched (x28==0). + final dvDone = label('lvldvdone'); + beq(register(Register.x12), register(Register.x0), dvDone); // no strobe + register(Register.x11).bind(li(1)); + beq(register(Register.x28), register(Register.x11), dvDone); // already set + register(Register.x28).bind(li(1)); // latch dv-found + register(Register.x29).bind(mv(register(Register.x27))); // first-dv TAP + register(Register.x30).bind(mv(register(Register.x26))); // first-dv RCS + placeLabel(dvDone); + + // INNER step: RDSLACK += 1; repeat while < slkTop (0..7). + register(Register.x25).bind(addi(register(Register.x25), 1)); + register(Register.x11).bind(li(slkTop)); + blt(register(Register.x25), register(Register.x11), slkTopLbl); + + // MID step: READCLKSEL += 1; repeat while < rcsTop (0..7). + register(Register.x26).bind(addi(register(Register.x26), 1)); + register(Register.x11).bind(li(rcsTop)); + blt(register(Register.x26), register(Register.x11), rcsTopLbl); + + // OUTER step: RDTAP += tapStep; repeat while < tapTop ({0,8,..,120}). + register(Register.x27).bind(addi(register(Register.x27), tapStep)); + register(Register.x11).bind(li(tapTop)); + blt(register(Register.x27), register(Register.x11), tapTopLbl); + + // Summary, looped 3x for UART-glitch tolerance (x19 = counter): + // LVLBEST TAP= RCS= SLK= (first full match) or NONE + // LVLDV TAP= RCS= (first strobe) or NONE + register(Register.x19).bind(li(0)); + final sumTop = label('lvlsumtop'); + + // LVLBEST line. + _printStr('LVLBEST '); + final bestNone = label('lvlbestnone'); + beq(register(Register.x20), register(Register.x0), bestNone); + _printStr('TAP='); + register(Register.x14).bind(mv(register(Register.x21))); + _printHexX14(); + _printStr(' RCS='); + register(Register.x14).bind(mv(register(Register.x22))); + _printHexX14(); + _printStr(' SLK='); + register(Register.x14).bind(mv(register(Register.x23))); + _printHexX14(); + final bestSumDone = label('lvlbestsumdone'); + jal(bestSumDone); + placeLabel(bestNone); + _printStr('NONE'); + placeLabel(bestSumDone); + _crlf(); + + // LVLDV line. + _printStr('LVLDV '); + final dvNone = label('lvldvnone'); + beq(register(Register.x28), register(Register.x0), dvNone); + _printStr('TAP='); + register(Register.x14).bind(mv(register(Register.x29))); + _printHexX14(); + _printStr(' RCS='); + register(Register.x14).bind(mv(register(Register.x30))); + _printHexX14(); + final dvSumDone = label('lvldvsumdone'); + jal(dvSumDone); + placeLabel(dvNone); + _printStr('NONE'); + placeLabel(dvSumDone); + _crlf(); + + // Repeat the summary block 3 times total. + register(Register.x19).bind(addi(register(Register.x19), 1)); + register(Register.x11).bind(li(3)); + blt(register(Register.x19), register(Register.x11), sumTop); + + // Layer-2 additive-WRDLY calibration sweep. Remaining bug is the DQ1/5/9 + // rise-beat float (0x0222 OR-mask on word0). reg7 WRDLY is additive: each + // per-lane offset retards the DQSW270 launch on top of the WL-trained pos + // (preserving WL strobe-centering). The sweep finds the per-lane offset that + // clears the float plus the read combo (RCS/SLK) that reads it back clean. + // Ordering: read WLRES, spin until wlDone==1 before any reg7 write (the + // additive base wlBasePos latches only once WL replay completes). Do not + // reset the controller between WL and the sweep (that clobbers wlBasePos). + register(Register.x10).bind(li(regWlres)); + register(Register.x24).bind(lw(register(Register.x10))); + _printStr('WLRES lane0='); + register(Register.x14).bind(andi(register(Register.x24), 0xF)); + _printHexX14(); + _printStr(' lane1='); + register(Register.x14).bind(andi(srli(register(Register.x24), 4), 0xF)); + _printHexX14(); + _printStr(' done='); + register(Register.x14).bind(andi(srli(register(Register.x24), 8), 0x1)); + _printHexX14(); + _crlf(); + + // SPIN until reg6[8] (wlDone) == 1 - WL replay must complete (wlBasePos + // latched) before any additive reg7 apply. + final wlWaitLbl = label('wlwait'); + register(Register.x10).bind(li(regWlres)); + register(Register.x11).bind(lw(register(Register.x10))); + register(Register.x11).bind(andi(srli(register(Register.x11), 8), 0x1)); + beq(register(Register.x11), register(Register.x0), wlWaitLbl); + + const wp0 = 0x40DE0000; + const wp1 = 0x40DE1111; + const wp2 = 0x40DE2222; + const wp3 = 0x40DE3333; + + // Park RDTAP=0 (reg0=0 + reg1 SET) once - the live read eye (Layer-1 data). + register(Register.x10).bind(li(regRdtap)); + register(Register.x11).bind(li(0)); + sw(register(Register.x10), register(Register.x11)); // reg0 RDTAP target = 0 + register(Register.x10).bind(li(regCtl)); + register(Register.x11).bind(li(0x1)); // SET: load the tap walk + sw(register(Register.x10), register(Register.x11)); + + // 4 nested loops, body emitted once. x25=RCS (reg4) {0,1,2} OUTER, x26=SLK + // (reg2) 0..7, x27=lane0Off (WRDLY [3:0]) 0..3, x28=lane1Off (WRDLY [7:4]) + // 0..3 INNER = 384 combos. CALBEST (first CLR): x20 found, x21 RCS, x22 SLK, + // x23 l0, x24 l1. Word results x4..x7. + const calWrDir = + 0; // WRDIRECTION (reg7 bit8); flip to 1 if dir=0 clears none + register(Register.x20).bind(li(0)); // CALBEST found flag + + register(Register.x25).bind(li(0)); // RCS + final calRcsLbl = label('calrcs'); + register(Register.x26).bind(li(0)); // SLK + final calSlkLbl = label('calslk'); + register(Register.x27).bind(li(0)); // lane0Off + final calL0Lbl = label('call0'); + register(Register.x28).bind(li(0)); // lane1Off + final calL1Lbl = label('call1'); + + // Program reg4=RCS, reg2=SLK. + register(Register.x10).bind(li(regReadClkSel)); + sw(register(Register.x10), register(Register.x25)); // reg4 READCLKSEL = RCS + register(Register.x10).bind(li(regRdslack)); + sw(register(Register.x10), register(Register.x26)); // reg2 RDSLACK = SLK + // reg7 = (calWrDir<<8) | (lane1Off<<4) | lane0Off (additive per-lane offset; + // the reg7 edge steps each lane to WL_base + laneOff). + register(Register.x11).bind(slli(register(Register.x28), 4)); // lane1Off<<4 + register( + Register.x11, + ).bind(or(register(Register.x11), register(Register.x27))); + if (calWrDir != 0) { + register(Register.x12).bind(li(calWrDir << 8)); + register( + Register.x11, + ).bind(or(register(Register.x11), register(Register.x12))); + } + register(Register.x10).bind(li(regWrdly)); + sw(register(Register.x10), register(Register.x11)); // apply edge -> WRMOVE + + // Write the 4-word pattern to dramBase 0x0/0x4/0x8/0xC. + register(Register.x10).bind(li(dramBase + 0x0)); + register(Register.x11).bind(li(wp0)); + sw(register(Register.x10), register(Register.x11)); + register(Register.x10).bind(li(dramBase + 0x4)); + register(Register.x11).bind(li(wp1)); + sw(register(Register.x10), register(Register.x11)); + register(Register.x10).bind(li(dramBase + 0x8)); + register(Register.x11).bind(li(wp2)); + sw(register(Register.x10), register(Register.x11)); + register(Register.x10).bind(li(dramBase + 0xC)); + register(Register.x11).bind(li(wp3)); + sw(register(Register.x10), register(Register.x11)); + + // Warm-up read (absorb write->read turnaround), then read w0..w3. + register(Register.x10).bind(li(dramBase + 0x0)); + register(Register.x14).bind(lw(register(Register.x10))); // warm-up + register(Register.x10).bind(li(dramBase + 0x0)); + register(Register.x4).bind(lw(register(Register.x10))); // w0 + register(Register.x10).bind(li(dramBase + 0x4)); + register(Register.x5).bind(lw(register(Register.x10))); // w1 + register(Register.x10).bind(li(dramBase + 0x8)); + register(Register.x6).bind(lw(register(Register.x10))); // w2 + register(Register.x10).bind(li(dramBase + 0xC)); + register(Register.x7).bind(lw(register(Register.x10))); // w3 + + // Score CLR (x12) iff all 4 words land exactly; Z0 (x19) iff (w0&0x0222)==0. + register(Register.x12).bind(li(1)); // CLR, cleared on any mismatch + final calClrFail = label('calclrfail'); + final calClrDone = label('calclrdone'); + register(Register.x11).bind(li(wp0)); + final cc1 = label('calcc1'); + beq(register(Register.x4), register(Register.x11), cc1); + jal(calClrFail); + placeLabel(cc1); + register(Register.x11).bind(li(wp1)); + final cc2 = label('calcc2'); + beq(register(Register.x5), register(Register.x11), cc2); + jal(calClrFail); + placeLabel(cc2); + register(Register.x11).bind(li(wp2)); + final cc3 = label('calcc3'); + beq(register(Register.x6), register(Register.x11), cc3); + jal(calClrFail); + placeLabel(cc3); + register(Register.x11).bind(li(wp3)); + final cc4 = label('calcc4'); + beq(register(Register.x7), register(Register.x11), cc4); + jal(calClrFail); + placeLabel(cc4); + jal(calClrDone); + placeLabel(calClrFail); + register(Register.x12).bind(li(0)); // a word mismatched + placeLabel(calClrDone); + // Z0 = ((w0 & 0x0222) == 0) ? 1 : 0. + register(Register.x11).bind(andi(register(Register.x4), 0x222)); + register(Register.x19).bind(li(0)); + final calNoZ0Set = label('calnoz0set'); + bne(register(Register.x11), register(Register.x0), calNoZ0Set); + register(Register.x19).bind(li(1)); // Z0 = float on word0 cleared + placeLabel(calNoZ0Set); + + // Print ONLY if CLR (x12) or Z0 (x19) - keep the UART readable. + register( + Register.x11, + ).bind(or(register(Register.x12), register(Register.x19))); + final calSkip = label('calskip'); + beq(register(Register.x11), register(Register.x0), calSkip); + _printStr('CAL l0='); + register(Register.x14).bind(mv(register(Register.x27))); + _printHexX14(); + _printStr(' l1='); + register(Register.x14).bind(mv(register(Register.x28))); + _printHexX14(); + _printStr(' RCS='); + register(Register.x14).bind(mv(register(Register.x25))); + _printHexX14(); + _printStr(' SLK='); + register(Register.x14).bind(mv(register(Register.x26))); + _printHexX14(); + _printStr(' -> '); + register(Register.x14).bind(mv(register(Register.x4))); + _printHexX14(); + _printChar(0x20); + register(Register.x14).bind(mv(register(Register.x5))); + _printHexX14(); + _printChar(0x20); + register(Register.x14).bind(mv(register(Register.x6))); + _printHexX14(); + _printChar(0x20); + register(Register.x14).bind(mv(register(Register.x7))); + _printHexX14(); + // CLR wins the token; else Z0 (the print gate guarantees at least one). + final calTokZ0 = label('caltokz0'); + final calTokDone = label('caltokdone'); + beq(register(Register.x12), register(Register.x0), calTokZ0); + _printStr(' CLR'); + jal(calTokDone); + placeLabel(calTokZ0); + _printStr(' Z0'); + placeLabel(calTokDone); + _crlf(); + placeLabel(calSkip); + + // Latch CALBEST: FIRST full CLR combo. Record only if CLR (x12!=0) and not + // already latched (x20==0). + final calBestDone = label('calbestdone'); + beq(register(Register.x12), register(Register.x0), calBestDone); // no CLR + register(Register.x11).bind(li(1)); + beq( + register(Register.x20), + register(Register.x11), + calBestDone, + ); // already set + register(Register.x20).bind(li(1)); // latch found + register(Register.x21).bind(mv(register(Register.x25))); // best RCS + register(Register.x22).bind(mv(register(Register.x26))); // best SLK + register(Register.x23).bind(mv(register(Register.x27))); // best lane0Off + register(Register.x24).bind(mv(register(Register.x28))); // best lane1Off + placeLabel(calBestDone); + + // INNER step: lane1Off += 1; repeat while < 4. + register(Register.x28).bind(addi(register(Register.x28), 1)); + register(Register.x11).bind(li(4)); + blt(register(Register.x28), register(Register.x11), calL1Lbl); + // lane0Off step: += 1; repeat while < 4. + register(Register.x27).bind(addi(register(Register.x27), 1)); + register(Register.x11).bind(li(4)); + blt(register(Register.x27), register(Register.x11), calL0Lbl); + // SLK step: += 1; repeat while < 8. + register(Register.x26).bind(addi(register(Register.x26), 1)); + register(Register.x11).bind(li(8)); + blt(register(Register.x26), register(Register.x11), calSlkLbl); + // OUTER RCS step: += 1; repeat while < 3 (RCS {0,1,2}). + register(Register.x25).bind(addi(register(Register.x25), 1)); + register(Register.x11).bind(li(3)); + blt(register(Register.x25), register(Register.x11), calRcsLbl); + + // CALBEST summary, looped 3x for UART-glitch tolerance. x19 = counter (not + // x17/x18, the print helpers). + register(Register.x19).bind(li(0)); + final calSumTop = label('calsumtop'); + _printStr('CALBEST '); + final calBestNone = label('calbestnone'); + beq(register(Register.x20), register(Register.x0), calBestNone); + _printStr('l0='); + register(Register.x14).bind(mv(register(Register.x23))); + _printHexX14(); + _printStr(' l1='); + register(Register.x14).bind(mv(register(Register.x24))); + _printHexX14(); + _printStr(' RCS='); + register(Register.x14).bind(mv(register(Register.x21))); + _printHexX14(); + _printStr(' SLK='); + register(Register.x14).bind(mv(register(Register.x22))); + _printHexX14(); + final calSumDone = label('calsumdone'); + jal(calSumDone); + placeLabel(calBestNone); + _printStr('NONE'); + placeLabel(calSumDone); + _crlf(); + register(Register.x19).bind(addi(register(Register.x19), 1)); + register(Register.x11).bind(li(3)); + blt(register(Register.x19), register(Register.x11), calSumTop); + + // 2-phase write-launch sweep. word0 (first 2 write beats on dqsw270) floats + // ~0x02DE on DQ1/DQ2 because the write launch is off-center vs the DQS + // preamble. Prior write sweeps were confounded by a fixed read combo, but the + // read eye moves per build: + // PHASE 1: find the read eye for word0 (DYNDELAY=0, sweep the read), latch + // (RDTAP,RCS,SLK) where word0 is most readable. + // PHASE 2: at that read eye, sweep the write launch (DYNDELAY + WRDIRECTION) + // and score word0 - the non-confounded write-launch test. + // Stays x0..x30 (x31 is codegen scratch; a tracker there bricks the boot). + const wtpark0 = 0x40DE0000; + const wtpark1 = 0x40DE1111; + const wtpark2 = 0x40DE2222; + const wtpark3 = 0x40DE3333; + + // Helper-free inline: write the 4-word pattern + warm-up read + read word0 + // into x4 (uses x10/x11/x14 scratch). Emitted at each measurement point. + void writeReadW0() { + register(Register.x10).bind(li(dramBase + 0x0)); + register(Register.x11).bind(li(wtpark0)); + sw(register(Register.x10), register(Register.x11)); + register(Register.x10).bind(li(dramBase + 0x4)); + register(Register.x11).bind(li(wtpark1)); + sw(register(Register.x10), register(Register.x11)); + register(Register.x10).bind(li(dramBase + 0x8)); + register(Register.x11).bind(li(wtpark2)); + sw(register(Register.x10), register(Register.x11)); + register(Register.x10).bind(li(dramBase + 0xC)); + register(Register.x11).bind(li(wtpark3)); + sw(register(Register.x10), register(Register.x11)); + register(Register.x10).bind(li(dramBase + 0x0)); + register(Register.x14).bind(lw(register(Register.x10))); // warm-up + register(Register.x10).bind(li(dramBase + 0x0)); + register(Register.x4).bind(lw(register(Register.x10))); // w0 + } + + // --- PHASE 1: find the read eye for word0 (DYNDELAY=0). -------------------- + // Set reg8 DYNDELAY = 0 (no write trim) - measure the READ only. + register(Register.x10).bind(li(regWtrim)); + sw(register(Register.x10), register(Register.x0)); // reg8 = 0 + + // Latched eye: x20 = min (w0 & 0x0FFF) so far (init 0x1000), x21 = best RDTAP, + // x22 = best RCS, x23 = best SLK. x4 = w0. + register(Register.x20).bind(li(0x1000)); // min residue + register(Register.x21).bind(li(0)); // best RDTAP + register(Register.x22).bind(li(0)); // best RCS + register(Register.x23).bind(li(0)); // best SLK + + // 3 nested loops: x25 = RDTAP (0,8,..,120 step 8), x26 = RCS (0..7), x27 = + // SLK (0..7). Step 8 not 16: the word0 eye is at tap 88 (0x58), which a + // step-16 grid skips. + register(Register.x25).bind(li(0)); // RDTAP + final p1TapLbl = label('p1tap'); + register(Register.x26).bind(li(0)); // RCS + final p1RcsLbl = label('p1rcs'); + register(Register.x27).bind(li(0)); // SLK + final p1SlkLbl = label('p1slk'); + + // Program reg0=RDTAP + reg1 SET, reg4=RCS, reg2=SLK. + register(Register.x10).bind(li(regRdtap)); + sw(register(Register.x10), register(Register.x25)); // reg0 RDTAP + register(Register.x10).bind(li(regCtl)); + register(Register.x11).bind(li(0x1)); // SET + sw(register(Register.x10), register(Register.x11)); + register(Register.x10).bind(li(regReadClkSel)); + sw(register(Register.x10), register(Register.x26)); // reg4 RCS + register(Register.x10).bind(li(regRdslack)); + sw(register(Register.x10), register(Register.x27)); // reg2 SLK + + writeReadW0(); + register(Register.x11).bind(andi(register(Register.x4), 0xFFF)); // residue + + // New min? latch (RDTAP,RCS,SLK) = the read eye for word0, and print the + // descent (RDMIN) so the running-min is visible on hardware as it falls. + final p1Skip = label('p1skip'); + register( + Register.x12, + ).bind(slt(register(Register.x11), register(Register.x20))); + beq(register(Register.x12), register(Register.x0), p1Skip); + register(Register.x20).bind(mv(register(Register.x11))); // new min residue + register(Register.x21).bind(mv(register(Register.x25))); // RDTAP + register(Register.x22).bind(mv(register(Register.x26))); // RCS + register(Register.x23).bind(mv(register(Register.x27))); // SLK + _printStr('RDMIN tap='); + register(Register.x14).bind(mv(register(Register.x25))); + _printHexX14(); + _printStr(' rcs='); + register(Register.x14).bind(mv(register(Register.x26))); + _printHexX14(); + _printStr(' slk='); + register(Register.x14).bind(mv(register(Register.x27))); + _printHexX14(); + _printStr(' res='); + register(Register.x14).bind(mv(register(Register.x20))); + _printHexX14(); + _crlf(); + placeLabel(p1Skip); + + // INNER SLK += 1 < 8; RCS += 1 < 8; RDTAP += 8 < 128 (0,8,..,120 = hits 88). + register(Register.x27).bind(addi(register(Register.x27), 1)); + register(Register.x11).bind(li(8)); + blt(register(Register.x27), register(Register.x11), p1SlkLbl); + register(Register.x26).bind(addi(register(Register.x26), 1)); + register(Register.x11).bind(li(8)); + blt(register(Register.x26), register(Register.x11), p1RcsLbl); + register(Register.x25).bind(addi(register(Register.x25), 8)); + register(Register.x11).bind(li(128)); + blt(register(Register.x25), register(Register.x11), p1TapLbl); + + // Print the latched read eye: RDEYE tap=<> rcs=<> slk=<> res=<>. + _printStr('RDEYE tap='); + register(Register.x14).bind(mv(register(Register.x21))); + _printHexX14(); + _printStr(' rcs='); + register(Register.x14).bind(mv(register(Register.x22))); + _printHexX14(); + _printStr(' slk='); + register(Register.x14).bind(mv(register(Register.x23))); + _printHexX14(); + _printStr(' res='); + register(Register.x14).bind(mv(register(Register.x20))); + _printHexX14(); + _crlf(); + + // --- PHASE 2: sweep the write launch at the latched read eye. -------------- + // Program the LATCHED eye (x21 RDTAP + SET, x22 RCS, x23 SLK) ONCE - fixed. + register(Register.x10).bind(li(regRdtap)); + sw(register(Register.x10), register(Register.x21)); // reg0 = best RDTAP + register(Register.x10).bind(li(regCtl)); + register(Register.x11).bind(li(0x1)); // SET + sw(register(Register.x10), register(Register.x11)); + register(Register.x10).bind(li(regReadClkSel)); + sw(register(Register.x10), register(Register.x22)); // reg4 = best RCS + register(Register.x10).bind(li(regRdslack)); + sw(register(Register.x10), register(Register.x23)); // reg2 = best SLK + + // Phase-2 trackers (x21/x22/x23 must stay LIVE - they are the fixed eye, but + // not re-read in phase 2, so reuse only x20/x24/x27..x30): + // x20 = min residue (reinit), x27 = best packed {dyn<<1 | dir}, x24 = best + // w0, x29 = clean flag, x30 = clean packed {dyn<<1 | dir}. + register(Register.x20).bind(li(0x1000)); // phase-2 min residue + register(Register.x29).bind(li(0)); // clean found flag + + // 2 nested loops: x25 = DYNDELAY (0,8,..,120 step 8), x26 = dir (0,1). + register(Register.x25).bind(li(0)); // DYNDELAY + final p2DynLbl = label('p2dyn'); + register(Register.x26).bind(li(0)); // dir + final p2DirLbl = label('p2dir'); + + // Program reg8 = DYNDELAY (x25), reg7 = (dir<<8) (lane0 tap 0, dir bit). + register(Register.x10).bind(li(regWtrim)); + sw(register(Register.x10), register(Register.x25)); // reg8 DYNDELAY + register(Register.x11).bind(slli(register(Register.x26), 8)); // dir<<8 + register(Register.x10).bind(li(regWrdly)); + sw(register(Register.x10), register(Register.x11)); // reg7 WRDLY (dir bit) + + writeReadW0(); + register(Register.x11).bind(andi(register(Register.x4), 0xFFF)); // residue + + // New min? print + latch best. + final p2Skip = label('p2skip'); + register( + Register.x12, + ).bind(slt(register(Register.x11), register(Register.x20))); + beq(register(Register.x12), register(Register.x0), p2Skip); + register(Register.x20).bind(mv(register(Register.x11))); // new min residue + register(Register.x27).bind(slli(register(Register.x25), 1)); // dyn<<1 + register( + Register.x27, + ).bind(or(register(Register.x27), register(Register.x26))); + register(Register.x24).bind(mv(register(Register.x4))); // best w0 + _printStr('WL dyn='); + register(Register.x14).bind(mv(register(Register.x25))); + _printHexX14(); + _printStr(' dir='); + register(Register.x14).bind(mv(register(Register.x26))); + _printHexX14(); + _printStr(' -> w0='); + register(Register.x14).bind(mv(register(Register.x4))); + _printHexX14(); + _crlf(); + placeLabel(p2Skip); + + // CLEAN: latch FIRST (dyn,dir) where w0 == 0x40DE0000. x29 flag, x30 packed. + final p2CleanDone = label('p2cleandone'); + register(Register.x12).bind(li(1)); + beq( + register(Register.x29), + register(Register.x12), + p2CleanDone, + ); // already set + register(Register.x12).bind(li(wtpark0)); + final p2NotClean = label('p2notclean'); + bne(register(Register.x4), register(Register.x12), p2NotClean); + register(Register.x29).bind(li(1)); // clean found + register(Register.x30).bind(slli(register(Register.x25), 1)); // dyn<<1 + register( + Register.x30, + ).bind(or(register(Register.x30), register(Register.x26))); + placeLabel(p2NotClean); + placeLabel(p2CleanDone); + + // INNER dir += 1 < 2; DYNDELAY += 8 < 128. + register(Register.x26).bind(addi(register(Register.x26), 1)); + register(Register.x11).bind(li(2)); + blt(register(Register.x26), register(Register.x11), p2DirLbl); + register(Register.x25).bind(addi(register(Register.x25), 8)); + register(Register.x11).bind(li(128)); + blt(register(Register.x25), register(Register.x11), p2DynLbl); + + // Summary, looped 3x for UART-glitch tolerance. x19 = counter. + register(Register.x19).bind(li(0)); + final wtSumTop = label('wtsumtop'); + // WLBEST: cleanest word0 (global-min residue) - always present. Unpack x27 = + // (dyn<<1 | dir). + _printStr('WLBEST dyn='); + register( + Register.x14, + ).bind(srli(register(Register.x27), 1)); // dyn = x27>>1 + _printHexX14(); + _printStr(' dir='); + register(Register.x14).bind(andi(register(Register.x27), 0x1)); // dir + _printHexX14(); + _printStr(' w0='); + register(Register.x14).bind(mv(register(Register.x24))); + _printHexX14(); + _crlf(); + // WLCLEAN: the (dyn,dir) that hit exact 0x40DE0000, or NONE. Unpack x30. + _printStr('WLCLEAN '); + final wtCleanNone = label('wlcleannone'); + beq(register(Register.x29), register(Register.x0), wtCleanNone); + _printStr('dyn='); + register( + Register.x14, + ).bind(srli(register(Register.x30), 1)); // dyn = x30>>1 + _printHexX14(); + _printStr(' dir='); + register(Register.x14).bind(andi(register(Register.x30), 0x1)); // dir + _printHexX14(); + final wtCleanSumDone = label('wlcleansumdone'); + jal(wtCleanSumDone); + placeLabel(wtCleanNone); + _printStr('NONE'); + placeLabel(wtCleanSumDone); + _crlf(); + register(Register.x19).bind(addi(register(Register.x19), 1)); + register(Register.x11).bind(li(3)); + blt(register(Register.x19), register(Register.x11), wtSumTop); + + final done = label('done'); + jal(done); + } + + /// Prints x14 as eight uppercase hex digits, MSB first. + void _printHexX14() { + register(Register.x17).bind(li(0x3A)); + register(Register.x18).bind(li(28)); + final nibble = label('nib'); + register( + Register.x15, + ).bind(srl(register(Register.x14), register(Register.x18))); + register(Register.x15).bind(andi(register(Register.x15), 0xF)); + register(Register.x15).bind(addi(register(Register.x15), 0x30)); + final noAdjust = Label('noadj'); + blt(register(Register.x15), register(Register.x17), noAdjust); + register(Register.x15).bind(addi(register(Register.x15), 7)); + placeLabel(noAdjust); + final poll = label('p'); + final lsr = lbu(register(Register.x13), offset: 5); + register(Register.x16).bind(andi(lsr, 0x20)); + beq(register(Register.x16), register(Register.x0), poll); + sb(register(Register.x13), register(Register.x15)); + register(Register.x18).bind(addi(register(Register.x18), -4)); + bge(register(Register.x18), register(Register.x0), nibble); + } + + /// Transmits a single byte, polling the LSR THRE bit first. + void _printChar(int ch) { + final poll = label('p'); + final lsr = lbu(register(Register.x13), offset: 5); + register(Register.x16).bind(andi(lsr, 0x20)); + beq(register(Register.x16), register(Register.x0), poll); + register(Register.x15).bind(li(ch)); + sb(register(Register.x13), register(Register.x15)); + } + + /// Transmits an ASCII string byte by byte (immediates only, no data table). + void _printStr(String s) { + for (final ch in s.codeUnits) { + _printChar(ch); + } + } + + void _crlf() { + for (final ch in const [0x0D, 0x0A]) { + _printChar(ch); + } + } + + /// Raw machine code for a monitor load frame. + Uint8List generateBytes() => Uint8List.fromList(generateBinary()); +} diff --git a/packages/river_maskrom/lib/src/ddr_level_xilinx.dart b/packages/river_maskrom/lib/src/ddr_level_xilinx.dart new file mode 100644 index 0000000..0e411cf --- /dev/null +++ b/packages/river_maskrom/lib/src/ddr_level_xilinx.dart @@ -0,0 +1,626 @@ +import 'dart:typed_data'; + +import 'package:river/river.dart'; +import 'package:river_adl/river_adl.dart'; + +/// Xilinx ISERDESE2 (Arty S7) DDR read-leveling boot program. +/// +/// The ddr3Fast (ISERDESE2) read path returns real DQ but the per-DQ IDELAYE2 +/// eye is uncentered and the ISERDESE2 BITSLIP beat rotation is arbitrary. This +/// centers each DQ lane's read eye against the DDR3 MPR page0 predefined pattern +/// (0b01010101), a write-independent target the DRAM hardwires, via the DDR +/// train-control MMIO block (built with `--ddr-trainable`): +/// +/// reg10 @ trainCtrlBase+0x50 IDELAY: [4:0]tap(CNTVALUEIN) [5]LD [9:6]lane +/// reg11 @ trainCtrlBase+0x58 BITSLIP: [3:0]lane [4]slip +/// reg3 @ trainCtrlBase+0x18 STATUS (read-only; bit0 = IDELAYCTRL RDY) +/// reg12 @ trainCtrlBase+0x60 WINDOW [3:0] ctrl100 read-pipe tap +/// +/// Golden target: the MPR pattern gives beat0=0, beat1=1, ... on every DQ lane. +/// Each read word = {fallBeat<<16 | riseBeat}, so a centered read = 0xFFFF0000. +/// Per lane L: rise bit = bit L (=0), fall bit = bit L+16 (=1). +/// +/// Algorithm (all RUNTIME loops, body emitted once; x0..x30 only, x31 scratch): +/// 1. UART init; print ST=/RDY. Pin reg12 = window 5 (the live burst cycle). +/// 2. Find the global BITSLIP (0..7) putting the most lanes in the 0xFFFF0000 +/// orientation at tap 16; apply it. Report `BS=` + `BEST BS=`. +/// 3. Per DQ lane: sweep IDELAY tap 0..31 (reg10 VAR_LOAD), judge only lane L's +/// two MPR bits (rise=0, fall=1), record the contiguous pass window [lo,hi] +/// and park at center. Report `LVLX L= TAP=
LO= HI=`. +/// 4. VERIFY: read word0 16x with centered taps; count hits vs 0xFFFF0000 and +/// 0x0000FFFF + a sample. Report `VER FF00= 00FF= S=`. +/// 5. Loop the centering forever (UART-glitch tolerance). +/// +/// Position-independent; only the UART, DRAM and train-control bases are +/// absolute. MPR reads ignore the address, so no DRAM bytes are modified. +class RiverDdrLevelXilinx extends Module { + @override + final RiscVIsaConfig isa; + + RiverDdrLevelXilinx({ + required this.isa, + required int uartBase, + required int dramBase, + required int trainCtrlBase, + int clockHz = 48000000, + int baud = 115200, + // Number of DQ lanes (each has its own IDELAYE2 tap). reg10's lane field is + // [3:0], so this must stay <= 16. Arty S7 DDR3 is x16. + int dataBits = 16, + // BITSLIP rotations to probe. The fabric BITSLIP re-pairs the two half-beat + // captures; width-2 has up to 4 distinct rotations. + int bitslipTop = 4, + // MPR mode: when true (--ddr-mpr build), run the write-independent MPR + // read-eye centering (DRAM returns the 0101 pattern). When false (real + // build), skip centering, park all lanes at [bakedCenterTap] + window 5, and + // run the A/B/C write-store test (does the array store what we write). + bool mprMode = true, + // Per-lane IDELAY center tap the MPR centering converged to (uniform across + // all 16 lanes). Parks a clean read in the non-MPR write test. + int bakedCenterTap = 17, + }) { + // Train-control register addresses (8-byte strided, decoded on bus[6:3]). + final regRdslack = trainCtrlBase + 0x10; // reg2 RDSLACK (read-back only) + final regStatus = trainCtrlBase + 0x18; // reg3 STATUS (read-only) + final regIdelay = + trainCtrlBase + 0x50; // reg10 IDELAY [4:0]tap [5]LD [9:6]lane + final regBitslip = trainCtrlBase + 0x58; // reg11 BITSLIP [3:0]lane [4]slip + final regWindow = trainCtrlBase + 0x60; // reg12 WINDOW [3:0]ctrl83 read tap + + const tapTop = 32; // IDELAYE2 5-bit counter: taps 0..31. + const kReads = 8; // per-tap stability reads (reject marginal-eye taps). + + // ns16550a setup (x13 holds uartBase for the whole program; the print + // helpers read it). + final divisor = (clockHz ~/ baud).clamp(1, 0xffff); + register(Register.x13).bind(li(uartBase)); + register(Register.x11).bind(li(0x83)); // LCR: DLAB=1, 8N1 + sb(register(Register.x13), register(Register.x11), offset: 3); + register(Register.x11).bind(li(divisor & 0xff)); // DLL + sb(register(Register.x13), register(Register.x11), offset: 0); + register(Register.x11).bind(li((divisor >> 8) & 0xff)); // DLM + sb(register(Register.x13), register(Register.x11), offset: 1); + register(Register.x11).bind(li(0x03)); // LCR: DLAB=0, 8N1 + sb(register(Register.x13), register(Register.x11), offset: 3); + + // Liveness: a fixed line + hex self-test so a UART reader knows the core is + // alive before the slow leveling sweep. + _printStr('LVLX START'); + _crlf(); + register(Register.x14).bind(li(0x12345678)); + _printHexX14(); + _crlf(); + + // One-shot STATUS snapshot (informational). + register(Register.x10).bind(li(regStatus)); + register(Register.x14).bind(lw(register(Register.x10))); + _printStr('LVLX ST='); + _printHexX14(); + _crlf(); + + // Keep regRdslack documented in the register map (read-back parity only on + // this PHY); assert suppresses the unused-warning. + assert(regRdslack > 0); + + // A 3D MPR window sweep (reg12 window x reg11 bitslip x reg10 IDELAY) + // localized the DRAM read burst to ctrl100 read-pipe window 5 (windows 4/5/6 + // carry live tap-varying data, center 5). Pin here. + const foundWin = 5; + // MPR centering leaves BITSLIP at its reset default and detects the resulting + // orientation instead (a whole-beat slip cannot swap rise<->fall). assert + // keeps regBitslip documented and suppresses the unused-warning. + assert(regBitslip > 0); + + // Read dramBase+0 into x4 (word0) and dramBase+4 into x5 (word1), with a + // warm-up read first to absorb the read-pipe turnaround. Position-independent. + void readW0W1() { + register(Register.x10).bind(li(dramBase + 0x0)); + register(Register.x14).bind(lw(register(Register.x10))); // warm-up + register(Register.x10).bind(li(dramBase + 0x0)); + register(Register.x4).bind(lw(register(Register.x10))); // word0 + register(Register.x10).bind(li(dramBase + 0x4)); + register(Register.x5).bind(lw(register(Register.x10))); // word1 + } + + // Set ALL 16 lanes' IDELAY to an absolute tap (reg10 = tap|LD|lane<<6, one + // VAR_LOAD per lane). reg10 lane field is [9:6], tap [4:0], LD [5]. + void setAllTaps(int tap) { + for (var l = 0; l < dataBits; l++) { + register(Register.x10).bind(li(regIdelay)); + register(Register.x11).bind(li((l << 6) | 0x20 | (tap & 0x1f))); + sw(register(Register.x10), register(Register.x11)); + } + } + + // MPR per-lane read-eye centering (window 5, against the DDR3 MPR page0 0101 + // pattern). The MPR read path (skip-ACTIVATE, A[1:0]=00) returns the + // write-independent pattern, so each DQ lane's eye centers against a known + // target. Golden target: beat0=0, beat1=1, ...; each read word = + // {fallBeat<<16 | riseBeat} so a centered read = 0xFFFF0000. Per lane L: rise + // bit = bit L (0), fall bit = bit L+16 (1); laneMask = (1< the write lands; + // A!=C => reads track address. + if (!mprMode) { + final wtLoop = label('lvlxwtloop'); + _printStr('LVLX WRITE TEST'); + _crlf(); + register(Register.x10).bind(li(regStatus)); + register(Register.x14).bind(lw(register(Register.x10))); + _printStr('ST='); + _printHexX14(); + _crlf(); + // Pin window 5 + park all lanes at the baked center tap for a clean read. + register(Register.x10).bind(li(regWindow)); + register(Register.x11).bind(li(foundWin)); + sw(register(Register.x10), register(Register.x11)); + setAllTaps(bakedCenterTap); + + void wtWrite(int off, int val) { + register(Register.x10).bind(li(dramBase + off)); + register(Register.x11).bind(li(val)); + sw(register(Register.x10), register(Register.x11)); + } + + void wtRead(int off) { + register(Register.x10).bind(li(dramBase + off)); + register(Register.x14).bind(lw(register(Register.x10))); // warm-up + register(Register.x10).bind(li(dramBase + off)); + register(Register.x4).bind(lw(register(Register.x10))); + } + + void wtPrint(String tag) { + _printStr(tag); + register(Register.x14).bind(mv(register(Register.x4))); + _printHexX14(); + _crlf(); + } + + // A: write 0x40DE0000 to +0 and read back. + wtWrite(0x0, 0x40DE0000); + wtRead(0x0); + wtPrint('A='); + // B: write a DIFFERENT value to the SAME address and read back. + wtWrite(0x0, 0x33221100); + wtRead(0x0); + wtPrint('B='); + // C: read an unwritten address (+0x1000). + wtRead(0x1000); + wtPrint('C='); + // D: write 0x0000CAFE to +0x40 and read it (a second distinct addr/value). + wtWrite(0x40, 0x0000CAFE); + wtRead(0x40); + wtPrint('D='); + + // Read-eye verify: write 0x40DE0000 to +0, sweep IDELAY tap 0..31 (all + // lanes) reading +0, dump WT=. A clean read is stable across the + // tap-10..24 eye band; if the written value ever appears the write lands. + // A stable band != the written value means reads are clean and the write is + // the residual failure. x25=tap, x8=laneField=0. + wtWrite(0x0, 0x40DE0000); + register(Register.x25).bind(li(0)); // tap + final wtEye = label('lvlxwteye'); + // set ALL lanes to this tap (reuse setAllTaps semantics inline for a var). + register(Register.x26).bind(li(0)); // lane + final wtEyeLane = label('lvlxwteyelane'); + register(Register.x10).bind(li(regIdelay)); + register(Register.x11).bind(slli(register(Register.x26), 6)); // lane<<6 + register( + Register.x11, + ).bind(or(register(Register.x11), register(Register.x25))); + register(Register.x11).bind(ori(register(Register.x11), 0x20)); + sw(register(Register.x10), register(Register.x11)); + register(Register.x26).bind(addi(register(Register.x26), 1)); + register(Register.x12).bind(li(dataBits)); + blt(register(Register.x26), register(Register.x12), wtEyeLane); + wtRead(0x0); + _printStr('WT'); + register(Register.x14).bind(mv(register(Register.x25))); + _printHexX14(); + _printChar(0x3D); + register(Register.x14).bind(mv(register(Register.x4))); + _printHexX14(); + _crlf(); + register(Register.x25).bind(addi(register(Register.x25), 1)); + register(Register.x11).bind(li(tapTop)); + blt(register(Register.x25), register(Register.x11), wtEye); + // Restore the baked center for the next A/B/C/D pass. + setAllTaps(bakedCenterTap); + + // Human/tool-paced delay, then loop forever (bottom-tested, ROM-fit). + register(Register.x24).bind(li(0x200000)); + final wtDelay = label('lvlxwtdelay'); + register(Register.x24).bind(addi(register(Register.x24), -1)); + bne(register(Register.x24), register(Register.x0), wtDelay); + jal(wtLoop); + return; + } + + final diagLoop = label('lvlxdiag'); + _printStr('LVLX MPR EYE'); + _crlf(); + register(Register.x10).bind(li(regStatus)); + register(Register.x14).bind(lw(register(Register.x10))); + _printStr('ST='); + _printHexX14(); + _crlf(); + + // DIAGNOSTIC: sweep the read window 0..7 (reg12) at tap 16 and dump word0 so + // a UART reader can see where the MPR pattern (target 0xFFFF0000) lands. + setAllTaps(16); + register(Register.x30).bind(li(0)); // window + final winDiag = label('lvlxwindiag'); + register(Register.x10).bind(li(regWindow)); + register(Register.x11).bind(mv(register(Register.x30))); + sw(register(Register.x10), register(Register.x11)); + readW0W1(); + _printChar(0x57); // 'W' + register(Register.x14).bind(mv(register(Register.x30))); + _printHexNibbleX14(); + _printChar(0x3D); // '=' + register(Register.x14).bind(mv(register(Register.x4))); + _printHexX14(); + _crlf(); + register(Register.x30).bind(addi(register(Register.x30), 1)); + register(Register.x11).bind(li(8)); + blt(register(Register.x30), register(Register.x11), winDiag); + + // Pin the read window to 5 (the live burst-landing cycle). + register(Register.x10).bind(li(regWindow)); + register(Register.x11).bind(li(foundWin)); + sw(register(Register.x10), register(Register.x11)); + + // STEP 1: detect the MPR orientation (golden reference word x19). The + // symmetric 0101 pattern lands as 0xFFFF0000 or 0x0000FFFF depending on the + // fixed beat rotation, which a whole-beat BITSLIP cannot swap, so detect the + // dominant orientation and center against it. Vote over kReads at tap 16 by + // the lane0-rise/lane0-fall sentinel bits; x19 = the chosen golden word. + setAllTaps(16); + register(Register.x28).bind(li(0)); // votes for 0x0000FFFF (rise=1/fall=0) + register(Register.x26).bind(li(kReads * 2)); // vote trials + final orLoop = label('lvlxorloop'); + readW0W1(); + // rise sentinel = bit0 of x4; fall sentinel = bit16. Vote 0x0000FFFF when + // rise==1 && fall==0. + register( + Register.x24, + ).bind(andi(register(Register.x4), 1)); // rise bit (0/1) + register(Register.x12).bind(srli(register(Register.x4), 16)); + register(Register.x12).bind(andi(register(Register.x12), 1)); // fall bit + // want rise==1 and fall==0 -> (rise & ~fall). x24 = rise, x12 = fall. + register( + Register.x12, + ).bind(xori(register(Register.x12), 1)); // ~fall (1 bit) + register( + Register.x24, + ).bind(and(register(Register.x24), register(Register.x12))); // 0/1 + // BRANCHLESS vote accumulation (no conditional bind): x28 += x24. + register( + Register.x28, + ).bind(add(register(Register.x28), register(Register.x24))); + register(Register.x26).bind(addi(register(Register.x26), -1)); + bne(register(Register.x26), register(Register.x0), orLoop); + // BRANCHLESS golden select: pick 0x0000FFFF iff votes >= threshold, else + // 0xFFFF0000. ge = ~(x28 < threshold) as 0/1; mask = -ge; x19 = select. + register( + Register.x11, + ).bind(li(kReads)); // majority threshold (half of trials) + register( + Register.x24, + ).bind(slt(register(Register.x28), register(Register.x11))); // 1 iff =thr + register( + Register.x24, + ).bind(sub(register(Register.x0), register(Register.x24))); // mask + register(Register.x12).bind(li(0x0000FFFF)); + register( + Register.x12, + ).bind(and(register(Register.x12), register(Register.x24))); // 00FF&mask + register(Register.x6).bind(li(0xFFFF0000 & 0xFFFFFFFF)); + register(Register.x11).bind(xori(register(Register.x24), -1)); // ~mask + register( + Register.x6, + ).bind(and(register(Register.x6), register(Register.x11))); // FF00&~mask + register( + Register.x19, + ).bind(or(register(Register.x12), register(Register.x6))); // golden + _printStr('GOLD='); + register(Register.x14).bind(mv(register(Register.x19))); + _printHexX14(); + _printStr(' V='); + register(Register.x14).bind(mv(register(Register.x28))); + _printHexX14(); + _crlf(); + + // DIAGNOSTIC: dump lane 0's read at every IDELAY tap 0..31 (other lanes at + // 16) so a UART reader sees the eye shape. One read per tap; x8=laneField=0. + register(Register.x8).bind(li(0)); // lane 0 field + register(Register.x25).bind(li(0)); // tap + final t0dump = label('lvlxt0dump'); + register(Register.x10).bind(li(regIdelay)); + register( + Register.x11, + ).bind(or(register(Register.x8), register(Register.x25))); + register(Register.x11).bind(ori(register(Register.x11), 0x20)); + sw(register(Register.x10), register(Register.x11)); + readW0W1(); + _printChar(0x54); // 'T' + register(Register.x14).bind(mv(register(Register.x25))); + _printHexX14(); // full 8-digit tap (unambiguous for 16..31) + _printChar(0x3D); // '=' + register(Register.x14).bind(mv(register(Register.x4))); + _printHexX14(); + _crlf(); + register(Register.x25).bind(addi(register(Register.x25), 1)); + register(Register.x11).bind(li(tapTop)); + blt(register(Register.x25), register(Register.x11), t0dump); + // Restore lane 0 to tap 16 for the sweep below. + register(Register.x10).bind(li(regIdelay)); + register(Register.x11).bind(li(0x20 | 16)); + sw(register(Register.x10), register(Register.x11)); + + // STEP 2: per-lane IDELAY tap sweep 0..31 for the contiguous MPR pass window; + // park each lane at center. Sweep one lane's tap with the others at 16, judge + // only lane L's two bits against golden x19 (rise bit L, fall bit L+16). + register(Register.x20).bind(li(0)); // lane + final laneScan = label('lvlxlanescan'); + register( + Register.x8, + ).bind(slli(register(Register.x20), 6)); // laneField = L<<6 + // Other lanes stay at 16 (step 1 never moved them). This lane sweeps. + register(Register.x21).bind(li(0)); // lo + register(Register.x22).bind(li(0)); // hi + register(Register.x29).bind(li(0)); // any-pass flag + register(Register.x25).bind(li(0)); // tap + final tapScan = label('lvlxtapscan'); + // Load this lane's absolute tap (reg10 VAR_LOAD = laneField | tap | 0x20). + register(Register.x10).bind(li(regIdelay)); + register( + Register.x11, + ).bind(or(register(Register.x8), register(Register.x25))); + register(Register.x11).bind(ori(register(Register.x11), 0x20)); + sw(register(Register.x10), register(Register.x11)); + // Stability judge: read word0 kReads times; the lane passes only if every + // read matches golden x19 in both of lane L's bits. Requiring all kReads + // consistent finds the stable eye, not a marginal edge. Mask = (1< TAP=
LO= HI=. + _printStr('LVLX L='); + register(Register.x14).bind(mv(register(Register.x20))); + _printHexX14(); + _printStr(' TAP='); + register(Register.x14).bind(mv(register(Register.x23))); + _printHexX14(); + _printStr(' LO='); + register(Register.x14).bind(mv(register(Register.x21))); + _printHexX14(); + _printStr(' HI='); + register(Register.x14).bind(mv(register(Register.x22))); + _printHexX14(); + _crlf(); + + register(Register.x20).bind(addi(register(Register.x20), 1)); + register(Register.x11).bind(li(dataBits)); + blt(register(Register.x20), register(Register.x11), laneScan); + + // STEP 3: verify the centered eye against golden x19. Read word0 nTrials + // times; count exact matches (GOOD) and OR a sticky per-bit error map (ERR). + // Low 16 = rise beats, high 16 = fall beats. ERR=0 = perfect stable eye. + register(Register.x28).bind(li(0)); // exact golden matches + register(Register.x7).bind(li(0)); // sticky error bitmap + register(Register.x26).bind(li(64)); // trials + final vloop = label('lvlxvloop'); + readW0W1(); + register( + Register.x24, + ).bind(xor(register(Register.x4), register(Register.x19))); + // Mask the error to the low 32 bits (lw sign-extends a bit-31-set read, so the + // raw 64-bit xor would smear the upper half). x12 = 0xFFFFFFFF. + register(Register.x12).bind(li(0xFFFF)); + register(Register.x12).bind(slli(register(Register.x12), 16)); + register( + Register.x12, + ).bind(ori(register(Register.x12), 0xFFFF)); // 0xFFFFFFFF + register( + Register.x24, + ).bind(and(register(Register.x24), register(Register.x12))); + register( + Register.x7, + ).bind(or(register(Register.x7), register(Register.x24))); + // BRANCHLESS exact-match count: match = (x24 == 0); x28 += match. + register( + Register.x24, + ).bind(sltiu(register(Register.x24), 1)); // 1 iff x24==0 + register( + Register.x28, + ).bind(add(register(Register.x28), register(Register.x24))); + register(Register.x26).bind(addi(register(Register.x26), -1)); + bne(register(Register.x26), register(Register.x0), vloop); + register(Register.x6).bind(mv(register(Register.x4))); // last sample + _printStr('VER GOOD='); + register(Register.x14).bind(mv(register(Register.x28))); + _printHexX14(); + _printStr(' ERR='); + register(Register.x14).bind(mv(register(Register.x7))); + _printHexX14(); + _printStr(' S='); + register(Register.x14).bind(mv(register(Register.x6))); + _printHexX14(); + _crlf(); + + // Short delay to pace the readout, then loop the centering forever + // (UART-glitch tolerance). x24 counts down, bottom-tested. + register(Register.x24).bind(li(0x200000)); // delay count + final delayLbl = label('lvlxdelay'); + register(Register.x24).bind(addi(register(Register.x24), -1)); + bne(register(Register.x24), register(Register.x0), delayLbl); + jal(diagLoop); // repeat the centering forever + } + + /// Prints x14 as eight uppercase hex digits, MSB first (clobbers x15..x18). + void _printHexX14() { + register(Register.x17).bind(li(0x3A)); + register(Register.x18).bind(li(28)); + final nibble = label('nib'); + register( + Register.x15, + ).bind(srl(register(Register.x14), register(Register.x18))); + register(Register.x15).bind(andi(register(Register.x15), 0xF)); + register(Register.x15).bind(addi(register(Register.x15), 0x30)); + final noAdjust = Label('noadj'); + blt(register(Register.x15), register(Register.x17), noAdjust); + register(Register.x15).bind(addi(register(Register.x15), 7)); + placeLabel(noAdjust); + final poll = label('p'); + final lsr = lbu(register(Register.x13), offset: 5); + register(Register.x16).bind(andi(lsr, 0x20)); + beq(register(Register.x16), register(Register.x0), poll); + sb(register(Register.x13), register(Register.x15)); + register(Register.x18).bind(addi(register(Register.x18), -4)); + bge(register(Register.x18), register(Register.x0), nibble); + } + + /// Prints the low nibble of x14 as one uppercase hex digit (clobbers + /// x15..x17). Used for the single-digit window/bitslip/varies indices. + void _printHexNibbleX14() { + register(Register.x17).bind(li(0x3A)); + register(Register.x15).bind(andi(register(Register.x14), 0xF)); + register(Register.x15).bind(addi(register(Register.x15), 0x30)); + final noAdjust = Label('nadjn'); + blt(register(Register.x15), register(Register.x17), noAdjust); + register(Register.x15).bind(addi(register(Register.x15), 7)); + placeLabel(noAdjust); + final poll = label('pn'); + final lsr = lbu(register(Register.x13), offset: 5); + register(Register.x16).bind(andi(lsr, 0x20)); + beq(register(Register.x16), register(Register.x0), poll); + sb(register(Register.x13), register(Register.x15)); + } + + /// Transmits a single byte, polling the LSR THRE bit first. + void _printChar(int ch) { + final poll = label('p'); + final lsr = lbu(register(Register.x13), offset: 5); + register(Register.x16).bind(andi(lsr, 0x20)); + beq(register(Register.x16), register(Register.x0), poll); + register(Register.x15).bind(li(ch)); + sb(register(Register.x13), register(Register.x15)); + } + + /// Transmits an ASCII string byte by byte (immediates only, no data table). + void _printStr(String s) { + for (final ch in s.codeUnits) { + _printChar(ch); + } + } + + void _crlf() { + for (final ch in const [0x0D, 0x0A]) { + _printChar(ch); + } + } + + /// Raw machine code for a monitor load frame. + Uint8List generateBytes() => Uint8List.fromList(generateBinary()); +} diff --git a/packages/river_maskrom/lib/src/ddr_probe.dart b/packages/river_maskrom/lib/src/ddr_probe.dart new file mode 100644 index 0000000..b3915d8 --- /dev/null +++ b/packages/river_maskrom/lib/src/ddr_probe.dart @@ -0,0 +1,117 @@ +import 'dart:typed_data'; + +import 'package:river/river.dart'; +import 'package:river_adl/river_adl.dart'; + +/// A DDR diagnostic payload: after a printer self-test line (12345678), it +/// writes one BL8 line twice with different patterns and prints every +/// readback as hex. +/// +/// Where [RiverDdrTest] only says pass/fail, the hex output names the +/// failure: readbacks that track the written pattern isolate the bug to +/// the read path (shifted half-words mean slot pairing or rdSlack, one +/// word repeated means beat select), while identical junk across both +/// passes means writes never reach the array at all. +class RiverDdrProbe extends Module { + @override + final RiscVIsaConfig isa; + + RiverDdrProbe({ + required this.isa, + required int uartBase, + required int dramBase, + int clockHz = 48000000, + int baud = 115200, + }) { + // ns16550a setup (the divisor gates the transmitter). + final divisor = (clockHz ~/ baud).clamp(1, 0xffff); + register(Register.x13).bind(li(uartBase)); + register(Register.x11).bind(li(0x83)); // LCR: DLAB=1, 8N1 + sb(register(Register.x13), register(Register.x11), offset: 3); + register(Register.x11).bind(li(divisor & 0xff)); // DLL + sb(register(Register.x13), register(Register.x11), offset: 0); + register(Register.x11).bind(li((divisor >> 8) & 0xff)); // DLM + sb(register(Register.x13), register(Register.x11), offset: 1); + register(Register.x11).bind(li(0x03)); // LCR: DLAB=0, 8N1 + sb(register(Register.x13), register(Register.x11), offset: 3); + + // Printer self-test: this line must read 12345678 on the terminal. + register(Register.x14).bind(li(0x12345678)); + _printHexX14(); + _crlf(); + + // Read-priming test. Hypothesis: the read rise beat (q0) mis-captures the + // write->read turnaround on the FIRST read of an unprimed column, and a + // prior read settles it. Write one word to a fresh line, then read it THREE + // times in a row with NO writes between. If the readback converges to the + // written 0xC1C10005, priming is the cure (-> controller issues a dummy read + // or discards the first captured beat-pair). If all three stay wrong, the + // capture is unconditionally broken for unprimed columns. + register(Register.x10).bind(li(dramBase + 0x60)); + register(Register.x11).bind(li(0xC1C10005)); + sw(register(Register.x10), register(Register.x11)); + for (var i = 0; i < 3; i++) { + register(Register.x14).bind(lw(register(Register.x10))); + _printHexX14(); + _crlf(); + } + _crlf(); + + // Control: a DIFFERENT fresh line written full (4 words), read word 0 three + // times. Expect 0xD3D30000 (or convergence) to compare partial vs full. + for (var i = 0; i < 4; i++) { + register(Register.x10).bind(li(dramBase + 0x70 + i * 4)); + register(Register.x11).bind(li(0xD3D30000 + i * 0x1111)); + sw(register(Register.x10), register(Register.x11)); + } + register(Register.x10).bind(li(dramBase + 0x70)); + for (var i = 0; i < 3; i++) { + register(Register.x14).bind(lw(register(Register.x10))); + _printHexX14(); + _crlf(); + } + _crlf(); + + final done = label('done'); + jal(done); + } + + /// Prints x14 as eight uppercase hex digits, MSB first. Loops over the + /// shift amount in x18; x17 holds the '9'+1 threshold for the A-F + /// adjustment. + void _printHexX14() { + register(Register.x17).bind(li(0x3A)); + register(Register.x18).bind(li(28)); + final nibble = label('nib'); + register( + Register.x15, + ).bind(srl(register(Register.x14), register(Register.x18))); + register(Register.x15).bind(andi(register(Register.x15), 0xF)); + register(Register.x15).bind(addi(register(Register.x15), 0x30)); + final noAdjust = Label('noadj'); + blt(register(Register.x15), register(Register.x17), noAdjust); + register(Register.x15).bind(addi(register(Register.x15), 7)); + placeLabel(noAdjust); + final poll = label('p'); + final lsr = lbu(register(Register.x13), offset: 5); + register(Register.x16).bind(andi(lsr, 0x20)); + beq(register(Register.x16), register(Register.x0), poll); + sb(register(Register.x13), register(Register.x15)); + register(Register.x18).bind(addi(register(Register.x18), -4)); + bge(register(Register.x18), register(Register.x0), nibble); + } + + void _crlf() { + for (final ch in const [0x0D, 0x0A]) { + final poll = label('p'); + final lsr = lbu(register(Register.x13), offset: 5); + register(Register.x16).bind(andi(lsr, 0x20)); + beq(register(Register.x16), register(Register.x0), poll); + register(Register.x15).bind(li(ch)); + sb(register(Register.x13), register(Register.x15)); + } + } + + /// Raw machine code for a monitor load frame. + Uint8List generateBytes() => Uint8List.fromList(generateBinary()); +} diff --git a/packages/river_maskrom/lib/src/ddr_sweep_probe.dart b/packages/river_maskrom/lib/src/ddr_sweep_probe.dart new file mode 100644 index 0000000..470de9a --- /dev/null +++ b/packages/river_maskrom/lib/src/ddr_sweep_probe.dart @@ -0,0 +1,115 @@ +import 'dart:typed_data'; + +import 'package:river/river.dart'; +import 'package:river_adl/river_adl.dart'; + +/// The diagnostic twin of [RiverDdrTest]: same coverage (a full BL8 line, +/// a neighboring line, column/row/bank crossings, then a byte-merge), but +/// every readback is printed as hex instead of pass/fail, so a failing +/// region names itself. Expected output: C0DE0000/1111/.../7777, then +/// C0DE5500 (merged word) and 00000055 (lbu of the merged byte). +class RiverDdrSweepProbe extends Module { + @override + final RiscVIsaConfig isa; + + RiverDdrSweepProbe({ + required this.isa, + required int uartBase, + required int dramBase, + int clockHz = 48000000, + int baud = 115200, + }) { + final offsets = [0x0, 0x4, 0x8, 0xC, 0x10, 0x800, 0x100000, 0x4000000]; + int patternFor(int i) => 0xC0DE0000 + i * 0x1111; + + // ns16550a setup (the divisor gates the transmitter). + final divisor = (clockHz ~/ baud).clamp(1, 0xffff); + register(Register.x13).bind(li(uartBase)); + register(Register.x11).bind(li(0x83)); // LCR: DLAB=1, 8N1 + sb(register(Register.x13), register(Register.x11), offset: 3); + register(Register.x11).bind(li(divisor & 0xff)); // DLL + sb(register(Register.x13), register(Register.x11), offset: 0); + register(Register.x11).bind(li((divisor >> 8) & 0xff)); // DLM + sb(register(Register.x13), register(Register.x11), offset: 1); + register(Register.x11).bind(li(0x03)); // LCR: DLAB=0, 8N1 + sb(register(Register.x13), register(Register.x11), offset: 3); + + for (var i = 0; i < offsets.length; i++) { + register(Register.x10).bind(li(dramBase + offsets[i])); + register(Register.x11).bind(li(patternFor(i))); + sw(register(Register.x10), register(Register.x11)); + } + for (var i = 0; i < offsets.length; i++) { + register(Register.x10).bind(li(dramBase + offsets[i])); + register(Register.x14).bind(lw(register(Register.x10))); + _printHexX14(); + _crlf(); + } + _crlf(); + + // Sub-word lane map: sb 0x55 into each byte lane of four fresh words, + // sh 0xBEEF into both halves of two more, print every merged word. + // Expected: C0DE0055, C0DE5511, C0552222, 55DE3333, C0DEBEEF, + // BEEF5555. + for (var i = 0; i < 4; i++) { + register(Register.x10).bind(li(dramBase + 0x40 + i * 4)); + register(Register.x11).bind(li(0xC0DE0000 + i * 0x1111)); + sw(register(Register.x10), register(Register.x11)); + register(Register.x11).bind(li(0x55)); + sb(register(Register.x10), register(Register.x11), offset: i); + register(Register.x14).bind(lw(register(Register.x10))); + _printHexX14(); + _crlf(); + } + for (var i = 0; i < 2; i++) { + register(Register.x10).bind(li(dramBase + 0x50 + i * 4)); + register(Register.x11).bind(li(0xC0DE0000 + (4 + i) * 0x1111)); + sw(register(Register.x10), register(Register.x11)); + register(Register.x11).bind(li(0xBEEF)); + sh(register(Register.x10), register(Register.x11), offset: i * 2); + register(Register.x14).bind(lw(register(Register.x10))); + _printHexX14(); + _crlf(); + } + + final done = label('done'); + jal(done); + } + + /// Prints x14 as eight uppercase hex digits, MSB first. + void _printHexX14() { + register(Register.x17).bind(li(0x3A)); + register(Register.x18).bind(li(28)); + final nibble = label('nib'); + register( + Register.x15, + ).bind(srl(register(Register.x14), register(Register.x18))); + register(Register.x15).bind(andi(register(Register.x15), 0xF)); + register(Register.x15).bind(addi(register(Register.x15), 0x30)); + final noAdjust = Label('noadj'); + blt(register(Register.x15), register(Register.x17), noAdjust); + register(Register.x15).bind(addi(register(Register.x15), 7)); + placeLabel(noAdjust); + final poll = label('p'); + final lsr = lbu(register(Register.x13), offset: 5); + register(Register.x16).bind(andi(lsr, 0x20)); + beq(register(Register.x16), register(Register.x0), poll); + sb(register(Register.x13), register(Register.x15)); + register(Register.x18).bind(addi(register(Register.x18), -4)); + bge(register(Register.x18), register(Register.x0), nibble); + } + + void _crlf() { + for (final ch in const [0x0D, 0x0A]) { + final poll = label('p'); + final lsr = lbu(register(Register.x13), offset: 5); + register(Register.x16).bind(andi(lsr, 0x20)); + beq(register(Register.x16), register(Register.x0), poll); + register(Register.x15).bind(li(ch)); + sb(register(Register.x13), register(Register.x15)); + } + } + + /// Raw machine code for a monitor load frame. + Uint8List generateBytes() => Uint8List.fromList(generateBinary()); +} diff --git a/packages/river_maskrom/lib/src/ddr_test.dart b/packages/river_maskrom/lib/src/ddr_test.dart new file mode 100644 index 0000000..7ffd82a --- /dev/null +++ b/packages/river_maskrom/lib/src/ddr_test.dart @@ -0,0 +1,220 @@ +import 'dart:typed_data'; + +import 'package:river/river.dart'; +import 'package:river_adl/river_adl.dart'; + +/// A DDR bring-up payload for the serial monitor: writes a known pattern +/// across the DRAM window, reads it back, and reports over the UART. +/// +/// Coverage is deliberate, not bulk: the four words of one BL8 line (every +/// beat-select), a neighboring line, and strides that cross the column, +/// row, and bank fields of the address mapping. A final byte store into a +/// written word proves the SEL-to-DM masking path end to end (MMU lane +/// shift, controller wrMask, PHY DM timing, part-side merge). +/// +/// Prints `DDR OK` when every readback matches, or `DDR ER` and spins on +/// the first mismatch. Position-independent code, like the other maskrom +/// programs; only the UART and DRAM bases are absolute. +class RiverDdrTest extends Module { + @override + final RiscVIsaConfig isa; + + RiverDdrTest({ + required this.isa, + required int uartBase, + required int dramBase, + // Train-control MMIO base (STATUS/reg block), just above the DRAM array at + // dramBase + dramSize. MUST be passed per-board: hardcoding a fixed offset + // (e.g. dramBase+128M for a 128MB part) lands INSIDE a larger array on a + // 256MB board, so the STATUS read returns array data, not the register. + required int trainCtrlBase, + int clockHz = 48000000, + int baud = 115200, + // When true, re-run the readback+verdict forever (with a delay between + // prints) instead of printing once and spinning. On real hardware the + // FPGA reconfiguration glitches the first UART bytes, so a one-shot print + // is unreadable; a looping print streams clean copies once the line + // settles. The DRAM writes still happen once up front, so the loop also + // exercises data retention. + bool loopForever = false, + // Diagnostic: test ONLY the first word (write 0x0, read it back, no + // neighbor writes, no byte-merge). Isolates a broken read path (this fails) + // from BL8-line DM-mask clobber by neighbor writes (this passes, the full + // test fails). + bool singleWord = false, + }) { + // Word-write/readback targets: one full BL8 line (4 words), the next + // line, then column/row/bank field crossings. + final fullOffsets = [ + // One BL8 line (every beat-select) + column/row/bank crossings. + 0x0, 0x4, 0x8, 0xC, 0x10, 0x800, 0x100000, + // Dense coverage of main Weir's .bss-clear span (0x9830..0x843a40, + // ~8.6MB): a contiguous memset main does before setting mtvec, so a + // single bad address here faults the boot with no output (the + // observed boot loop). Unique pattern per offset (write-all then + // read-all) also catches a high-address alias clobbering a low one. + 0x200000, 0x400000, 0x600000, 0x800000, 0x840000, 0x843a3c, + // High bank/rank crossing well past the .bss span. + 0x4000000, + ]; + final offsets = singleWord ? [0x0] : fullOffsets; + // Bit 31 MUST be clear: on RV64 `lw` sign-extends the loaded word while the + // `li` that builds the expected value zero-extends it, so a bit-31-set + // pattern (e.g. 0xC0DE...) read back as 0xFFFFFFFF_C0DE... never matches the + // 0x00000000_C0DE... it was compared against - a false "DDR ER" even on + // perfect memory. Keep every pattern <= 0x7FFFFFFF. + int patternFor(int i) => 0x40DE0000 + i * 0x1111; + + // ns16550a setup, same dance as the other programs (the divisor gates + // the transmitter, so this is mandatory). + final divisor = (clockHz ~/ baud).clamp(1, 0xffff); + register(Register.x13).bind(li(uartBase)); + register(Register.x11).bind(li(0x83)); // LCR: DLAB=1, 8N1 + sb(register(Register.x13), register(Register.x11), offset: 3); + register(Register.x11).bind(li(divisor & 0xff)); // DLL + sb(register(Register.x13), register(Register.x11), offset: 0); + register(Register.x11).bind(li((divisor >> 8) & 0xff)); // DLM + sb(register(Register.x13), register(Register.x11), offset: 1); + register(Register.x11).bind(li(0x03)); // LCR: DLAB=0, 8N1 + sb(register(Register.x13), register(Register.x11), offset: 3); + + // DRAM-INIT SETTLE: the DDR sequencer's JEDEC init runs ~700 us (sPower + // 200us + sResetHold 500us) AFTER its reset releases; the core comes out of + // reset at the same instant and would otherwise write/read an uninitialised + // DRAM. Burn a generous fixed countdown (~200k core cycles, ~8 ms at 25 MHz) + // before ANY DRAM access so init has finished. (A STATUS init_done poll is + // the clean form, but a fixed delay cannot hang if init never completes, + // which keeps the failure observable during bring-up.) + register(Register.x22).bind(li(0x30000)); + final settle = label('initsettle'); + register(Register.x22).bind(addi(register(Register.x22), -1)); + blt(register(Register.x0), register(Register.x22), settle); + + // Per-check error report: on a mismatch (x14 != x11) print "DDR E=" + // (tag = offset index, or 'm'/'b' for byte-merge) and CONTINUE, so one run + // yields the full corruption map. x25 counts failures. + void checkXa(String tag) { + final ok = label('ck$tag'); + beq(register(Register.x14), register(Register.x11), ok); + register(Register.x25).bind(addi(register(Register.x25), 1)); // err count + register(Register.x24).bind(addi(register(Register.x14), 0)); // save read + _print('DDR E$tag='); + register(Register.x14).bind(addi(register(Register.x24), 0)); + _printHexX14(); + _print('\r\n'); + placeLabel(ok); + } + + // Error counter (x25): incremented by checkXa on every mismatch; the final + // verdict prints "DDR OK" only when it is still 0. + register(Register.x25).bind(li(0)); + + // Write the pattern. + for (var i = 0; i < offsets.length; i++) { + register(Register.x10).bind(li(dramBase + offsets[i])); + register(Register.x11).bind(li(patternFor(i))); + sw(register(Register.x10), register(Register.x11)); + } + + // Read it back; report every mismatch. + for (var i = 0; i < offsets.length; i++) { + register(Register.x10).bind(li(dramBase + offsets[i])); + register(Register.x11).bind(li(patternFor(i))); + register(Register.x14).bind(lw(register(Register.x10))); + checkXa('$i'); + } + + // Byte-merge: replace byte 1 of word 0 (0x40DE0000 -> 0x40DE5500), + // then check both the merged word and a sub-word readback. Skipped in + // [singleWord] mode (it is itself a sub-word DM write). + if (!singleWord) { + register(Register.x10).bind(li(dramBase)); + register(Register.x11).bind(li(0x55)); + sb(register(Register.x10), register(Register.x11), offset: 1); + // Expected merged word = word0's pattern with byte 1 replaced by 0x55. + // Compute it from patternFor(0) so it is correct in dense mode too (dense + // word0 = 0x01001000, not the non-dense 0x40DE0000); hardcoding the + // non-dense value made the byte-merge check a false error under DENSE. + register(Register.x11).bind(li((patternFor(0) & 0xFFFF00FF) | 0x5500)); + register(Register.x14).bind(lw(register(Register.x10))); + checkXa('m'); + register(Register.x11).bind(li(0x55)); + register(Register.x14).bind(lbu(register(Register.x10), offset: 1)); + checkXa('b'); + } + + // DQS PHY bring-up probe: read train-control STATUS (reg3 @ trainCtrlBase+0x18) + // once as "DDR ST=". Bits: [8]DATAVALID [9]BURSTDET [10]DLL_LOCK + // [11]BDET_SEEN(sticky) [12]DVALID_SEEN(sticky). The read rides the bus-clock + // control window, so it ACKs even when the DQS datapath is dead: it shows + // WHERE the DLL-on read breaks. + // _print clobbers x14 (its THRE poll does x14 = LSR & 0x20), so print the tag + // BEFORE loading the value into x14, else _printHexX14 streams the leaked 0x20 + // mask instead of the register. _printHexX14 polls on x16, preserving x14. + void dumpWord(String tag, int addr) { + _print(tag); + register(Register.x10).bind(li(addr)); + register(Register.x14).bind(lw(register(Register.x10))); + _printHexX14(); + _print('\r\n'); + } + + dumpWord('DDR ST=', trainCtrlBase + 0x18); // reg3 STATUS + + // Verdict, streamed in a loop: "DDR OK" only when x25 (mismatch count) is 0, + // else "DDR ERRS=". The per-offset "DDR E=" lines above + // already streamed the full corruption map once. Looping the verdict rides + // out the FPGA-reconfig UART glitch. + final vtop = label('vtop'); + final okLbl = label('vok'); + final vdone = label('vdone'); + beq(register(Register.x25), register(Register.x0), okLbl); + _print('DDR ERRS='); + register(Register.x14).bind(addi(register(Register.x25), 0)); + _printHexX14(); + _print('\r\n'); + jal(vdone); + placeLabel(okLbl); + _print('DDR OK\r\n'); + placeLabel(vdone); + jal(vtop); + } + + /// THRE-polled UART print, one unrolled poll loop per byte. + void _print(String message) { + for (var i = 0; i < message.length; i++) { + final poll = label('p'); + final lsr = lbu(register(Register.x13), offset: 5); + register(Register.x14).bind(andi(lsr, 0x20)); + beq(register(Register.x14), register(Register.x0), poll); + register(Register.x11).bind(li(message.codeUnitAt(i))); + sb(register(Register.x13), register(Register.x11)); + } + } + + /// Prints x14 as eight uppercase hex digits, MSB first (clobbers x15..x18). + void _printHexX14() { + register(Register.x17).bind(li(0x3A)); + register(Register.x18).bind(li(28)); + final nibble = label('nib'); + register( + Register.x15, + ).bind(srl(register(Register.x14), register(Register.x18))); + register(Register.x15).bind(andi(register(Register.x15), 0xF)); + register(Register.x15).bind(addi(register(Register.x15), 0x30)); + final noAdjust = Label('noadj'); + blt(register(Register.x15), register(Register.x17), noAdjust); + register(Register.x15).bind(addi(register(Register.x15), 7)); + placeLabel(noAdjust); + final poll = label('p'); + final lsr = lbu(register(Register.x13), offset: 5); + register(Register.x16).bind(andi(lsr, 0x20)); + beq(register(Register.x16), register(Register.x0), poll); + sb(register(Register.x13), register(Register.x15)); + register(Register.x18).bind(addi(register(Register.x18), -4)); + bge(register(Register.x18), register(Register.x0), nibble); + } + + /// Raw machine code for a monitor load frame. + Uint8List generateBytes() => Uint8List.fromList(generateBinary()); +} diff --git a/packages/river_maskrom/lib/src/ddr_verify.dart b/packages/river_maskrom/lib/src/ddr_verify.dart new file mode 100644 index 0000000..2a5e4b5 --- /dev/null +++ b/packages/river_maskrom/lib/src/ddr_verify.dart @@ -0,0 +1,403 @@ +import 'dart:typed_data'; + +import 'package:river/river.dart'; +import 'package:river_adl/river_adl.dart'; + +/// Minimal DDR write-read-verify probe with plainly-readable output, so the DDR +/// state at a given clock is unambiguous. Output lines: +/// 1. `DDRVERIFY 12345678` - UART/core liveness. +/// 2. `ST ` - train-control STATUS (reg3) read 4x. Bit10 (0x400, +/// DLL_LOCK) set means the PHY DLL locked (init reached); 0 means the DDR +/// never calibrated (so all-zeros readback is just uninitialised DRAM). +/// 3. `WREF ...` - the reference pattern. +/// 4. `R ` x[iters] - fresh write, warm-up read, then readback per +/// pass. == pattern => works; all-zeros => write not landing; varying => +/// marginal. Repeated to expose the error rate and consistency. +/// 5. `RET ` - write, long delay, read (coarse retention/refresh hint). +/// 6. `DONE`, then spin. +/// +/// No STATUS busy-poll, so it can never hang on a flag that never fires. +/// Register discipline: printers clobber x14..x18 and read x13 (uartBase); +/// x4..x7 readback, x10 addr, x11 write value, x28/x29 loop scratch. +class RiverDdrVerify extends Module { + @override + final RiscVIsaConfig isa; + + RiverDdrVerify({ + required this.isa, + required int uartBase, + required int dramBase, + required int trainCtrlBase, + int clockHz = 48000000, + int baud = 115200, + int iters = 8, + }) { + final regStatus = trainCtrlBase + 0x18; // reg3 STATUS (read-only) + + // Four distinctive words (not 0, not all-equal, so zeros/garbage stand out). + const p0 = 0xA5A5A5A5; + const p1 = 0x5A5A5A5A; + const p2 = 0xDEADBEEF; + const p3 = 0xCAFEF00D; + + // ns16550a setup (x13 holds uartBase for the whole program). + final divisor = (clockHz ~/ baud).clamp(1, 0xffff); + register(Register.x13).bind(li(uartBase)); + register(Register.x11).bind(li(0x83)); // LCR: DLAB=1, 8N1 + sb(register(Register.x13), register(Register.x11), offset: 3); + register(Register.x11).bind(li(divisor & 0xff)); // DLL + sb(register(Register.x13), register(Register.x11), offset: 0); + register(Register.x11).bind(li((divisor >> 8) & 0xff)); // DLM + sb(register(Register.x13), register(Register.x11), offset: 1); + register(Register.x11).bind(li(0x03)); // LCR: DLAB=0, 8N1 + sb(register(Register.x13), register(Register.x11), offset: 3); + + // 1. Liveness. + _printStr('DDRVERIFY '); + register(Register.x14).bind(li(0x12345678)); + _printHexX14(); + _crlf(); + + // Give the DDR PHY init/DLL time to settle before we look at STATUS. + _fixedDelay(200000); + + // 2. STATUS (reg3) read four times - DLL lock + valid/burst flags. + _printStr('ST '); + for (var i = 0; i < 4; i++) { + register(Register.x10).bind(li(regStatus)); + register(Register.x14).bind(lw(register(Register.x10))); + _printHexX14(); + _printChar(0x20); + } + _crlf(); + + // 3. Reference pattern line. + _printStr('WREF '); + for (final w in const [p0, p1, p2, p3]) { + register(Register.x14).bind(li(w)); + _printHexX14(); + _printChar(0x20); + } + _crlf(); + + // 4. Write-read-verify loop. + register(Register.x28).bind(li(iters)); // pass counter + final loopTop = label('vtop'); + + _writePattern(dramBase, p0, p1, p2, p3); + _readAndPrint(dramBase, 'R '); + + register(Register.x28).bind(addi(register(Register.x28), -1)); + bne(register(Register.x28), register(Register.x0), loopTop); + + // 4b. Isolated mid-address write+read (word 64 = dramBase+0x100). A clean + // single access here plus a garbage post-bulk read at the same address + // (SMP below) pins corruption on the bulk WRITE STREAM, not the address. + _writePattern( + dramBase + 0x100, + 0x11110040, + 0x22220041, + 0x33330042, + 0x44440043, + ); + _readAndPrint(dramBase + 0x100, 'M64 '); + + // 5. BULK STREAM: 4KB sequential write then two read-verify passes drive 512 + // back-to-back two-beat dcache refills (the streaming path Weir hits that + // the single-word loop does not). word[i] = 0x0BAD0000|i. B0/B1 ERR= = + // mismatch count per pass; 0 = clean, differing B0 vs B1 = transient. + _bulkStream(dramBase, 1024); + + // 5b. Write-vs-read discriminator: a single low-rate read of mid-stream words + // 64..67 (a fresh refill; the 4KB bulk evicted them from the dcache). + // Correct => the bulk write landed and the bulk READ is the bug; wrong => + // the bulk WRITE corrupted the array. + _readAndPrint(dramBase + 0x100, 'SMP '); + + // 5c. Address-bit walk: write a distinct value to dramBase+(1< (bit k set => addr bit k + // broken) + A0= to catch a low write aliasing onto 0. + _addrWalk(dramBase); + + // 5d. N-sweep: write+verify n words for rising n (`N=`). Words 0..127 + // are all bank0/row0 (bank = wordIndex[9:7]); word 128 enters bank1, 1024 + // enters row1. Clean at n<=128 but broken at n=1024 => corruption crosses + // banks/rows; breaking at n<128 => a same-row count effect. + _rangeCheck(dramBase, 8, 0x01110000, 'N8'); + _rangeCheck(dramBase, 32, 0x02220000, 'N32'); + _rangeCheck(dramBase, 64, 0x03330000, 'N64'); + _rangeCheck(dramBase, 128, 0x04440000, 'N128'); + _rangeCheck(dramBase, 256, 0x05550000, 'N256'); + _rangeCheck(dramBase, 512, 0x06660000, 'N512'); + + // 5e. SRAM control: the same loop against on-chip SRAM (0x08000000, no DDR + // path). SRAM also wrong => the bug is the core store-address path (loop + // pointer); SRAM clean => the DDR genuinely aliases loop-addressed writes. + _rangeCheck(0x08000000, 8, 0x07770000, 'SR8'); + _rangeCheck(0x08000000, 512, 0x08880000, 'SR512'); + + // 6. Retention hint: write, long compute-only delay, then read. + _writePattern(dramBase, p0, p1, p2, p3); + _fixedDelay(4000000); + _readAndPrint(dramBase, 'RET '); + + _printStr('DONE'); + _crlf(); + + // Spin forever. + final spin = label('spin'); + jal(spin); + } + + /// Store the 4 words at dramBase+0/4/8/C. Uses x10 (addr), x11 (value). + void _writePattern(int dramBase, int w0, int w1, int w2, int w3) { + final words = [w0, w1, w2, w3]; + for (var i = 0; i < 4; i++) { + register(Register.x10).bind(li(dramBase + i * 4)); + register(Register.x11).bind(li(words[i])); + sw(register(Register.x10), register(Register.x11)); + } + } + + /// Warm-up read then read the 4 words into x4..x7 and print ``. + void _readAndPrint(int dramBase, String prefix) { + register(Register.x10).bind(li(dramBase + 0x0)); + register(Register.x14).bind(lw(register(Register.x10))); // warm-up + register(Register.x10).bind(li(dramBase + 0x0)); + register(Register.x4).bind(lw(register(Register.x10))); + register(Register.x10).bind(li(dramBase + 0x4)); + register(Register.x5).bind(lw(register(Register.x10))); + register(Register.x10).bind(li(dramBase + 0x8)); + register(Register.x6).bind(lw(register(Register.x10))); + register(Register.x10).bind(li(dramBase + 0xC)); + register(Register.x7).bind(lw(register(Register.x10))); + _printStr(prefix); + for (final r in const [ + Register.x4, + Register.x5, + Register.x6, + Register.x7, + ]) { + register(Register.x14).bind(mv(register(r))); + _printHexX14(); + _printChar(0x20); + } + _crlf(); + } + + /// Sequential 4-byte write of `n` words (word[i] = 0x0BAD0000|i) to dramBase, + /// then two read-verify passes counting mismatches. Drives back-to-back dcache + /// refills (the streaming path). x10 addr, x28 index, x29 limit, x20 err, + /// x11 expected, x4 readback - all safe across the printers (x13..x18). + void _bulkStream(int dramBase, int n) { + // Write pass. + register(Register.x10).bind(li(dramBase)); + register(Register.x28).bind(li(0)); + register(Register.x29).bind(li(n)); + final wl = label('bwl'); + register(Register.x11).bind(li(0x0BAD0000)); + register( + Register.x11, + ).bind(or(register(Register.x11), register(Register.x28))); + sw(register(Register.x10), register(Register.x11)); + register(Register.x10).bind(addi(register(Register.x10), 4)); + register(Register.x28).bind(addi(register(Register.x28), 1)); + blt(register(Register.x28), register(Register.x29), wl); + + // Two read-verify passes. + for (var pass = 0; pass < 2; pass++) { + register(Register.x10).bind(li(dramBase)); + register(Register.x28).bind(li(0)); + register(Register.x20).bind(li(0)); // error count + final rl = label('brl$pass'); + register(Register.x4).bind(lw(register(Register.x10))); + register(Register.x11).bind(li(0x0BAD0000)); + register( + Register.x11, + ).bind(or(register(Register.x11), register(Register.x28))); + final ok = Label('bok$pass'); + beq(register(Register.x4), register(Register.x11), ok); + register(Register.x20).bind(addi(register(Register.x20), 1)); // mismatch + placeLabel(ok); + register(Register.x10).bind(addi(register(Register.x10), 4)); + register(Register.x28).bind(addi(register(Register.x28), 1)); + blt(register(Register.x28), register(Register.x29), rl); + _printStr('B$pass ERR='); + register(Register.x14).bind(mv(register(Register.x20))); + _printHexX14(); + _crlf(); + } + } + + /// Address-bit walk. Writes a distinct value to dramBase + (1< that DRAM address bit is unwired / + /// mis-mapped). Prints `A0=` (the dramBase+0 sentinel readback - changes if + /// a low write aliased onto it) then `AWALK=` (bit k set => addr bit k + /// broken; 0 => all walked address bits are wired). x10 addr, x11 val, x28 k, + /// x5 (1< Uint8List.fromList(generateBinary()); +} diff --git a/packages/river_maskrom/lib/src/dram_exec.dart b/packages/river_maskrom/lib/src/dram_exec.dart new file mode 100644 index 0000000..5f12ced --- /dev/null +++ b/packages/river_maskrom/lib/src/dram_exec.dart @@ -0,0 +1,163 @@ +import 'dart:typed_data'; + +import 'package:river/river.dart'; +import 'package:river_adl/river_adl.dart'; + +/// Proves the core can FETCH AND EXECUTE from DRAM, not just load/store data +/// there. The other DRAM tests ([RiverDdrTest], [RiverDdrProbe]) only exercise +/// the data path; booting Weir is the first time PC ever enters DRAM (the FSBL +/// copies main to 0x80000000 and jumps), which this isolates. +/// +/// Sequence: configure the UART, print "DEXEC\r\n" (boot ROM ran), copy +/// [stubBytes] (a position-independent print-and-spin stub, e.g. a built +/// [RiverHelloWorld] with `loop: true`) word by word into DRAM, then `jalr` to +/// it. Stub banner streams => fetch from DRAM works; dead after "DEXEC" => the +/// core cannot fetch from DRAM. +/// +/// [stubBytes] must be already-built machine code (`await stub.build()` then +/// `stub.generateBinary()`); a Module's binary is empty until built. +class RiverDramExec extends Module { + @override + final RiscVIsaConfig isa; + + RiverDramExec({ + required this.isa, + required int uartBase, + required int dramBase, + required List stubBytes, + int clockHz = 48000000, + int baud = 115200, + }) { + // Pad to a whole number of 32-bit words. + final words = []; + for (var i = 0; i < stubBytes.length; i += 4) { + var w = 0; + for (var b = 0; b < 4; b++) { + if (i + b < stubBytes.length) w |= stubBytes[i + b] << (8 * b); + } + words.add(w & 0xffffffff); + } + + // ns16550a setup (the divisor gates the transmitter). + final divisor = (clockHz ~/ baud).clamp(1, 0xffff); + register(Register.x13).bind(li(uartBase)); + register(Register.x11).bind(li(0x83)); // LCR: DLAB=1, 8N1 + sb(register(Register.x13), register(Register.x11), offset: 3); + register(Register.x11).bind(li(divisor & 0xff)); // DLL + sb(register(Register.x13), register(Register.x11), offset: 0); + register(Register.x11).bind(li((divisor >> 8) & 0xff)); // DLM + sb(register(Register.x13), register(Register.x11), offset: 1); + register(Register.x11).bind(li(0x03)); // LCR: DLAB=0, 8N1 + sb(register(Register.x13), register(Register.x11), offset: 3); + + // Marker: the boot ROM program reached the copy stage. + _print('DEXEC\r\n'); + + // Copy the stub into DRAM. Keep the destination base in x10 and use the sw + // immediate offset (12-bit signed) for each word; chunk the base forward + // every 256 words so the offsets never exceed the +2047 range. + const chunk = 256; + for (var start = 0; start < words.length; start += chunk) { + register(Register.x10).bind(li(dramBase + start * 4)); + for (var i = start; i < words.length && i < start + chunk; i++) { + register(Register.x11).bind(li(words[i])); + sw( + register(Register.x10), + register(Register.x11), + offset: (i - start) * 4, + ); + // Progress marker every 8 words: emit '.' so the copy STREAMS its + // progress on HW and we can see exactly which write it hangs on (the + // count of dots x8 = the hang word index). x11/x10 are reloaded next + // iteration; the marker only touches x13(uart)/x14/x15/x16. + if ((i & 7) == 7) { + final poll = label('cpoll$i'); + final lsr = lbu(register(Register.x13), offset: 5); + register(Register.x16).bind(andi(lsr, 0x20)); + beq(register(Register.x16), register(Register.x0), poll); + register(Register.x15).bind(li(0x2E)); // '.' + sb(register(Register.x13), register(Register.x15)); + // Restore x10 base (the marker didn't touch it, but keep explicit). + register(Register.x10).bind(li(dramBase + start * 4)); + } + } + } + + // Marker: the sustained-write COPY loop completed (isolates a copy/write hang + // from a verify/read hang). + _print('COPIED\r\n'); + + // COPY-VERIFY (isolates DDR-read-corruption from the ifetch/CDC path): read + // the copied stub back as data and compare. A mismatch => the DDR read + // corrupted the code; all match => the code is correct in DRAM, so silence + // after the jump is the instruction-fetch (CDC ifetch) path. Up to 64 words. + final vN = words.length < 64 ? words.length : 64; + for (var i = 0; i < vN; i++) { + register(Register.x10).bind(li(dramBase + i * 4)); + register(Register.x14).bind(lw(register(Register.x10))); // readback + register(Register.x11).bind(li(words[i])); // expected + final good = label('cv$i'); + beq(register(Register.x14), register(Register.x11), good); + // Report EVERY mismatch and CONTINUE (no spin) so we see the corruption + // extent: only word0 (write->read turnaround) or all words. + register( + Register.x24, + ).bind(addi(register(Register.x14), 0)); // save readback + register(Register.x12).bind(li(i)); + _print('CB i='); + _printHex(Register.x12); + _print(' e='); + register(Register.x25).bind(li(words[i])); + _printHex(Register.x25); + _print(' r='); + _printHex(Register.x24); + _print('\r\n'); + placeLabel(good); + } + _print('CVDONE\r\n'); + + // Jump into DRAM. If the core can fetch from DRAM, the stub takes over and + // streams "DRAM EXEC OK" forever. + register(Register.x10).bind(li(dramBase)); + jalr(register(Register.x10)); + } + + /// Prints the low 32 bits of [reg] as 8 hex digits (clobbers x15..x18). + void _printHex(Register reg) { + register(Register.x14).bind(addi(register(reg), 0)); + register(Register.x17).bind(li(0x3A)); + register(Register.x18).bind(li(28)); + final nibble = label('nib'); + register( + Register.x15, + ).bind(srl(register(Register.x14), register(Register.x18))); + register(Register.x15).bind(andi(register(Register.x15), 0xF)); + register(Register.x15).bind(addi(register(Register.x15), 0x30)); + final noAdjust = Label('noadj'); + blt(register(Register.x15), register(Register.x17), noAdjust); + register(Register.x15).bind(addi(register(Register.x15), 7)); + placeLabel(noAdjust); + final poll = label('hp'); + final lsr = lbu(register(Register.x13), offset: 5); + register(Register.x16).bind(andi(lsr, 0x20)); + beq(register(Register.x16), register(Register.x0), poll); + sb(register(Register.x13), register(Register.x15)); + register(Register.x18).bind(addi(register(Register.x18), -4)); + bge(register(Register.x18), register(Register.x0), nibble); + } + + /// THRE-polled UART print, one unrolled poll loop per byte. + void _print(String message) { + for (var i = 0; i < message.length; i++) { + final poll = label('p'); + final lsr = lbu(register(Register.x13), offset: 5); + register(Register.x14).bind(andi(lsr, 0x20)); + beq(register(Register.x14), register(Register.x0), poll); + register(Register.x11).bind(li(message.codeUnitAt(i))); + sb(register(Register.x13), register(Register.x11)); + } + } + + /// Raw machine code for baking into a boot ROM's init data. + Uint8List generateBytes() => Uint8List.fromList(generateBinary()); +} diff --git a/packages/river_maskrom/lib/src/dram_ping.dart b/packages/river_maskrom/lib/src/dram_ping.dart new file mode 100644 index 0000000..49f598d --- /dev/null +++ b/packages/river_maskrom/lib/src/dram_ping.dart @@ -0,0 +1,53 @@ +import 'dart:typed_data'; + +import 'package:river/river.dart'; +import 'package:river_adl/river_adl.dart'; + +/// A diagnostic stub meant to run FROM DRAM (copied there and jumped to, e.g. by +/// [RiverDramExec]). It isolates instruction-fetch integrity from every other +/// variable: +/// +/// - It prints its characters from IMMEDIATES (`li`), never reading a data +/// buffer, so a garbled line cannot be blamed on a DDR data read/write. +/// - It paces each line with a long delay loop, so the UART is nowhere near +/// saturated and the host-side USB-serial cannot overrun (which would also +/// garble a sustained stream). +/// +/// So the ONLY DRAM traffic while it runs is the core re-fetching this loop body +/// every iteration. If the printed `[PING]` lines are clean, instruction fetch +/// from DRAM is sound and any earlier garble was data or readout. If they are +/// still corrupted, instruction fetch from DRAM is itself marginal. +/// +/// Assumes the UART divisor is already programmed (the copier set it up). +/// Position independent (PC-relative control flow, immediate UART base). +class RiverDramPing extends Module { + @override + final RiscVIsaConfig isa; + + RiverDramPing({ + required this.isa, + required int uartBase, + int delayCount = 0x40000, + }) { + const msg = '[PING]\r\n'; + register(Register.x13).bind(li(uartBase)); + + final top = label('ping_top'); + for (var i = 0; i < msg.length; i++) { + final poll = label('p$i'); + final lsr = lbu(register(Register.x13), offset: 5); + register(Register.x14).bind(andi(lsr, 0x20)); + beq(register(Register.x14), register(Register.x0), poll); + register(Register.x11).bind(li(msg.codeUnitAt(i))); + sb(register(Register.x13), register(Register.x11)); + } + // Delay so the line is not saturated: count x12 down to zero. + register(Register.x12).bind(li(delayCount)); + final delay = label('ping_delay'); + register(Register.x12).bind(addi(register(Register.x12), -1)); + bne(register(Register.x12), register(Register.x0), delay); + jal(top); + } + + Uint8List generateBytes() => Uint8List.fromList(generateBinary()); +} diff --git a/packages/river_maskrom/lib/src/dram_stress.dart b/packages/river_maskrom/lib/src/dram_stress.dart new file mode 100644 index 0000000..13418ab --- /dev/null +++ b/packages/river_maskrom/lib/src/dram_stress.dart @@ -0,0 +1,74 @@ +import 'dart:typed_data'; + +import 'package:river/river.dart'; +import 'package:river_adl/river_adl.dart'; + +/// A diagnostic stub run FROM DRAM (copied and jumped to by [RiverDramExec]) +/// that reproduces the Weir-main bss-memset hang in isolation. [RiverDramPing] +/// showed instruction fetch from DRAM alone is clean; the hang only appears when +/// the core fetches its loop from DRAM WHILE streaming heavy writes to DRAM. +/// This recreates that: a tight store loop across a multi-MB region (every store +/// crosses the MMU arbiter, the 2:1 downsizer, and the CDC bridge into the PHY), +/// with the loop body itself re-fetched from DRAM every iteration. +/// +/// Prints a '.' after each sweep: steady dots => fetch-under-write is sound; +/// dots stop/garble => the core wandered mid-sweep (the hang). +/// +/// Position-independent; UART base and write region are absolute immediates. The +/// write region starts at dramBase + 0x100000 so it never overwrites this stub. +class RiverDramWriteStress extends Module { + @override + final RiscVIsaConfig isa; + + RiverDramWriteStress({ + required this.isa, + required int uartBase, + required int dramBase, + int unroll = 512, // inline stores per pass: makes the CODE span many DRAM + // rows so instruction fetch constantly row-misses (like Weir main's MB of + // code), which a tight one-row loop never hits. Bounded by the boot ROM. + bool useSd = false, // 64-bit `sd` stores (drive BOTH downsizer lanes, sel + // 0xFF) instead of 32-bit `sw` (one lane). Weir's memset is 8-byte; the + // both-lanes split is an untested downsizer path under contention. + int writeOffset = 0x100000, // store-region offset from dramBase. The stub + // CODE is fetched from low DRAM (dramBase); a LARGE writeOffset puts the + // store stream far from the fetch stream (like Weir: code low, bss reaching + // ~8MB up), exposing any ifetch-vs-dport address-mux race in the arbiter/CDC + // that close-together stubs never hit. + }) { + final writeBase = dramBase + writeOffset; // store region + final step = useSd ? 8 : 4; + register(Register.x13).bind(li(uartBase)); // UART base + register(Register.x19).bind(li(0xA5A5A5A5)); // store pattern + + // Walk a pointer CONTIGUOUSLY up DRAM (NO reset), emitting a '.' every 64 + // KiB, exactly like Weir's bss clear. This reproduces the Weir hang outside + // Weir: from a PAGE-ALIGNED writeOffset it runs for many MB, but from a + // page-MISALIGNED writeOffset (e.g. Weir's bss_start 0x9xx) it should hang + // after ~1 MiB if the controller's alignment handling is the bug. [unroll] + // is ignored here (kept for the API); the per-dot count gives a 64 KiB body. + final perDot = 0x10000 ~/ step; // stores per 64 KiB + register(Register.x17).bind(li(writeBase)); // ptr (walks, never resets) + final outer = label('stress_outer'); + register(Register.x18).bind(li(perDot)); // down-counter for this 64 KiB + final inner = label('stress_inner'); + if (useSd) { + sd(register(Register.x17), register(Register.x19)); + } else { + sw(register(Register.x17), register(Register.x19)); + } + register(Register.x17).bind(addi(register(Register.x17), step)); + register(Register.x18).bind(addi(register(Register.x18), -1)); + bne(register(Register.x18), register(Register.x0), inner); + // 64 KiB done: print '.'. + final poll = label('stress_poll'); + final lsr = lbu(register(Register.x13), offset: 5); + register(Register.x14).bind(andi(lsr, 0x20)); + beq(register(Register.x14), register(Register.x0), poll); + register(Register.x11).bind(li(0x2e)); // '.' + sb(register(Register.x13), register(Register.x11)); + jal(outer); + } + + Uint8List generateBytes() => Uint8List.fromList(generateBinary()); +} diff --git a/packages/river_maskrom/lib/src/flash_hexdump.dart b/packages/river_maskrom/lib/src/flash_hexdump.dart new file mode 100644 index 0000000..077bd16 --- /dev/null +++ b/packages/river_maskrom/lib/src/flash_hexdump.dart @@ -0,0 +1,212 @@ +import 'dart:typed_data'; + +import 'package:river/river.dart'; +import 'package:river_adl/river_adl.dart'; + +/// One flash window to hex-dump: [length] bytes read by lbu XIP starting at the +/// absolute [base], preceded by an optional [header] line (e.g. "FLASH @0:"). +/// The [length] should be a multiple of 16 so the dump ends on a line boundary. +class HexdumpRegion { + /// Absolute base address of the window (the flash XIP address to lbu from). + final int base; + + /// How many bytes to dump from [base]. Multiple of 16 for a clean tail. + final int length; + + /// Optional header line emitted (with CRLF) before this region's hex dump. + final String? header; + + const HexdumpRegion({required this.base, required this.length, this.header}); +} + +/// A flash bring-up monitor: configures the ns16550a UART, then reads +/// [dumpBytes] from the SPI flash XIP region at [flashBase] and streams them as +/// a classic hex dump (`OOOOOOOO: HH HH ...`, offset then 16 bytes), then prints +/// `DUMP DONE\r\n` and spins. Proves the maskrom copied this image out of flash +/// to SRAM, the image executes from SRAM, and the flash XIP read path works. +/// +/// UART writes poll the LSR THRE bit so the loop paces itself to the +/// transmitter. Position-independent (PC-relative control flow); only [flashBase] +/// and [uartBase] are absolute. +/// +/// Register convention (monitor owns the machine, all caller-saved): +/// x13 = UART base x14 = LSR scratch +/// x11 = byte scratch x10 = flash read cursor (absolute) +/// x12 = flash end pointer x15 = running flash offset (line label) +/// x16 = byte read from flash x17 = column counter (0..15) x18 = nibble scratch +/// +/// A non-empty [regions] instead dumps each region in sequence with its +/// [HexdumpRegion.header] line: the multi-region diagnostic probe, running +/// entirely from ROM with no flash-write or maskrom-copy dependency. +class RiverFlashHexdump extends Module { + @override + final RiscVIsaConfig isa; + + /// Base of the SPI flash XIP region. The dump reads [dumpBytes] from here. + /// Ignored when [regions] is non-empty. + final int flashBase; + + /// How many flash bytes to dump (default 512 = 32 lines of 16). Ignored when + /// [regions] is non-empty. + final int dumpBytes; + + /// Bytes per hex-dump line. + static const int bytesPerLine = 16; + + int _labelSeq = 0; + + RiverFlashHexdump({ + required this.isa, + required int uartBase, + this.flashBase = 0x20000000, + this.dumpBytes = 512, + int clockHz = 12000000, + int baud = 115200, + List regions = const [], + }) { + // Configure the ns16550a for 8N1 at the requested baud. Harbor's UART gates + // its transmitter on a non-zero divisor (which resets to 0), so this setup + // is mandatory on real hardware, not just cosmetic. Baud = clockHz/divisor. + final divisor = (clockHz ~/ baud).clamp(1, 0xffff); + register(Register.x13).bind(li(uartBase)); // UART base + register(Register.x11).bind(li(0x83)); // LCR: DLAB=1, 8 data bits, 1 stop + sb(register(Register.x13), register(Register.x11), offset: 3); + register(Register.x11).bind(li(divisor & 0xff)); // DLL (divisor low) + sb(register(Register.x13), register(Register.x11), offset: 0); + register( + Register.x11, + ).bind(li((divisor >> 8) & 0xff)); // DLM (divisor high) + sb(register(Register.x13), register(Register.x11), offset: 1); + register(Register.x11).bind(li(0x03)); // LCR: DLAB=0, 8N1 (latch divisor) + sb(register(Register.x13), register(Register.x11), offset: 3); + + // Dump every region in sequence. A single-region call (the classic + // bring-up image) collapses to one synthesized region; a multi-region call + // (the diagnostic probe) dumps each with its own header line. + final dumpRegions = regions.isNotEmpty + ? regions + : [HexdumpRegion(base: flashBase, length: dumpBytes)]; + for (final region in dumpRegions) { + _dumpRegion(region); + } + + // Trailer: "DUMP DONE\r\n". + for (final ch in 'DUMP DONE\r\n'.codeUnits) { + _sendImm(ch); + } + + // Done: spin forever. + final done = label('done'); + jal(done); + } + + /// Emits the hex dump of a single [region]: its optional header line first, + /// then "OFFSET: HH HH ..\r\n" lines covering [HexdumpRegion.length] bytes + /// read by lbu XIP from [HexdumpRegion.base]. + void _dumpRegion(HexdumpRegion region) { + // Optional header line for this region, e.g. "FLASH @0:\r\n". + if (region.header != null) { + for (final ch in '${region.header}\r\n'.codeUnits) { + _sendImm(ch); + } + } + + // Set up the dump cursors. x10 walks the flash, x12 marks the end, x15 is + // the running offset (relative to the region base) used for the line label. + register(Register.x10).bind(li(region.base)); // read cursor (absolute) + register(Register.x12).bind(li(region.base + region.length)); // end + register(Register.x15).bind(li(0)); // running offset + + // One line per 16 bytes. + final lineLoop = label('line'); + // Print the 8-hex-digit offset of this line, then ": ". + _sendHexWord(Register.x15); + _sendImm(0x3a); // ':' + _sendImm(0x20); // ' ' + + // 16 bytes, space-separated. + register(Register.x17).bind(li(0)); // column counter + final byteLoop = label('byte'); + register(Register.x16).bind(lbu(register(Register.x10))); // flash[cursor] + _sendHexByte(Register.x16); + _sendImm(0x20); // ' ' + register(Register.x10).bind(addi(register(Register.x10), 1)); + register(Register.x17).bind(addi(register(Register.x17), 1)); + register(Register.x18).bind(li(bytesPerLine)); + bne(register(Register.x17), register(Register.x18), byteLoop); + + // End of line. + _sendImm(0x0d); // '\r' + _sendImm(0x0a); // '\n' + + // Advance the running offset and loop until the whole region is dumped. + register(Register.x15).bind(addi(register(Register.x15), bytesPerLine)); + bne(register(Register.x10), register(Register.x12), lineLoop); + } + + /// Polls LSR (offset 5) bit 5 (THRE), then writes x11 to THR (offset 0). + void _sendX11() { + final wait = label('txw${_labelSeq++}'); + final lsr = lbu(register(Register.x13), offset: 5); + register(Register.x14).bind(andi(lsr, 0x20)); + beq(register(Register.x14), register(Register.x0), wait); + sb(register(Register.x13), register(Register.x11)); + } + + /// Sends the immediate byte [ch]. + void _sendImm(int ch) { + register(Register.x11).bind(li(ch & 0xff)); + _sendX11(); + } + + /// Sends the low nibble of [value] (0..15) as an ASCII hex digit. Maps + /// 0..9 -> '0'+n and 10..15 -> 'a'+(n-10). Uses x18 as scratch, clobbers x11. + void _sendHexNibble(DataField value) { + // ASCII hex digit, computed branchlessly so there is no two-writes-to-one- + // register-across-a-branch pattern (the ADL's dead-store pass drops the + // first write of such a pair, not seeing that a jump skips the second). + // + // n = value & 0xf + // ltTen = (n < 10) ? 1 : 0 (slti) + // geTenMask = ltTen - 1 (0 if n<10, 0xFFFF.. if n>=10) + // adj = geTenMask & 0x27 (0 for digits, 0x27 for a-f) + // ascii = n + 0x30 + adj ('0'+n, or 'a'+(n-10)) + final n = andi(value, 0xf); + register(Register.x18).bind(n); + final ltTen = slti(register(Register.x18), 10); + final geTenMask = addi(ltTen, -1); + final adj = andi(geTenMask, 0x27); + final base = addi(register(Register.x18), 0x30); + register(Register.x11).bind(add(base, adj)); + _sendX11(); + } + + /// Sends the byte in register [reg] as two ASCII hex digits (high then low). + void _sendHexByte(Register reg) { + _sendHexNibble(srli(register(reg), 4)); // high nibble + _sendHexNibble(register(reg)); // low nibble (masked inside) + } + + /// Sends the low 32 bits of register [reg] as 8 ASCII hex digits, MSB first. + void _sendHexWord(Register reg) { + for (var shift = 28; shift >= 0; shift -= 4) { + _sendHexNibble(srli(register(reg), shift)); + } + } + + /// Raw machine code for baking into a boot ROM's init data. + Uint8List generateBytes() => Uint8List.fromList(generateBinary()); + + /// An ELF wrapping the program at [entryPoint], for the emulator/HDL sim. + Uint8List emitElfBytes({required int entryPoint}) { + final section = emitToSection(name: '.text', baseAddress: entryPoint); + final writer = ElfWriter( + entryPoint: entryPoint, + elfClass: isa.mxlen == RiscVMxlen.rv64 + ? ElfWriterClass.elf64 + : ElfWriterClass.elf32, + ); + writer.addSection(section, address: entryPoint); + return Uint8List.fromList(writer.write()); + } +} diff --git a/packages/river_maskrom/lib/src/hello_world.dart b/packages/river_maskrom/lib/src/hello_world.dart new file mode 100644 index 0000000..8d0fb00 --- /dev/null +++ b/packages/river_maskrom/lib/src/hello_world.dart @@ -0,0 +1,100 @@ +import 'dart:typed_data'; + +import 'package:river/river.dart'; +import 'package:river_adl/river_adl.dart'; + +/// Minimal boot program for SRAM-class systems (data RAM usable straight out of +/// reset). A first bring-up smoke test: write a message into RAM, read it back, +/// stream each byte out the ns16550a UART, then spin. +/// +/// UART writes poll the LSR THRE bit so the loop paces to the transmitter, +/// keeping the image safe on real silicon as well as the emulator. +/// +/// Code is position independent (all control flow PC-relative), so the same +/// image runs from boot ROM or RAM. Only [ramBase] and [uartBase] are absolute. +class RiverHelloWorld extends Module { + @override + final RiscVIsaConfig isa; + + /// The message streamed out the UART. Defaults to a CRLF-terminated banner. + final String message; + + RiverHelloWorld({ + required this.isa, + required int uartBase, + required int ramBase, + int clockHz = 12000000, + int baud = 115200, + this.message = 'Hello from River!\r\n', + bool loop = false, + }) { + // Configure the ns16550a for 8N1. Harbor's UART gates TX on a non-zero + // divisor (resets to 0), so this setup is mandatory on hardware, not + // cosmetic. Baud = clockHz/divisor. + final divisor = (clockHz ~/ baud).clamp(1, 0xffff); + register(Register.x13).bind(li(uartBase)); // UART base + register(Register.x11).bind(li(0x83)); // LCR: DLAB=1, 8 data bits, 1 stop + sb(register(Register.x13), register(Register.x11), offset: 3); + register(Register.x11).bind(li(divisor & 0xff)); // DLL (divisor low) + sb(register(Register.x13), register(Register.x11), offset: 0); + register( + Register.x11, + ).bind(li((divisor >> 8) & 0xff)); // DLM (divisor high) + sb(register(Register.x13), register(Register.x11), offset: 1); + register(Register.x11).bind(li(0x03)); // LCR: DLAB=0, 8N1 (latch divisor) + sb(register(Register.x13), register(Register.x11), offset: 3); + + // Write the message into data RAM one byte at a time (exercises stores). + register(Register.x10).bind(li(ramBase)); + for (var i = 0; i < message.length; i++) { + register(Register.x11).bind(li(message.codeUnitAt(i))); + sb(register(Register.x10), register(Register.x11), offset: i); + } + + // Read it back from RAM and stream to the UART (exercises loads + MMIO). + // Re-entry point: when [loop] is set, jump here to re-emit the banner forever + // so bring-up can dial in the baud. The read cursor resets each pass. + final streamStart = label('stream_start'); + register(Register.x10).bind(li(ramBase)); // read cursor + register(Register.x12).bind(li(ramBase + message.length)); // end of message + register(Register.x13).bind(li(uartBase)); // UART base + + final txLoop = label('tx_loop'); + // Wait for the transmit holding register to drain: poll LSR (offset 5), + // bit 5 (THRE). While it is clear, branch back and re-poll. + final lsr = lbu(register(Register.x13), offset: 5); + register(Register.x14).bind(andi(lsr, 0x20)); + beq(register(Register.x14), register(Register.x0), txLoop); + + // Transmitter is ready: load the next byte from RAM and write it to THR. + final ch = lbu(register(Register.x10)); + sb(register(Register.x13), ch); + register(Register.x10).bind(addi(register(Register.x10), 1)); + bne(register(Register.x10), register(Register.x12), txLoop); + + if (loop) { + // Re-emit the banner forever (bring-up baud sweep aid). + jal(streamStart); + } else { + // Done: spin forever. + final done = label('done'); + jal(done); + } + } + + /// Raw machine code for baking into a boot ROM's init data. + Uint8List generateBytes() => Uint8List.fromList(generateBinary()); + + /// An ELF wrapping the program at [entryPoint], for the emulator/HDL sim. + Uint8List emitElfBytes({required int entryPoint}) { + final section = emitToSection(name: '.text', baseAddress: entryPoint); + final writer = ElfWriter( + entryPoint: entryPoint, + elfClass: isa.mxlen == RiscVMxlen.rv64 + ? ElfWriterClass.elf64 + : ElfWriterClass.elf32, + ); + writer.addSection(section, address: entryPoint); + return Uint8List.fromList(writer.write()); + } +} diff --git a/packages/river_maskrom/lib/src/maskrom.dart b/packages/river_maskrom/lib/src/maskrom.dart new file mode 100644 index 0000000..8c52609 --- /dev/null +++ b/packages/river_maskrom/lib/src/maskrom.dart @@ -0,0 +1,196 @@ +import 'dart:typed_data'; + +import 'package:river/river.dart'; +import 'package:river_adl/river_adl.dart'; + +/// [sram] copies the payload from flash into SRAM and runs it there. +/// [cacheAsRam] locks a cache region as scratch first (for SRAM-less systems +/// that wire the cache-lock CSRs). [xipLaunch] does no copy: it warms up the +/// flash XIP controller (spins up the Xilinx STARTUPE2/CCLK path so instruction +/// fetch from flash works, which fails on the first cold-reset cycle), then +/// jumps to the FSBL executing in place from flash. +enum RiverBootMode { sram, cacheAsRam, xipLaunch } + +/// Optional USB DFU download-mode parameters for the maskrom. +/// +/// When supplied, the maskrom arms USB DFU before the flash copy, waits for a +/// host to download an image into RAM, then jumps to it. Addresses are the MMIO +/// registers of the [RiverDfuStatus] block: +/// * [controlAddr] write 1 to assert usb_enable (USB pull-up / connect). +/// * [statusAddr] poll; bit0 set means the image has landed in RAM. +/// * [entryAddr] read the RAM entry address to jump to once ready. +class RiverDfuConfig { + final int controlAddr; + final int statusAddr; + final int entryAddr; + + const RiverDfuConfig({ + required this.controlAddr, + required this.statusAddr, + required this.entryAddr, + }); +} + +class RiverMaskromConfig { + final RiscVIsaConfig isa; + final int resetVector; + final int flashSource; + final int copyDest; + final int copySize; + final int stackTop; + final RiverBootMode bootMode; + + /// When non-null, the maskrom enters USB DFU download mode: assert usb_enable, + /// poll until an image lands in RAM, jump to the reported entry. Skips the copy. + final RiverDfuConfig? dfu; + + const RiverMaskromConfig({ + required this.isa, + required this.resetVector, + required this.flashSource, + required this.copyDest, + required this.copySize, + required this.stackTop, + this.bootMode = RiverBootMode.sram, + this.dfu, + }); +} + +class RiverMaskrom extends Module { + @override + final RiscVIsaConfig isa; + + RiverMaskrom(RiverMaskromConfig config) : isa = config.isa { + register(Register.x2).bind(li(config.stackTop)); + + register(Register.x5).bind(li(config.resetVector)); + csrrw(CsrAddress.mtvec.address, register(Register.x5)); + + if (config.dfu != null) { + // USB DFU: arm USB, wait for the host to push an image into RAM, jump to + // it. Supersedes the flash copy below. + _dfuDownload(config.dfu!); + } + + if (config.bootMode == RiverBootMode.xipLaunch) { + // No copy: warm up the flash XIP controller, then jump to the FSBL running + // in place. flashSource = warmup read window; copyDest = FSBL entry. + _warmupRead(config.flashSource, config.copySize); + fence(); + register(Register.x10).bind(li(0)); // a0 = hartid (boot hart) + register( + Register.x11, + ).bind(li(0)); // a1 = dtb (none; FSBL uses comptime SoC) + register(Register.x5).bind(li(config.copyDest)); + jalr(register(Register.x5)); + final xtrap = label('xip_trap'); + jal(xtrap); + return; + } + + if (config.bootMode == RiverBootMode.cacheAsRam) { + _lockCache( + config.copyDest, + config.copySize + config.stackTop - config.copyDest, + ); + } + + _copyLoop(config.flashSource, config.copyDest, config.copySize); + + fence(); + + // RISC-V boot convention: a0 = hartid (0), a1 = dtb (0 = none). Without this + // a0 holds the copy loop's leftover source pointer, so a bootloader (Weir + // FSBL) reads it as a nonzero hartid and parks the boot hart in a wfi spin. + register(Register.x10).bind(li(0)); // a0 = hartid + register(Register.x11).bind(li(0)); // a1 = dtb + register(Register.x5).bind(li(config.copyDest)); + jalr(register(Register.x5)); + + final trap = label('trap'); + jal(trap); + } + + void _dfuDownload(RiverDfuConfig dfu) { + // Assert usb_enable (write 1 to CONTROL) so the device enumerates and the + // host can DFU-download into RAM. + register(Register.x10).bind(li(dfu.controlAddr)); + register(Register.x11).bind(li(1)); + sw(register(Register.x10), register(Register.x11)); + + // Poll the STATUS register until bit0 (image_ready) is set. + register(Register.x12).bind(li(dfu.statusAddr)); + final poll = label('dfu_poll'); + final status = lw(register(Register.x12)); + final ready = andi(status, 1); + beq(ready, zero, poll); // not ready yet -> keep polling + + // Read the entry address the image landed at and jump to it. + register(Register.x13).bind(li(dfu.entryAddr)); + register(Register.x5).bind(lw(register(Register.x13))); + fence(); + jalr(register(Register.x5)); + + // Safety trap: if the jump ever returns, spin. + final dfuTrap = label('dfu_trap'); + jal(dfuTrap); + } + + void _lockCache(int addr, int size) { + register(Register.x5).bind(li(addr)); + csrrw(CsrAddress.rcacheaddr.address, register(Register.x5)); + register(Register.x5).bind(li(size)); + csrrw(CsrAddress.rcachesize.address, register(Register.x5)); + register(Register.x5).bind(li(1)); + csrrw(CsrAddress.rcachectl.address, register(Register.x5)); + } + + /// Read [size] bytes from [src] (flash) word by word, discarding the data. The + /// act of reading spins up the flash XIP controller + Xilinx STARTUPE2/CCLK + /// path so the subsequent fetch from flash succeeds. x15 is pinned so the + /// dead-code pass keeps the loads even though nothing consumes them. + void _warmupRead(int src, int size) { + register(Register.x10).bind(li(src)); + register(Register.x12).bind(li(src + size)); + final loop = label('warmup'); + register(Register.x15).bind(lw(register(Register.x10))); + register(Register.x10).bind(addi(register(Register.x10), 4)); + bne(register(Register.x10), register(Register.x12), loop); + } + + void _copyLoop(int src, int dst, int size) { + // One loop-carried pointer (x10, source); dst is recomputed each iteration + // as x10 + (dst - src). The ADL dead-code pass is not loop-aware: a separate + // `dst += 4` read only across the back-edge has no straight-line consumer and + // is dropped, so every store hits the same address and the copy silently + // fails. x10 survives because `bne` reads it; the dst `add` is consumed by `sw`. + register(Register.x10).bind(li(src)); + register(Register.x13).bind(li(dst - src)); // dst = src + delta + register(Register.x12).bind(li(src + size)); + + final loop = label('copy'); + register(Register.x15).bind(lw(register(Register.x10))); + register( + Register.x14, + ).bind(add(register(Register.x10), register(Register.x13))); + sw(register(Register.x14), register(Register.x15)); + register(Register.x10).bind(addi(register(Register.x10), 4)); + bne(register(Register.x10), register(Register.x12), loop); + } + + Section emitMaskrom({int? baseAddress}) { + return emitToSection(name: '.text', baseAddress: baseAddress ?? 0); + } + + Uint8List emitElfBytes({required int entryPoint}) { + final section = emitMaskrom(); + final writer = ElfWriter( + entryPoint: entryPoint, + elfClass: isa.mxlen == RiscVMxlen.rv64 + ? ElfWriterClass.elf64 + : ElfWriterClass.elf32, + ); + writer.addSection(section, address: entryPoint); + return Uint8List.fromList(writer.write()); + } +} diff --git a/packages/river_maskrom/lib/src/serial_monitor.dart b/packages/river_maskrom/lib/src/serial_monitor.dart new file mode 100644 index 0000000..8e9f47c --- /dev/null +++ b/packages/river_maskrom/lib/src/serial_monitor.dart @@ -0,0 +1,120 @@ +import 'dart:typed_data'; + +import 'package:river/river.dart'; +import 'package:river_adl/river_adl.dart'; + +/// A serial boot monitor for SRAM-class systems: the development workflow +/// for boards where re-synthesizing the bitstream per program is too slow. +/// +/// On boot it configures the ns16550a, prints [banner], then loops: +/// +/// host -> board: len_lo len_hi payload[len] checksum +/// board -> host: 'K' on a checksum match (then jumps to the payload at +/// [ramBase]), 'E' on a mismatch (then waits again) +/// +/// The checksum is the byte-sum of the payload, modulo 256. A length of zero +/// is a no-op (useful for resynchronizing). The monitor jumps into the loaded +/// program, and a program that wants the monitor back jumps to the boot ROM +/// base (the monitor re-initializes everything on entry). +/// +/// Register convention (all caller-saved, the monitor owns the machine): +/// x13 = UART base, x10 = write cursor, x11 = byte scratch, x12 = length, +/// x14 = LSR scratch, x15 = running checksum, x6 = end pointer, x5 = jump +/// target. +class RiverSerialMonitor extends Module { + @override + final RiscVIsaConfig isa; + + /// Banner printed once at boot. + final String banner; + + int _labelSeq = 0; + + RiverSerialMonitor({ + required this.isa, + required int uartBase, + required int ramBase, + int clockHz = 12000000, + int baud = 115200, + this.banner = 'River boot\r\n', + }) { + // Configure the ns16550a for 8N1 at the requested baud (the transmitter + // and receiver are both gated on a non-zero divisor). + final divisor = (clockHz ~/ baud).clamp(1, 0xffff); + register(Register.x13).bind(li(uartBase)); + register(Register.x11).bind(li(0x83)); // LCR: DLAB=1, 8N1 + sb(register(Register.x13), register(Register.x11), offset: 3); + register(Register.x11).bind(li(divisor & 0xff)); // DLL + sb(register(Register.x13), register(Register.x11), offset: 0); + register(Register.x11).bind(li((divisor >> 8) & 0xff)); // DLM + sb(register(Register.x13), register(Register.x11), offset: 1); + register(Register.x11).bind(li(0x03)); // LCR: DLAB=0, latch divisor + sb(register(Register.x13), register(Register.x11), offset: 3); + + for (final ch in banner.codeUnits) { + _sendImm(ch); + } + + final mainLoop = label('main'); + + // Length, little endian. A zero length resynchronizes. + _recvByte(); // x11 = len_lo + register(Register.x12).bind(andi(register(Register.x11), 0xff)); + _recvByte(); // x11 = len_hi + register( + Register.x12, + ).bind(or(register(Register.x12), slli(register(Register.x11), 8))); + beq(register(Register.x12), register(Register.x0), mainLoop); + + // Payload: write to RAM, summing as we go. + register(Register.x10).bind(li(ramBase)); + register(Register.x15).bind(li(0)); + register( + Register.x6, + ).bind(add(register(Register.x10), register(Register.x12))); + final payloadLoop = label('payload'); + _recvByte(); + sb(register(Register.x10), register(Register.x11)); + register( + Register.x15, + ).bind(add(register(Register.x15), register(Register.x11))); + register(Register.x10).bind(addi(register(Register.x10), 1)); + bne(register(Register.x10), register(Register.x6), payloadLoop); + + // Checksum byte, then verdict. + _recvByte(); + register(Register.x15).bind(andi(register(Register.x15), 0xff)); + final fail = Label('fail'); + bne(register(Register.x11), register(Register.x15), fail); + _sendImm(0x4B); // 'K' + register(Register.x5).bind(li(ramBase)); + jalr(register(Register.x5)); + + placeLabel(fail); + _sendImm(0x45); // 'E' + jal(mainLoop); + } + + /// Receives one byte into x11: poll LSR (offset 5) bit 0 (data ready), + /// then read RBR (offset 0). + void _recvByte() { + final wait = label('rxw${_labelSeq++}'); + final lsr = lbu(register(Register.x13), offset: 5); + register(Register.x14).bind(andi(lsr, 0x01)); + beq(register(Register.x14), register(Register.x0), wait); + register(Register.x11).bind(lbu(register(Register.x13))); + } + + /// Sends the immediate byte [ch]: poll LSR bit 5 (THRE), then write THR. + void _sendImm(int ch) { + final wait = label('txw${_labelSeq++}'); + final lsr = lbu(register(Register.x13), offset: 5); + register(Register.x14).bind(andi(lsr, 0x20)); + beq(register(Register.x14), register(Register.x0), wait); + register(Register.x11).bind(li(ch)); + sb(register(Register.x13), register(Register.x11)); + } + + /// Raw machine code for baking into a boot ROM's init data. + Uint8List generateBytes() => Uint8List.fromList(generateBinary()); +} diff --git a/packages/river_maskrom/lib/src/timer_poll_demo.dart b/packages/river_maskrom/lib/src/timer_poll_demo.dart new file mode 100644 index 0000000..86a7f00 --- /dev/null +++ b/packages/river_maskrom/lib/src/timer_poll_demo.dart @@ -0,0 +1,83 @@ +import 'dart:typed_data'; + +import 'package:river/river.dart'; +import 'package:river_adl/river_adl.dart'; + +/// A CLINT validation payload for cores without trap machinery (the nano +/// tier): polls `mtime` over the bus and prints one 'T' per elapsed +/// [tickHz]-cycle interval, [ticks] times, then jumps back to the boot +/// monitor at [monitorBase] (which reprints its banner, a visible clean exit). +/// +/// Elapsed time uses wrap-safe unsigned arithmetic on the low `mtime` word: +/// the loop spins while `(now - start) - delta` is negative, tested via the +/// sign bit (the DSL has only beq/bne, so ordering comparisons are built from +/// sub + srli). +/// +/// Registers: x13 UART base, x12 mtime address, x10 tick start, x6 delta, +/// x7 scratch, x11/x14 UART scratch, x5 jump target. +class RiverTimerPollDemo extends Module { + @override + final RiscVIsaConfig isa; + + int _labelSeq = 0; + + RiverTimerPollDemo({ + required this.isa, + required int uartBase, + required int clintBase, + int monitorBase = 0x00010000, + int tickHz = 12000000, + int ticks = 5, + }) { + final mtimeLo = clintBase + 0xBFF8; + + // Standalone UART re-init with the divisor HARDCODED for 115200 at a + // 12MHz clock (12e6/115200 = 104). On the iCESugar this matches what the + // monitor already set; a board at another clock should parametrize this + // (or drop the re-init and rely on the monitor's configuration). + register(Register.x13).bind(li(uartBase)); + register(Register.x11).bind(li(0x83)); + sb(register(Register.x13), register(Register.x11), offset: 3); + register(Register.x11).bind(li(104 & 0xff)); + sb(register(Register.x13), register(Register.x11), offset: 0); + register(Register.x11).bind(li(0)); + sb(register(Register.x13), register(Register.x11), offset: 1); + register(Register.x11).bind(li(0x03)); + sb(register(Register.x13), register(Register.x11), offset: 3); + + register(Register.x12).bind(li(mtimeLo)); + register(Register.x6).bind(li(tickHz)); + + for (var t = 0; t < ticks; t++) { + register(Register.x10).bind(lw(register(Register.x12))); // tick start + final wait = label('wait$t'); + final now = lw(register(Register.x12)); + register(Register.x7).bind(sub(now, register(Register.x10))); + register( + Register.x7, + ).bind(sub(register(Register.x7), register(Register.x6))); + register(Register.x7).bind(srli(register(Register.x7), 31)); + bne(register(Register.x7), register(Register.x0), wait); + _sendImm(0x54); // 'T' + } + _sendImm(0x0d); + _sendImm(0x0a); + + // Hand control back to the boot monitor. + register(Register.x5).bind(li(monitorBase)); + jalr(register(Register.x5)); + } + + /// Sends the immediate byte [ch]: poll LSR bit 5 (THRE), then write THR. + void _sendImm(int ch) { + final wait = label('txw${_labelSeq++}'); + final lsr = lbu(register(Register.x13), offset: 5); + register(Register.x14).bind(andi(lsr, 0x20)); + beq(register(Register.x14), register(Register.x0), wait); + register(Register.x11).bind(li(ch)); + sb(register(Register.x13), register(Register.x11)); + } + + /// Raw machine code for loading via the serial monitor. + Uint8List generateBytes() => Uint8List.fromList(generateBinary()); +} diff --git a/packages/river_maskrom/lib/src/trap_wfi_test.dart b/packages/river_maskrom/lib/src/trap_wfi_test.dart new file mode 100644 index 0000000..44e9d7a --- /dev/null +++ b/packages/river_maskrom/lib/src/trap_wfi_test.dart @@ -0,0 +1,121 @@ +import 'dart:typed_data'; + +import 'package:river/river.dart'; +import 'package:river_adl/river_adl.dart'; + +/// Tiny SRAM-class bring-up that proves two microcode fixes on silicon without +/// the DDR/Weir stack: MRET redirects the PC, and WFI retires instead of wedging. +/// +/// UART marker sequence: +/// "CREEK " core ran from the boot ROM +/// "M " about to MRET +/// "R " MRET landed at mepc and jal'd back +/// "W " WFI retired +/// "OK\r\n" full pass, then loops +/// +/// Broken MRET loops on the mret (no "R"); broken WFI wedges (no "W"/"OK"). +/// +/// The landing pad sits at [romBase]+4: the first instruction is a `jal` over it, +/// so its absolute address is known at build time for MRET's mepc (the ADL has +/// no absolute label-load). +class RiverTrapWfiTest extends Module { + @override + final RiscVIsaConfig isa; + + RiverTrapWfiTest({ + required this.isa, + required int uartBase, + required int romBase, + int clockHz = 12000000, + int baud = 115200, + }) { + final divisor = (clockHz ~/ baud).clamp(1, 0xffff); + var uid = 0; + + // UART 8N1 setup (ns16550a). x13 holds the UART base; each block + // re-materializes it so nothing depends on register state carried across the + // MRET edge (invisible to the assembler). + void uartInit() { + register(Register.x13).bind(li(uartBase)); + register(Register.x11).bind(li(0x83)); // LCR: DLAB=1, 8N1 + sb(register(Register.x13), register(Register.x11), offset: 3); + register(Register.x11).bind(li(divisor & 0xff)); + sb(register(Register.x13), register(Register.x11), offset: 0); + register(Register.x11).bind(li((divisor >> 8) & 0xff)); + sb(register(Register.x13), register(Register.x11), offset: 1); + register(Register.x11).bind(li(0x03)); // LCR: DLAB=0, 8N1 + sb(register(Register.x13), register(Register.x11), offset: 3); + } + + // Poll THRE (LSR bit 5) then write one byte to THR. x13 must hold uartBase. + void putc(int c) { + final wait = label('tx_${uid++}'); + final lsr = lbu(register(Register.x13), offset: 5); + register(Register.x14).bind(andi(lsr, 0x20)); + beq(register(Register.x14), register(Register.x0), wait); + register(Register.x11).bind(li(c)); + sb(register(Register.x13), register(Register.x11)); + } + + void puts(String s) { + register(Register.x13).bind(li(uartBase)); + for (final u in s.codeUnits) { + putc(u); + } + } + + final mainStart = label('main_start'); + final afterMret = label('after_mret'); + + // RV+0: single jal over the landing pad, so the pad sits at a known RV+4. + jal(mainStart); + + // Landing pad @ romBase+4: the MRET target. Mark that MRET landed, rejoin main. + puts('R '); + jal(afterMret); + + // Main flow. + placeLabel(mainStart); + uartInit(); + puts('CREEK '); + puts('M '); + + // MRET to the landing pad at romBase+4, staying in M-mode (mstatus.MPP=3). + register(Register.x10).bind(li(romBase + 4)); + csrrw(CsrAddress.mepc.address, register(Register.x10)); + register(Register.x11).bind(li(0x1800)); // MPP = M + csrrw(CsrAddress.mstatus.address, register(Register.x11)); + mret(); + + // Only reached if MRET failed to redirect: shout and spin. + puts('MFAIL '); + final deadSpin = label('dead_spin'); + jal(deadSpin); + + // Reached from the landing pad after a good MRET. + placeLabel(afterMret); + // Prove WFI retires: if it wedged, "W" and "OK" never print. + wfi(); + puts('W '); + puts('OK\r\n'); + + // Loop the whole sequence so a settled UART line reads a clean pass. + jal(mainStart); + } + + /// Raw machine code for baking into a boot ROM's init data. + Uint8List generateBytes() => Uint8List.fromList(generateBinary()); + + /// An ELF wrapping the program at [entryPoint], for the emulator/HDL sim. + Uint8List emitElfBytes({required int entryPoint}) { + final section = emitToSection(name: '.text', baseAddress: entryPoint); + final writer = ElfWriter( + entryPoint: entryPoint, + elfClass: isa.mxlen == RiscVMxlen.rv64 + ? ElfWriterClass.elf64 + : ElfWriterClass.elf32, + ); + writer.addSection(section, address: entryPoint); + return Uint8List.fromList(writer.write()); + } +} diff --git a/packages/river_maskrom/pubspec.yaml b/packages/river_maskrom/pubspec.yaml new file mode 100644 index 0000000..ba13b72 --- /dev/null +++ b/packages/river_maskrom/pubspec.yaml @@ -0,0 +1,21 @@ +name: river_maskrom +description: Maskrom firmware generator for River SoCs. +version: 1.0.0 +resolution: workspace + +environment: + sdk: ^3.11.2 + +dependencies: + bintools: ^1.0.0 + harbor: ^0.0.1 + river: ^1.0.0 + river_adl: ^1.0.0 + +dev_dependencies: + lints: ^6.0.0 + river_emulator: ^1.0.0 + river_hdl: ^1.0.0 + rohd: ^0.6.8 + rohd_hcl: ^0.2.1 + test: ^1.28.0 diff --git a/packages/river_maskrom/test/bundle_selftest_copy_test.dart b/packages/river_maskrom/test/bundle_selftest_copy_test.dart new file mode 100644 index 0000000..83849ba --- /dev/null +++ b/packages/river_maskrom/test/bundle_selftest_copy_test.dart @@ -0,0 +1,165 @@ +import 'dart:async'; + +import 'package:bintools/bintools.dart'; +import 'package:river/river.dart'; +import 'package:river_emulator/river_emulator.dart'; +import 'package:river_maskrom/river_maskrom.dart'; +import 'package:test/test.dart'; + +/// Reproduce the silent-bundle COPY bug in the emulator. The HDL flash-read bug +/// is fixed (the on-hardware probe now dumps dense flash), but the maskrom's +/// flash->SRAM copy left SRAM all-zero except word0 (= the firmware's trailing +/// `jal`), i.e. the destination pointer never advanced. The emulator models the +/// flash as perfect memory, so if the COPY LOOP the ADL emits is broken this +/// test reproduces it (SRAM holds only word0); if the copy is correct here, the +/// fault is HDL-core lw/sw lane handling instead. +RiverCoreConfig _rv64() => RiverCoreConfigV1.micro( + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + interrupts: [], + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + resetVector: 0x70000000, +); + +void main() { + test('bundleselftest copy lands the whole firmware in SRAM', () async { + const romBase = 0x70000000; // selftest runs from here + const flashBase = 0x20000000; + const fwOffset = 0x100000; + const uartBase = 0x10000000; + const ramBase = 0x80000000; + + final config = _rv64(); + + // The firmware that gets copied (and its length -> copyWords). + final fw = RiverFlashHexdump( + isa: config.isa, + uartBase: uartBase, + flashBase: flashBase, + dumpBytes: 16, + clockHz: 10000, + baud: 1250, + ); + await fw.build(); + final fwBytes = fw.generateBytes(); + final copyWords = (fwBytes.length + 3) >> 2; + + final probe = RiverBundleSelfTest( + isa: config.isa, + uartBase: uartBase, + flashSource: flashBase + fwOffset, + copyDest: ramBase, + copyWords: copyWords, + probeBytes: 32, + clockHz: 10000, + baud: 1250, + ); + await probe.build(); + final probeBytes = probe.generateBytes(); + + final rom = Sram( + RiverDevice( + name: 'rom', + compatible: 'river,sram', + range: BusAddressRange(romBase, 0x10000), + clockFrequency: 10000, + ), + ); + final flash = Sram( + RiverDevice( + name: 'flash', + compatible: 'river,sram', + range: BusAddressRange(flashBase, 0x200000), + clockFrequency: 10000, + ), + ); + final sram = Sram( + RiverDevice( + name: 'sram', + compatible: 'river,sram', + range: BusAddressRange(ramBase, 0x10000), + clockFrequency: 10000, + ), + ); + + final outputController = StreamController>(sync: true); + final inputController = StreamController>(sync: true); + final uartOutput = []; + outputController.stream.listen(uartOutput.addAll); + final uart = Uart( + RiverDevice( + name: 'uart0', + compatible: 'ns16550a', + range: BusAddressRange(uartBase, 0x100), + interrupts: [0], + clockFrequency: 10000, + ), + input: inputController.stream, + output: outputController.sink, + ); + + // selftest in ROM, firmware in flash at fwOffset. + for (var i = 0; i < probeBytes.length; i++) { + rom.data[i] = probeBytes[i]; + } + for (var i = 0; i < fwBytes.length; i++) { + flash.data[fwOffset + i] = fwBytes[i]; + } + + final core = RiverCore( + config, + memDevices: Map.fromEntries([rom.mem!, flash.mem!, sram.mem!, uart.mem!]), + ); + + var pc = romBase; + for (var i = 0; i < 2000000; i++) { + final instr = await core.fetch(pc); + final next = await core.cycle(pc, instr); + if (next == pc) break; // hit a spin (firmware's jal done, or trap) + pc = next; + } + await uart.flush(); + await Future.delayed(Duration.zero); + + // Check the SRAM the copy produced, directly (independent of UART parsing). + final fw0 = + fwBytes[0] | + (fwBytes[1] << 8) | + (fwBytes[2] << 16) | + (fwBytes[3] << 24); + final sr0 = + sram.data[0] | + (sram.data[1] << 8) | + (sram.data[2] << 16) | + (sram.data[3] << 24); + final fw4 = + fwBytes[4] | + (fwBytes[5] << 8) | + (fwBytes[6] << 16) | + (fwBytes[7] << 24); + final sr4 = + sram.data[4] | + (sram.data[5] << 8) | + (sram.data[6] << 16) | + (sram.data[7] << 24); + // ignore: avoid_print + print( + 'fw[0]=0x${fw0.toRadixString(16)} sram[0]=0x${sr0.toRadixString(16)} ' + 'fw[4]=0x${fw4.toRadixString(16)} sram[4]=0x${sr4.toRadixString(16)}', + ); + + expect(sr0, equals(fw0), reason: 'SRAM word0 != firmware word0 (copy bug)'); + expect( + sr4, + equals(fw4), + reason: 'SRAM word1 == 0 -> dst pointer never advanced (copy bug)', + ); + }); +} diff --git a/packages/river_maskrom/test/ddr_level_xilinx_test.dart b/packages/river_maskrom/test/ddr_level_xilinx_test.dart new file mode 100644 index 0000000..e0b3159 --- /dev/null +++ b/packages/river_maskrom/test/ddr_level_xilinx_test.dart @@ -0,0 +1,40 @@ +import 'package:river/river.dart'; +import 'package:river_maskrom/river_maskrom.dart'; +import 'package:test/test.dart'; + +RiverCoreConfig _cfg() => RiverCoreConfigV1.micro( + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + interrupts: [], + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + resetVector: 0x80000000, +); + +void main() { + test( + 'RiverDdrLevelXilinx generates a non-empty position-independent ROM', + () async { + final prog = RiverDdrLevelXilinx( + isa: _cfg().isa, + uartBase: 0x10000000, + dramBase: 0x80000000, + // Train-control window sits just above a 256M DRAM array (non-DRAM MMIO). + trainCtrlBase: 0x80000000 + 0x10000000, + ); + await prog.build(); + final bytes = prog.generateBytes(); + // Non-trivial (the leveling loops are runtime, not Dart-unrolled, so the ROM + // stays small but is clearly more than the UART setup). + expect(bytes.length, greaterThan(200)); + // ROM-fit guard (unroll-romfit lesson: stay well under the boot-ROM budget). + expect(bytes.length, lessThan(8192)); + }, + ); +} diff --git a/packages/river_maskrom/test/flash_hexdump_test.dart b/packages/river_maskrom/test/flash_hexdump_test.dart new file mode 100644 index 0000000..96d594b --- /dev/null +++ b/packages/river_maskrom/test/flash_hexdump_test.dart @@ -0,0 +1,266 @@ +import 'dart:async'; + +import 'package:bintools/bintools.dart'; +import 'package:river/river.dart'; +import 'package:river_emulator/river_emulator.dart'; +import 'package:river_maskrom/river_maskrom.dart'; +import 'package:test/test.dart'; + +RiverCoreConfig _microConfig() => RiverCoreConfigV1.micro( + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv32, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + interrupts: [], + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + resetVector: 0x80000000, +); + +void main() { + group('RiverFlashHexdump', () { + test('emits a non-empty binary with the UART and flash bases', () async { + final fw = RiverFlashHexdump( + isa: _microConfig().isa, + uartBase: 0x10000000, + flashBase: 0x20000000, + clockHz: 12000000, + ); + await fw.build(); + final bin = fw.generateBytes(); + expect(bin, isNotEmpty); + + final asm = fw.generateAssembly(); + // UART setup, flash read, hex-dump control flow. + expect(asm, contains('lbu')); + expect(asm, contains('sb')); + expect(asm, contains('andi')); + expect(asm, contains('srli')); + expect(asm, contains('bne')); + + // A valid ELF can wrap it for the sim path. + final elf = Elf.load(fw.emitElfBytes(entryPoint: 0x80000000)); + expect(elf.header.entry, 0x80000000); + }); + + test('dumps flash bytes over the UART as a hex dump', () async { + // Run the firmware in the emulator from SRAM, reading a small flash + // window, and check the streamed hex dump. + const flashBase = 0x20000000; + const uartBase = 0x10000000; + const ramBase = 0x80000000; + const dumpBytes = 32; // 2 lines, keeps the cycle count modest. + + final config = _microConfig(); + final fw = RiverFlashHexdump( + isa: config.isa, + uartBase: uartBase, + flashBase: flashBase, + dumpBytes: dumpBytes, + clockHz: 10000, + baud: 1250, // divisor 8: non-zero so TX drains quickly in sim + ); + await fw.build(); + final bin = fw.generateBytes(); + + final flash = Sram( + RiverDevice( + name: 'flash', + compatible: 'river,sram', + range: BusAddressRange(flashBase, 0x200000), + clockFrequency: 10000, + ), + ); + final sram = Sram( + RiverDevice( + name: 'sram', + compatible: 'river,sram', + range: BusAddressRange(ramBase, 0x10000), + clockFrequency: 10000, + ), + ); + + final outputController = StreamController>(sync: true); + final inputController = StreamController>(sync: true); + final uartOutput = []; + outputController.stream.listen(uartOutput.addAll); + final uart = Uart( + RiverDevice( + name: 'uart0', + compatible: 'ns16550a', + range: BusAddressRange(uartBase, 0x100), + interrupts: [0], + clockFrequency: 10000, + ), + input: inputController.stream, + output: outputController.sink, + ); + + // The firmware executes from SRAM (the bundled-flash path: maskrom copied + // it here). Load it at ramBase. + for (var i = 0; i < bin.length; i++) { + sram.data[i] = bin[i]; + } + + // Known flash contents: a recognizable ramp so we can check the hex. + for (var i = 0; i < dumpBytes; i++) { + flash.data[i] = i & 0xff; + } + + final core = RiverCore( + config, + memDevices: Map.fromEntries([flash.mem!, sram.mem!, uart.mem!]), + ); + + var pc = ramBase; + for (var i = 0; i < 200000; i++) { + final instr = await core.fetch(pc); + final next = await core.cycle(pc, instr); + // The firmware spins on itself at the end (jal done): detect the + // self-loop and stop. + if (next == pc) break; + pc = next; + } + + await uart.flush(); + await Future.delayed(Duration.zero); + + final text = String.fromCharCodes(uartOutput); + // First line: offset 00000000, bytes 00..0f. + expect( + text, + contains('00000000: 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f'), + ); + // Second line: offset 00000010, bytes 10..1f. + expect( + text, + contains('00000010: 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f'), + ); + expect(text, contains('DUMP DONE')); + }); + + test('dumps two regions with headers (SILENT bring-up probe)', () async { + // The diagnostic probe: dump two flash windows in one boot, each with its + // own header. Region A = a known pattern at the flash base; region B = a + // different known pattern 0x100000 above it. This proves the probe logic + // before silicon. Both windows are read by lbu XIP from flash. + const flashBase = 0x20000000; + const uartBase = 0x10000000; + const ramBase = 0x80000000; + const regionBLen = 16; // one line, keeps the cycle count modest. + const regionAOffset = 0x0; + const regionBOffset = 0x100000; + + final config = _microConfig(); + final fw = RiverFlashHexdump( + isa: config.isa, + uartBase: uartBase, + flashBase: flashBase, + clockHz: 10000, + baud: 1250, // divisor 8: non-zero so TX drains quickly in sim + regions: [ + // Region A: a 16-byte window with an ascending ramp (stand-in for the + // ECP5 bitstream preamble). + HexdumpRegion(base: flashBase, length: 16, header: 'FLASH @0:'), + // Region B: a 16-byte window at +0x100000 with a 0xa? pattern + // (stand-in for the firmware slot). + HexdumpRegion( + base: flashBase + regionBOffset, + length: regionBLen, + header: 'FLASH @100000:', + ), + ], + ); + await fw.build(); + final bin = fw.generateBytes(); + + final flash = Sram( + RiverDevice( + name: 'flash', + compatible: 'river,sram', + range: BusAddressRange(flashBase, 0x200000), + clockFrequency: 10000, + ), + ); + final sram = Sram( + RiverDevice( + name: 'sram', + compatible: 'river,sram', + range: BusAddressRange(ramBase, 0x10000), + clockFrequency: 10000, + ), + ); + + final outputController = StreamController>(sync: true); + final inputController = StreamController>(sync: true); + final uartOutput = []; + outputController.stream.listen(uartOutput.addAll); + final uart = Uart( + RiverDevice( + name: 'uart0', + compatible: 'ns16550a', + range: BusAddressRange(uartBase, 0x100), + interrupts: [0], + clockFrequency: 10000, + ), + input: inputController.stream, + output: outputController.sink, + ); + + // The probe executes from SRAM here (in the real bitstream it runs from + // the boot ROM); load it at ramBase. + for (var i = 0; i < bin.length; i++) { + sram.data[i] = bin[i]; + } + + // Region A pattern: an ascending ramp at flash offset 0. + for (var i = 0; i < 16; i++) { + flash.data[regionAOffset + i] = i & 0xff; + } + // Region B pattern: 0xa0 | i at flash offset 0x100000 (distinct from A). + for (var i = 0; i < regionBLen; i++) { + flash.data[regionBOffset + i] = (0xa0 | i) & 0xff; + } + + final core = RiverCore( + config, + memDevices: Map.fromEntries([flash.mem!, sram.mem!, uart.mem!]), + ); + + var pc = ramBase; + for (var i = 0; i < 400000; i++) { + final instr = await core.fetch(pc); + final next = await core.cycle(pc, instr); + if (next == pc) break; // self-loop at the end (jal done) + pc = next; + } + + await uart.flush(); + await Future.delayed(Duration.zero); + + final text = String.fromCharCodes(uartOutput); + // Region A header + its bytes. + expect(text, contains('FLASH @0:')); + expect( + text, + contains('00000000: 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f'), + ); + // Region B header + its bytes (distinct pattern). + expect(text, contains('FLASH @100000:')); + expect( + text, + contains('00000000: a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 aa ab ac ad ae af'), + ); + // Header A must precede header B in the stream. + expect( + text.indexOf('FLASH @0:') < text.indexOf('FLASH @100000:'), + isTrue, + ); + expect(text, contains('DUMP DONE')); + }); + }); +} diff --git a/packages/river_maskrom/test/maskrom_copy_jump_test.dart b/packages/river_maskrom/test/maskrom_copy_jump_test.dart new file mode 100644 index 0000000..493e660 --- /dev/null +++ b/packages/river_maskrom/test/maskrom_copy_jump_test.dart @@ -0,0 +1,142 @@ +import 'dart:typed_data'; + +import 'package:river/river.dart'; +import 'package:river_emulator/river_emulator.dart'; +import 'package:river_maskrom/river_maskrom.dart'; +import 'package:test/test.dart'; + +/// End-to-end regression for the silent-bundle COPY bug in the PRODUCTION +/// maskrom: it must copy the whole firmware from flash into SRAM (not just the +/// last word to dst[0]) and jump to it. The bug was the ADL dropping the +/// destination-pointer increment in the copy loop. A tiny firmware stores a +/// sentinel to a known SRAM address and spins; we check both that SRAM received +/// the full firmware image AND that the sentinel landed (so the jump ran it). +RiverCoreConfig _rv64() => RiverCoreConfigV1.micro( + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + interrupts: [], + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + resetVector: 0x70000000, +); + +void main() { + test('maskrom copies the full firmware to SRAM and jumps to it', () async { + const romBase = 0x70000000; + const flashBase = 0x20000000; + const fwOffset = 0x100000; + const ramBase = 0x80000000; + const sentinelAddr = ramBase + 0x4000; // outside the copied image + const sentinel = 0xdeadbeef; + + final config = _rv64(); + + // Tiny position-independent firmware: x5 = sentinelAddr; x6 = sentinel; + // sw x6,(x5); spin. Hand-assembled RV32/64 (li via lui+addi, sw, jal 0). + final fwWords = [ + 0x80004337, // lui x6, 0x80004 -> x6 = 0x80004000 (sentinelAddr) + // addi x6,x6,0 omitted (offset 0) + 0xdeadc2b7, // lui x5, 0xdeadc -> x5 = 0xdeadc000 + 0xeef28293, // addi x5,x5,-273 -> x5 = 0xdeadbeef (sentinel) + 0x00532023, // sw x5, 0(x6) -> mem[sentinelAddr] = sentinel + 0x0000006f, // jal x0, 0 -> spin + ]; + final fwBytes = Uint8List(fwWords.length * 4); + for (var i = 0; i < fwWords.length; i++) { + fwBytes[i * 4] = fwWords[i] & 0xff; + fwBytes[i * 4 + 1] = (fwWords[i] >> 8) & 0xff; + fwBytes[i * 4 + 2] = (fwWords[i] >> 16) & 0xff; + fwBytes[i * 4 + 3] = (fwWords[i] >> 24) & 0xff; + } + + final rom = RiverMaskrom( + RiverMaskromConfig( + isa: config.isa, + resetVector: romBase, + flashSource: flashBase + fwOffset, + copyDest: ramBase, + copySize: (fwBytes.length + 3) & ~3, + stackTop: ramBase + 0x8000, + ), + ); + await rom.build(); + final romBytes = rom.generateBinary(); + + final romMem = Sram( + RiverDevice( + name: 'rom', + compatible: 'river,sram', + range: BusAddressRange(romBase, 0x10000), + clockFrequency: 10000, + ), + ); + final flash = Sram( + RiverDevice( + name: 'flash', + compatible: 'river,sram', + range: BusAddressRange(flashBase, 0x200000), + clockFrequency: 10000, + ), + ); + final sram = Sram( + RiverDevice( + name: 'sram', + compatible: 'river,sram', + range: BusAddressRange(ramBase, 0x10000), + clockFrequency: 10000, + ), + ); + + for (var i = 0; i < romBytes.length; i++) { + romMem.data[i] = romBytes[i]; + } + for (var i = 0; i < fwBytes.length; i++) { + flash.data[fwOffset + i] = fwBytes[i]; + } + + final core = RiverCore( + config, + memDevices: Map.fromEntries([romMem.mem!, flash.mem!, sram.mem!]), + ); + + var pc = romBase; + var spun = false; + for (var i = 0; i < 200000; i++) { + final instr = await core.fetch(pc); + final next = await core.cycle(pc, instr); + if (next == pc) { + spun = true; + break; + } + pc = next; + } + + // Firmware image must be byte-for-byte in SRAM. + for (var i = 0; i < fwBytes.length; i++) { + expect( + sram.data[i], + equals(fwBytes[i]), + reason: 'SRAM[$i] != firmware[$i] (copy dropped bytes)', + ); + } + // The jump ran the firmware: the sentinel landed. + final off = sentinelAddr - ramBase; + final got = + sram.data[off] | + (sram.data[off + 1] << 8) | + (sram.data[off + 2] << 16) | + (sram.data[off + 3] << 24); + expect( + got, + equals(sentinel), + reason: 'sentinel not written -> maskrom never jumped into the copy', + ); + expect(spun, isTrue, reason: 'firmware never reached its spin loop'); + }); +} diff --git a/packages/river_maskrom/test/maskrom_hdl_test.dart b/packages/river_maskrom/test/maskrom_hdl_test.dart new file mode 100644 index 0000000..6e9c641 --- /dev/null +++ b/packages/river_maskrom/test/maskrom_hdl_test.dart @@ -0,0 +1,85 @@ +import 'package:river/river.dart'; +import 'package:river_maskrom/river_maskrom.dart'; +import 'package:test/test.dart'; + +RiverCoreConfig _microConfig() => RiverCoreConfigV1.micro( + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv32, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + interrupts: [], + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + resetVector: 0x0, +); + +void main() { + test('maskrom binary is valid for HDL loading', () async { + final config = _microConfig(); + + final rom = RiverMaskrom( + RiverMaskromConfig( + isa: config.isa, + resetVector: 0x0, + flashSource: 0x400, + copyDest: 0x800, + copySize: 4, + stackTop: 0xC00, + ), + ); + + await rom.build(); + + final binary = rom.generateBinary(); + expect(binary.length, greaterThan(0)); + expect(binary.length % 4, 0); + + // Every 4-byte word should be a valid 32-bit instruction + for (var i = 0; i < binary.length; i += 4) { + final word = + binary[i] | + (binary[i + 1] << 8) | + (binary[i + 2] << 16) | + (binary[i + 3] << 24); + // Bottom 2 bits = 0x3 for 32-bit instructions + expect(word & 0x3, 0x3, reason: 'instruction at offset $i is not 32-bit'); + } + + final asm = rom.generateAssembly(); + expect(asm, contains('lw')); + expect(asm, contains('sw')); + expect(asm, contains('bne')); + expect(asm, contains('jalr')); + expect(asm, contains('csrrw')); + }); + + test('CAR maskrom includes cache lock CSRs', () async { + final config = _microConfig(); + + final rom = RiverMaskrom( + RiverMaskromConfig( + isa: config.isa, + resetVector: 0x0, + flashSource: 0x400, + copyDest: 0x800, + copySize: 4, + stackTop: 0xC00, + bootMode: RiverBootMode.cacheAsRam, + ), + ); + + await rom.build(); + final asm = rom.generateAssembly(); + + // Should have CSR writes for rcachectl (0x7C0), rcacheaddr (0x7C1), rcachesize (0x7C2) + final csrWrites = asm + .split('\n') + .where((l) => l.contains('csrrw')) + .toList(); + expect(csrWrites.length, greaterThanOrEqualTo(4)); // mtvec + 3 cache CSRs + }); +} diff --git a/packages/river_maskrom/test/maskrom_test.dart b/packages/river_maskrom/test/maskrom_test.dart new file mode 100644 index 0000000..8d7aa6f --- /dev/null +++ b/packages/river_maskrom/test/maskrom_test.dart @@ -0,0 +1,202 @@ +import 'package:bintools/bintools.dart'; +import 'package:river/river.dart'; +import 'package:river_emulator/river_emulator.dart'; +import 'package:river_maskrom/river_maskrom.dart'; +import 'package:test/test.dart'; + +RiverCoreConfig _microConfig() => RiverCoreConfigV1.micro( + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv32, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + interrupts: [], + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + resetVector: 0x20000000, +); + +RiverMaskromConfig _maskromConfig({int copySize = 64}) => RiverMaskromConfig( + isa: _microConfig().isa, + resetVector: 0x20000000, + flashSource: 0x20100000, + copyDest: 0x80000000, + copySize: copySize, + stackTop: 0x20010000, +); + +void main() { + group('Maskrom', () { + test('produces assembly with copy loop and jalr', () async { + final rom = RiverMaskrom(_maskromConfig()); + await rom.build(); + + final asm = rom.generateAssembly(); + expect(asm, contains('lw')); + expect(asm, contains('sw')); + expect(asm, contains('bne')); + expect(asm, contains('jalr')); + }); + + test('produces valid ELF', () async { + final rom = RiverMaskrom(_maskromConfig()); + await rom.build(); + + final elf = Elf.load(rom.emitElfBytes(entryPoint: 0x20000000)); + + expect(elf.header.entry, 0x20000000); + expect(elf.programHeaders.where((ph) => ph.type == 1), isNotEmpty); + }); + + test('copies firmware from flash to SRAM and jumps', () async { + final config = _microConfig(); + final rom = RiverMaskrom(_maskromConfig(copySize: 8)); + await rom.build(); + + final flash = Sram( + RiverDevice( + name: 'flash', + compatible: 'river,sram', + range: BusAddressRange(0x20000000, 0x200000), + clockFrequency: 10000, + ), + ); + + final sram = Sram( + RiverDevice( + name: 'sram', + compatible: 'river,sram', + range: BusAddressRange(0x80000000, 0x10000), + clockFrequency: 10000, + ), + ); + + final core = RiverCore( + config, + memDevices: Map.fromEntries([flash.mem!, sram.mem!]), + ); + + final binary = rom.generateBinary(); + for (var i = 0; i < binary.length; i++) { + flash.data[i] = binary[i]; + } + + // addi x5, x0, 42 + final fwOffset = 0x20100000 - 0x20000000; + flash.data[fwOffset + 0] = 0x93; + flash.data[fwOffset + 1] = 0x02; + flash.data[fwOffset + 2] = 0xA0; + flash.data[fwOffset + 3] = 0x02; + // nop + flash.data[fwOffset + 4] = 0x13; + flash.data[fwOffset + 5] = 0x00; + flash.data[fwOffset + 6] = 0x00; + flash.data[fwOffset + 7] = 0x00; + + var pc = 0x20000000; + for (var i = 0; i < 200; i++) { + final instr = await core.fetch(pc); + pc = await core.cycle(pc, instr); + if (pc.toUnsigned(32) == 0x80000000) break; + } + + expect(pc.toUnsigned(32), 0x80000000); + expect(core.mode, PrivilegeMode.machine); + + expect(sram.data[0], 0x93); + expect(sram.data[1], 0x02); + expect(sram.data[2], 0xA0); + expect(sram.data[3], 0x02); + + final fwInstr = await core.fetch(pc); + pc = await core.cycle(pc, fwInstr); + expect(core.xregs[Register.x5], 42); + }); + + test('CAR mode locks cache and copies firmware', () async { + final coreConfig = RiverCoreConfigV1.micro( + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv32, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + interrupts: [], + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + resetVector: 0x20000000, + l1cache: HarborL1CacheConfig.split( + iSize: 0x4000, + dSize: 0x4000, + ways: 4, + lineSize: 64, + ), + ); + + final rom = RiverMaskrom( + RiverMaskromConfig( + isa: coreConfig.isa, + resetVector: 0x20000000, + flashSource: 0x20100000, + copyDest: 0x80000000, + copySize: 8, + stackTop: 0x80001000, + bootMode: RiverBootMode.cacheAsRam, + ), + ); + + await rom.build(); + final asm = rom.generateAssembly(); + expect(asm, contains('csrrw')); + expect(asm, contains('jalr')); + + final flash = Sram( + RiverDevice( + name: 'flash', + compatible: 'river,sram', + range: BusAddressRange(0x20000000, 0x200000), + clockFrequency: 10000, + ), + ); + + final core = RiverCore( + coreConfig, + memDevices: Map.fromEntries([flash.mem!]), + ); + + final binary = rom.generateBinary(); + for (var i = 0; i < binary.length; i++) { + flash.data[i] = binary[i]; + } + + // Firmware at flash source + final fwOffset = 0x20100000 - 0x20000000; + flash.data[fwOffset + 0] = 0x93; + flash.data[fwOffset + 1] = 0x02; + flash.data[fwOffset + 2] = 0xA0; + flash.data[fwOffset + 3] = 0x02; + flash.data[fwOffset + 4] = 0x13; + flash.data[fwOffset + 5] = 0x00; + flash.data[fwOffset + 6] = 0x00; + flash.data[fwOffset + 7] = 0x00; + + var pc = 0x20000000; + for (var i = 0; i < 300; i++) { + final instr = await core.fetch(pc); + pc = await core.cycle(pc, instr); + if (pc.toUnsigned(32) == 0x80000000) break; + } + + expect(pc.toUnsigned(32), 0x80000000); + + // Firmware should be readable from locked L1D cache + final cached = await core.read(0x80000000, 4); + expect(cached & 0xFFFFFFFF, 0x02A00293); + }); + }); +} diff --git a/packages/river_maskrom/test/min_tracker_test.dart b/packages/river_maskrom/test/min_tracker_test.dart new file mode 100644 index 0000000..71c44c4 --- /dev/null +++ b/packages/river_maskrom/test/min_tracker_test.dart @@ -0,0 +1,172 @@ +import 'package:river/river.dart'; +import 'package:river_emulator/river_emulator.dart'; +import 'package:river_adl/river_adl.dart'; +import 'package:test/test.dart'; + +/// Isolates the min-residue tracker pattern the DDR sweeps use (slt/beq/latch). +/// This is the recurring "tracker never updates / latches the first combo" bug. +/// A tiny ADL program walks a residue array in SRAM, runs the EXACT +/// `x12 = slt(res, min); beq x12,x0,skip; min=res; idx=i` pattern, and writes +/// (min, idx) to SRAM. We inject a sequence whose true minimum is NOT the first +/// element and assert the tracker finds it. +class _MinTracker extends Module { + _MinTracker({ + required this.isa, + required this.arrBase, + required this.outBase, + required this.n, + }); + @override + final RiscVIsaConfig isa; + final int arrBase; + final int outBase; + final int n; + + void emit() { + // x20 = min (init 0x1000), x21 = best idx, x25 = i (0..n-1). + register(Register.x20).bind(li(0x1000)); + register(Register.x21).bind(li(0)); + register(Register.x25).bind(li(0)); // i + final top = label('top'); + // load res = mem[arrBase + i*4]; addr = arrBase + (i<<2). + register(Register.x11).bind(slli(register(Register.x25), 2)); // i*4 + register(Register.x10).bind(li(arrBase)); + register( + Register.x10, + ).bind(add(register(Register.x10), register(Register.x11))); + register(Register.x4).bind(lw(register(Register.x10))); // res + register(Register.x11).bind(andi(register(Register.x4), 0xFFF)); // residue + // min-tracker: if residue < min, latch. + final skip = label('skip'); + register( + Register.x12, + ).bind(slt(register(Register.x11), register(Register.x20))); + beq(register(Register.x12), register(Register.x0), skip); + register(Register.x20).bind(mv(register(Register.x11))); // min = residue + register(Register.x21).bind(mv(register(Register.x25))); // idx = i + placeLabel(skip); + // i++; while i < n. + register(Register.x25).bind(addi(register(Register.x25), 1)); + register(Register.x11).bind(li(n)); + blt(register(Register.x25), register(Register.x11), top); + // store min -> out[0], idx -> out[1]. + register(Register.x10).bind(li(outBase)); + sw(register(Register.x10), register(Register.x20)); + register(Register.x10).bind(li(outBase + 4)); + sw(register(Register.x10), register(Register.x21)); + // spin. + final done = label('done'); + jal(done); + } +} + +void main() { + test( + 'min-residue tracker finds the global minimum (not the first element)', + () async { + const romBase = 0x70000000; + const ramBase = 0x80000000; + const arrBase = ramBase + 0x1000; + const outBase = ramBase + 0x2000; + + // Residue sequence: first element is large (0xFCE, the observed false min), + // the TRUE minimum (0x002) is at index 5, with smaller values before and + // after to exercise descent + non-update. + final residues = [0xFCE, 0x800, 0x400, 0xFCE, 0x100, 0x002, 0x050, 0x900]; + final trueMin = residues.reduce((a, b) => a < b ? a : b); // 0x002 + final trueIdx = residues.indexOf(trueMin); // 5 + + final config = RiverCoreConfigV1.micro( + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + ), + interrupts: [], + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(10000), + ), + resetVector: romBase, + ); + + final prog = _MinTracker( + isa: config.isa, + arrBase: arrBase, + outBase: outBase, + n: residues.length, + ); + prog.emit(); + await prog.build(); + final romBytes = prog.generateBinary(); + + final romMem = Sram( + RiverDevice( + name: 'rom', + compatible: 'river,sram', + range: BusAddressRange(romBase, 0x10000), + clockFrequency: 10000, + ), + ); + final sram = Sram( + RiverDevice( + name: 'sram', + compatible: 'river,sram', + range: BusAddressRange(ramBase, 0x10000), + clockFrequency: 10000, + ), + ); + for (var i = 0; i < romBytes.length; i++) { + romMem.data[i] = romBytes[i]; + } + // Seed the residue array into SRAM. + for (var i = 0; i < residues.length; i++) { + final off = (arrBase - ramBase) + i * 4; + sram.data[off] = residues[i] & 0xff; + sram.data[off + 1] = (residues[i] >> 8) & 0xff; + sram.data[off + 2] = (residues[i] >> 16) & 0xff; + sram.data[off + 3] = (residues[i] >> 24) & 0xff; + } + + final core = RiverCore( + config, + memDevices: Map.fromEntries([romMem.mem!, sram.mem!]), + ); + + var pc = romBase; + for (var i = 0; i < 200000; i++) { + final instr = await core.fetch(pc); + final next = await core.cycle(pc, instr); + if (next == pc) break; + pc = next; + } + + int read32(int addr) { + final off = addr - ramBase; + return sram.data[off] | + (sram.data[off + 1] << 8) | + (sram.data[off + 2] << 16) | + (sram.data[off + 3] << 24); + } + + final gotMin = read32(outBase); + final gotIdx = read32(outBase + 4); + expect( + gotMin, + equals(trueMin), + reason: + 'tracker latched min=0x${gotMin.toRadixString(16)} but the true ' + 'minimum is 0x${trueMin.toRadixString(16)} - the min-tracker never ' + 'descended past the first/large element (the recurring sweep bug)', + ); + expect( + gotIdx, + equals(trueIdx), + reason: + 'tracker latched idx=$gotIdx but the true minimum is at index ' + '$trueIdx', + ); + }, + ); +} diff --git a/packages/river_maskrom/test/trap_wfi_test_sim.dart b/packages/river_maskrom/test/trap_wfi_test_sim.dart new file mode 100644 index 0000000..8c592c9 --- /dev/null +++ b/packages/river_maskrom/test/trap_wfi_test_sim.dart @@ -0,0 +1,104 @@ +import 'dart:async'; + +import 'package:river/river.dart'; +import 'package:river_emulator/river_emulator.dart'; +import 'package:river_maskrom/river_maskrom.dart'; +import 'package:test/test.dart'; + +/// Emulator sim of the [RiverTrapWfiTest] boot program: proves the program +/// STRUCTURE is sound (the jal-over landing pad, and MRET redirecting to +/// romBase+4) independent of any FPGA. The emulator halts on WFI (idle), so it +/// stops after "CREEK M R "; the WFI NOP-advance itself is covered by the HDL +/// core_wfi_test. Seeing "R" proves MRET landed at mepc. +RiverCoreConfig _rv64(int romBase) => RiverCoreConfigV1.small( + mmu: HarborMmuConfig( + mxlen: RiscVMxlen.rv64, + pagingModes: const [RiscVPagingMode.bare, RiscVPagingMode.sv39], + tlbLevels: const [], + pmp: HarborPmpConfig.none, + hasSupervisorUserMemory: true, + hasMakeExecutableReadable: true, + ), + interrupts: [], + clock: const HarborClockConfig( + name: 'test', + rate: HarborFixedClockRate(12000000), + ), + resetVector: romBase, +); + +void main() { + test('trapwfi boot program: core runs + MRET lands (emulator)', () async { + const romBase = 0x10000; + const uartBase = 0x10000000; + final config = _rv64(romBase); + + final prog = RiverTrapWfiTest( + isa: config.isa, + uartBase: uartBase, + romBase: romBase, + clockHz: 12000000, + ); + await prog.build(); + final progBytes = prog.generateBinary(); + + final romMem = Sram( + RiverDevice( + name: 'rom', + compatible: 'river,sram', + range: BusAddressRange(romBase, 0x10000), + clockFrequency: 12000000, + ), + ); + final uartOut = []; + final outCtl = StreamController>(sync: true); + final inCtl = StreamController>(sync: true); + outCtl.stream.listen(uartOut.addAll); + final uart = Uart( + RiverDevice( + name: 'uart0', + compatible: 'ns16550a', + range: BusAddressRange(uartBase, 0x1000), + interrupts: [0], + clockFrequency: 12000000, + ), + input: inCtl.stream, + output: outCtl.sink, + ); + + for (var i = 0; i < progBytes.length; i++) { + romMem.data[i] = progBytes[i]; + } + + final core = RiverCore( + config, + memDevices: Map.fromEntries([romMem.mem!, uart.mem!]), + ); + + var pc = romBase; + for (var i = 0; i < 2000000; i++) { + final instr = await core.fetch(pc); + pc = await core.cycle(pc, instr); + final s = String.fromCharCodes(uartOut); + if (s.contains('R ')) break; // MRET landed + } + + final out = String.fromCharCodes(uartOut); + // ignore: avoid_print + print( + 'trapwfi emulator UART: ${out.replaceAll('\r', '\\r').replaceAll('\n', '\\n')}', + ); + expect(out, contains('CREEK'), reason: 'core did not run; got: $out'); + expect(out, contains('M '), reason: 'never reached MRET; got: $out'); + expect( + out, + contains('R '), + reason: 'MRET did not land at mepc (still looping?); got: $out', + ); + expect( + out, + isNot(contains('MFAIL')), + reason: 'MRET fell through instead of redirecting; got: $out', + ); + }); +} diff --git a/pkgs/river-fpga/default.nix b/pkgs/river-fpga/default.nix new file mode 100644 index 0000000..c2db821 --- /dev/null +++ b/pkgs/river-fpga/default.nix @@ -0,0 +1,81 @@ +# Takes a river-ip derivation and runs FPGA synthesis + place-and-route. +# +# Usage: +# mkFpga { ip = self'.packages.creek-v1; } +# +# Produces: synth JSON, PnR output, bitstream +{ + lib, + stdenvNoCC, + yosys, + nextpnr, + icestorm, + trellis, +}: + +lib.extendMkDerivation { + constructDrv = stdenvNoCC.mkDerivation; + + excludeDrvArgNames = [ + "ip" + ]; + + extendDrvArgs = + finalAttrs: + { + ip, + name ? "river-fpga-${ip.socName}", + ... + }@args: + + builtins.removeAttrs args [ "ip" ] + // { + inherit name; + + dontUnpack = true; + dontConfigure = true; + + nativeBuildInputs = (args.nativeBuildInputs or [ ]) ++ [ + yosys + nextpnr + icestorm # icepack + trellis # ecppack + ]; + + buildPhase = '' + runHook preBuild + + # Copy IP output to writable directory + cp -r ${ip}/* . + chmod -R u+w . + + make all + + runHook postBuild + ''; + + installPhase = '' + runHook preInstall + + mkdir -p $out + cp -r rtl $out/ + cp *.json $out/ 2>/dev/null || true + cp *.asc $out/ 2>/dev/null || true + cp *.config $out/ 2>/dev/null || true + cp *.bin $out/ 2>/dev/null || true + cp *.bit $out/ 2>/dev/null || true + cp *.dts $out/ 2>/dev/null || true + cp *.dot $out/ 2>/dev/null || true + cp *.pcf $out/ 2>/dev/null || true + cp *.lpf $out/ 2>/dev/null || true + + runHook postInstall + ''; + + passthru = { + inherit ip; + inherit (ip) socName; + } + // (args.passthru or { }); + }; +} diff --git a/pkgs/river-hdl/default.nix b/pkgs/river-hdl/default.nix new file mode 100644 index 0000000..2470592 --- /dev/null +++ b/pkgs/river-hdl/default.nix @@ -0,0 +1,50 @@ +{ + lib, + buildDartApplication, + callPackage, + yosys, + nextpnr, + icestorm, + trellis, + surfer, + flakever, +}: +buildDartApplication (finalAttrs: { + pname = "river-hdl"; + inherit (flakever) version; + + src = ../../.; + packageRoot = "packages/river_hdl"; + + inherit (import ../../nix/common-dart.nix lib) + pubspecLock + gitHashes + ; + + dartEntryPoints = { + "bin/river-genip" = "packages/river_hdl/bin/river_genip.dart"; + "bin/river-sim" = "packages/river_hdl/bin/river_sim.dart"; + }; + + preBuild = '' + mkdir -p bin + ''; + + # ASIC tapeout/verify are no longer built here: the SoC IP is generated by + # mkSoC, then handed to asix.mkTapeout / asix.mkVerify in the flake. asix owns + # the Yosys/OpenROAD/KLayout/Magic/Netgen orchestration. + passthru = rec { + mkSoC = callPackage ../river-ip { + river-hdl = finalAttrs.finalPackage; + inherit yosys nextpnr surfer; + }; + mkFpga = callPackage ../river-fpga { + inherit + yosys + nextpnr + icestorm + trellis + ; + }; + }; +}) diff --git a/pkgs/river-ip/default.nix b/pkgs/river-ip/default.nix new file mode 100644 index 0000000..bff796f --- /dev/null +++ b/pkgs/river-ip/default.nix @@ -0,0 +1,143 @@ +{ + lib, + stdenvNoCC, + mkShell, + yosys, + nextpnr, + surfer, + river-hdl, +}: + +lib.extendMkDerivation { + constructDrv = stdenvNoCC.mkDerivation; + + excludeDrvArgNames = [ + "socName" + "cores" + "interconnect" + "clockFreq" + "oscFreq" + "memories" + "devices" + "target" + "pdkRoot" + "pins" + ]; + + extendDrvArgs = + finalAttrs: + { + name ? "river-ip-${socName}", + socName ? "river_soc", + cores ? [ "rc1-s" ], + interconnect ? "wishbone", + clockFreq ? 48000000, + # The board's physical oscillator; the clock generator synthesizes + # clockFreq from it, so a wrong value scales every clock on the chip. + oscFreq ? 12000000, + memories ? [ ], + devices ? [ ], + target ? null, + pdkRoot ? null, + pins ? [ ], + bootProgram ? null, + ... + }@args: + + assert lib.assertMsg (builtins.all ( + c: + builtins.elem c [ + "rc1-n" + "rc1-mi" + "rc1-s" + "rc1-m" + ] + ) cores) "river-ip: cores must each be one of [rc1-n, rc1-mi, rc1-s, rc1-m]"; + assert lib.assertMsg (builtins.elem interconnect [ + "wishbone" + "axi" + "tilelink" + ]) "river-ip: interconnect must be one of [wishbone, axi, tilelink], got ${interconnect}"; + + let + cliArgs = lib.cli.toCommandLineShellGNU { } { + name = socName; + inherit interconnect; + clock-freq = clockFreq; + osc-freq = oscFreq; + }; + + coreFlags = lib.concatMapStringsSep " " (c: "--core ${c}") cores; + # Memory regions are devices in the unified genip interface. Reorder the + # declarative addr:size:type[:board][:params] form to the genip device + # form type:addr:size[:board][:params] and pass each via --device. + memoryFlags = lib.concatMapStringsSep " " ( + m: + let + p = lib.splitString ":" m; + in + "--device ${builtins.elemAt p 2}:${builtins.elemAt p 0}:${builtins.elemAt p 1}${ + lib.concatMapStrings (x: ":${x}") (lib.drop 3 p) + }" + ) memories; + deviceFlags = lib.concatMapStringsSep " " (d: "--device ${d}") devices; + targetFlag = lib.optionalString (target != null) "--target ${target}"; + pdkRootFlag = lib.optionalString (pdkRoot != null) "--pdk-root ${pdkRoot}"; + pinFlags = lib.concatMapStringsSep " " (p: "--pin ${p}") pins; + bootProgramFlag = lib.optionalString (bootProgram != null) "--boot-program ${bootProgram}"; + in + builtins.removeAttrs args [ + "socName" + "cores" + "interconnect" + "clockFreq" + "oscFreq" + "memories" + "devices" + "target" + "pdkRoot" + "pins" + "bootProgram" + ] + // { + inherit name; + + dontUnpack = true; + dontConfigure = true; + + nativeBuildInputs = (args.nativeBuildInputs or [ ]) ++ [ + river-hdl + ]; + + buildPhase = '' + runHook preBuild + river-genip ${cliArgs} ${coreFlags} ${memoryFlags} ${deviceFlags} ${targetFlag} ${pdkRootFlag} ${pinFlags} ${bootProgramFlag} --output "$out" + runHook postBuild + ''; + + dontInstall = true; + + passthru = { + inherit + socName + cores + interconnect + clockFreq + memories + devices + target + pins + ; + shell = mkShell { + name = "river-${socName}-shell"; + packages = [ + river-hdl + yosys + nextpnr + surfer + ]; + }; + } + // (args.passthru or { }); + }; +} diff --git a/pubspec.lock b/pubspec.lock index 7906a39..26f6eb1 100644 --- a/pubspec.lock +++ b/pubspec.lock @@ -121,6 +121,15 @@ packages: url: "https://pub.dev" source: hosted version: "2.1.3" + harbor: + dependency: "direct overridden" + description: + path: "packages/harbor" + ref: master + resolved-ref: "4f4352e654e735ae1d117d9087b7fa72583d8dea" + url: "https://github.com/MidstallSoftware/harbor.git" + source: git + version: "0.0.1" html: dependency: transitive description: @@ -253,18 +262,17 @@ packages: dependency: transitive description: name: rohd_bridge - sha256: "541577b8af73f1f1a5965f4646b7cff2552727a01d42a87246ec51f94c7351e7" + sha256: "40a8a7e4166186622a83f4b486c244601f3903dca4fd8e3c2caff175919cbe7a" url: "https://pub.dev" source: hosted - version: "0.2.1" + version: "0.2.2" rohd_hcl: dependency: transitive description: - path: "." - ref: integration - resolved-ref: a5cde623e091724be491cfa4f61dca8b99cb0daa - url: "https://github.com/MidstallSoftware/rohd-hcl.git" - source: git + name: rohd_hcl + sha256: "2f97380982453f491a1eafb5349046e7f679a937825fcee7f42bdc7c2df1b8df" + url: "https://pub.dev" + source: hosted version: "0.2.1" rohd_vf: dependency: transitive @@ -451,4 +459,4 @@ packages: source: hosted version: "3.1.3" sdks: - dart: ">=3.9.4 <4.0.0" + dart: ">=3.11.2 <4.0.0" diff --git a/pubspec.lock.json b/pubspec.lock.json index 38010ef..22f48ec 100644 --- a/pubspec.lock.json +++ b/pubspec.lock.json @@ -150,6 +150,17 @@ "source": "hosted", "version": "2.1.3" }, + "harbor": { + "dependency": "direct overridden", + "description": { + "path": "packages/harbor", + "ref": "master", + "resolved-ref": "4f4352e654e735ae1d117d9087b7fa72583d8dea", + "url": "https://github.com/MidstallSoftware/harbor.git" + }, + "source": "git", + "version": "0.0.1" + }, "html": { "dependency": "transitive", "description": { @@ -314,21 +325,20 @@ "dependency": "transitive", "description": { "name": "rohd_bridge", - "sha256": "541577b8af73f1f1a5965f4646b7cff2552727a01d42a87246ec51f94c7351e7", + "sha256": "40a8a7e4166186622a83f4b486c244601f3903dca4fd8e3c2caff175919cbe7a", "url": "https://pub.dev" }, "source": "hosted", - "version": "0.2.1" + "version": "0.2.2" }, "rohd_hcl": { "dependency": "transitive", "description": { - "path": ".", - "ref": "integration", - "resolved-ref": "a5cde623e091724be491cfa4f61dca8b99cb0daa", - "url": "https://github.com/MidstallSoftware/rohd-hcl.git" + "name": "rohd_hcl", + "sha256": "2f97380982453f491a1eafb5349046e7f679a937825fcee7f42bdc7c2df1b8df", + "url": "https://pub.dev" }, - "source": "git", + "source": "hosted", "version": "0.2.1" }, "rohd_vf": { @@ -563,6 +573,6 @@ } }, "sdks": { - "dart": ">=3.9.4 <4.0.0" + "dart": ">=3.11.2 <4.0.0" } } diff --git a/pubspec.yaml b/pubspec.yaml index b1ab759..114f21d 100644 --- a/pubspec.yaml +++ b/pubspec.yaml @@ -2,15 +2,22 @@ name: river_workspace publish_to: none environment: - sdk: ^3.9.3 + sdk: ^3.11.2 workspace: - packages/bintools - - packages/riscv - packages/river - packages/river_adl - packages/river_emulator - packages/river_hdl + - packages/river_maskrom + +dependency_overrides: + harbor: + git: + url: https://github.com/MidstallSoftware/harbor.git + path: packages/harbor + ref: master dev_dependencies: coverage: ^1.15.0