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Author: cfallin

src/lib.rs

@@ -676,6 +676,28 @@ pub struct Operand {
 }
 
 impl Operand {
+    const VREG_BITS: usize = 32;
+    const VREG_SHIFT: usize = 0;
+    const VREG_MASK: u64 = (1 << Self::VREG_BITS) - 1;
+
+    const CLASS_BITS: usize = 2;
+    const CLASS_SHIFT: usize = Self::VREG_SHIFT + Self::VREG_BITS;
+    const CLASS_MASK: u64 = (1 << Self::CLASS_BITS) - 1;
+
+    const POS_BITS: usize = 1;
+    const POS_SHIFT: usize = Self::CLASS_SHIFT + Self::CLASS_BITS;
+    const POS_MASK: u64 = (1 << Self::POS_BITS) - 1;
+
+    const KIND_BITS: usize = 1;
+    const KIND_SHIFT: usize = Self::POS_SHIFT + Self::POS_BITS;
+    const KIND_MASK: u64 = (1 << Self::KIND_BITS) - 1;
+
+    const CONSTRAINT_BITS: usize = 7;
+    const CONSTRAINT_SHIFT: usize = Self::KIND_SHIFT + Self::KIND_BITS;
+    const CONSTRAINT_MASK: u64 = (1 << Self::CONSTRAINT_BITS) - 1;
+
+    const TOTAL_BITS: usize = Self::CONSTRAINT_SHIFT + Self::CONSTRAINT_BITS;
+
     /// Construct a new operand.
     #[inline(always)]
     pub fn new(
@@ -711,11 +733,11 @@ impl Operand {
         let pos_field = pos as u8 as u64;
         let kind_field = kind as u8 as u64;
         Operand {
-            bits: vreg.vreg() as u64
-                | (class_field << 32)
-                | (pos_field << 34)
-                | (kind_field << 35)
-                | (constraint_field << 36),
+            bits: ((vreg.vreg() as u64) << Self::VREG_SHIFT)
+                | (class_field << Self::CLASS_SHIFT)
+                | (pos_field << Self::POS_SHIFT)
+                | (kind_field << Self::KIND_SHIFT)
+                | (constraint_field << Self::CONSTRAINT_SHIFT),
         }
     }
 
@@ -915,14 +937,14 @@ impl Operand {
     /// are used to track dataflow.
     #[inline(always)]
     pub fn vreg(self) -> VReg {
-        let vreg_idx = ((self.bits as usize) & VReg::MAX) as usize;
+        let vreg_idx = ((self.bits >> Self::VREG_SHIFT) & Self::VREG_MASK) as usize;
         VReg::new(vreg_idx, self.class())
     }
 
     /// Get the register class used by this operand.
     #[inline(always)]
     pub fn class(self) -> RegClass {
-        let class_field = (self.bits >> 32) & 3;
+        let class_field = (self.bits >> Self::CLASS_SHIFT) & Self::CLASS_MASK;
         match class_field {
             0 => RegClass::Int,
             1 => RegClass::Float,
@@ -935,7 +957,7 @@ impl Operand {
     /// (read).
     #[inline(always)]
     pub fn kind(self) -> OperandKind {
-        let kind_field = (self.bits >> 35) & 1;
+        let kind_field = (self.bits >> Self::KIND_SHIFT) & Self::KIND_MASK;
         match kind_field {
             0 => OperandKind::Def,
             1 => OperandKind::Use,
@@ -949,7 +971,7 @@ impl Operand {
     /// at "after", though there are cases where this is not true.
     #[inline(always)]
     pub fn pos(self) -> OperandPos {
-        let pos_field = (self.bits >> 34) & 1;
+        let pos_field = (self.bits >> Self::POS_SHIFT) & Self::POS_MASK;
         match pos_field {
             0 => OperandPos::Early,
             1 => OperandPos::Late,
@@ -961,7 +983,8 @@ impl Operand {
     /// its allocation must fulfill.
     #[inline(always)]
     pub fn constraint(self) -> OperandConstraint {
-        let constraint_field = ((self.bits >> 36) as usize) & 0b1111111;
+        let constraint_field =
+            ((self.bits >> Self::CONSTRAINT_SHIFT) & Self::CONSTRAINT_MASK) as usize;
         if constraint_field & 0b1000000 != 0 {
             OperandConstraint::FixedReg(PReg::new(constraint_field & 0b0111111, self.class()))
         } else if constraint_field & 0b0100000 != 0 {
@@ -999,7 +1022,7 @@ impl Operand {
     /// from `bits()`.
     #[inline(always)]
     pub fn from_bits(bits: u64) -> Self {
-        debug_assert!(bits >> 40 <= 4);
+        debug_assert_eq!(bits >> Self::TOTAL_BITS, 0);
         Operand { bits }
     }
 }