As part of hunting down potential QSFP temperature glitches, CC oxidecomputer/hubris#2664, we suspect (but have not yet proven) that our "too hot transceivers" may actually be a bit-error in the temperature reading.
As the I2C query of a transceiver's temperature transits over a fairly long SPI link that is running at a fairly high speed (3MHz), it's conceivable that we could be observing a bit error (for example flipping the 64C bit from 0 to 1, bumping the temp from 59C to 123C).
We may want to consider adding some kind of CRC or other integrity check over the SPI protocol to the front-io FPGAs to rule this out.
This will require HDL changes, SP changes, and coordination that we roll both into the same release.
As part of hunting down potential QSFP temperature glitches, CC oxidecomputer/hubris#2664, we suspect (but have not yet proven) that our "too hot transceivers" may actually be a bit-error in the temperature reading.
As the I2C query of a transceiver's temperature transits over a fairly long SPI link that is running at a fairly high speed (3MHz), it's conceivable that we could be observing a bit error (for example flipping the 64C bit from
0to1, bumping the temp from 59C to 123C).We may want to consider adding some kind of CRC or other integrity check over the SPI protocol to the front-io FPGAs to rule this out.
This will require HDL changes, SP changes, and coordination that we roll both into the same release.