finalProject.qsf

# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
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# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
# Date created = 09:25:30  January 23, 2017
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		finalProject_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE EP3C16F484C6
set_global_assignment -name TOP_LEVEL_ENTITY phase4
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:25:30  JANUARY 23, 2017"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH phase3_tb -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME register_64_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id register_64_tb
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "100 ns" -section_id register_64_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME register_64_tb -section_id register_64_tb
set_global_assignment -name EDA_TEST_BENCH_NAME booth_32_algorithm_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id booth_32_algorithm_tb
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "500 ns" -section_id booth_32_algorithm_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME booth_32_algorithm_tb -section_id booth_32_algorithm_tb
set_global_assignment -name EDA_TEST_BENCH_NAME encoder_32_to_5_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id encoder_32_to_5_tb
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "500 ns" -section_id encoder_32_to_5_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME encoder_32_to_5_tb -section_id encoder_32_to_5_tb
set_global_assignment -name EDA_TEST_BENCH_NAME bus_mux_32_to_1_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id bus_mux_32_to_1_tb
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "500 ns" -section_id bus_mux_32_to_1_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME bus_mux_32_to_1_tb -section_id bus_mux_32_to_1_tb
set_global_assignment -name EDA_TEST_BENCH_NAME MDMux_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id MDMux_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME MDMux_tb -section_id MDMux_tb
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "300 ns" -section_id MDMux_tb
set_global_assignment -name EDA_TEST_BENCH_NAME phase1_tb_add -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id phase1_tb_add
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "240 ns" -section_id phase1_tb_add
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME phase1_tb_add -section_id phase1_tb_add
set_global_assignment -name EDA_TEST_BENCH_NAME phase1_tb_sub -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id phase1_tb_sub
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "240 ns" -section_id phase1_tb_sub
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME phase1_tb_sub -section_id phase1_tb_sub
set_global_assignment -name EDA_TEST_BENCH_NAME phase1_tb_mul -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id phase1_tb_mul
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "260 ns" -section_id phase1_tb_mul
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME phase1_tb_mul -section_id phase1_tb_mul
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_global_assignment -name EDA_TEST_BENCH_NAME phase1_tb_div -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id phase1_tb_div
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "300 ns" -section_id phase1_tb_div
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME phase1_tb_div -section_id phase1_tb_div
set_global_assignment -name EDA_TEST_BENCH_NAME phase1_tb_and -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id phase1_tb_and
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "240 ns" -section_id phase1_tb_and
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME phase1_tb_and -section_id phase1_tb_and
set_global_assignment -name EDA_TEST_BENCH_NAME phase1_tb_or -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id phase1_tb_or
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "240 ns" -section_id phase1_tb_or
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME phase1_tb_or -section_id phase1_tb_or
set_global_assignment -name EDA_TEST_BENCH_NAME phase1_tb_srl -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id phase1_tb_srl
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "240 ns" -section_id phase1_tb_srl
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME phase1_tb_srl -section_id phase1_tb_srl
set_global_assignment -name EDA_TEST_BENCH_NAME phase1_tb_sll -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id phase1_tb_sll
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "240 ns" -section_id phase1_tb_sll
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME phase1_tb_sll -section_id phase1_tb_sll
set_global_assignment -name EDA_TEST_BENCH_NAME phase1_tb_neg -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id phase1_tb_neg
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "240 ns" -section_id phase1_tb_neg
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME phase1_tb_neg -section_id phase1_tb_neg
set_global_assignment -name EDA_TEST_BENCH_NAME phase1_tb_not -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id phase1_tb_not
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "240 ns" -section_id phase1_tb_not
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME phase1_tb_not -section_id phase1_tb_not
set_global_assignment -name EDA_TEST_BENCH_NAME CLA_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id CLA_tb
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "500 ns" -section_id CLA_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME CLA_tb -section_id CLA_tb
set_global_assignment -name EDA_TEST_BENCH_NAME phase1_tb_ror -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id phase1_tb_ror
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "240 ns" -section_id phase1_tb_ror
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME phase1_tb_ror -section_id phase1_tb_ror
set_global_assignment -name EDA_TEST_BENCH_NAME phase1_tb_rol -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id phase1_tb_rol
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "240 ns" -section_id phase1_tb_rol
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME phase1_tb_rol -section_id phase1_tb_rol
set_global_assignment -name EDA_TEST_BENCH_NAME booth_32_bitPairRecoding_algorithm_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id booth_32_bitPairRecoding_algorithm_tb
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "200 ns" -section_id booth_32_bitPairRecoding_algorithm_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME booth_32_bitPairRecoding_algorithm_tb -section_id booth_32_bitPairRecoding_algorithm_tb
set_global_assignment -name EDA_TEST_BENCH_NAME array_multiplier_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id array_multiplier_tb
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "500 ns" -section_id array_multiplier_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME array_multiplier_tb -section_id array_multiplier_tb
set_global_assignment -name EDA_TEST_BENCH_NAME select_encode_logic_sel_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id select_encode_logic_sel_tb
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "500 ns" -section_id select_encode_logic_sel_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME select_encode_logic_sel_tb -section_id select_encode_logic_sel_tb
set_global_assignment -name EDA_TEST_BENCH_NAME con_ff_logic_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id con_ff_logic_tb
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "500 ns" -section_id con_ff_logic_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME con_ff_logic_tb -section_id con_ff_logic_tb
set_global_assignment -name EDA_TEST_BENCH_NAME phase2_tb_ld -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id phase2_tb_ld
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "10000 ns" -section_id phase2_tb_ld
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME phase2_tb_ld -section_id phase2_tb_ld
set_global_assignment -name EDA_TEST_BENCH_NAME phase2_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id phase2_tb
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "9000 ns" -section_id phase2_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME phase2_tb -section_id phase2_tb
set_global_assignment -name EDA_TEST_BENCH_NAME phase3_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id phase3_tb
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "15 ms" -section_id phase3_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME phase3_tb -section_id phase3_tb
set_location_assignment PIN_E1 -to run
set_location_assignment PIN_J6 -to in_port_input[0]
set_location_assignment PIN_H5 -to in_port_input[1]
set_location_assignment PIN_H6 -to in_port_input[2]
set_location_assignment PIN_G4 -to in_port_input[3]
set_location_assignment PIN_G5 -to in_port_input[4]
set_location_assignment PIN_J7 -to in_port_input[5]
set_location_assignment PIN_H7 -to in_port_input[6]
set_location_assignment PIN_E3 -to in_port_input[7]
set_location_assignment PIN_H2 -to reset
set_location_assignment PIN_G3 -to stop
set_location_assignment PIN_G21 -to clk_in
set_location_assignment PIN_E11 -to output1[0]
set_location_assignment PIN_F11 -to output1[1]
set_location_assignment PIN_H12 -to output1[2]
set_location_assignment PIN_H13 -to output1[3]
set_location_assignment PIN_G12 -to output1[4]
set_location_assignment PIN_F12 -to output1[5]
set_location_assignment PIN_F13 -to output1[6]
set_location_assignment PIN_D13 -to output1[7]
set_location_assignment PIN_A13 -to output2[0]
set_location_assignment PIN_B13 -to output2[1]
set_location_assignment PIN_C13 -to output2[2]
set_location_assignment PIN_A14 -to output2[3]
set_location_assignment PIN_B14 -to output2[4]
set_location_assignment PIN_E14 -to output2[5]
set_location_assignment PIN_A15 -to output2[6]
set_location_assignment PIN_B15 -to output2[7]
set_global_assignment -name MIF_FILE ram_mif.mif
set_global_assignment -name VHDL_FILE phase4.vhd
set_global_assignment -name VHDL_FILE phase3.vhd
set_global_assignment -name VHDL_FILE control_unit.vhd
set_global_assignment -name VHDL_FILE reg_64_tb.vhd
set_global_assignment -name VHDL_FILE register_R0.vhd
set_global_assignment -name VHDL_FILE select_encode_logic_sel_tb.vhd
set_global_assignment -name VHDL_FILE select_encode_logic_sel.vhd
set_global_assignment -name VHDL_FILE Z_split.vhd
set_global_assignment -name VHDL_FILE register_64.vhd
set_global_assignment -name VHDL_FILE register_32.vhd
set_global_assignment -name VHDL_FILE MDMux.vhd
set_global_assignment -name VHDL_FILE encoder_32_to_5.vhd
set_global_assignment -name VHDL_FILE bus_mux_32_to_1.vhd
set_global_assignment -name VHDL_FILE ALU.vhd
set_global_assignment -name VHDL_FILE con_ff_logic.vhd
set_global_assignment -name VHDL_FILE D_flipflop.vhd
set_global_assignment -name VHDL_FILE con_ff_logic_tb.vhd
set_global_assignment -name VHDL_FILE MAR_splicer.vhd
set_global_assignment -name VHDL_FILE SelecEncodeLogic_R_splitter.vhd
set_global_assignment -name VHDL_FILE IR_ConFF_Split.vhd
set_global_assignment -name QIP_FILE ram_TA.qip
set_global_assignment -name QIP_FILE lpm_add_sub0.qip
set_global_assignment -name VHDL_FILE IncPC.vhd
set_global_assignment -name VHDL_FILE R14MUX.vhd
set_global_assignment -name VHDL_FILE in_port_reg.vhd
set_global_assignment -name VHDL_FILE phase3_tb.vhd
set_global_assignment -name VHDL_FILE Seven_Seg_Display_Out.vhd
set_global_assignment -name VHDL_FILE display_splitter.vhd
set_global_assignment -name VHDL_FILE clock_divider.vhd
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name EDA_TEST_BENCH_FILE reg_64_tb.vhd -section_id register_64_tb
set_global_assignment -name EDA_TEST_BENCH_FILE booth_32_algorithm_tb.vhd -section_id booth_32_algorithm_tb
set_global_assignment -name EDA_TEST_BENCH_FILE encoder_32_to_5_tb.vhd -section_id encoder_32_to_5_tb
set_global_assignment -name EDA_TEST_BENCH_FILE bus_mux_32_to_1_tb.vhd -section_id bus_mux_32_to_1_tb
set_global_assignment -name EDA_TEST_BENCH_FILE MDMux_tb.vhd -section_id MDMux_tb
set_global_assignment -name EDA_TEST_BENCH_FILE phase1_tb_add.vhd -section_id phase1_tb_add
set_global_assignment -name EDA_TEST_BENCH_FILE phase1_tb_sub.vhd -section_id phase1_tb_sub
set_global_assignment -name EDA_TEST_BENCH_FILE phase1_tb_mul.vhd -section_id phase1_tb_mul
set_global_assignment -name EDA_TEST_BENCH_FILE phase1_tb_div.vhd -section_id phase1_tb_div
set_global_assignment -name EDA_TEST_BENCH_FILE phase1_tb_and.vhd -section_id phase1_tb_and
set_global_assignment -name EDA_TEST_BENCH_FILE phase1_tb_or.vhd -section_id phase1_tb_or
set_global_assignment -name EDA_TEST_BENCH_FILE phase1_tb_srl.vhd -section_id phase1_tb_srl
set_global_assignment -name EDA_TEST_BENCH_FILE phase1_tb_sll.vhd -section_id phase1_tb_sll
set_global_assignment -name EDA_TEST_BENCH_FILE phase1_tb_neg.vhd -section_id phase1_tb_neg
set_global_assignment -name EDA_TEST_BENCH_FILE phase1_tb_not.vhd -section_id phase1_tb_not
set_global_assignment -name EDA_TEST_BENCH_FILE CLA_tb.vhd -section_id CLA_tb
set_global_assignment -name EDA_TEST_BENCH_FILE phase1_tb_ror.vhd -section_id phase1_tb_ror
set_global_assignment -name EDA_TEST_BENCH_FILE phase1_tb_rol.vhd -section_id phase1_tb_rol
set_global_assignment -name EDA_TEST_BENCH_FILE booth_32_bitPairRecoding_algorithm_tb.vhd -section_id booth_32_bitPairRecoding_algorithm_tb
set_global_assignment -name EDA_TEST_BENCH_FILE array_multiplier_tb.vhd -section_id array_multiplier_tb
set_global_assignment -name EDA_TEST_BENCH_FILE select_encode_logic_sel_tb.vhd -section_id select_encode_logic_sel_tb
set_global_assignment -name EDA_TEST_BENCH_FILE con_ff_logic_tb.vhd -section_id con_ff_logic_tb
set_global_assignment -name EDA_TEST_BENCH_FILE phase2_tb_ld.vhd -section_id phase2_tb_ld
set_global_assignment -name EDA_TEST_BENCH_FILE phase2_tb.vhd -section_id phase2_tb
set_global_assignment -name EDA_TEST_BENCH_FILE phase3_tb.vhd -section_id phase3_tb
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top