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AndrewMcClelland
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RISC_Computer
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41 Commits
Folders and files
Name
Name
Last commit message
Last commit date
db
db
greybox_tmp
greybox_tmp
incremental_db
incremental_db
output_files
output_files
simulation/
modelsim
simulation/
modelsim
ALU.bsf
ALU.bsf
ALU.vhd
ALU.vhd
ALU.vhd.bak
ALU.vhd.bak
ALU_tb.vhd
ALU_tb.vhd
CLA.bsf
CLA.bsf
CLA.vhd
CLA.vhd
CLA.vhd.bak
CLA.vhd.bak
CLA_tb.vhd
CLA_tb.vhd
CLA_tb.vhd.bak
CLA_tb.vhd.bak
D_flipflop.vhd
D_flipflop.vhd
D_flipflop.vhd.bak
D_flipflop.vhd.bak
IR_ConFF_Split.bsf
IR_ConFF_Split.bsf
IR_ConFF_Split.vhd
IR_ConFF_Split.vhd
IR_ConFF_Split.vhd.bak
IR_ConFF_Split.vhd.bak
IncPC.bsf
IncPC.bsf
IncPC.vhd
IncPC.vhd
MAR_splicer.bsf
MAR_splicer.bsf
MAR_splicer.vhd
MAR_splicer.vhd
MAR_splicer.vhd.bak
MAR_splicer.vhd.bak
MDMUX.bsf
MDMUX.bsf
MDMux.vhd
MDMux.vhd
MDMux.vhd.bak
MDMux.vhd.bak
MDMux_tb.vhd
MDMux_tb.vhd
MDMux_tb.vhd.bak
MDMux_tb.vhd.bak
MDR_register.bsf
MDR_register.bsf
MDR_register.vhd
MDR_register.vhd
MDR_register.vhd.bak
MDR_register.vhd.bak
R14MUX.bsf
R14MUX.bsf
R14MUX.vhd
R14MUX.vhd
RAM.bsf
RAM.bsf
RAM.cmp
RAM.cmp
RAM.qip
RAM.qip
RAM.vhd
RAM.vhd
README.md
README.md
SelecEncodeLogic_R_splitter.vhd
SelecEncodeLogic_R_splitter.vhd
SelecEncodeLogic_R_splitter.vhd.bak
SelecEncodeLogic_R_splitter.vhd.bak
SelectEncodeLogic_R_splitter.bsf
SelectEncodeLogic_R_splitter.bsf
Seven_Seg_Display_Out.bsf
Seven_Seg_Display_Out.bsf
Seven_Seg_Display_Out.vhd
Seven_Seg_Display_Out.vhd
Seven_Seg_Display_Out.vhd.bak
Seven_Seg_Display_Out.vhd.bak
Z_split.bsf
Z_split.bsf
Z_split.vhd
Z_split.vhd
array_multiplier.vhd
array_multiplier.vhd
array_multiplier_tb.vhd
array_multiplier_tb.vhd
booth_32_algorithm.bsf
booth_32_algorithm.bsf
booth_32_algorithm.vhd
booth_32_algorithm.vhd
booth_32_algorithm.vhd.bak
booth_32_algorithm.vhd.bak
booth_32_algorithm_tb.vhd
booth_32_algorithm_tb.vhd
booth_32_algorithm_tb.vhd.bak
booth_32_algorithm_tb.vhd.bak
booth_32_bitPairRecoding_algorithm.vhd
booth_32_bitPairRecoding_algorithm.vhd
booth_32_bitPairRecoding_algorithm.vhd.bak
booth_32_bitPairRecoding_algorithm.vhd.bak
booth_32_bitPairRecoding_algorithm_tb.vhd
booth_32_bitPairRecoding_algorithm_tb.vhd
booth_32_bitPairRecoding_algorithm_tb.vhd.bak
booth_32_bitPairRecoding_algorithm_tb.vhd.bak
bus_mux_32_to_1.bsf
bus_mux_32_to_1.bsf
bus_mux_32_to_1.vhd
bus_mux_32_to_1.vhd
bus_mux_32_to_1.vhd.bak
bus_mux_32_to_1.vhd.bak
bus_mux_32_to_1_tb.vhd
bus_mux_32_to_1_tb.vhd
bus_mux_32_to_1_tb.vhd.bak
bus_mux_32_to_1_tb.vhd.bak
carry_look_ahead.vhd
carry_look_ahead.vhd
carry_lookahead_adder.vhd
carry_lookahead_adder.vhd
clk200Hz.bsf
clk200Hz.bsf
clock_divider.bsf
clock_divider.bsf
clock_divider.vhd
clock_divider.vhd
clock_divider.vhd.bak
clock_divider.vhd.bak
con_ff_logic.bsf
con_ff_logic.bsf
con_ff_logic.vhd
con_ff_logic.vhd
con_ff_logic.vhd.bak
con_ff_logic.vhd.bak
con_ff_logic_tb.vhd
con_ff_logic_tb.vhd
con_ff_logic_tb.vhd.bak
con_ff_logic_tb.vhd.bak
control_unit.bsf
control_unit.bsf
control_unit.vhd
control_unit.vhd
control_unit.vhd.bak
control_unit.vhd.bak
datapath_tb.vhd.bak
datapath_tb.vhd.bak
display_splitter.bsf
display_splitter.bsf
display_splitter.vhd
display_splitter.vhd
display_splitter.vhd.bak
display_splitter.vhd.bak
encoder_32_to_5.bsf
encoder_32_to_5.bsf
encoder_32_to_5.vhd
encoder_32_to_5.vhd
encoder_32_to_5.vhd.bak
encoder_32_to_5.vhd.bak
encoder_32_to_5_tb.vhd
encoder_32_to_5_tb.vhd
encoder_32_to_5_tb.vhd.bak
encoder_32_to_5_tb.vhd.bak
finalProject.bdf
finalProject.bdf
finalProject.mif
finalProject.mif
finalProject.qpf
finalProject.qpf
finalProject.qsf
finalProject.qsf
finalProject.qws
finalProject.qws
finalProject.vhd
finalProject.vhd
finalProject_nativelink_simulation.rpt
finalProject_nativelink_simulation.rpt
in_port_reg.bsf
in_port_reg.bsf
in_port_reg.vhd
in_port_reg.vhd
in_port_reg.vhd.bak
in_port_reg.vhd.bak
lpm_add_sub0.bsf
lpm_add_sub0.bsf
lpm_add_sub0.cmp
lpm_add_sub0.cmp
lpm_add_sub0.qip
lpm_add_sub0.qip
lpm_add_sub0.vhd
lpm_add_sub0.vhd
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ELEC374_RISC_Computer
ELEC 374 Project - Simple RISC Computer Design
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ELEC 374 Project - Simple RISC Computer Design
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