RISC_Computer/finalProject_nativelink_simulation.rpt at master · BenLoerick/RISC_Computer · GitHub

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Info: Start Nativelink Simulation process
Info: NativeLink has detected VHDL design -- VHDL simulation models will be used

========= EDA Simulation Settings =====================

Sim Mode              :  RTL
Family                :  cycloneiii
Quartus root          :  c:/altera/13.0sp1/quartus/bin64/
Quartus sim root      :  c:/altera/13.0sp1/quartus/eda/sim_lib
Simulation Tool       :  modelsim-altera
Simulation Language   :  vhdl
Version               :  93
Simulation Mode       :  GUI
Sim Output File       :
Sim SDF file          :
Sim dir               :  simulation\modelsim

=======================================================

Info: Starting NativeLink simulation with ModelSim-Altera software
Sourced NativeLink script c:/altera/13.0sp1/quartus/common/tcl/internal/nativelink/modelsim.tcl
Warning: File finalProject_run_msim_rtl_vhdl.do already exists - backing up current file as finalProject_run_msim_rtl_vhdl.do.bak11
Info: Spawning ModelSim-Altera Simulation software