Sorted netlists, take 2

edg/core/TransformUtil.py

@@ -93,6 +93,11 @@ def link_component(self, must_have_link: bool = True) -> Path:
             assert self.links
         return Path(self.blocks, self.links, (), ())
 
+    def port_component(self, must_have_port: bool = True) -> Path:
+        if must_have_port:
+            assert self.ports
+        return Path(self.blocks, self.links, self.ports, ())
+
     def to_tuple(self) -> Tuple[str, ...]:
         return self.blocks + self.links + self.ports + self.params
 

edg/electronics_model/NetlistGenerator.py

@@ -82,15 +82,13 @@ def __init__(self, design: CompiledDesign):
         self.all_scopes = [BoardScope.empty(TransformUtil.Path.empty())]  # list of unique scopes
         self.scopes: Scopes = {TransformUtil.Path.empty(): self.all_scopes[0]}
         self.class_paths: ClassPaths = {TransformUtil.Path.empty(): []}  # seed root
-        self.block_link_order: List[TransformUtil.Path] = []
+        self.path_traverse_order: List[TransformUtil.Path] = []
 
         self.design = design
 
     def process_blocklike(
         self, path: TransformUtil.Path, block: Union[edgir.Link, edgir.LinkArray, edgir.HierarchyBlock]
     ) -> None:
-        self.block_link_order.append(path)
-
         # TODO may need rethought to support multi-board assemblies
         scope = self.scopes[path]  # including footprint and exports, and everything within a link
         internal_scope = scope  # for internal blocks
@@ -245,16 +243,23 @@ def connect_ports(
 
     @override
     def visit_block(self, context: TransformUtil.TransformContext, block: edgir.BlockTypes) -> None:
+        self.path_traverse_order.append(context.path)
         self.process_blocklike(context.path, block)
 
     @override
     def visit_link(self, context: TransformUtil.TransformContext, link: edgir.Link) -> None:
+        self.path_traverse_order.append(context.path)
         self.process_blocklike(context.path, link)
 
     @override
     def visit_linkarray(self, context: TransformUtil.TransformContext, link: edgir.LinkArray) -> None:
+        self.path_traverse_order.append(context.path)
         self.process_blocklike(context.path, link)
 
+    @override
+    def visit_portlike(self, context: TransformUtil.TransformContext, port: edgir.PortLike) -> None:
+        self.path_traverse_order.append(context.path)
+
     @staticmethod
     def name_net(net: Iterable[TransformUtil.Path]) -> TransformUtil.Path:
         """Names a net based on all the paths of ports and links that are part of the net."""
@@ -291,7 +296,7 @@ def pin_name_goodness(pin1: TransformUtil.Path, pin2: TransformUtil.Path) -> int
         return best_path
 
     def scope_to_netlist(self, scope: BoardScope) -> Netlist:
-        path_ordering = {path: i for i, path in enumerate(self.block_link_order)}
+        path_ordering = {path: i for i, path in enumerate(self.path_traverse_order)}
 
         # Convert to the netlist format
         seen: Set[TransformUtil.Path] = set()
@@ -320,7 +325,7 @@ def scope_to_netlist(self, scope: BoardScope) -> Netlist:
 
         named_nets = sorted(
             [(self.name_net(net), net) for net in nets],
-            key=lambda pair: path_ordering[pair[0].link_component(must_have_link=False)],
+            key=lambda pair: path_ordering[pair[0].port_component(must_have_port=False)],
         )
 
         board_refdes_prefix = self.design.get_value(("refdes_prefix",))

examples/BasicKeyboard/BasicKeyboard.net

@@ -179,10 +179,10 @@
   (node (ref U1) (pin 10))
   (node (ref D3) (pin 2))
   (node (ref D6) (pin 2)))
-(net (code 6) (name "mcu.pwr_out")
-  (node (ref U1) (pin 12)))
-(net (code 7) (name "mcu.gnd")
+(net (code 6) (name "mcu.gnd")
   (node (ref U1) (pin 13)))
+(net (code 7) (name "mcu.pwr_out")
+  (node (ref U1) (pin 12)))
 (net (code 8) (name "mcu.vusb_out")
   (node (ref U1) (pin 14)))
 (net (code 9) (name "sw.d[0,0].cathode")

examples/BasicKeyboard/BasicKeyboard.svgpcb.js

@@ -13,8 +13,8 @@ board.setNetlist([
   {name: "mcu.gpio.1_0", pads: [["U1", "9"], ["D1", "2"], ["D4", "2"]]},
   {name: "mcu.gpio.1_1", pads: [["U1", "11"], ["D2", "2"], ["D5", "2"]]},
   {name: "mcu.gpio.1_2", pads: [["U1", "10"], ["D3", "2"], ["D6", "2"]]},
-  {name: "mcu.pwr_out", pads: [["U1", "12"]]},
   {name: "mcu.gnd", pads: [["U1", "13"]]},
+  {name: "mcu.pwr_out", pads: [["U1", "12"]]},
   {name: "mcu.vusb_out", pads: [["U1", "14"]]},
   {name: "sw.d[0,0].cathode", pads: [["SW1", "1"], ["D1", "1"]]},
   {name: "sw.d[0,1].cathode", pads: [["SW2", "1"], ["D2", "1"]]},

examples/BldcController/BldcController.net

@@ -1039,12 +1039,7 @@
   (node (ref R11) (pin 2))
   (node (ref R12) (pin 1))
   (node (ref TP7) (pin 1)))
-(net (code 26) (name "isense.out")
-  (node (ref U3) (pin 6))
-  (node (ref R16) (pin 1))
-  (node (ref TP8) (pin 1))
-  (node (ref R18) (pin 1)))
-(net (code 27) (name "isense.pwr_out")
+(net (code 26) (name "isense.pwr_out")
   (node (ref R13) (pin 2))
   (node (ref R14) (pin 1))
   (node (ref U4) (pin 11))
@@ -1053,6 +1048,11 @@
   (node (ref C4) (pin 1))
   (node (ref C5) (pin 1))
   (node (ref C8) (pin 2)))
+(net (code 27) (name "isense.out")
+  (node (ref U3) (pin 6))
+  (node (ref R16) (pin 1))
+  (node (ref TP8) (pin 1))
+  (node (ref R18) (pin 1)))
 (net (code 28) (name "isense.amp.r1.b")
   (node (ref U3) (pin 2))
   (node (ref R14) (pin 2))

examples/BldcController/BldcController.svgpcb.js

@@ -397,8 +397,8 @@ board.setNetlist([
   {name: "hall.phases.v", pads: [["U1", "24"], ["J3", "3"], ["R9", "2"], ["TP5", "1"]]},
   {name: "hall.phases.w", pads: [["U1", "25"], ["J3", "4"], ["R10", "2"], ["TP6", "1"]]},
   {name: "vsense.output", pads: [["U1", "6"], ["R11", "2"], ["R12", "1"], ["TP7", "1"]]},
-  {name: "isense.out", pads: [["U3", "6"], ["R16", "1"], ["TP8", "1"], ["R18", "1"]]},
   {name: "isense.pwr_out", pads: [["R13", "2"], ["R14", "1"], ["U4", "11"], ["U4", "4"], ["C3", "1"], ["C4", "1"], ["C5", "1"], ["C8", "2"]]},
+  {name: "isense.out", pads: [["U3", "6"], ["R16", "1"], ["TP8", "1"], ["R18", "1"]]},
   {name: "isense.amp.r1.b", pads: [["U3", "2"], ["R14", "2"], ["R16", "2"]]},
   {name: "isense.amp.r2.b", pads: [["U3", "3"], ["R15", "2"], ["R17", "2"]]},
   {name: "isense_clamp.signal_out", pads: [["U1", "5"], ["R18", "2"]]},

examples/BleJoystick/BleJoystick.net

@@ -656,44 +656,44 @@
 (net (code 6) (name "Jusb.usb.dm")
   (node (ref JJ2) (pin A7))
   (node (ref JJ2) (pin B7)))
-(net (code 7) (name "Jmp2722.cc.cc1")
-  (node (ref JJ2) (pin A5))
-  (node (ref JU1) (pin 1)))
-(net (code 8) (name "Jmp2722.cc.cc2")
-  (node (ref JJ2) (pin B5))
-  (node (ref JU1) (pin 22)))
-(net (code 9) (name "Jmp2722.pwr_out")
+(net (code 7) (name "Jmp2722.pwr_out")
   (node (ref JU1) (pin 13))
   (node (ref JL1) (pin 2))
   (node (ref JC6) (pin 1))
   (node (ref JU2) (pin 2))
   (node (ref JC7) (pin 1)))
-(net (code 10) (name "Jmp2722.vrntc")
+(net (code 8) (name "Jmp2722.vrntc")
   (node (ref JU1) (pin 7))
   (node (ref JR1) (pin 1)))
-(net (code 11) (name "Jmp2722.int")
+(net (code 9) (name "Jmp2722.int")
   (node (ref JU1) (pin 8)))
-(net (code 12) (name "Jmp2722.stat")
+(net (code 10) (name "Jmp2722.stat")
   (node (ref JU1) (pin 11)))
-(net (code 13) (name "Jmp2722.pg")
+(net (code 11) (name "Jmp2722.pg")
   (node (ref JU1) (pin 9)))
-(net (code 14) (name "Jmp2722.usb.dp")
+(net (code 12) (name "Jmp2722.usb.dp")
   (node (ref JU1) (pin 21)))
-(net (code 15) (name "Jmp2722.usb.dm")
+(net (code 13) (name "Jmp2722.usb.dm")
   (node (ref JU1) (pin 20)))
+(net (code 14) (name "Jmp2722.cc.cc1")
+  (node (ref JJ2) (pin A5))
+  (node (ref JU1) (pin 1)))
+(net (code 15) (name "Jmp2722.cc.cc2")
+  (node (ref JJ2) (pin B5))
+  (node (ref JU1) (pin 22)))
 (net (code 16) (name "Jmp2722.ic.pmid")
   (node (ref JU1) (pin 3))
   (node (ref JC2) (pin 1)))
 (net (code 17) (name "Jmp2722.ic.vcc")
   (node (ref JU1) (pin 19))
   (node (ref JC4) (pin 1)))
-(net (code 18) (name "Jmp2722.vbst_cap.neg")
+(net (code 18) (name "Jmp2722.vbst_cap.pos")
+  (node (ref JU1) (pin 6))
+  (node (ref JC1) (pin 1)))
+(net (code 19) (name "Jmp2722.vbst_cap.neg")
   (node (ref JU1) (pin 4))
   (node (ref JC1) (pin 2))
   (node (ref JL1) (pin 1)))
-(net (code 19) (name "Jmp2722.vbst_cap.pos")
-  (node (ref JU1) (pin 6))
-  (node (ref JC1) (pin 1)))
 (net (code 20) (name "Jfake_ntc.output")
   (node (ref JU1) (pin 10))
   (node (ref JR1) (pin 2))
@@ -714,16 +714,16 @@
   (node (ref JJ3) (pin 2))
   (node (ref JSW1) (pin 1))
   (node (ref JR10) (pin 2)))
-(net (code 25) (name "Jstick.ax1")
+(net (code 25) (name "Jstick.sw")
+  (node (ref JU1) (pin 17))
+  (node (ref JU3) (pin 5))
+  (node (ref JU4) (pin 1)))
+(net (code 26) (name "Jstick.ax1")
   (node (ref JU4) (pin 4))
   (node (ref JR4) (pin 1)))
-(net (code 26) (name "Jstick.ax2")
+(net (code 27) (name "Jstick.ax2")
   (node (ref JU4) (pin 7))
   (node (ref JR6) (pin 1)))
-(net (code 27) (name "Jstick.sw")
-  (node (ref JU1) (pin 17))
-  (node (ref JU3) (pin 5))
-  (node (ref JU4) (pin 1)))
 (net (code 28) (name "Jax1_div.output")
   (node (ref JU3) (pin 3))
   (node (ref JR4) (pin 2))

examples/BleJoystick/BleJoystick.svgpcb.js

@@ -248,27 +248,27 @@ board.setNetlist([
   {name: "Jv3v3", pads: [["JU2", "3"], ["JC8", "1"], ["JTP4", "1"], ["JD1", "1"], ["JU3", "1"], ["JU3", "16"], ["JU3", "7"], ["JC9", "1"], ["JC10", "1"], ["JJ3", "1"], ["JR3", "1"], ["JU4", "5"], ["JU4", "6"], ["JU5", "1"], ["JC12", "1"], ["JD2", "2"], ["JR13", "1"], ["JR14", "1"]]},
   {name: "Jusb.usb.dp", pads: [["JJ2", "A6"], ["JJ2", "B6"]]},
   {name: "Jusb.usb.dm", pads: [["JJ2", "A7"], ["JJ2", "B7"]]},
-  {name: "Jmp2722.cc.cc1", pads: [["JJ2", "A5"], ["JU1", "1"]]},
-  {name: "Jmp2722.cc.cc2", pads: [["JJ2", "B5"], ["JU1", "22"]]},
   {name: "Jmp2722.pwr_out", pads: [["JU1", "13"], ["JL1", "2"], ["JC6", "1"], ["JU2", "2"], ["JC7", "1"]]},
   {name: "Jmp2722.vrntc", pads: [["JU1", "7"], ["JR1", "1"]]},
   {name: "Jmp2722.int", pads: [["JU1", "8"]]},
   {name: "Jmp2722.stat", pads: [["JU1", "11"]]},
   {name: "Jmp2722.pg", pads: [["JU1", "9"]]},
   {name: "Jmp2722.usb.dp", pads: [["JU1", "21"]]},
   {name: "Jmp2722.usb.dm", pads: [["JU1", "20"]]},
+  {name: "Jmp2722.cc.cc1", pads: [["JJ2", "A5"], ["JU1", "1"]]},
+  {name: "Jmp2722.cc.cc2", pads: [["JJ2", "B5"], ["JU1", "22"]]},
   {name: "Jmp2722.ic.pmid", pads: [["JU1", "3"], ["JC2", "1"]]},
   {name: "Jmp2722.ic.vcc", pads: [["JU1", "19"], ["JC4", "1"]]},
-  {name: "Jmp2722.vbst_cap.neg", pads: [["JU1", "4"], ["JC1", "2"], ["JL1", "1"]]},
   {name: "Jmp2722.vbst_cap.pos", pads: [["JU1", "6"], ["JC1", "1"]]},
+  {name: "Jmp2722.vbst_cap.neg", pads: [["JU1", "4"], ["JC1", "2"], ["JL1", "1"]]},
   {name: "Jfake_ntc.output", pads: [["JU1", "10"], ["JR1", "2"], ["JR2", "1"]]},
   {name: "Jmcu.program_uart_node.a_tx", pads: [["JU3", "12"], ["JJ3", "3"]]},
   {name: "Jmcu.program_uart_node.b_tx", pads: [["JU3", "11"], ["JJ3", "4"]]},
   {name: "Jmcu.program_en_node", pads: [["JU3", "2"], ["JJ3", "6"], ["JR3", "2"], ["JC11", "1"]]},
   {name: "Jmcu.program_boot_node", pads: [["JU3", "8"], ["JJ3", "2"], ["JSW1", "1"], ["JR10", "2"]]},
+  {name: "Jstick.sw", pads: [["JU1", "17"], ["JU3", "5"], ["JU4", "1"]]},
   {name: "Jstick.ax1", pads: [["JU4", "4"], ["JR4", "1"]]},
   {name: "Jstick.ax2", pads: [["JU4", "7"], ["JR6", "1"]]},
-  {name: "Jstick.sw", pads: [["JU1", "17"], ["JU3", "5"], ["JU4", "1"]]},
   {name: "Jax1_div.output", pads: [["JU3", "3"], ["JR4", "2"], ["JR5", "1"]]},
   {name: "Jax2_div.output", pads: [["JU3", "15"], ["JR6", "2"], ["JR7", "1"]]},
   {name: "Jtrig.out", pads: [["JU5", "2"], ["JR8", "1"]]},

examples/CanAdapter/CanAdapter.net

@@ -422,13 +422,13 @@
   (node (ref OU2) (pin 4))
   (node (ref OR1) (pin 2))
   (node (ref OR2) (pin 1)))
-(net (code 6) (name "Oreg_3v3.boot_cap.neg")
+(net (code 6) (name "Oreg_3v3.boot_cap.pos")
+  (node (ref OU2) (pin 6))
+  (node (ref OC2) (pin 1)))
+(net (code 7) (name "Oreg_3v3.boot_cap.neg")
   (node (ref OU2) (pin 2))
   (node (ref OC2) (pin 2))
   (node (ref OL1) (pin 1)))
-(net (code 7) (name "Oreg_3v3.boot_cap.pos")
-  (node (ref OU2) (pin 6))
-  (node (ref OC2) (pin 1)))
 (net (code 8) (name "Oreg_3v3.en_res.b")
   (node (ref OU2) (pin 5))
   (node (ref OR3) (pin 2)))
@@ -447,18 +447,18 @@
   (node (ref OU3) (pin 8))
   (node (ref OJ1) (pin 2))
   (node (ref OR5) (pin 2)))
-(net (code 13) (name "Ocan.can.canh")
-  (node (ref OU1) (pin 6))
-  (node (ref OU4) (pin 7)))
-(net (code 14) (name "Ocan.can.canl")
-  (node (ref OU1) (pin 14))
-  (node (ref OU4) (pin 6)))
-(net (code 15) (name "Ocan.controller.txd")
+(net (code 13) (name "Ocan.controller.txd")
   (node (ref OU3) (pin 6))
   (node (ref OU4) (pin 1)))
-(net (code 16) (name "Ocan.controller.rxd")
+(net (code 14) (name "Ocan.controller.rxd")
   (node (ref OU3) (pin 5))
   (node (ref OU4) (pin 4)))
+(net (code 15) (name "Ocan.can.canh")
+  (node (ref OU1) (pin 6))
+  (node (ref OU4) (pin 7)))
+(net (code 16) (name "Ocan.can.canl")
+  (node (ref OU1) (pin 14))
+  (node (ref OU4) (pin 6)))
 (net (code 17) (name "Oledr.res.a")
   (node (ref OD2) (pin 1))
   (node (ref OR5) (pin 1)))

examples/CanAdapter/CanAdapter.svgpcb.js

@@ -162,17 +162,17 @@ board.setNetlist([
   {name: "Ov3v3", pads: [["OR1", "1"], ["OL1", "2"], ["OC4", "1"], ["OD1", "1"], ["OU3", "1"], ["OU3", "16"], ["OU3", "7"], ["OC5", "1"], ["OC6", "1"], ["OJ1", "1"], ["OR4", "1"], ["OU4", "3"], ["OC8", "1"], ["OD2", "2"]]},
   {name: "Oobd.pwr", pads: [["OU1", "16"], ["OFB1", "1"]]},
   {name: "Oreg_3v3.fb.output", pads: [["OU2", "4"], ["OR1", "2"], ["OR2", "1"]]},
-  {name: "Oreg_3v3.boot_cap.neg", pads: [["OU2", "2"], ["OC2", "2"], ["OL1", "1"]]},
   {name: "Oreg_3v3.boot_cap.pos", pads: [["OU2", "6"], ["OC2", "1"]]},
+  {name: "Oreg_3v3.boot_cap.neg", pads: [["OU2", "2"], ["OC2", "2"], ["OL1", "1"]]},
   {name: "Oreg_3v3.en_res.b", pads: [["OU2", "5"], ["OR3", "2"]]},
   {name: "Omcu.program_uart_node.a_tx", pads: [["OU3", "12"], ["OJ1", "3"]]},
   {name: "Omcu.program_uart_node.b_tx", pads: [["OU3", "11"], ["OJ1", "4"]]},
   {name: "Omcu.program_en_node", pads: [["OU3", "2"], ["OJ1", "6"], ["OR4", "2"], ["OC7", "1"]]},
   {name: "Omcu.program_boot_node", pads: [["OU3", "8"], ["OJ1", "2"], ["OR5", "2"]]},
-  {name: "Ocan.can.canh", pads: [["OU1", "6"], ["OU4", "7"]]},
-  {name: "Ocan.can.canl", pads: [["OU1", "14"], ["OU4", "6"]]},
   {name: "Ocan.controller.txd", pads: [["OU3", "6"], ["OU4", "1"]]},
   {name: "Ocan.controller.rxd", pads: [["OU3", "5"], ["OU4", "4"]]},
+  {name: "Ocan.can.canh", pads: [["OU1", "6"], ["OU4", "7"]]},
+  {name: "Ocan.can.canl", pads: [["OU1", "14"], ["OU4", "6"]]},
   {name: "Oledr.res.a", pads: [["OD2", "1"], ["OR5", "1"]]},
   {name: "Oledg.signal", pads: [["OU3", "13"], ["OD3", "2"]]},
   {name: "Oledg.res.a", pads: [["OD3", "1"], ["OR6", "1"]]},