Clean node retention implementation with extended coverage

[robtaylor]

Summary

This PR provides a clean, restructured implementation of the node retention feature, based on the original work by @AdvaySingh1. The key changes:

• Cleaned up history: The original 103 WIP commits have been reorganized into 11 logical, bisectable commits grouped by subsystem (core data structures, lifecycle, classic Ntk ops, AIG/GIA conversion, GIA optimization passes, I/O integration, tests)
• Extended retention coverage: Propagation has been added to many operations that were previously missing, covering both the classic abc and abc9 synthesis pipelines end-to-end
• CI: Full test coverage across Posix (make), Posix (CMake), and Windows builds with retention validation scripts
• New &write_retention command: Dumps GIA retention map for debugging/validation

New retention propagation (not in original branch)

Area	Functions
CEC/SAT sweeping	Cec4_ManStartNew, sweep loops, Gia_ManLocalRehash
DCH	Dch_DeriveTotalAig, Dch_ManSweep
GIA sweep	Gia_ManDupWithBoxes, Gia_ManFraigCreateGia, Gia_ManFraigReduceGia
GIA script	Gia_ManDupFromBarBufs, Gia_ManDupToBarBufs
Correlation	Gia_ManCorrReduce
Classic strash	Abc_NtkRestrash
Classic balance	Abc_NodeBalance_rec
Classic Dar	Abc_NtkFromDar, Abc_NtkFromDarChoices
Classic If (LUT mapping)	Abc_NtkToIf, Abc_NodeFromIf_rec
Classic Ntk dup	Abc_NtkDup
Netlist conversion	Abc_NtkAigToLogicSop

Validated with Yosys integration

This ABC branch is used by two Yosys PRs that preserve \src attributes through synthesis:

• Classic abc pass: robtaylor/yosys#1
• abc9 pass: robtaylor/yosys#2

Both pass CI with test fixtures including Amaranth-style and SpinalHDL-style Verilog designs.

Test plan

• All ABC CI passing (Posix make, Posix CMake, Windows)
• Node retention integration tests (get_and_put, v3, full pipeline)
• GIA retention validation (&write_retention output verified)
• Yosys classic abc src retention tests passing
• Yosys abc9 src retention tests passing
• Tested with i10.aig benchmark (smoke test + CEC equivalence check)

cc @AdvaySingh1

[greptile-apps]

Greptile Summary

This PR implements a comprehensive node retention system for tracking source node origins through ABC synthesis transformations, enabling Yosys to preserve \src attributes through both classic abc and abc9 passes.

Key Changes

• Core infrastructure: Added Nr_Man_t hash table-based retention manager to Abc_Ntk_t, Aig_Man_t, and Gia_Man_t structures
• Retention propagation: Extended coverage to 30+ operations across classic ABC (strash, balance, Dar, If mapping) and GIA subsystems (dup, hash, sweep, CEC, DCH)
• New &write_retention command: Outputs GIA retention map with CI position mappings for Yosys integration
• Comprehensive testing: Unit tests, integration scripts, and CI validation across Posix (make/CMake) and Windows builds

Issues Found

• Critical logic error in src/base/abci/abcDar.c:303-307 - missing braces cause retention call to execute unconditionally for all latches instead of only Init1 latches
• Minor cleanup needed: duplicate commented include in abc.h, TODO comment and duplicate declaration in mainInt.h

The implementation is well-structured with proper memory management, validation functions, and thorough test coverage. The retention manager uses dynamic hash table resizing and provides comprehensive debugging/profiling capabilities.

Confidence Score: 3/5

• Safe to merge after fixing the critical logic error in abcDar.c latch handling
• Score reflects one critical logic bug (missing braces in latch retention propagation) that could cause incorrect retention tracking for Init1 latches. The core implementation is solid with good test coverage, but this bug needs fixing before merge. All other changes appear correct and well-tested.
• src/base/abci/abcDar.c requires immediate attention for the brace error at lines 303-307

Important Files Changed

Filename	Overview
src/base/abc/node_retention.c	Core retention manager implementation - hash table-based tracking system with proper memory management and validation
src/base/abc/node_retention.h	Header defines retention manager API and data structures for tracking node origins through transformations
src/base/abci/abcDar.c	Dar conversion with retention propagation - contains logic error in latch handling (line 306 outside if block)
src/proof/cec/cecSatG2.c	CEC/SAT sweeping operations with retention propagation for both CI/CO and internal AND nodes
src/aig/gia/giaDup.c	GIA duplication operations properly propagate retention through various dup functions
src/base/abci/abc.c	Added &write_retention command and self-origin seeding in &r - well documented
src/base/abc/abc.h	Added pNodeRetention field to Abc_Ntk_t structure with duplicate comment line
src/base/main/mainInt.h	Added vNodeRetention global vector - has commented duplicate declaration and TODO

Flowchart

%%{init: {'theme': 'neutral'}}%%
flowchart TB
    subgraph Input["Input Stage"]
        READ["read/&r command"]
        SEED["Self-origin seeding<br/>(CI and AND nodes)"]
    end
    
    subgraph Core["Core Data Structures"]
        ABC_NTK["Abc_Ntk_t<br/>pNodeRetention"]
        AIG_MAN["Aig_Man_t<br/>pNodeRetention"]
        GIA_MAN["Gia_Man_t<br/>pNodeRetention"]
        NR_MAN["Nr_Man_t<br/>(hash table)"]
    end
    
    subgraph Transforms["Transformation Layer"]
        direction LR
        CLASSIC["Classic ABC<br/>- Strash<br/>- Balance<br/>- Dar<br/>- If mapping"]
        GIA_OPS["GIA Ops<br/>- Dup<br/>- Hash<br/>- Sweep<br/>- Script"]
        CEC["CEC/SAT<br/>- Sweeping<br/>- Correlation"]
    end
    
    subgraph Output["Output Stage"]
        WRITE_BLIF["write_blif<br/>(retention map)"]
        WRITE_RET["&write_retention<br/>(GIA retention)"]
    end
    
    READ --> SEED
    SEED --> ABC_NTK
    SEED --> GIA_MAN
    
    ABC_NTK --> NR_MAN
    AIG_MAN --> NR_MAN
    GIA_MAN --> NR_MAN
    
    NR_MAN --> CLASSIC
    NR_MAN --> GIA_OPS
    NR_MAN --> CEC
    
    CLASSIC --> |Nr_ManCopyOrigins| NR_MAN
    GIA_OPS --> |Nr_ManCopyOrigins| NR_MAN
    CEC --> |Nr_ManCopyOrigins| NR_MAN
    
    NR_MAN --> WRITE_BLIF
    NR_MAN --> WRITE_RET
    
    WRITE_BLIF --> YOSYS["Yosys integration<br/>(classic abc pass)"]
    WRITE_RET --> YOSYS2["Yosys integration<br/>(abc9 pass)"]

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_{Last reviewed commit: 0163b34}

[greptile-apps]

_{56 files reviewed, 4 comments}

_{Edit Code Review Agent Settings | Greptile}

[akashlevy]

Hey @robtaylor sorry I missed this! This looks awesome. I'll test this out and give some feedback soon.

[akashlevy]

In the meantime, can you take a look at the conflicts?

[robtaylor]

Ah, it’s now been superseded by berkeley-abc#487

…

On Sat, 7 Mar 2026 at 01:49, Akash Levy ***@***.***> wrote: *akashlevy* left a comment (Silimate/abc#4) <#4 (comment)> In the meantime, can you take a look at the conflicts? — Reply to this email directly, view it on GitHub <#4 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AAB4O4DNWIABP7VYH2MTYDD4PN54BAVCNFSM6AAAAACV24OKXSVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHM2DAMJVGIYDINJWGI> . You are receiving this because you were mentioned.Message ID: ***@***.***>