enable lec check

[nanocoh]

No description provided.

[maliberty]

I see some errors that look like tool issues on your side, eg ng45/swerv

[2026-02-10T22:12:14.527Z] [2026-02-10 22:12:13.459] [info] [KeplerFormal.cpp:263] Found top design: swerv
[2026-02-10T22:12:14.527Z] [2026-02-10 22:12:13.681] [error] [KeplerFormal.cpp:339] Workflow failed: Anonymous instance in SNLPath constructor.
[2026-02-10T22:12:14.527Z] child process exited abnormally

[nanocoh]

I see some errors that look like tool issues on your side, eg ng45/swerv

[2026-02-10T22:12:14.527Z] [2026-02-10 22:12:13.459] [info] [KeplerFormal.cpp:263] Found top design: swerv [2026-02-10T22:12:14.527Z] [2026-02-10 22:12:13.681] [error] [KeplerFormal.cpp:339] Workflow failed: Anonymous instance in SNLPath constructor. [2026-02-10T22:12:14.527Z] child process exited abnormally

A lot of issues are regarding instances that need to be cleaned before dumping the verilog through "write_verilog -remove_cells", will need to edit it one by one but there might be also tool issues indeed among the tests.

Working on cleaning it all one by one and will update the pr right after.

[nanocoh]

We filtered the majority of config issues.

Some issues remain on the tool that we are solving.

There is also one issue in the verilog parsing level for which @xtofalex have some comments:

Parser error: syntax error, unexpected ESCAPED_IDENTIFIER_TK, expecting '(
That can be found on ibex asap7 for example.

[maliberty]

There is a pending fix for a Verilog escaping issue. Perhaps that is what you are seeing. What does that line look like?

[nanocoh]

There is a pending fix for a Verilog escaping issue. Perhaps that is what you are seeing. What does that line look like?

It very might well be the case here. Will let @xtofalex comment on what he saw.

[nanocoh]

In case it is a pending fix, I can disable it for now in the related test cases.

[xtofalex]

There is a pending fix for a Verilog escaping issue. Perhaps that is what you are seeing. What does that line look like?

We saw an escaping issue coming from the OpenSTA Verilog dumper when reading results/ihp-sg13g2/ibex/base/4_before_rsz_lec.v

%Error: 4_before_rsz_lec.v:70061:7: syntax error, unexpected IDENTIFIER-for-type, expecting ')'
70061 |     .Y\[32:1\]({net462,
      |       ^~~~~~~~~~~~~~~~~
        ... See the manual at https://verilator.org/verilator_doc.html?v=5.044 for more assistance.
%Error: Exiting due to 1 error(s)
zsh: exit 1     verilator --lint-only -Wall 4_before_rsz_lec.v

The line should be: ".\Y[32:1] ({net462,".

From quick analysis, the problem comes from:
https://github.com/The-OpenROAD-Project/OpenSTA/blame/e872c55bfe1c005cb0dae8cd281f986dd39cfd34/verilog/VerilogWriter.cc#L391

where in "void VerilogWriter::writeInstBusPin" :

fprintf(stream_, ".%s({", network_->name(port));

should be replace with something like in "void VerilogWriter::writeInstPin" :

 string net_vname = netVerilogName(net_name);

@maliberty, If this is not related to the pending fix you are referring to, I can open an issue in OpenSTA.

[povik]

@xtofalex looks to be related to the pending fix. See #3826

[xtofalex]

@xtofalex looks to be related to the pending fix. See #3826

Yes thanks !

[maliberty]

I'm curious about the ones with DISABLE_LEC_CHECK=1 - do you plan to look at those later?

[maliberty]

The variable should be defined and documented in variables.yaml (e.g. EQUIVALENCE_CHECK). It is better to have positive names to avoid having double negatives like DISABLE_LEC_CHECK=false. Let's use LEC_CHECK with the default=1.

[nanocoh]

Done

[maliberty]

REMOVE_CELLS_FOR_LEC in variables.yaml

[nanocoh]

Done

[maliberty]

It would be better to put this in the platform rather than every design's config.mk. Use ?= so it can be overridden if needed.

[nanocoh]

Done

[nanocoh]

I'm curious about the ones with DISABLE_LEC_CHECK=1 - do you plan to look at those later?

We disabled all designs with the pending fix for Verilog escaping. We will of-course turn them on and verify them in another pr when the fix is integrated.