Add transpose-form FIR option to SSR_FIR example

[robgraessle]

Summary

• Adds a transpose-form SSR FIR (TRANSPOSE_SSR_FIR) as a second DUT alongside the existing direct-form filter in the Examples/HDL/Digital_Filtering/SSR_FIR example, so the two architectures can be compared side by side.
• Both forms share a unified fixed_pkg/cfixed_pkg VHDL base, are driven by the same stimulus, and are functionally equivalent to within one output LSB; the direct form is also checked against the golden floating-point Discrete FIR Filter reference.
• Model now defaults to SSR=8, TAPS=64, non-symmetric; README and screenshot updated to document both architectures and when to choose each.

Changes

• New: TRANSPOSE_SSR_FIR.vhd, TRANSPOSE_SSR_FIR_CHAIN.vhd, WRAPPER_TRANSPOSE_SSR_FIR.vhd, WRAPPER_TRANSPOSE_SSR_FIR_config.m, fixed_pkg.vhd, cfixed_pkg.vhd
• Migrated the direct-form core and support blocks (SSR_FIR, SDELAY, BDELAY, DSPx8_WRAPPER, WRAPPER_SSR_FIR) onto the shared fixed_pkg/cfixed_pkg base
• Removed obsolete TYPES_PKG.vhd and SSR_FIR_TEST.vhd
• Updated README.md, README.html, and the model screenshot; SSR_FIR.slx saved in R2025a

Test plan

• All VHDL sources compile and elaborate (xvhdl/xelab, VHDL-2008)
• Direct form matches the golden floating-point reference in Simulink (max |err| ~6e-05)
• Direct and transpose outputs agree to within one output LSB (2^-16) after latency alignment
• Saved model reloads and compiles cleanly from disk
• Reviewer: open in Vitis Model Composer (2026.1), run the model, confirm Input/Output spectrum analyzers and error scope

Note: the transpose path currently supports non-symmetric (NS) filters; even/odd symmetric (ES/OS) support in the transpose core is still under development, so use the direct form for ES/OS designs.

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