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Pull requests: Xilinx/mlir-aie
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Purge VCK5000/AMDAIR/HSA runtime support
#3335
opened Jul 13, 2026 by
jgmelber
Collaborator
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4 tasks done
Add CI check that no submodule pin regresses relative to main
#3331
opened Jul 13, 2026 by
jgmelber
Collaborator
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3 tasks done
Bump bootgen to upstream Xilinx/bootgen xilinx_v2026.1, drop the jgmelber fork
#3329
opened Jul 13, 2026 by
jgmelber
Collaborator
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5 of 6 tasks
Repoint mlirDistro.yml at ROCm/llvm-project
#3324
opened Jul 13, 2026 by
jgmelber
Collaborator
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2 tasks
[cert] Add page/section-based CERT lowering
#3253
opened Jun 30, 2026 by
fifield
Collaborator
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[IRON] Add specialized FIFO subclasses (Cascade / Packet / Accum / Sparse / Memtile / VariableRate)
#3039
opened Apr 27, 2026 by
matteius
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3 of 5 tasks
Expose set_aie_stream() on IRON ObjectFifo class
#2971
opened Mar 14, 2026 by
RobinMelhuish
Contributor
•
Draft
add aie-chess-simulation as examples for single core chess simulation in BFP16 and BF16
#2538
opened Aug 26, 2025 by
ChengyueWang
Contributor
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