feat: STM32 add SPIv2 and add Digital_IO for pinv2 to drive NSS #776
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mathk
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@mathk if you accept your invitation to the org, CI should run automatically for you now. |
mattnite
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Dec 23, 2025
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Looks good! just have some naming nits
| @@ -1,3 +1,4 @@ | |||
| const util = @import("../common/util.zig"); | |||
| pub const UARTType = enum(usize) { | |||
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| pub const UARTType = enum(usize) { | |
| pub const UART_Type = enum(usize) { |
| I2C2, | ||
| }; | ||
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| pub const SPIType = util.create_peripheral_enum("SPI", "spi_v2"); |
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| pub const SPIType = util.create_peripheral_enum("SPI", "spi_v2"); | |
| pub const SPI_Type = util.create_peripheral_enum("SPI", "spi_v2"); |
| @@ -0,0 +1,3 @@ | |||
| const spi = @import("../common/spi_v2.zig"); | |||
| pub const SPI = spi.SPI; | |||
| pub const SPIConfig = spi.Config; | |||
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| pub const SPIConfig = spi.Config; | |
| pub const SPI_Config = spi.Config; |
| std.log.info("SPI status {}", .{self.spi.SR.read()}); | ||
| } | ||
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| fn check_TX(self: *const SPI) bool { |
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| fn check_TX(self: *const SPI) bool { | |
| fn check_tx(self: *const SPI) bool { |
| return self.spi.SR.read().TXE != 0; | ||
| } | ||
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| fn check_RX(self: *const SPI) bool { |
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| fn check_RX(self: *const SPI) bool { | |
| fn check_rx(self: *const SPI) bool { |
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There is a limitation as spi_v2 only generate teh DR8 register. I will plan a fix for embassy to have both DR8 and DR16. For now it only support less than 8bit data read.