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Antmicro

Antmicro is a software-driven tech company developing open and modern industrial edge and cloud AI systems.

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  1. jetson-orin-baseboard jetson-orin-baseboard Public

    Baseboard targetting the NVIDIA Jetson Orin Nano and Jetson Orin NX

    187 51

  2. google-coral-baseboard google-coral-baseboard Public

    Antmicro's open hardware baseboard for the Google Coral i.MX8 + Edge TPU SoM

    80 31

  3. zynq-video-board zynq-video-board Public

    Open Hardware carrier board supporting modules with Zynq 7000 All Programmable SoC devices.

    63 29

  4. renode renode Public

    Forked from renode/renode

    Renode - virtual development tool for multinode embedded networks

    RobotFramework 37 3

  5. tensorflow-arduino-examples tensorflow-arduino-examples Public

    TensorFlow Lite Micro examples built in collaboration between Google and Antmicro, runnable in Google Colab and with Renode CI tests

    Shell 25 4

  6. fastvdma fastvdma Public

    Antmicro's fast, vendor-neutral DMA IP in Chisel

    Scala 128 27

Repositories

Showing 10 of 828 repositories
  • rdfm Public
    antmicro/rdfm’s past year of commit activity
    Python 36 Apache-2.0 7 0 0 Updated Dec 30, 2025
  • sv-tests Public Forked from chipsalliance/sv-tests

    Test suite designed to check compliance with the SystemVerilog standard.

    antmicro/sv-tests’s past year of commit activity
    SystemVerilog 2 ISC 88 0 22 Updated Dec 29, 2025
  • busperf Public

    Bus performance analysis tool

    antmicro/busperf’s past year of commit activity
    Rust 9 Apache-2.0 0 0 0 Updated Dec 29, 2025
  • renode Public Forked from renode/renode

    Renode - virtual development tool for multinode embedded networks

    antmicro/renode’s past year of commit activity
    RobotFramework 37 394 0 0 Updated Dec 29, 2025
  • testplanner Public
    antmicro/testplanner’s past year of commit activity
    Python 8 Apache-2.0 0 0 0 Updated Dec 29, 2025
  • verilator Public Forked from verilator/verilator

    Verilator open-source SystemVerilog simulator and lint system

    antmicro/verilator’s past year of commit activity
    SystemVerilog 22 LGPL-3.0 740 0 0 Updated Dec 29, 2025
  • xls Public Forked from google/xls

    XLS: Accelerated HW Synthesis

    antmicro/xls’s past year of commit activity
    C++ 0 Apache-2.0 237 0 1 Updated Dec 29, 2025
  • topwrap Public

    A Python package for generating HDL wrappers and top modules for HDL sources

    antmicro/topwrap’s past year of commit activity
    Python 52 Apache-2.0 7 1 0 Updated Dec 29, 2025
  • verilator-verification Public

    Test dashboard for verification features in Verilator

    antmicro/verilator-verification’s past year of commit activity
    SystemVerilog 28 Apache-2.0 5 0 0 Updated Dec 29, 2025
  • f4pga-arch-defs Public Forked from f4pga/f4pga-arch-defs

    FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

    antmicro/f4pga-arch-defs’s past year of commit activity
    Jupyter Notebook 1 ISC 123 0 10 Updated Dec 25, 2025
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