π―
Focusing
π Transforming Ideas into Silicon Dreams
Pinned Loading
-
Aegis
Aegis PublicOut-of-Order Memory Subsystem and Cache Coherency Engine for RISC-V
SystemVerilog
-
GrayMatter
GrayMatter PublicA simple pre-silicon hardware Trojan detection using entropy metrics and confidence-bound statistical analysis.
Python
-
Ultron
Ultron PublicStreaming connected-component labeling (CCL) and centroid engine for binary vision pipelines.
Python
-
Tiny-GPU
Tiny-GPU PublicForked from adam-maj/tiny-gpu
A minimal GPU design in Verilog to learn how GPUs work from the ground up - Advancements
SystemVerilog
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.


