Update submodule content

docs/_docs/A03-constant.md

@@ -2,21 +2,36 @@
 title: "Constants"
 permalink: /docs/constant/
 excerpt: "Constants"
-last_modified_at: 2022-12-06
+last_modified_at: 2026-07-14
 toc: true
 ---
 
 Constants can often be inferred by ROHD automatically, but can also be explicitly defined using [`Const`](https://intel.github.io/rohd/rohd/Const-class.html), which extends `Logic`.
 
 ```dart
 // a 16 bit constant with value 5
-var x = Const(5, width:16);
+var x = Const(5, width: 16);
 ```
 
+## Preferred radix
+
+The optional `preferredRadix` controls how a `Const` is displayed in generated outputs. Supported radices are binary (2), octal (8), decimal (10), and hexadecimal (16). The radix only affects formatting, not the value of the constant.
+
+```dart
+var binary = Const(42, width: 8, preferredRadix: 2);     // 8'b101010
+var octal = Const(42, width: 8, preferredRadix: 8);      // 8'o52
+var decimal = Const(42, width: 8, preferredRadix: 10);   // 8'd42
+var hexadecimal = Const(42, width: 8, preferredRadix: 16); // 8'h2a
+```
+
+Constants containing `x` or `z` may fall back to binary so all bit states can be represented.
+
+## Binary integer conversion
+
 There is a convenience function for converting binary to an integer:
 
 ```dart
-// this is equvialent to and shorter than int.parse('010101', radix:2)
+// this is equivalent to and shorter than int.parse('010101', radix: 2)
 // you can put underscores to help with readability, they are ignored
 bin('01_0101')
 ```

docs/_docs/A21-generation.md

@@ -28,6 +28,31 @@ void main() async {
 
 The `generateSynth` function will return a `String` with the SystemVerilog `module` definitions for the top-level it is called on, as well as any sub-modules (recursively).  You can dump the entire contents to a file and use it anywhere you would any other SystemVerilog.
 
+## Controlling port types
+
+Generated ports default to `input logic`, `output logic`, and `inout wire`, preserving the traditional ROHD declarations. Use a `SystemVerilogSynthesizerConfiguration` to independently control whether object types, such as `wire` and `var`, and data types, such as `logic`, are explicit for each port direction:
+
+```dart
+final generatedSv = myModule.generateSynth(
+  configuration: const SystemVerilogSynthesizerConfiguration(
+    inputPortType: SystemVerilogPortTypeConfiguration(
+      objectType: SystemVerilogPortType.explicit,
+      dataType: SystemVerilogPortType.implicit,
+    ),
+    outputPortType: SystemVerilogPortTypeConfiguration(
+      objectType: SystemVerilogPortType.implicit,
+      dataType: SystemVerilogPortType.implicit,
+    ),
+    inOutPortType: SystemVerilogPortTypeConfiguration(
+      objectType: SystemVerilogPortType.implicit,
+      dataType: SystemVerilogPortType.explicit,
+    ),
+  ),
+);
+```
+
+The same configuration can be passed directly to `SystemVerilogSynthesizer` when using `SynthBuilder`.
+
 ## Controlling naming
 
 ### Modules