plat-qcom: nord: add PIL bring-up for HPASS, SOCCP and Turing DSPs - #41
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Taniya Das (taniyadas20) wants to merge 1 commit into
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plat-qcom: nord: add PIL bring-up for HPASS, SOCCP and Turing DSPs#41Taniya Das (taniyadas20) wants to merge 1 commit into
Taniya Das (taniyadas20) wants to merge 1 commit into
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Add the clock and PAS bring-up support required to load the additional
DSP images on the Nord platform:
- clock-qcom: add a Lucid-OLE PLL enable helper. Lucid-OLE reuses the
Lucid-EVO register layout but packs PLL_L_VAL as an 8-bit L value plus
separate 8-bit process-cal and ring-osc-cal fields, and requires the
PLL_TEST_CTL* trim registers to be programmed, so it gets its own
config struct and enable path.
- clk_qcom: add QCOM_CLKS_{SOCCP,HPASS0,HPASS1,HPASS2,TURING2,TURING3}
clock groups and route them through the PAS enable path.
- pas_data: add PAS IDs for TURING2/3, HPASS0-2 and SOCCP.
- nord: add the per-platform clock-qcom-pas.c and clock_group_qcom.h
describing the PLL and clock-group configuration for these subsystems.
- arch/target config: add the register base/size definitions needed by
the new bring-up code.
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Taniya Das (taniyadas20)
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Contributor
|
Please modify the commit messages removing the how the change is done as to why the change is needed. |
Copilot started reviewing on behalf of
Jorge A. Ramirez-Ortiz (ldts)
August 12, 2026 11:56
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Pull request overview
Adds Nord clock and reset sequencing for HPASS, SOCCP, and Turing DSP bring-up.
Changes:
- Adds Lucid-OLE PLL configuration and enable support.
- Adds PAS IDs, clock groups, and subsystem bring-up sequences.
- Defines Nord MMIO regions and clock/reset registers.
Reviewed changes
Copilot reviewed 7 out of 7 changed files in this pull request and generated 5 comments.
Show a summary per file
| File | Description |
|---|---|
core/pta/qcom/pas/platform/pas_data.h |
Adds subsystem PAS IDs. |
core/include/drivers/clk_qcom.h |
Adds clock groups and Lucid-OLE API. |
core/drivers/clk/qcom/platform/nord/clock-qcom-pas.c |
Implements Nord clock, reset, and processor sequencing. |
core/drivers/clk/qcom/platform/nord/clock_group_qcom.h |
Defines Nord clock/reset registers. |
core/drivers/clk/qcom/clock-qcom.c |
Implements Lucid-OLE PLL enablement and routing. |
core/arch/arm/plat-qcom/wildcat/nord/target_config.h |
Adds Nord peripheral MMIO regions. |
core/arch/arm/plat-qcom/wildcat/arch_config.h |
Adds Wildcat architecture register regions. |
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| /* 6. Wait for the FSM to auto-break. */ | ||
| while (!(io_read32(pub + CDSP_QDSP6SS_BOOT_STATUS) & | ||
| QDSP6SS_BOOT_STATUS_AUTO_BREAK_BIT)) | ||
| udelay(5); |
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| { | ||
| uint64_t timeout = 0; | ||
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| io_clrbits32(tcsr + TCSR_HPASS_AG_NOC_QCHANNEL_QREQN, qreqn_bit); | ||
| timeout = timeout_init_us(500); | ||
| while (io_read32(tcsr + TCSR_HPASS_AG_NOC_QCHANNEL_QACCEPTN) & | ||
| qaccept_bit) { | ||
| if (timeout_elapsed(timeout)) | ||
| goto retry; | ||
| udelay(5); | ||
| } | ||
| return TEE_SUCCESS; | ||
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| retry: | ||
| if (!(io_read32(tcsr + TCSR_HPASS_AG_NOC_QCHANNEL_QACCEPTN) & | ||
| qdeny_bit)) | ||
| return TEE_SUCCESS; |
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||
| #define TCSR_HPASS_AG_NOC_QDENY_BIT BIT(1) | ||
| #define TCSR_HPASS_ENPU_NOC_QDENY_BIT BIT(5) | ||
| #define TCSR_HPASS_AUDIO_NOC_QDENY_BIT TCSR_HPASS_AG_NOC_QDENY_BIT |
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| while (!timeout_elapsed(timeout)) { | ||
| if (io_read32(v + HPASS_QDSP6SS_BOOT_STATUS) & | ||
| QDSP6SS_BOOT_STATUS_AUTO_BREAK_BIT) | ||
| break; | ||
| udelay(5); | ||
| } |
| return TEE_SUCCESS; | ||
| } | ||
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| TEE_Result qcom_clock_enable_pas(enum qcom_clk_group group) |
| #define TARGET_CONFIG_H | ||
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| #define GENI_UART_REG_BASE UL(0x884000) | ||
| #define GCC_BASE UL(0x110000) |
There was a problem hiding this comment.
Please explicit add some tag like WIP, if change is not tested. It will help to avoid review confusion.
There was a problem hiding this comment.
Sure, will add WIP
| #define SE_GCC_CBCR_CLK_OFF_BIT BIT(31) | ||
| #define SE_GCC_CBCR_HW_CTL_ENABLE_BIT BIT(1) | ||
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| #define CDSP_NSP_SS_CC_OFFSET 0x00000000 |
There was a problem hiding this comment.
for one group of #define can follow same indent for macro value?
Contributor
|
If this change is not tested, can you please move the PR to draft Taniya Das (@taniyadas20). We can mark it as ready to review once all the dependent parts are avail/change is ready to review. |
Taniya Das (taniyadas20)
marked this pull request as draft
August 14, 2026 05:10
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Add the clock and PAS bring-up support required to load the additional DSP images on the Nord platform: