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@lipengfei28 lipengfei28 commented Nov 25, 2025

Summary

Summary
arm/arm64 add api
up_set_irq_type
up_prioritize_irq
up_trigger_irq

Impact

some drvier need config irq type,prioritize,separately
so add this api

Testing

This is debug log on imx95

  diff --git a/arch/arm64/src/common/arm64_gicv3.c b/arch/arm64/src/common/arm64_gicv3.c
      index e776dd6e92a..d225d644c3a 100644
      --- a/arch/arm64/src/common/arm64_gicv3.c
      +++ b/arch/arm64/src/common/arm64_gicv3.c
      @@ -200,7 +200,7 @@ int up_set_irq_type(int irq, int mode)
               {
                 val |= (GICD_ICFGR_TYPE << shift);
               }
      -
      +      syslog (1, "addr %lx", ICFGR(base, idx));
             putreg32(val, ICFGR(base, idx));
             spin_unlock_irqrestore(&g_gic_lock, irq_flags);
             return OK;
      diff --git a/arch/arm64/src/imx9/imx9_lpuart.c b/arch/arm64/src/imx9/imx9_lpuart.c
      index 497d73ca5c7..aae205fbd74 100644
      --- a/arch/arm64/src/imx9/imx9_lpuart.c
      +++ b/arch/arm64/src/imx9/imx9_lpuart.c
      @@ -1456,6 +1456,8 @@ static int imx9_attach(struct uart_dev_s *dev)
              * in the UART
              */   
      +         syslog (1, "irq %d\n", priv->irq);
      +      up_set_irq_type(priv->irq, IRQ_RISING_EDGE);
             up_enable_irq(priv->irq);
           }
BuildInfo:
  - SM firmware Build 550, Commit 548961fd, Aug 14 2025 06:34:21
  - ELE firmware version 1.3.0-5c5ab5c4

switch to partitions #0, OK
mmc0(part 0) is current device
flash target is MMC:0
Net:   WARNING: no MAC address assigned for MAC0
imx_get_mac_from_fuse: fuse read err: 0
eth0: enetc-0 [PRIME]WARNING: no MAC address assigned for MAC1
imx_get_mac_from_fuse: fuse read err: 0
, eth1: enetc-1ERROR enetc-2 firmware loading disabled.
WARNING: no MAC address assigned for MAC2
imx_get_mac_from_fuse: fuse read err: 0
, eth2: enetc-2
Fastboot: Normal
Normal Boot
Hit any key to stop autoboot:  0
u-boot=> dcache off; fatload mmc 0 0xa0100000 nuttx.bin; go 0xa0100000
347136 bytes read in 15 ms (22.1 MiB/s)
## Starting application at 0xA0100000 ...
- Ready to Boot Primary CPU
- Boot from EL2
- Boot from EL1
- Boot to C runtime for OS Initialize
irq 51
addr 48000c0c

NuttShell (NSH) NuttX-12.11.0
nsh> mw 0x48000c0c
  0x48000c0c = 0x00000080     //irq 51 edge-triggered.
nsh> ls
/:
 dev/
 proc/
nsh> pwd
/
nsh>

This is debug log on qemu-system-arm,gic v2

diff --git a/arch/arm/src/armv8-r/arm_gicv2.c b/arch/arm/src/armv8-r/arm_gicv2.c
index 579ef893110..57557bf2ab5 100644
--- a/arch/arm/src/armv8-r/arm_gicv2.c
+++ b/arch/arm/src/armv8-r/arm_gicv2.c
@@ -504,7 +504,6 @@
 #define GIC_ICDICFR_ID_SHIFT(n)    GIC_SHIFT16(n)
 #define GIC_ICDICFR_ID_MASK(n)     GIC_MASK16(n)
 #  define GIC_ICDICFR_ID(n,c)      ((uint32_t)(c) << GIC_SHIFT16(n))
-
 /* PPI Status Register */

 #define GIC_ICDPPISR_PPI(n)        (1 << ((n) + 11)) /* Bits 11-15:  PPI(n) status, n=0-4 */
@@ -1269,6 +1268,7 @@ int up_set_irq_type(int irq, int mode)
       regval  = getreg32(regaddr);
       regval &= ~GIC_ICDICFR_ID_MASK(irq);
       regval |= GIC_ICDICFR_ID(irq, intcfg);
+         syslog(1, "== addr %x", regaddr);
       putreg32(regval, regaddr);

       return OK;
diff --git a/drivers/can/ctucanfd_pci.c b/drivers/can/ctucanfd_pci.c
index ccb64c563bc..c5ca22b35e3 100644
--- a/drivers/can/ctucanfd_pci.c
+++ b/drivers/can/ctucanfd_pci.c
@@ -1936,6 +1936,7 @@ static void ctucanfd_init(FAR struct ctucanfd_driver_s *priv)
   /* REVISIT: Only legacy IRQ supported in QEMU driver */

   priv->irq = pci_get_irq(priv->pcidev);
+  syslog(1, "irq number %d \n", priv->irq);
   up_set_irq_type(priv->irq, IRQ_RISING_EDGE);
   irq_attach(priv->irq, ctucanfd_interrupt, priv);

./prebuilts/qemu/linux-x86_64//bin/qemu-system-arm -L ./prebuilts/qemu/linux-x86_64//share/qemu/ -cpu cortex-r52 -semihosting -machine virt,virtualiza
tion=on,gic-version=2,highmem=off -m 1G -nographic -serial mon:stdio -s -kernel /home/lipengfei28/disk1/qemu/dev/out/nuttx_qemu-armv8r-aarch32_can_sil
test/nuttx -object can-bus,id=canbus0-bus -object can-host-socketcan,id=canhost0,if=can0,canbus=canbus0-bus -device ctucan_pci,canbus0=canbus0-bus,can
bus1=canbus0-bus,bus=pcie.1 -M npd=2
[    0.015797] [core0] find_blockdriver: ERROR: Failed to find /dev/virtblk0
[    0.017053] [core0] find_mtddriver: ERROR: Failed to find /dev/virtblk0
[    0.017303] [core0] mtd_proxy: ERROR: Failed to find /dev/virtblk0 mtd driver
[    0.017596] [core0] coredump_initialize: /dev/virtblk0 Coredump device init failed:-2
[    0.048348] [core0] pci_scan_bus: pci_scan_bus for bus 0
[    0.049391] [core0] pci_scan_bus: class = 00000600, hdr_type = 00000000
[    0.049667] [core0] pci_scan_bus: 00:00 [1b36:0008]
[    0.055229] [core0] pci_setup_device: pbar0 set bad mask
[    0.055433] [core0] pci_setup_device: pbar1 set bad mask
[    0.055573] [core0] pci_setup_device: pbar2 set bad mask
[    0.055713] [core0] pci_setup_device: pbar3 set bad mask
[    0.055853] [core0] pci_setup_device: pbar4 set bad mask
[    0.055993] [core0] pci_setup_device: pbar5 set bad mask
[    0.056310] [core0] pci_scan_bus: class = 00000c09, hdr_type = 00000000
[    0.056497] [core0] pci_scan_bus: 00:08 [1760:ff00]
[    0.056715] [core0] pci_setup_device: pbar0: mask64=fffffff0 32768bytes
[    0.056971] [core0] pci_setup_device: pbar1: mask64=fffffff0 65536bytes
[    0.057149] [core0] pci_setup_device: pbar2 set bad mask
[    0.057292] [core0] pci_setup_device: pbar3 set bad mask
[    0.057432] [core0] pci_setup_device: pbar4 set bad mask
[    0.057571] [core0] pci_setup_device: pbar5 set bad mask
[    0.058392] [core0] ctucanfd_probe: Enabled bus mastering
[    0.058848] [core0] ctucanfd_probe: Enabled memory resources
[    0.059249] [core0] ctucanfd_probe: detected 2 CTUCANFD channels
[    0.059559] [core0] irq number 36
[    0.059710] [core0] == addr 8000c08
[    0.061483] [core0] pci_scan_bus: pci_scan_bus for bus 0
[    0.061633] [core0] pci_scan_bus: class = 00000600, hdr_type = 00000000
[    0.061808] [core0] pci_scan_bus: 00:00 [1b36:0008]
[    0.061940] [core0] pci_setup_device: pbar0 set bad mask
[    0.062076] [core0] pci_setup_device: pbar1 set bad mask
[    0.062211] [core0] pci_setup_device: pbar2 set bad mask
[    0.062348] [core0] pci_setup_device: pbar3 set bad mask
[    0.062482] [core0] pci_setup_device: pbar4 set bad mask
[    0.062619] [core0] pci_setup_device: pbar5 set bad mask
[    0.062763] [core0] pci_scan_bus: class = 00000200, hdr_type = 00000000
[    0.062940] [core0] pci_scan_bus: 00:08 [1af4:1000]
[    0.063091] [core0] pci_setup_device: pbar0: mask64=fffffffe 32bytes
[    0.063262] [core0] pci_setup_device: pbar1: mask64=fffffff0 4096bytes
[    0.063431] [core0] pci_setup_device: pbar2 set bad mask
[    0.063566] [core0] pci_setup_device: pbar3 set bad mask
[    0.063780] [core0] pci_setup_device: pbar4: mask64=fffffffffffffff0 16384bytes

NuttShell (NSH) NuttX-12.3.0
core0> mw 8000c08
  0x8000c08 = 0x00000200  // irq 36  edge-triggered.

@github-actions github-actions bot added Arch: arm Issues related to ARM (32-bit) architecture Arch: arm64 Issues related to ARM64 (64-bit) architecture Area: OS Components OS Components issues Board: arm64 Size: M The size of the change in this PR is medium labels Nov 25, 2025
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@jerpelea jerpelea left a comment

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please update PR message to describe the actual change!

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@linguini1 linguini1 left a comment

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PR requires proper description according to template.

@lipengfei28 lipengfei28 force-pushed the config_irq_type branch 5 times, most recently from 6bd2202 to 47276f1 Compare November 27, 2025 03:59
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PR requires proper description according to template.

done

@lipengfei28 lipengfei28 requested a review from acassis as a code owner November 27, 2025 07:02
@lipengfei28 lipengfei28 force-pushed the config_irq_type branch 2 times, most recently from 951081f to cbd9f64 Compare November 27, 2025 07:25
add api to config irq type

Signed-off-by: lipengfei28 <[email protected]>
arm64 add api to config irq type

Signed-off-by: lipengfei28 <[email protected]>
@lipengfei28 lipengfei28 force-pushed the config_irq_type branch 3 times, most recently from e19b03e to dfad497 Compare November 27, 2025 11:15
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done

I'm sorry but your descriptions still do not meet the requirements. Please read the contribution guidelines.

Your summary doesn't really explain what you've done, it just lists function names.
Your impact should include any required changes by other code to use this change or what this change effects. Right now your impact is closer to a summary.

Your testing section provides no information on how this change was tested and does not include logs. You also still have part of the default template there.

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acassis commented Nov 27, 2025

@lipengfei28 please include Testing hardware proving it still working fine

arm add api to config irq type

Signed-off-by: lipengfei28 <[email protected]>
arm64_gic_irq_set_priority

use use up_prioritize_irq and up_set_type_irq as std api

Signed-off-by: lipengfei28 <[email protected]>
14:35:29  chip/a64_twi.c:1846:3: error: implicit declaration of function 'up_prioritize_irq' [-Werror=implicit-function-declaration]
14:35:29   1846 |   up_prioritize_irq(priv->config->irq, 0);
14:35:29        |   ^~~~~~~~~~~~~~~~~

Signed-off-by: wangzhi16 <[email protected]>
Signed-off-by: lipengfei28 <[email protected]>
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@lipengfei28 please include Testing hardware proving it still working fine

done

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Please format the description properly.

@jerpelea jerpelea changed the title Config irq type arch/arm64: config irq type Dec 1, 2025
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Arch: arm Issues related to ARM (32-bit) architecture Arch: arm64 Issues related to ARM64 (64-bit) architecture Area: OS Components OS Components issues Board: arm64 Size: M The size of the change in this PR is medium

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7 participants