arch/arm64: config irq type

arch/arm/src/armv7-a/arm_gicv2.c

@@ -668,7 +668,7 @@ void up_trigger_irq(int irq, cpu_set_t cpuset)
 }
 
 /****************************************************************************
- * Name: arm_gic_irq_trigger
+ * Name: up_set_irq_type
  *
  * Description:
  *   Set the trigger type for the specified IRQ source and the current CPU.
@@ -677,32 +677,37 @@ void up_trigger_irq(int irq, cpu_set_t cpuset)
  *   avoided in common implementations where possible.
  *
  * Input Parameters:
- *   irq - The interrupt request to modify.
- *   edge - False: Active HIGH level sensitive, True: Rising edge sensitive
+ *   irq  - The interrupt request to modify.
+ *   mode - Level sensitive or edge sensitive
  *
  * Returned Value:
  *   Zero (OK) on success; a negated errno value is returned on any failure.
  *
  ****************************************************************************/
 
-int arm_gic_irq_trigger(int irq, bool edge)
+int up_set_irq_type(int irq, int mode)
 {
   uintptr_t regaddr;
   uint32_t regval;
   uint32_t intcfg;
 
-  if (irq > GIC_IRQ_SGI15 && irq < NR_IRQS)
+  if (!GIC_IS_SGI(irq))
     {
+      if (mode == IRQ_HIGH_LEVEL || mode == IRQ_LOW_LEVEL)
+        {
+          intcfg = INT_ICDICFR_1N;
+        }
+      else
+        {
+          intcfg = INT_ICDICFR_EDGE | INT_ICDICFR_1N;
+        }
+
       /* Get the address of the Interrupt Configuration Register for this
        * irq.
        */
 
       regaddr = GIC_ICDICFR(irq);
 
-      /* Get the new Interrupt configuration bit setting */
-
-      intcfg = (edge ? (INT_ICDICFR_EDGE | INT_ICDICFR_1N) : INT_ICDICFR_1N);
-
       /* Write the correct interrupt trigger to the Interrupt Configuration
        * Register.
        */

arch/arm/src/armv7-a/arm_gicv2m.c

@@ -26,6 +26,7 @@
 
 #include <errno.h>
 
+#include <nuttx/arch.h>
 #include <nuttx/bits.h>
 #include <nuttx/kmalloc.h>
 #include <nuttx/pci/pci.h>
@@ -117,7 +118,7 @@ int up_alloc_irq_msi(uint8_t busno, uint32_t devfn, int *pirq, int num)
   irq = g_v2m.spi_start + offset;
   for (i = 0; i < num; i++)
     {
-      arm_gic_irq_trigger(i + irq, true);
+      up_set_irq_type(i + irq, IRQ_RISING_EDGE);
       pirq[i] = i + irq;
     }
 

arch/arm/src/armv7-a/gic.h

@@ -623,6 +623,8 @@
 #define GIC_IRQ_SGI14            14 /* Software Generated Interrupt (SGI) 14 */
 #define GIC_IRQ_SGI15            15 /* Software Generated Interrupt (SGI) 15 */
 
+#define GIC_IRQ_PPI0             16
+
 #define GIC_IRQ_VM               25 /* Virtual Maintenance Interrupt (VM) PPI(6) */
 #define GIC_IRQ_HTM              26 /* Hypervisor Timer (HTM) PPI(5) */
 #define GIC_IRQ_VTM              27 /* Virtual Timer (VTM) PPI(4) */
@@ -631,6 +633,9 @@
 #define GIC_IRQ_PTM              30 /* Non-secure Physical Timer (PTM) PPI(2) */
 #define GIC_IRQ_IRQ              31 /* Interrupt Request (nIRQ) PPI(3) */
 
+#define GIC_IS_SGI(intid)        ((intid) >= GIC_IRQ_SGI0 && \
+                                  (intid) < GIC_IRQ_PPI0)
+
 /* Shared Peripheral Interrupts (SPI) follow */
 
 #define GIC_IRQ_SPI              32 /* First SPI interrupt ID */
@@ -746,26 +751,6 @@ void arm_gic0_initialize(void);
 
 void arm_gic_initialize(void);
 
-/****************************************************************************
- * Name: arm_gic_irq_trigger
- *
- * Description:
- *   Set the trigger type for the specificd IRQ source and the current CPU.
- *
- *   Since this API is not supported on all architectures, it should be
- *   avoided in common implementations where possible.
- *
- * Input Parameters:
- *   irq - The interrupt request to modify.
- *   edge - False: Active HIGH level sensitive, True: Rising edge sensitive
- *
- * Returned Value:
- *   Zero (OK) on success; a negated errno value is returned on any failure.
- *
- ****************************************************************************/
-
-int arm_gic_irq_trigger(int irq, bool edge);
-
 /****************************************************************************
  * Name: arm_decodeirq
  *

arch/arm/src/armv7-r/arm_gicv2.c

@@ -610,7 +610,7 @@ void up_trigger_irq(int irq, cpu_set_t cpuset)
 }
 
 /****************************************************************************
- * Name: arm_gic_irq_trigger
+ * Name: up_set_irq_type
  *
  * Description:
  *   Set the trigger type for the specified IRQ source and the current CPU.
@@ -619,32 +619,37 @@ void up_trigger_irq(int irq, cpu_set_t cpuset)
  *   avoided in common implementations where possible.
  *
  * Input Parameters:
- *   irq - The interrupt request to modify.
- *   edge - False: Active HIGH level sensitive, True: Rising edge sensitive
+ *   irq  - The interrupt request to modify.
+ *   mode - Level sensitive or edge sensitive
  *
  * Returned Value:
  *   Zero (OK) on success; a negated errno value is returned on any failure.
  *
  ****************************************************************************/
 
-int arm_gic_irq_trigger(int irq, bool edge)
+int up_set_irq_type(int irq, int mode)
 {
   uintptr_t regaddr;
   uint32_t regval;
   uint32_t intcfg;
 
-  if (irq > GIC_IRQ_SGI15 && irq < NR_IRQS)
+  if (!GIC_IS_SGI(irq))
     {
+      if (mode == IRQ_HIGH_LEVEL || mode == IRQ_LOW_LEVEL)
+        {
+          intcfg = INT_ICDICFR_1N;
+        }
+      else
+        {
+          intcfg = INT_ICDICFR_EDGE | INT_ICDICFR_1N;
+        }
+
       /* Get the address of the Interrupt Configuration Register for this
        * irq.
        */
 
       regaddr = GIC_ICDICFR(irq);
 
-      /* Get the new Interrupt configuration bit setting */
-
-      intcfg = (edge ? (INT_ICDICFR_EDGE | INT_ICDICFR_1N) : INT_ICDICFR_1N);
-
       /* Write the correct interrupt trigger to the Interrupt Configuration
        * Register.
        */

arch/arm/src/armv7-r/gic.h

@@ -596,6 +596,8 @@
 #define GIC_IRQ_SGI14            14 /* Software Generated Interrupt (SGI) 14 */
 #define GIC_IRQ_SGI15            15 /* Software Generated Interrupt (SGI) 15 */
 
+#define GIC_IRQ_PPI0             16
+
 #define GIC_IRQ_VM               25 /* Virtual Maintenance Interrupt (VM) PPI(6) */
 #define GIC_IRQ_HTM              26 /* Hypervisor Timer (HTM) PPI(5) */
 #define GIC_IRQ_VTM              27 /* Virtual Timer (VTM) PPI(4) */
@@ -604,6 +606,9 @@
 #define GIC_IRQ_PTM              30 /* Non-secure Physical Timer (PTM) PPI(2) */
 #define GIC_IRQ_IRQ              31 /* Interrupt Request (nIRQ) PPI(3) */
 
+#define GIC_IS_SGI(intid)        ((intid) >= GIC_IRQ_SGI0 && \
+                                  (intid) < GIC_IRQ_PPI0)
+
 /* Shared Peripheral Interrupts (SPI) follow */
 
 #define GIC_IRQ_SPI              32 /* First SPI interrupt ID */
@@ -748,26 +753,6 @@ void arm_gic0_initialize(void);
 
 void arm_gic_initialize(void);
 
-/****************************************************************************
- * Name: arm_gic_irq_trigger
- *
- * Description:
- *   Set the trigger type for the specificd IRQ source and the current CPU.
- *
- *   Since this API is not supported on all architectures, it should be
- *   avoided in common implementations where possible.
- *
- * Input Parameters:
- *   irq - The interrupt request to modify.
- *   edge - False: Active HIGH level sensitive, True: Rising edge sensitive
- *
- * Returned Value:
- *   Zero (OK) on success; a negated errno value is returned on any failure.
- *
- ****************************************************************************/
-
-int arm_gic_irq_trigger(int irq, bool edge);
-
 /****************************************************************************
  * Name: arm_decodeirq
  *

arch/arm/src/armv8-r/arm_gic.h

@@ -335,8 +335,6 @@ void arm_gic_irq_set_priority(unsigned int intid, unsigned int prio,
 void arm_gic_set_group(unsigned int intid, unsigned int group);
 #endif
 
-int arm_gic_irq_trigger(unsigned int intid, uint32_t flags);
-
 int arm_gic_raise_sgi(unsigned int sgi_id, uint16_t target_list);
 
 #ifdef CONFIG_SMP

arch/arm/src/armv8-r/arm_gicv3.c

@@ -207,7 +207,7 @@ void arm_gic_irq_set_priority(unsigned int intid, unsigned int prio,
 }
 
 /***************************************************************************
- * Name: arm_gic_irq_trigger
+ * Name: up_set_irq_type
  *
  * Description:
  *   Set the trigger type for the specified IRQ source and the current CPU.
@@ -216,27 +216,26 @@ void arm_gic_irq_set_priority(unsigned int intid, unsigned int prio,
  *   avoided in common implementations where possible.
  *
  * Input Parameters:
- *   irq   - The interrupt request to modify.
- *   flags - irq type, IRQ_TYPE_EDGE or IRQ_TYPE_LEVEL
- *           Default is IRQ_TYPE_LEVEL
+ *   irq  - The interrupt request to modify.
+ *   mode - Level sensitive or edge sensitive
  *
  * Returned Value:
  *   Zero (OK) on success; a negated errno value is returned on any failure.
  *
  ***************************************************************************/
 
-int arm_gic_irq_trigger(unsigned int intid, uint32_t flags)
+int up_set_irq_type(int irq, int mode)
 {
-  uint32_t      idx  = intid / GIC_NUM_INTR_PER_REG;
+  uint32_t      idx  = irq / GIC_NUM_INTR_PER_REG;
   uint32_t      shift;
   uint32_t      val;
-  unsigned long base = GET_DIST_BASE(intid);
+  unsigned long base = GET_DIST_BASE(irq);
   irqstate_t    irq_flags;
 
-  if (!GIC_IS_SGI(intid))
+  if (!GIC_IS_SGI(irq))
     {
-      idx   = intid / GIC_NUM_CFG_PER_REG;
-      shift = (intid & (GIC_NUM_CFG_PER_REG - 1)) * 2;
+      idx   = irq / GIC_NUM_CFG_PER_REG;
+      shift = (irq & (GIC_NUM_CFG_PER_REG - 1)) * 2;
 
       /* GICD_ICFGR requires full 32-bit RMW operations.
        * Each interrupt uses 2 bits; thus updates must be synchronized
@@ -246,7 +245,7 @@ int arm_gic_irq_trigger(unsigned int intid, uint32_t flags)
       irq_flags = spin_lock_irqsave(&g_gic_lock);
       val = getreg32(ICFGR(base, idx));
       val &= ~(GICD_ICFGR_MASK << shift);
-      if (flags & IRQ_TYPE_EDGE)
+      if (mode != IRQ_HIGH_LEVEL && mode != IRQ_LOW_LEVEL)
         {
           val |= (GICD_ICFGR_TYPE << shift);
         }

arch/arm/src/imx6/imx_enet.c

@@ -39,6 +39,7 @@
 
 #include <arpa/inet.h>
 
+#include <nuttx/arch.h>
 #include <nuttx/wdog.h>
 #include <nuttx/irq.h>
 #include <nuttx/arch.h>
@@ -2581,7 +2582,7 @@ int imx_netinitialize(int intf)
 
   /* Configure as a (high) level interrupt */
 
-  arm_gic_irq_trigger(IMX_IRQ_ENET0, false);
+  up_set_irq_type(IMX_IRQ_ENET0, IRQ_HIGH_LEVEL);
 
 #ifdef CONFIG_NET_ETHERNET
   /* Determine a semi-unique MAC address from MCU UID

arch/arm/src/imx6/imx_serial.c

@@ -599,7 +599,7 @@ static int imx_attach(struct uart_dev_s *dev)
     {
       /* Configure as a (high) level interrupt */
 
-      arm_gic_irq_trigger(priv->irq, false);
+      up_set_irq_type(priv->irq, IRQ_HIGH_LEVEL);
 
       /* Enable the interrupt (RX and TX interrupts are still disabled
        * in the UART

arch/arm/src/imx6/imx_timerisr.c

@@ -246,7 +246,7 @@ void up_timer_initialize(void)
 
   /* Configure as a (rising) edge-triggered interrupt */
 
-  arm_gic_irq_trigger(IMX_IRQ_GPT, true);
+  up_set_irq_type(IMX_IRQ_GPT, IRQ_RISING_EDGE);
 
   /* Attach the timer interrupt vector */
 

arch/arm64/Kconfig

@@ -34,6 +34,7 @@ config ARCH_CHIP_A64
 	select ARCH_HAVE_IRQTRIGGER
 	select ARCH_NEED_ADDRENV_MAPPING
 	select ARM64_HAVE_PSCI
+	select ARCH_HAVE_IRQPRIO
 	---help---
 		Allwinner A64 SoC
 
@@ -44,6 +45,7 @@ config ARCH_CHIP_RK3399
 	select ARCH_HAVE_RESET
 	select ARCH_NEED_ADDRENV_MAPPING
 	select ARM64_HAVE_PSCI
+	select ARCH_HAVE_IRQPRIO
 	---help---
 		Rockchip RK3399 SoC
 
@@ -57,6 +59,7 @@ config ARCH_CHIP_QEMU
 	select ARCH_HAVE_RESET
 	select ARCH_HAVE_TEXT_HEAP
 	select ARM64_HAVE_PSCI
+	select ARCH_HAVE_IRQPRIO
 	---help---
 		QEMU virt platform (ARMv8a)
 
@@ -72,6 +75,7 @@ config ARCH_CHIP_GOLDFISH
 	select ARCH_HAVE_RESET
 	select ARCH_NEED_ADDRENV_MAPPING
 	select ARM64_HAVE_PSCI
+	select ARCH_HAVE_IRQPRIO
 	---help---
 		Android GoldFish platform for NuttX (ARMv8a),
 		based on ARM virt board
@@ -80,6 +84,7 @@ config ARCH_CHIP_FVP_ARMV8R
 	bool "ARM FVP virt platform (ARMv8r)"
 	select ARCH_CORTEX_R82
 	select ARCH_HAVE_IRQTRIGGER
+	select ARCH_HAVE_IRQPRIO
 	---help---
 		ARM FVP virt platform (ARMv8r)
 
@@ -88,6 +93,7 @@ config ARCH_CHIP_IMX8
 	select ARCH_HAVE_ADDRENV
 	select ARCH_HAVE_IRQTRIGGER
 	select ARCH_NEED_ADDRENV_MAPPING
+	select ARCH_HAVE_IRQPRIO
 	---help---
 		NXP i.MX8 (ARMv8a) applications processors
 
@@ -98,6 +104,7 @@ config ARCH_CHIP_IMX9
 	select ARCH_HAVE_I2CRESET
 	select ARCH_HAVE_IRQTRIGGER
 	select ARCH_NEED_ADDRENV_MAPPING
+	select ARCH_HAVE_IRQPRIO
 	---help---
 		NXP i.MX9 (ARMv8.2a) applications processors
 
@@ -109,6 +116,7 @@ config ARCH_CHIP_ZYNQ_MPSOC
 	select ARCH_HAVE_IRQTRIGGER
 	select ARCH_NEED_ADDRENV_MAPPING
 	select ARM64_HAVE_PSCI
+	select ARCH_HAVE_IRQPRIO
 	---help---
 		XilinX ZYNQ MPSOC
 
@@ -123,6 +131,7 @@ config ARCH_CHIP_BCM2711
 	select ARCH_USE_MMU # Required for up_testset
 	select ARMV8A_HAVE_GICv2
 	select ARCH_HAVE_SDIO
+	select ARCH_HAVE_IRQPRIO
 	---help---
 		Broadcom BCM2711 quad-core ARM Cortex A72
 

arch/arm64/src/a64/a64_serial.c

@@ -648,7 +648,8 @@ static int a64_uart_attach(struct uart_dev_s *dev)
 
   /* Set Interrupt Priority in Generic Interrupt Controller v2 */
 
-  arm64_gic_irq_set_priority(port->irq_num, 0, IRQ_TYPE_LEVEL);
+  up_prioritize_irq(port->irq_num, 0);
+  up_set_irq_type(port->irq_num, IRQ_HIGH_LEVEL);
 
   /* Enable UART Interrupt */